A B C D E

1 1

LCFC Confidential
CG510 M/B Schematics Document
2 2

Intel Broadwell U-Processor with DDRIIIL + NV920

2015-05-09
3

REV:0.2 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 1 of 59
A B C D E
 A B C D E

LCFC confidential File Name : CG510

NV (N16V-GM)
GB2B-64 Package PCI-Express DDR3L-SO-DIMM X1
Page 18~28 PCIe Port5
4x Gen2 Memory BUS (CHA)
Page 14,15
1
VRAM 256/128*16 1.35V DDR3L 1600 MT/s 1

UP TO 4G
DDR3L*4 2GB/1GB Memory BUS (CHB)
Page 19~28
Memory down 256/128*16
1.35V DDR3L 1600 MT/s DDR3L*8 4G/2G

HDMI
HDMI Conn. USB Left
Page 34
USB 3.0 1x
Intel MCP USB 3.0 Port1
USB 2.0 Port1
eDP x2 Lane
eDP Conn USB 2.0 2x
USB2.0 1x USB 2.0 Port2
Int. Camera Page 41
USB2.0 Port5

2
Haswell U 15W / 2

Int. MIC Conn. Broadwell U 15W

USB2.0 1x Cardreader Realtek SD/MMC Conn.
Page 33
RTS5170 USB2.0 Port3

SATA HDD SATA Gen3

Page 42 SATA Port0
BGA-1168
USB 2.0 1x
SATA ODD SATA Gen1 40mm*24mm NGFF Card
PCIe 1x WLAN&BT
Page 42 SATA Port1
PCIe Port4
Page 40 USB2.0 Port6

LAN Realtek
RJ45 Conn. PCIe 1x
Page 38 RTL8106EUL (10M/100M) SPI BUS SPI ROM
3
Page 37 PCIe Port3 8MB Page 07
3

HD Audio
Page 3~13

Codec SPK Conn.

Conexant CX11802 Page 43
Page 43

EC
ITE IT8586E-LQFP
Page 44

Mic HP&Mic Combo Conn. Sub-board ( for 15")

Page 44

Touch Pad Int.KBD Thermal Sensor ODD Board

4 Page 45 Page 45 NCT7718W 4
Page 39

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 2 of 59
C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+1.35VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+1.05VS 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3VALW +0.675VS
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH CPU_CORE

+5VALW +1.35V S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

+VGA_CORE
State +3VGS
+1.8VGS
+1.35VGS
+0.95VGS
USB Port Table BOM Structure Table
USB 2.0 USB 3.0
BOM Structure BTO Item
XHCI XHCI Not stuff
@
S0 O O O O O 0 USB Port (Right Side) 14@ For 14" part
15@ For 15" part
1 USB Port1 (Left Side) 1 USB Port1 (Left Side) UMA SKU part
UMA@
S3 O O O O X 2 USB Port2 (Left Side) 2 PX@ Discrete GPU SKU part
2 100M@ 100M LAN Part 2
3 Cardreader 3
GIGA@ GIGA LAN Part
S3
Battery only O O O O X 4 TOUCH PANEL 4 JET@ For AMD Jet GPU part
TOPAZ@ For AMD Topaz GPU part
5 Camera For VRAM RankA part
RANKA@
6 NGFF(WLAN) RANKB@ For VRAM RankB part
S5 S4/AC Only O O O X X ME@ ME part(connector, hole)
7 For support touch panel sku part
TS@
S5 S4 AOAC@ AOAC support part
Battery only O X X X X H2@ Hynix 128Mx16 VRAM part
H4@ Hynix 256Mx16 VRAM part
S5 S4 M2@ Micron 128Mx16 VRAM part
AC & Battery X X X X X M4@ Micron 256Mx16 VRAM part
don't exist S2@ Samsung 128Mx16 VRAM part
PCIE PORT LIST S4@ Samsung 256Mx16 VRAM part
H2GX4@ Hynix 128Mx16 VRAM x4pcs sku
SMBUS Control Table Port Device
3 M2GX4@ Micron 128Mx16 VRAM x4pcs sku 3

WLAN Thermal TP 1 S2GX4@ Samsung 128Mx16 VRAM x4pcs sku

SOURCE VGA BATT IT8586E SODIMM PCH charger
WiMAX Sensor Module 2 H4GX4@ Hynix 256Mx16 VRAM x4pcs sku
3 LAN
M4GX4@ Micron 256Mx16 VRAM x4pcs sku
4 WLAN Samsung 256Mx16 VRAM x4pcs sku
EC_SMB_CK1 IT8586E V 5 Discrete GPU
S4GX4@
EC_SMB_DA1 +3VALW X V +3VALW X X X X X V H2GX8@ Hynix 128Mx16 VRAM x8pcs sku
6 M2GX8@ Micron 128Mx16 VRAM x8pcs sku
EC_SMB_CK2 IT8586E V V S2GX8@ Samsung 128Mx16 VRAM x8pcs sku
X X V X X X
EC_SMB_DA2 +3VS +3VGS X +3VS +3VS +3VALW_PCH H4GX8@ Hynix 256Mx16 VRAM x8pcs sku
M4GX8@ Micron 256Mx16 VRAM x8pcs sku
PCH_SMB_CLK PCH S4GX8@ Samsung 256Mx16 VRAM x8pcs sku
PCH_SMB_DATA +3VALW_PCH X X X V V X V X X Cost down part
+3VS +3VS +3VALW_PCH CD@
BCD@ Cost down part for BDW project
SINGLE@ Single Rank VRAM sku
DUAL@ Dual Rank VRAM sku
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address
Device Address
Device Device Address DDR DIMMA 1010 000Xb
4 4
Smart Battery 0X16 Thermal Sensor NCT7718W 1001_100xb DDR DIMMB 1010 010Xb
Charger 0001 0010 b VGA 0x41(default) Wlan Rsvd
PCH need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 3 of 59
A B C D E
 5 4 3 2 1

UC1A HSW_ULT_DDR3L

HDMI_TX2- C54 C45 CPU_EDP_TX0-

34 HDMI_TX2- HDMI_TX2+ DDI1_TXN0 EDP_TXN0 CPU_EDP_TX0+ CPU_EDP_TX0- 33
HDMI D2 C55 B46
D 34 HDMI_TX2+ HDMI_TX1- DDI1_TXP0 EDP_TXP0 CPU_EDP_TX1- CPU_EDP_TX0+ 33
B58 A47 D
34 HDMI_TX1- HDMI_TX1+ DDI1_TXN1 EDP_TXN1 CPU_EDP_TX1+ CPU_EDP_TX1- 33
HDMI D1 C58 B47
34 HDMI_TX1+ HDMI_TX0- DDI1_TXP1 EDP_TXP1 CPU_EDP_TX1+ 33
B55
34 HDMI_TX0- HDMI_TX0+ DDI1_TXN2
HDMI D0 A55 C47
34 HDMI_TX0+ HDMI_CLK- DDI1_TXP2 EDP_TXN2
A57 C46
34 HDMI_CLK- HDMI_CLK+ DDI1_TXN3 EDP_TXP2
HDMI CLK B57 A49
34 HDMI_CLK+ DDI1_TXP3 EDP_TXN3
DDI EDP B49
C51 EDP_TXP3
C50 DDI2_TXN0 A45 CPU_EDP_AUX# +VCCIOA_OUT
DDI2_TXP0 EDP_AUXN CPU_EDP_AUX# 33 +VCCIOA_OUT & EDP_COMP :
C53 B45 CPU_EDP_AUX
DDI2_TXN1 EDP_AUXP CPU_EDP_AUX 33 Trace Width: 20mil
B54 Space: 25mil
C49 DDI2_TXP1 D20 EDP_COMP RC1 1 2 24.9_0402_1%
B50 DDI2_TXN2 EDP_RCOMP A43
Max length: 100mil
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3
DDI2_TXP3

1 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@

+3VS

RPC19
DDPB_DATA 3 2
UC1I HSW_ULT_DDR3L DDPB_CLK 4 1

C C
2.2K_0404_4P2R_5%

PCH_EDP_PWM B8 B9 DDPB_CLK DDPx_CTRLDATA

33 PCH_EDP_PWM PCH_ENBKL EDP_BKLCTL DDPB_CTRLCLK DDPB_DATA DDPB_CLK 34
A9 C9 DDPB_DATA 34 The signal has a weak internal pull-down.
33 PCH_ENBKL PCH_ENVDD EDP_BKLEN DDPB_CTRLDATA
C6 eDP SIDEBAND D9
33 PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK
DDPC_CTRLDATA
D11 * H
L
Port is detected.
Port is not detected.

PCI_PIRQA# U6
PCI_PIRQB# P4 PIRQA/GPIO77 C5
PCI_PIRQC# N4 PIRQB/GPIO78 DDPB_AUXN B6
PCI_PIRQD# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5
@ PAD 1 AD4 PIRQD/GPIO80 DDPB_AUXP A6
TC1 PME PCIE DDPC_AUXP
BOARD_ID3 U7
9 BOARD_ID3 GPIO55
GPIO52 L1
PXS_PWREN RC7 1 OPT@2 1K_0402_5% PXS_PWREN_R L3 GPIO52 C8 HDMI_HPD
21,58 PXS_PWREN PXS_RST# PXS_RST#_R GPIO54 DDPB_HPD HDMI_HPD 34
RC8 1 OPT@2 0_0402_5% R5 A8
19 PXS_RST# GPIO51 DDPC_HPD EDP_HPD
GPIO53 L4 D6
GPIO53 EDP_HPD

9 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@

B B

+3VS

1
RC9
+3VS 1M_0402_5%
@

2
RPC1 @
1 8 PCI_PIRQA# EDP_HPD RC16 1 2 CPU_EDP_HPD 33
2 7 PCI_PIRQB#
3 6 PCI_PIRQC# 0_0402_5%
4 5 PCI_PIRQD#

1
10K_0804_8P4R_5% RC13
100K_0402_5%

+3VS

2
RC10 1 2 10K_0402_5% GPIO52

RC11 1 2 10K_0402_5% GPIO53

RC14 1 2 10K_0402_5% PXS_PWREN_R

RC15 1 @ 2 10K_0402_5% PXS_RST#_R

A A

PXS_PWREN_R Security Classification LC Future Center Secret Data Title

RC17 2 @ 1 100K_0402_5%

RC18 1 2 10K_0402_5% PXS_RST#_R Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 4 of 59
3 2 1
 5 4 3 2 1

UC1B HSW_ULT_DDR3L

+1.05V_VCCST

D61
PROC_DETECT

1
D K61 MISC D
RC19 H_PECI N62 CATERR J62
44 H_PECI PECI PRDY
62_0402_1% K62
PREQ E60 XDP_TCLK 1 PAD @
PROC_TCK E61 XDP_TMS 1 TC6
PAD @
TC7

2
56_0402_5% 1 2 RC20 H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# 1 PAD @
44 H_PROCHOT# PROCHOT PROC_TRST XDP_TDI TC8
THERMAL F63 1 PAD @
PROC_TDI XDP_TDO TC9
F62 1 PAD @
PROC_TDO TC10
+1.35V 1 2 RC21 CPU_PROCPWRGD C61
10K_0402_5% PROCPWRGD PWR
J60
BPM#0

1
H60
RC22 BPM#1 H61
470_0402_5% BPM#2 H62
SM_RCOMP_0 AU60 BPM#3 K59
SM_RCOMP_1 AV60 SM_RCOMP0 DDR3L BPM#4 H63

2
SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60
RC23 1 @ 2 CPU_DRAMRST#_R AV15 SM_RCOMP2 BPM#6 J61
14,15 CPU_DRAMRST# SM_PG_CNTL1 AV61 SM_DRAMRST BPM#7
0_0402_5%
SM_PG_CNTL1
1
CC1 2 OF 19
0.1U_0402_25V6 BROADWELL-ULT-DDR3L_BGA1168
2 EMC@ @
C C

100_0402_1% 2 1 RC24 SM_RCOMP_2

121_0402_1% 2 1 RC25 SM_RCOMP_1

+3VALW
200_0402_1% 2 1 RC26 SM_RCOMP_0

1
RC28
100K_0402_5%

2
CPU_DRAMPG_CNTL 55
+1.35V
B B

1
C +1.35V
RC3 1 2 2 QC14
1K_0402_5% B
E

3
MMBT3904WH_SOT323-3 1 QC5
D
RC31 1 2 0_0402_5% 2
SM_PG_CNTL1 @ G
1 S
CD1 PJA138K_SOT23-3
3
2

.1U_0402_10V6-K
RC29 @ DDR_ODT RD3 1 2 66.5_0402_1% DDRB_ODT0
2 DDRB_ODT0 15
10K_0402_5%
@ RD4 1 2 66.5_0402_1% DDRB_ODT1
DDRB_ODT1 15
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (MISC,THERMAL,JATG)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 5 of 59
5 4 3 2 1
 5 4 3 2 1

l
UC1C HSW_ULT_DDR3L UC1D HSW_ULT_DDR3L

14 DDRA_DQ[0..15] DDRA_DQ2 AH63 AU37

SA_DQ0 SA_CLK#0 DDRA_CLK0# 14 14 DDRA_DQ[32..47]

a
DDRA_DQ4 AH62 AV37 DDRA_DQ37 AY31 AM38
DDRA_DQ7 AK63 SA_DQ1 SA_CLK0 AW36 DDRA_CLK0 14 DDRA_DQ36 AW31 SB_DQ0 SB_CK#0 AN38 DDRB_CLK0# 15
D DDRA_DQ6 AK62 SA_DQ2 SA_CLK#1 AY36 DDRA_DQ38 AY29 SB_DQ1 SB_CK0 AK38 DDRB_CLK0 15 D
DDRA_DQ1 AH61 SA_DQ3 SA_CLK1 DDRA_DQ35 AW29 SB_DQ2 SB_CK#1 AL38 DDRB_CLK1# 15
DDRA_DQ3 AH60 SA_DQ4 AU43 DDRA_DQ32 AV31 SB_DQ3 SB_CK1 DDRB_CLK1 15
DDRA_DQ0 AK61 SA_DQ5 SA_CKE0 AW43 DDRA_CKE0 14 DDRA_DQ33 AU31 SB_DQ4 AY49
DDRA_DQ5 AK60 SA_DQ6 SA_CKE1 AY42 DDRA_CKE1 14 DDRA_DQ34 AV29 SB_DQ5 SB_CKE0 AU50 DDRB_CKE0 15

i
DDRA_DQ15 AM63 SA_DQ7 SA_CKE2 AY43 DDRA_DQ39 AU29 SB_DQ6 SB_CKE1 AW49 DDRB_CKE1 15
DDRA_DQ10 AM62 SA_DQ8 SA_CKE3 DDRA_DQ41 AY27 SB_DQ7 SB_CKE2 AV50
DDRA_DQ9 AP63 SA_DQ9 AP33 DDRA_DQ47 AW27 SB_DQ8 SB_CKE3
DDRA_DQ8 AP62 SA_DQ10 SA_CS#0 AR32 DDRA_CS0# 14 DDRA_DQ44 AY25 SB_DQ9 AM32
DDRA_DQ14 AM61 SA_DQ11 SA_CS#1 DDRA_CS1# 14 DDRA_DQ43 AW25 SB_DQ10 SB_CS#0 AK32 DDRB_CS0# 15
DDRA_DQ11 AM60 SA_DQ12 AP32 DDRA_DQ45 AV27 SB_DQ11 SB_CS#1 DDRB_CS1# 15
SA_DQ13 SA_ODT0 SB_DQ12

t
DDRA_DQ13 AP61 DDRA_DQ40 AU27 AL32
DDRA_DQ12 AP60 SA_DQ14 AY34 DDRA_DQ42 AV25 SB_DQ13 SB_ODT0
15 DDRB_DQ[0..15] DDRB_DQ0 AP58 SA_DQ15 SA_RAS AW34 DDRA_RAS# 14 DDRA_DQ46 AU25 SB_DQ14 AM35
DDRB_DQ1 AR58 SA_DQ16 SA_WE AU34 DDRA_W E# 14 15 DDRB_DQ[32..47] DDRB_DQ32 AM29 SB_DQ15 SB_RAS AK35 DDRB_RAS# 15
DDRB_DQ2 AM57 SA_DQ17 SA_CAS DDRA_CAS# 14 DDRB_DQ33 AK29 SB_DQ16 SB_WE AM33 DDRB_W E# 15
DDRB_DQ3 AK57 SA_DQ18 AU35 DDRB_DQ34 AL28 SB_DQ17 SB_CAS DDRB_CAS# 15
DDRB_DQ4 AL58 SA_DQ19 SA_BA0 AV35 DDRA_BS0# 14 DDRB_DQ35 AK28 SB_DQ18 AL35

n
DDRB_DQ5 AK58 SA_DQ20 SA_BA1 AY41 DDRA_BS1# 14 DDRB_DQ36 AR29 SB_DQ19 SB_BA0 AM36 DDRB_BS0# 15
DDRB_DQ6 AR57 SA_DQ21 SA_BA2 DDRA_BS2# 14 DDRB_DQ37 AN29 SB_DQ20 SB_BA1 AU49 DDRB_BS1# 15
DDRB_DQ7 AN57 SA_DQ22 AU36 DDRA_MA0 DDRA_MA[0..15] 14 DDRB_DQ38 AR28 SB_DQ21 4 OF 19 SB_BA2 DDRB_BS2# 15
DDRB_DQ8 AP55 SA_DQ23 SA_MA0 AY37 DDRA_MA1 DDRB_DQ39 AP28 SB_DQ22 AP40 DDRB_MA0 DDRB_MA[0..15] 15
DDRB_DQ9 AR55 SA_DQ24 SA_MA1 AR38 DDRA_MA2 DDRB_DQ40 AN26 SB_DQ23 SB_MA0 AR40 DDRB_MA1
DDRB_DQ10 AM54 SA_DQ25 SA_MA2 AP36 DDRA_MA3 DDRB_DQ41 AR26 SB_DQ24 SB_MA1 AP42 DDRB_MA2

e
DDRB_DQ11 AK54 SA_DQ26 SA_MA3 AU39 DDRA_MA4 DDRB_DQ42 AR25 SB_DQ25 SB_MA2 AR42 DDRB_MA3
DDRB_DQ12 AL55 SA_DQ27 SA_MA4 AR36 DDRA_MA5 DDRB_DQ43 AP25 SB_DQ26 SB_MA3 AR45 DDRB_MA4
DDRB_DQ13 AK55 SA_DQ28 SA_MA5 AV40 DDRA_MA6 DDRB_DQ44 AK26 SB_DQ27 SB_MA4 AP45 DDRB_MA5
DDRB_DQ14 AR54 SA_DQ29 SA_MA6 AW39 DDRA_MA7 DDRB_DQ45 AM26 SB_DQ28 SB_MA5 AW46 DDRB_MA6
DDRB_DQ15 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDRA_MA8 DDRB_DQ46 AK25 SB_DQ29 SB_MA6 AY46 DDRB_MA7
14 DDRA_DQ[16..31] DDRA_DQ19 AY58 SA_DQ31 SA_MA8 AU40 DDRA_MA9 DDRB_DQ47 AL25 SB_DQ30 SB_MA7 AY47 DDRB_MA8
DDRA_DQ20 AW58 SA_DQ32 SA_MA9 AP35 DDRA_MA10 14 DDRA_DQ[48..63] DDRA_DQ53 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDRB_MA9

d
DDRA_DQ18 AY56 SA_DQ33 SA_MA10 AW41 DDRA_MA11 DDRA_DQ50 AW23 SB_DQ32 SB_MA9 AK36 DDRB_MA10
C DDRA_DQ17 AW56 SA_DQ34 SA_MA11 AU41 DDRA_MA12 DDRA_DQ51 AY21 SB_DQ33 SB_MA10 AV47 DDRB_MA11 C
DDRA_DQ23 AV58 SA_DQ35 SA_MA12 AR35 DDRA_MA13 DDRA_DQ55 AW21 SB_DQ34 SB_MA11 AU47 DDRB_MA12
DDRA_DQ22 AU58 SA_DQ36 SA_MA13 AV42 DDRA_MA14 DDRA_DQ54 AV23 SB_DQ35 SB_MA12 AK33 DDRB_MA13
DDRA_DQ21 AV56 SA_DQ37 SA_MA14 AU42 DDRA_MA15 DDRA_DQ48 AU23 SB_DQ36 SB_MA13 AR46 DDRB_MA14
DDRA_DQ16 AU56 SA_DQ38 SA_MA15 DDRA_DQ49 AV21 SB_DQ37 SB_MA14 AP46 DDRB_MA15

i
DDRA_DQ28 AY54 SA_DQ39 AJ61 DDRA_DQS#0 DDRA_DQ52 AU21 SB_DQ38 SB_MA15
DDRA_DQ25 AW54 SA_DQ40 SA_DQSN0 AN62 DDRA_DQS#1 DDRA_DQ58 AY19 SB_DQ39 AW30 DDRA_DQS#4
DDRA_DQ26 AY52 SA_DQ41 SA_DQSN1 AM58 DDRB_DQS#0 DDRA_DQ62 AW19 SB_DQ40 SB_DQSN0 AV26 DDRA_DQS#5
DDRA_DQ27 AW52 SA_DQ42 SA_DQSN2 AM55 DDRB_DQS#1 DDRA_DQ60 AY17 SB_DQ41 SB_DQSN1 AN28 DDRB_DQS#4
DDRA_DQ24 AV54 SA_DQ43 SA_DQSN3 AV57 DDRA_DQS#2 DDRA_DQ57 AW17 SB_DQ42 SB_DQSN2 AN25 DDRB_DQS#5
DDRA_DQ29 AU54 SA_DQ44 SA_DQSN4 AV53 DDRA_DQS#3 DDRA_DQ59 AV19 SB_DQ43 SB_DQSN3 AW22 DDRA_DQS#6
DDRA_DQ31 SA_DQ45 SA_DQSN5 DDRB_DQS#2 DDRA_DQ63 SB_DQ44 SB_DQSN4 DDRA_DQS#7

f
AV52 AL43 AU19 AV18
DDRA_DQ30 AU52 SA_DQ46 SA_DQSN6 AL48 DDRB_DQS#3 DDRA_DQ56 AV17 SB_DQ45 SB_DQSN5 AN21 DDRB_DQS#6
15 DDRB_DQ[16..31] DDRB_DQ16 AK40 SA_DQ47 SA_DQSN7 DDRA_DQ61 AU17 SB_DQ46 SB_DQSN6 AN18 DDRB_DQS#7
DDRB_DQ17 AK42 SA_DQ48 AJ62 DDRA_DQS0 15 DDRB_DQ[48..63] DDRB_DQ48 AR21 SB_DQ47 SB_DQSN7
DDRB_DQ18 AM43 SA_DQ49 SA_DQSP0 AN61 DDRA_DQS1 DDRB_DQ49 AR22 SB_DQ48 AV30 DDRA_DQS4
DDRB_DQ19 AM45 SA_DQ50 SA_DQSP1 AN58 DDRB_DQS0 DDRB_DQ50 AL21 SB_DQ49 SB_DQSP0 AW26 DDRA_DQS5
DDRB_DQ20 AK45 SA_DQ51 SA_DQSP2 AN55 DDRB_DQS1 DDRB_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 DDRB_DQS4

n
DDRB_DQ21 AK43 SA_DQ52 SA_DQSP3 AW57 DDRA_DQS2 DDRB_DQ52 AN22 SB_DQ51 SB_DQSP2 AM25 DDRB_DQS5
DDRB_DQ22 AM40 SA_DQ53 SA_DQSP4 AW53 DDRA_DQS3 DDRB_DQ53 AP21 SB_DQ52 SB_DQSP3 AV22 DDRA_DQS6
DDRB_DQ23 AM42 SA_DQ54 SA_DQSP5 AL42 DDRB_DQS2 DDRB_DQ54 AK21 SB_DQ53 SB_DQSP4 AW18 DDRA_DQS7
DDRB_DQ24 AM46 SA_DQ55 SA_DQSP6 AL49 DDRB_DQS3 DDRB_DQ55 AK22 SB_DQ54 SB_DQSP5 AM21 DDRB_DQS6
DDRB_DQ25 AK46 SA_DQ56 SA_DQSP7 DDRB_DQ56 AN20 SB_DQ55 SB_DQSP6 AM18 DDRB_DQS7
DDRB_DQ26 AM49 SA_DQ57 AP49 DDRB_DQ57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA DDR_SM_VREFCA 14 SB_DQ57

o
DDRB_DQ27 AK49 AR51 DDRB_DQ58 AK18
DDRB_DQ28 AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_SA_VREFDQ 14 DDRB_DQ59 AL18 SB_DQ58
DDRB_DQ29 AK48 SA_DQ60 SM_VREF_DQ1 DDR_SB_VREFDQ 15 DDRB_DQ60 AK20 SB_DQ59
DDRB_DQ30 AM51 SA_DQ61 DDRB_DQ61 AM20 SB_DQ60
SA_DQ62 SMVREF SB_DQ61
DDRB_DQ31 AK51 WIDTH:20MIL DDRB_DQ62 AR18
SA_DQ63 DDRB_DQ63 AP18 SB_DQ62
SPACING: 20MIL SB_DQ63

C
B B

DDRA_DQS#[0..7] DDRB_DQS#[0..7]
DDRA_DQS#[0..7] 14 DDRB_DQS#[0..7] 15
DDRA_DQS[0..7] DDRB_DQS[0..7]
DDRA_DQS[0..7] 14 DDRB_DQS[0..7] 15
3 OF 19
BROADWELL-ULT-DDR3L_BGA1168 BROADWELL-ULT-DDR3L_BGA1168
@ @

F C
L C
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (DDR3L)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 6 of 59
5 4 3 2 1
 5 4 3 2 1

RTC_X1

RC32 2 1 10M_0402_5% RTC_X2

1
CC3
YC1 VCCRTC 1U_0402_10V6K SATA0GP
1 2 SATA0GP 9
SATA2GP
2 SATA2GP 9
SATA3GP
1 2 20K_0402_1% SRTC_RST# SATA3GP 9
2 32.768KHZ_12.5PF_202740-PG14 2 RC33
RC34 1 2 20K_0402_1% RTC_RST#
RTC_RST# 44
CC4 CC5
15P_0402_50V8J 18P_0402_50V8J 1

1
1 1 CC6 JCMOS1
1U_0402_10V6K SHORT PADS
@

2
2
D D
CRYSTAL +3VALW _PCH
1, Space 15MIL
2, No trace under crystal SML0_CLK
3, Place on oppsosit side of MCP for temp influence RC35 1 2 2.2K_0402_5%

SML0_DATA RC36 1 2 2.2K_0402_5%

UC1E HSW_ULT_DDR3L

VCCRTC
RTC_X1 AW5
RTC_X2 AY5 RTCX1
RC39 2 1 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5 SATA_PRX_DTX_N0
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 42 SMB_ALERT#
RC41 2 1 330K_0402_5% INTVRMEN AV7 H5
SRTC_RST# INTVRMEN SATA_RP0/PERP6_L3 SATA_PTX_DRX_N0 SATA_PRX_DTX_P0 42 SML0_ALERT# SMB_ALERT# 9
AV6 RTC B15 HDD
RTC_RST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 42 SML1_ALERT# SML0_ALERT# 9
INTVRMEN RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 42 SML1_ALERT# 9
* H Integrated VRM enable (Default) SATA_PRX_DTX_N1
L Integrated VRM disable J8 SATA_PRX_DTX_N1 42
SATA_RN1/PERN6_L2 H8 SATA_PRX_DTX_P1
(INTVRMEN should always be pull high.) SATA_RP1/PERP6_L2 A17 SATA_PTX_DRX_N1 SATA_PRX_DTX_P1 42
SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 42
ODD
B17 SATA_PTX_DRX_P1
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 42
RC42 1 2 33_0402_5% HDA_BCLK AW8 J6
43 HDA_BITCLK_AUDIO HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
RC43 1 2 33_0402_5% AV11 H6
43 HDA_SYNC_AUDIO HDA_RST# HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
RC44 1 2 33_0402_5% AU8 B14
43 HDA_RST_AUDIO# HDA_SDIN0 AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15
43 HDA_SDIN0 AU12 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
+3VALW _PCH RC45 1 2 33_0402_5% HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
43 HDA_SDOUT_AUDIO HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
RC46 1 2 0_0402_5% AW10 E5
44 ME_FLASH AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
@
RC47 1 @ 2 1K_0402_5% HDA_SDOUT AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
I2S1_SCLK SATA_TP3/PETP6_L0

HDA_SDO This signal has a weak internal pull-down. V1 SATA0GP

SATA0GP/GPIO34 U1 ODD_DETECT#
* 0 = Enable security measures defined in the Flash Descriptor. SATA1GP/GPIO35 ODD_DETECT# 9,42
V6 SATA2GP IREF&RCOMP
1 = Disable Flash Descriptor Security(override). This strap SATA2GP/GPIO36 AC1 SATA3GP +1.05VS_PSATA3PLL Width: 12-15Mil
should only be asserted high during external pull-up in TC24 @ 1 PCH_JTAG_TRST# AU62 SATA3GP/GPIO37
manufacturing/debug environments ONLY. PCH_JTAG_TCK PCH_TRST Space:12Mil
C TC25 @ 1 AE62 A12 C
TC26 @ 1 PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
Length: 500Mil
TC28 @ 1 PCH_JTAG_TDO AE61 PCH_TDI RSVD3 K10
TC30 @ 1 PCH_JTAG_TMS AD62 PCH_TDO RSVD4 C12 SATA_RCOMP RC48 2 1 3.01K_0402_1%
For EMI PCH_TMS
JTAG
SATA_RCOMP
HDA_SDIN0 AL11 U3
AC4 RSVD1 SATALED
AE63 RSVD2
AV2 JTAGX
1 RSVD0
CC7
10P_0402_50V8J
2 EMC_NS@
5 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@

UC1G HSW_ULT_DDR3L

AU14 AN2 SMB_ALERT#

32,44 LPC_AD0 AW12 LAD0 SMBALERT/GPIO11 AP2 PCH_SMB_CLK
32,44 LPC_AD1 AY12 LAD1 SMBCLK AH1 PCH_SMB_DATA
LPC
32,44 LPC_AD2 AW11 LAD2 SMBUS SMBDATA AL2 SML0_ALERT#
32,44 LPC_AD3 AV12 LAD3 SML0ALERT/GPIO60 AN1 SML0_CLK
32,44 LPC_FRAME# LFRAME SML0CLK AK1 SML0_DATA
SML0DATA AU4 SML1_ALERT#
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_SML1_CLK
SML1CLK/GPIO75 AH3 PCH_SML1_DAT
SPI_CLK SPI_CLK_R SML1DATA/GPIO74 DIMM1, DIMM2, NGFF
RC50 1 2 15_0402_5% AA3
44 SPI_CLK SPI_CS0# SPI_CS0#_R SPI_CLK
RC51 1 2 0_0402_5% Y7 AF2
44 SPI_CS0# Y4 SPI_CS0 CL_CLK AD2
@ +3VALW _PCH +3VS +3VS
AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R AA2 SPI_CS2 CL_RST
44 SPI_SI SPI_SO SPI_SO_R SPI_MOSI
RC53 1 2 15_0402_5% AA4
44 SPI_SO Y6 SPI_MISO
SPI_IO2

3
4

4
3
AF1
B SPI_IO3 RPC20 RPC24
B

2
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
7 OF 19

2
1

1
2
BROADWELL-ULT-DDR3L_BGA1168 PCH_SMB_CLK QC2A 6 1

S
@ SMB_CLK_S3 15,40

D
2N7002KDW H_SOT363-6

5
G
+3V_SPI PCH_SMB_DATA QC2B 3 4

S
SMB_DATA_S3 15,40

D
+3V_SPI 2N7002KDW H_SOT363-6

UC3
1

SPI_CS0# 1 8
RC60 RC61 CS# VCC
1K_0402_5% 1K_0402_5% SPI_SO 2 7 SPI_HOLD#
DO HOLD# 1
CC8 GPU, EC, Thermal Sensor
SPI_W P# 3 6 SPI_CLK .1U_0402_10V6-K
2

WP# CLK
SPI_W P# 4 5 SPI_SI 2 +3VALW _PCH +3VS
GND DI

SPI_HOLD# W 25Q64FVSSIQ_SO8

4
3
RPC25

2
2.2K_0404_4P2R_5%

G
1
2
PCH_SML1_CLK QC3A 6 1 @

S
EC_SMB_CK2 19,44

D
2N7002KDW H_SOT363-6

5
A A

G
+3VALW _PCH +3V_SPI

RC1711 @ 2 PCH_SML1_DAT QC3B 3 4 @

S
EC_SMB_DA2 19,44

D
0_0402_5%
2N7002KDW H_SOT363-6

Security Classification LC Future Center Secret Data Title

+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code; Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (RTC&AUDIO&SATA&SMBUS)
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 7 of 59
3 2 1
 5 4 3 2 1

RC71 2 1 1M_0402_5%

YC2
PCIE_CLKREQ1#
9 PCIE_CLKREQ1# PCIE_CLKREQ0# XTAL24_OUT
2 3
9 PCIE_CLKREQ0# PCIE_CLKREQ5# GND1 OSC2
9 PCIE_CLKREQ5# XTAL24_IN 1 4
OSC1 GND2
1
1 24MHZ_6PF_7V24000032
CC12 CC11
D D
4.7P_0402_50V8B 3.3P_0402_50V8-C
2
SYS_RESET# 2
9 SYS_RESET# PM_CLKRUN# UC1F HSW_ULT_DDR3L
9 PM_CLKRUN#

C43 A25 XTAL24_IN

C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCIE_CLKREQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKRQ0/GPIO18 K21 +1.05VS_PLPTCLKPLL
RSVD5
DIFFCLK_BIASREF
B41 M21 Width: 12-15Mil
A41 CLKOUT_PCIE_N1 RSVD6 C26 DIFFCLK_BIASREF 2 1
PCIE_CLKREQ1# CLKOUT_PCIE_P1 DIFFCLK_BIASREF Space:12Mil
Y5 RC72 3.01K_0402_1%
PCIECLKRQ1/GPIO19 C35 MCP_TESTLOW1 Length: 500Mil
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2
37 CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N2 TESTLOW_C34 MCP_TESTLOW3
PCIE CLK2 LAN B42 AK8
37 CLK_PCIE_LAN LAN_CLKREQ# CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 MCP_TESTLOW4
AD1 AL8
9,37 LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CLK_PCIE_WLAN# B38 AN15 CLK_PCI_EC_R RC73 2 1 22_0402_5% RPC5
40 CLK_PCIE_WLAN# CLK_PCIE_WLAN C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI_TPM_R 2 1 22_0402_5% CLK_PCI_EC 44 MCP_TESTLOW1 8 1
PCIE CLK3 WLAN 40 RC183
CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM 32 MCP_TESTLOW2
N1 TPM@ 7 2
9,40 WLAN_CLKREQ# PCIECLKRQ3/GPIO21 MCP_TESTLOW3
B35 6 3
CLK_PCIE_GPU# A39 CLKOUT_ITPXDP A35 MCP_TESTLOW4 5 4
19 CLK_PCIE_GPU# CLK_PCIE_GPU CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
PCIE CLK4 GPU B39
19 CLK_PCIE_GPU GPU_CLKREQ# U5 CLKOUT_PCIE_P4 10K_0804_8P4R_5%
19 GPU_CLKREQ# PCIECLKRQ4/GPIO22
+3VS B37
C A37 CLKOUT_PCIE_N5 C
PCIE_CLKREQ5# T2 CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
RC120 1 2 10K_0402_5% GPU_CLKREQ#
6 OF 19
BROADWELL-ULT-DDR3L_BGA1168 VCCRTC
@

1
+3VALW_PCH RC77
330K_0402_5%

2
RC74 1 2 10K_0402_5% AC_PRESENT_R
DSWODVREN
RC76 1 2 10K_0402_5% WAKE#

1
RC78 1 2 10K_0402_5% SUSWARN#_R
RC80
RC90 1 2 10K_0402_5% PCH_GPIO72 330K_0402_5%
UC1H HSW_ULT_DDR3L @

2
Reserve for DS3 SYSTEM POWER MANAGEMENT

SUSWARN#_R RC79 1 @ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN

SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_DPWROK_R RC182 1 @ 2 0_0402_5% EC_RSMRST#
SYS_RESET DPWROK DSWODVREN - On Die DSW VR Enable
RC139 1 @ 2 0_0402_5% SYS_PWROK_R AG2 AJ5 WAKE# RC82 1 @ 2 0_0402_5%
44
10,44
SYS_PWROK
PCH_PWROK
RC126 1 @ 2 0_0402_5% PCH_PWROK_R AY7 SYS_PWROK
PCH_PWROK
WAKE PCIE_WAKE# 44 * H Enable
L Disable
RC83 1 @ 2 0_0402_5% APWROK AB5
RC84 1 @ 2 0_0402_5% PLT_RST#_R AG7 APWROK V5 PM_CLKRUN#
B 19,32,37,40,44 PLT_RST# PLTRST CLKRUN/GPIO32 B
AG4
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 AP5 PM_SLP_S5#
PCH_RSMRST#_R SLP_S5/GPIO63 PM_SLP_S5# 44
RC85 1 @ 2 0_0402_5% AW6
44 EC_RSMRST# SUSWARN#_R RSMRST
AV4
RC87 1 @ 2 0_0402_5% PBTN_OUT#_R AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6 PM_SLP_S4#_R RC140 1 @ 2 0_0402_5%
44 PBTN_OUT# AC_PRESENT_R PWRBTN SLP_S4 PM_SLP_S3#_R PM_SLP_S4# 44
AJ8 AT4 RC141 1 @ 2 0_0402_5%
PCH_GPIO72 AN4 ACPRESENT/GPIO31 SLP_S3 AL5 PM_SLP_S3# 44
AF3 BATLOW/GPIO72 SLP_A AP4
AM5 SLP_S0 SLP_SUS AJ7
SLP_WLAN/GPIO29 SLP_LAN

CC104 1 2 PCH_PWROK
EMC_NS@ 1000P_0402_50V7K
8 OF 19
BROADWELL-ULT-DDR3L_BGA1168
CC103 1 2 PCH_DPWROK_R @
EMC_NS@ 1000P_0402_50V7K

CC101 1 2 1000P_0402_50V7K
EMC@
RC91 1 2 10K_0402_5% SYS_PWROK RC88 1 @ 2 0_0402_5% AC_PRESENT_R
44 AC_PRESENT

RPC21
1 4 PCH_PWROK
2 3 PCH_RSMRST#_R

A 10K_0404_4P2R_5% A
CC142 1 2
EMC_NS@ 1000P_0402_50V7K

100K_0402_5% 2 1 RC92 PLT_RST#_R

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R Title

Security Classification LC Future Center Secret Data
1K_0402_5% 1 @ 2 RC95 SUSCLK
Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (Clock,PM)
10K_0402_5% 2 @ 1 RC105 GPU_CLKREQ#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Monday, May 11, 2015 Sheet 8 of 59
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH +3VS
H_THRMTRIP#_R
RC97 1 @ 2 10K_0402_5% PCH_GPIO12
DS3_WAKE# PCH_GPIO14

.01U_0402_16V7-K
RC98 1 2 10K_0402_5% 44 EC_LID_OUT# RC96 1 @ 2
PCH_GPIO25

CC102
RC99 1 2 10K_0402_5% 0_0402_5%

2
1
+3VALW_PCH RC100 RC101 RC102 RC121 RC184
RPC6 +1.05V_VCCST 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
8 1 PCH_GPIO13 OPT@ 15@ @ @ @
7 2 PCH_GPIO57 @ 2

1
2
6 3 PCH_GPIO26 BOARD_ID0
5 4 PCH_GPIO9 UC1J HSW_ULT_DDR3L RC104 BOARD_ID1
1K_0402_5% BOARD_ID2
10K_0804_8P4R_5% BOARD_ID3
4 BOARD_ID3 BOARD_ID4

1
RPC7

2
8 1 PCH_GPIO45 PCH_GPIO76 P1 D60 H_THRMTRIP#_R
7 2 PCH_GPIO46 PCH_GPIO8 AU2 BMBUSY/GPIO76 THRMTRIP V4 KBRST# RC107 RC108 RC109 RC123 RC185
D GPIO8 RCIN/GPIO82 KBRST# 44 D
6 3 USB_OC2# PCH_GPIO12 AM7 T4 SERIRQ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
PCH_GPIO14 LAN_PHY_PWR_CTRL/GPIO12 SERIRQ OPI_COMP SERIRQ 32,44
5 4 AD6 CPU/ AW15 RC106 2 149.9_0402_1% UMA@ 14@ @ @ @
BOARD_ID0 Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 1 @

1
10K_0804_8P4R_5% ODD_DA# T3 GPIO16 RSVD7 AB21 TC41
GPIO17 RSVD8
OPI_RCOMP
ODD_EN AD5 Width 20Mil
RPC8 DS3_WAKE# AN5 GPIO24
8 1 PCH_GPIO47 PCH_GPIO28 AD7 GPIO27 Space 15Mil
7 2 PCH_GPIO28 PCH_GPIO26 AN3 GPIO28 Length 500Mil
6 3 ODD_EN GPIO26 R6 PCH_GPIO83
5 4 PCH_GPIO56 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 BOARD_ID1
PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
10K_0804_8P4R_5% PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86 BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 Description
PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_BT_OFF#
PCH_GPIO44 GPIO59 GSPI1_CS/GPIO87 PCH_WLAN_OFF# PCH_BT_OFF# 40
RPC9 AK4 GPIO L5
PCH_GPIO10 PCH_GPIO47 GPIO44 GSPI1_CLK/GPIO88 PCH_GPIO89 PCH_WLAN_OFF# 40
8 1 AB6 N7 1 X X X X DIS SKU
7 2 SML0_ALERT# VGA_PWRGD U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
USB_OC0# SML0_ALERT# 7 BOARD_ID4 GPIO48 GSPI_MOSI/GPIO90 PCH_GPIO91
6 3 Y3 J1
5 4 PCH_GPIO44 PCH_GPIO50 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92 0 X X X X UMA SKU
PCH_GPIO71 Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_GPIO93
10K_0804_8P4R_5% PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_GPIO94
PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0 X 1 X X X 15" SKU
RPC17 @ PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
1 8 PCH_GPIO8 EC_SMI# RC111 1 2 PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
44 EC_SMI# GPIO45 UART1_RST/GPIO2
2 7 USB_OC3# PCH_GPIO46 AG3 J4 PCH_GPIO3 X 0 X X X 14" SKU
3 6 USB_OC1# 0_0402_5% GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
4 5 SMB_ALERT# PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5
SMB_ALERT# 7 PCH_GPIO10 GPIO9 I2C0_SCL/GPIO5 PCH_GPIO6
AM2 G4 X X 0 0 0 MS2G@: K4B4G1646Q-HYK0
10K_0804_8P4R_5% PCH_GPIO33 P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_GPIO7 RC112 1 2 0_0402_5%
PCH_GPIO70 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 PCH_GPIO64 EC_SCI# 44
C4 E3 @
RPC22 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65 X X 0 0 1 MH2G@: H5TC4G63CFR-PBA
8 1 PCH_GPIO58 BOARD_ID2 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3
7 2 PCH_GPIO59 PCH_BEEP V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
SML1_ALERT# 43 PCH_BEEP SPKR/GPIO81 SDIO_D1/GPIO67 CMOS_ON#
6 3 C3 X X 0 1 0 MM2G@: MT41K256M16LY-107:N
SML1_ALERT# 7 SDIO_D2/GPIO68 PCH_GPIO69
5 4 E2
SDIO_D3/GPIO69
+3VS 10K_0804_8P4R_5% 10 OF 19 X X 0 1 1 MS4G@: K4B8G1646Q-MYK0
BROADW ELL-ULT-DDR3L_BGA1168
C RPC2 @ C
8 1 SERIRQ X X 1 0 0 MH4G@: H5TC8G63AMR-PBA
7 2 PCIE_CLKREQ0#
PCIE_CLKREQ0# 8
6 3 SATA0GP
ODD_DETECT# SATA0GP 7
5 4 19 PCIE_CRX_GTX_N[0..3] X X 1 0 1 MM4G@: MT41K512M16HA-125:A
ODD_DETECT# 7,42
10K_0804_8P4R_5% 19 PCIE_CRX_GTX_P[0..3]
RPC3
PCH_GPIO83 19 PCIE_CTX_C_GRX_N[0..3]
1 8
2 7 PCH_GPIO92
PCH_GPIO85 19 PCIE_CTX_C_GRX_P[0..3]
3 6
4 5
UC1K HSW_ULT_DDR3L
10K_0804_8P4R_5%

RPC4 PCIE_CRX_GTX_N0 F10 AN8 USB20_N0

PCH_GPIO38 PCIE_CRX_GTX_P0 PERN5_L0 USB2N0 USB20_P0 USB20_N0 41
1 8 E10 AM8
2 7 PCH_BT_OFF# PERP5_L0 USB2P0 USB20_P0 41 LEFT USB (2.0)
3 6 WLAN_CLKREQ# PCIE_CTX_C_GRX_N0 .1U_0402_10V6-K OPT@ 1 2 CC16 PCIE_CTX_GRX_N0 C23 AR7 USB20_N1
PCH_GPIO33 WLAN_CLKREQ# 8,40 PCIE_CTX_C_GRX_P0 PCIE_CTX_GRX_P0 PETN5_L0 USB2N1 USB20_P1 USB20_N1 41
4 5 .1U_0402_10V6-K OPT@ 1 2 CC14 C22 AT7
PETP5_L0 USB2P1 USB20_P1 41 LEFT USB (3.0)
10K_0804_8P4R_5% PCIE_CRX_GTX_N1 F8 AR8
PCIE_CRX_GTX_P1 E8 PERN5_L1 USB2N2 AP8
GPU PCIE5 PERP5_L1 USB2P2
RPC10
8 1 LAN_CLKREQ# PCIE_CTX_C_GRX_N1 .1U_0402_10V6-K OPT@ 1 2 CC15 PCIE_CTX_GRX_N1 B23 AR10 USB20_N3
SYS_RESET# LAN_CLKREQ# 8,37 PCIE_CTX_C_GRX_P1 PCIE_CTX_GRX_P1 PETN5_L1 USB2N3 USB20_P3 USB20_N3 30
7 2 .1U_0402_10V6-K OPT@ 1 2 CC17 A23 AT10
6 3 SATA3GP
SYS_RESET# 8 PETP5_L1 USB2P3 USB20_P3 30 Card reader
PCH_GPIO71 SATA3GP 7 PCIE_CRX_GTX_N2
5 4 H10 AM15
PCIE_CRX_GTX_P2 G10 PERN5_L2 USB2N4 AL15
10K_0804_8P4R_5% PERP5_L2 USB2P4
PCIE_CTX_C_GRX_N2 .1U_0402_10V6-K OPT@ 1 2 CC18 PCIE_CTX_GRX_N2 B21 AM13 USB20_N5
PCIE_CTX_C_GRX_P2 PCIE_CTX_GRX_P2 PETN5_L2 USB2N5 USB20_P5 USB20_N5 33
RPC11 .1U_0402_10V6-K OPT@ 1 2 CC19 C21 AN13
8 1 ODD_DA# PETP5_L2 USB2P5 USB20_P5 33 Camera
7 2 PCIE_CLKREQ5# PCIE_CRX_GTX_N3 E6 AP11 USB20_N6
PCH_GPIO50 PCIE_CLKREQ5# 8 PCIE_CRX_GTX_P3 PERN5_L3 USB2N6 USB20_P6 USB20_N6 40
6 3 F6 AN11
5 4 PCH_GPIO76 PERP5_L3 USB2P6 USB20_P6 40 BT
PCIE_CTX_C_GRX_N3 .1U_0402_10V6-K OPT@ 1 2 CC20 PCIE_CTX_GRX_N3 B22 AR13
B
10K_0804_8P4R_5% PCIE_CTX_C_GRX_P3 .1U_0402_10V6-K OPT@ 1 2 CC21 PCIE_CTX_GRX_P3 A21 PETN5_L3 USB2N7 AP13 B
PETP5_L3 USB2P7
RPC12 PCIE_PRX_DTX_N3 G11
PCH_GPIO90 37 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PERN3 USB30_RX_N1
8 1 37 PCIE_PRX_DTX_P3 F11 G20
PCH_GPIO2 PERP3 USB3RN1 USB30_RX_P1 USB30_RX_N1 41
7 2 LAN PCIE3 H20
PCH_GPIO93 PCIE_PTX_DRX_N3 USB3RP1 USB30_RX_P1 41 PCH_GPIO86
6 3 CC22 1 2 .1U_0402_10V6-K C29 RC116 2 @ 1 1K_0402_5%
5 4 PCH_GPIO91 37 PCIE_PTX_C_DRX_N3
CC23 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33 USB30_TX_N1 LEFT USB (3.0)
37 PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB30_TX_P1 USB30_TX_N1 41
B34
PCIE_PRX_DTX_N4 USB3TP1 USB30_TX_P1 41
10K_0804_8P4R_5% 40 PCIE_PRX_DTX_N4 F13 GPIO86, Internal PD
PCIE_PRX_DTX_P4 G13 PERN4 E18
40 PCIE_PRX_DTX_P4 PERP4 USB3RN2 1: LPC
RPC13 WLAN PCIE4 F18 *0: SPI
8 1 PCH_GPIO3 CC24 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N4 B29 USB3RP2
PCH_GPIO1 40 PCIE_PTX_C_DRX_N4 PCIE_PTX_DRX_P4 PETN4
7 2 CC25 1 2 .1U_0402_10V6-K A29 B33
PCH_GPIO94 40 PCIE_PTX_C_DRX_P4 PETP4 USB3TN2
6 3 A33
5 4 PCH_GPIO4 G17 USB3TP2
F17 PERN1/USB3RN3
10K_0804_8P4R_5% PERP1/USB3RP3 +3VS
C30
RPC14 C31 PETN1/USB3TN3 AJ10 USBRBIAS RC118 2 1
8 1 PCH_GPIO5 PETP1/USB3TP3 USBRBIAS AJ11 22.6_0402_1% PCH_BEEP RC117 2 @ 1 1K_0402_5%
USBRBIAS USBRBIAS
7 2 PCH_GPIO69 F15 AN10 Width 20Mil
6 3 CMOS_ON# G15 PERN2/USB3RN4 RSVD11 AM10
5 4 PCH_GPIO70 PERP2/USB3RP4 RSVD12 Space 15Mil
Length 500Mil GPIO81, No Reboot, Internal PD
B31 1: Enabled No Reboot Mode
10K_0804_8P4R_5% A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0# *0: Disable No Reboot Mode
RPC15 OC0/GPIO40 AT1 USB_OC1#
PCH_GPIO7 OC1/GPIO41 USB_OC2# USB_OC1# 41
8 1 AH2
7 2 PCH_GPIO65 +1.05VS_PUSB3PLL E15 OC2/GPIO42 AV3 USB_OC3#
6 3 PCH_GPIO0 E13 RSVD9 OC3/GPIO43
5 4 PCH_GPIO89 RC119 2 1 3.01K_0402_1% PCIE_RCOMP A27 RSVD10
B27 PCIE_RCOMP
10K_0804_8P4R_5% PCIE_IREF
PCIE_RCOMP&PCIE_IREF
RPC16 Width 12~15Mil
8 1 PCH_GPIO67 11 OF 19
7 2 PCH_GPIO64
Space >12Mil BROADW ELL-ULT-DDR3L_BGA1168
A 6 3 PCH_GPIO6 Length 500Mil @ A
5 4 PCH_WLAN_OFF#

10K_0804_8P4R_5%

RPC18
1 8 PCIE_CLKREQ1#
PCIE_CLKREQ1# 8
2 7 KBRST#
3 6 SATA2GP
PM_CLKRUN# SATA2GP 7
4 5
PM_CLKRUN# 8
Security Classification LC Future Center Secret Data Title
10K_0804_8P4R_5%
Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (GPIO,USB,PCIE)
RC181 1 2 10K_0402_5% VGA_PWRGD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 9 of 59
5 4 3 2 1
 5 4 3 2 1

CPU_CORE +1.35V_CPU
UC1L HSW_ULT_DDR3L

+1.35V Need short +1.35V_CPU L59 C36

RSVD13 VCC8

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K
J58 C40
JC1 @ RSVD14 VCC9 C44
VCC10 1 1 1 1

CC26

CC27

CC28

CC29
1 2 AH26 C48
1 2 AJ31 VDDQ1 VCC11 C52
AJ33 VDDQ2 VCC12 C56
JUMP_43X79 AJ37 VDDQ3 VCC13 E23 2 2 2 2
AN33 VDDQ4 VCC14 E25
AP43 VDDQ5 VCC15 E27 CD@
AR48 VDDQ6 VCC16 E29 BCD@
D
AY35 VDDQ7 VCC17 E31 D

AY40 VDDQ8 VCC18 E33

CPU_CORE
VDDQ9 VCC19
For cost down, change to X5R.
AY44 E35
CPU_CORE AY50 VDDQ10 VCC20 E37
VDDQ11 VCC21

2
VCC_SENSE E39
F59 VCC22 E41
Length Match: <25Mil RC127
VCC1 VCC23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
Space: More Than 25Mil 100_0402_1% N58 E43
RSVD15 VCC24

330U_2.5V_M
AC58 E45 1 1 1 1 1 1 1
GND Reference RSVD16 VCC25

CC34

CC30

CC35

CC31

CC32

CC33
E47

1
VCC26

CC41
+VCCIO_OUT RC128 1 @ 2 E63 E49 +
59 CPU_VCC_SENSE AB23 VCC_SENSE VCC27 E51
0_0402_5%
A59 RSVD17 VCC28 E53 2 2 2 @2 2 2
E20 VCCIO_OUT VCC29 E55 2
+VCCIOA_OUT VCCIOA_OUT VCC30
1 AD23 E57 @
CC36 AA23 RSVD18 VCC31 F24 CD@ BCD@
4.7U_0603_10V6-K AE59 RSVD19 VCC32 F28
@ RSVD20 VCC33 F32
2 CPU_SVID_ALERT#_R L62 VCC34 F36
CPU_SVID_CLK_R VIDALERT VCC35 1.35V_CPU(1.4A)
N63 HSW ULT POWER F40
CPU_SVID_DAT_R L63 VIDSCLK VCC36 F44
VIDSOUT VCC37
HW 4PCS 2.2UF CAP Mounted
VCCST_PW RGD B59 F48
CPU_VR_ON VCCST_PWRGD VCC38 HW 6PCS 10UF CAP Mounted
F60 F52
59 CPU_VR_ON CPU_VR_READY C59 VR_EN VCC39 F56
PWR 2PCS 470U Near VR Output
+1.05VS VR_READY VCC40 G23
D63 VCC41 G25
RC129 2 @ 1 150_0402_1% PW R_DEBUG H59 VSS344 VCC42 G27
P62 PWR_DEBUG VCC43 G29
@ TC53 1 P60 VSS345 VCC44 G31 +1.35V_CPU
@ TC54 1 P61 RSVD_TP1 VCC45 G33
@ TC55 1 N59 RSVD_TP2 VCC46 G35
RSVD_TP3 VCC47

CC37

CC38
RC130 2 1 N61 G37
10K_0402_5% T59 RSVD_TP4 VCC48 G39
RSVD21 VCC49

33P_0402_50V8J

33P_0402_50V8J
AD60 G41
AD59 RSVD22 VCC50 G43
RSVD23 VCC51 1 1
AA59 G45
AE60 RSVD24 VCC52 G47
AC59 RSVD25 VCC53 G49
C AG58 RSVD26 VCC54 G51 2 2 C
RSVD27 VCC55

@
U59 G53
+1.05VS +1.05V_VCCST V59 RSVD28 VCC56 G55
RSVD29 VCC57 G57
VCCST(0.1A) VCC58
LC1 1 @ 2 AC22 H23
0_0402_5% AE22 VCCST1 VCC59 J23
CPU_CORE AE23 VCCST2 VCC60 K23
1 1 VCCST3 VCC61 K57
CC39 CC40 AB57 VCC62 L22
VCC2 VCC63 For RF
22U_0805_6.3V6M 1U_0402_10V6K AD57 M23
2 2 VCC3 VCC64
CC2
BCD@ BCD@ 33P_0402_50V8J AG57 M57
C24 VCC4 VCC65 P57
1 VCC5 VCC66
C28 U57
C32 VCC6 VCC67 W57
VCC7 VCC68
2 12 OF 19
@

BROADWELL-ULT-DDR3L_BGA1168
SVID
1, Stripline Line, No More Than 6000Mil @
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil For RF
+1.05VS
2

CC42
RC131 RC132 .1U_0402_10V6-K
75_0402_1% 130_0402_1% @
2
1

RC133 2 1 43_0402_5% CPU_SVID_ALERT#_R

59 CPU_SVID_ALERT#

RC134 1 @ 2 0_0402_5% CPU_SVID_CLK_R

59 CPU_SVID_CLK

B CPU_SVID_DAT_R B
RC135 1 @ 2 0_0402_5%
59 CPU_SVID_DAT
CPU_VR_ON

2
+1.05V_VCCST
RC146
10K_0402_5%
2

+3VALW RC137

1
1K_0402_5%
2

RC155 1 2 0_0402_5% CPU_VR_READY

44,59 VR_CPU_PW ROK
1

RC136 VCCST_PW RGD

VCCST_PW RGD 8,44
10K_0402_5%
@
3

D 1
1

5 QC6B 2 CC141
G 2N7002KDW H_SOT363-6 CC140 100P_0402_50V8J
@ 1000P_0402_50V7K @
6

D S @ 2
4

RC138 2 @ 1 2 QC6A 1
8,44 PCH_PW ROK G 2N7002KDW H_SOT363-6
0_0402_5% 1 @
CC46 S
1

0.01U_0402_16V7K
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (Power)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 10 of 59
2 1
 5 4 3 2 1

+3VALW _PCH

HSW_ULT_DDR3L 2
+1.05VS UC1M CC50
VCCHSIO 1.838A 1U_0402_10V6K
K9
L10 VCCHSIO[1] 1
VCCHSIO[2]

1U_0402_10V6K

1U_0402_10V6K
+1.05VS VCC1_05[1:9] 1.741A M9 VCCRTC
N8 VCCHSIO[3] HSIO RTC AH11
1 1 VCC1_05[1] VCCSUS3_3[5] VCCRTC 1mA

CC53

CC51

1U_0402_10V6K
P9 AG10
VCC1_05[2] VCCRTC

CC55

CC56

CC57
1 +1.05VS_PUSB3PLL
B18 AE7 +DCPRTC CC52 2 1
VCCUSB3PLL DCPRTC

CC54

0.1U_0402_10V7K

0.1U_0402_10V7K
B11
D 2 2 +1.05VS_PSATA3PLL VCCSATA3PLL D

1U_0402_10V6K
VCCSPI 0.1U_0402_10V7K
2
VCCSPI 18mA 2 2 2

0.1U_0402_10V7K
+1.05VS_POPIPLL Y20 SPI Y8
BCD@ AA21 RSVD30 OPI
VCCSPI
VCCAPLL[1] 2

CC58 @
W21 +1.05VS
VCCAPLL[2] AG14 1 1 1
VCCASW[1] AG13
VCCASW[2] 1 +1.05VS
VCCASW[1:5] 658mA
@ 1U_0402_10V6K 1 2 CC59 +1.05VS_DCPSUS3 J13 USB3
VCCHDA DCPSUS3 J11 CD@
VCC1_05[3]

CC63

CC64

CC65
VCCHDA 11mA H11
AH14 HDA VCC1_05[4] H15
VCCHDA VCC1_05[5]

1U_0402_10V6K

1U_0402_10V6K

10U_0603_6.3V6M
AE8
VCC1_05[6]
1U_0402_10V6K

AF22 1U_0402_10V6K 2 2 2
@ 1U_0402_10V6K 1 2 CC60 +1.05VS_DCPSUS2 AH13 VRM VCC1_05[7] AG19 +PCH_DCPSUSBYP CC61 2 1 +1.05VS
1 DCPSUS2 DCPSUSBYP[1]
CC62

CORE AG20
+3VALW _PCH DCPSUSBYP[2] AE9
VCCASW[3] 1 1 1

CC68

CC69
VCCSUS3_3[1:5] 65mA AF9
2 AC9 VCCASW[4] AG8
VCCSUS3_3[1] VCCASW[5] +1.05VS_DCPSUS1
22U_0805_6.3V6M

1U_0402_10V6K

22U_0805_6.3V6M
VCCDSW 114mA AA9 GPIO/LPC AD10 CC66 2 1 @
AH10 VCCSUS3_3[2] DCPSUS1[1] AD8
1 VCCDSW 3_3 VCCDSW3_3 DCPSUS1[2] 2 1
CC67

1U_0402_10V6K

+3VS
V8 +1.5VS 1U_0402_10V6K
W9 VCC3_3[1]
1 VCC3_3[1:4] 41mA VCC3_3[2] VCCTS1_5 3mA
CC70 @

22U_0805_6.3V6M J15 +3VS

2 THERMAL SENSOR VCCTS1_5 K14 1 2
1 VCC3_3[3]
CC71

@
K16 @
2 VCC3_3[4]

0.1U_0402_10V7K
+1.05VS_PLPTVCC1P05
+3VS 2
2

CC72
+1.05VS_PLPTCLKPLL J18 VCCSDIO 17mA
+1.05VS K19 VCCCLK[1] SERIAL IO U8
VCCCLK[2] VCCSDIO[1]

1U_0402_10V6K
A20 T9
J17 VCCACLKPLL VCCSDIO[2] 1
VCCCLK[3] 2

CC74
R21
VCCCLK[4]
1U_0402_10V6K

1U_0402_10V6K

T21 LPT LP POWER 1U_0402_10V6K

K18 VCCCLK[5] SUS OSCILLATOR AB8 +1.05VS_DCPSUS4 CC73 2 1 @
1 1 RSVD31 DCPSUS4 1
CC75

CC76

M20
V21 RSVD32 +1.05VS
C AE20 RSVD33 AC20 BCD@ C
2 2 AE21 VCCSUS3_3[3] RSVD34 AG16
+3VALW _PCH VCCSUS3_3[4] VCC1_05[8]
USB2 AG17
VCC1_05[9]

1U_0402_10V6K
CD@ 2

CC77
+3VALW _PCH 13 OF 19
BROADWELL-ULT-DDR3L_BGA1168 1
RC150 2 @ 1 VCCDSW 3_3 @
0_0402_5%

+1.05VS
+1.05VS_PUSB3PLL +1.05VS +1.05VS_PLPTVCC1P05
+3VS
+1.05VS_PUSB3PLL 41mA +1.05VS_PLPTVCC1P05 185mA
RC152 2 @ 1 VCCHDA 1 2 1 2
0_0402_5% LC2 0_0603_5% LC3 0_0603_5%
1 1 1 1 1 1 1 1
CC78 CC79 CC80
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC81 CC100 CC82 CC83 CC84
@ 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 BCD@ 2 2 BCD@ 2 2

+3V_SPI

0_0402_5% 2 @ 1 RC154 VCCSPI

+1.05VS_PSATA3PLL +1.05VS_PLPTCLKPLL 31mA +1.05VS_PLPTCLKPLL
+1.05VS_PSATA3PLL 42mA
1 2 1 2
B B
LC4 0_0603_5% LC5 0_0603_5%

1 1 1 1 1 1 1 1
CC85 CC86 CC87
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC88 CC95 CC98 CC99 CC89
@ 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 2 BCD@ 2 BCD@ 2 2

VCCDSW 3_3 CC90 1 2 0.47U_0402_25V6K +PCH_DCPSUSBYP

For Intel recommend, place one 0.47uF +1.05VS_POPIPLL

capacitor to address temporary inrush +1.05VS_POPIPLL 57mA
LC6 1 @ 2 0_0603_5%
current.(DOC.489999)
1 1 1
1
CC91 CC92 CC93 CC94
33P_0402_50V8J 47U_0805_4V6-M 47U_0805_4V6-M 1U_0402_10V6K
@ 2@ 2@ 2
2

For RF

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 11 of 59
2 1
 5 4 3 2 1

UC1N HSW_ULT_DDR3L UC1O HSW_ULT_DDR3L

A11 AJ35 AP22 AV59

A14 VSS1 VSS65 AJ39 AP23 VSS129 VSS193 AV8
D A18 VSS2 VSS66 AJ41 AP26 VSS130 VSS194 AW16 D
A24 VSS3 VSS67 AJ43 AP29 VSS131 VSS195 AW24
A28 VSS4 VSS68 AJ45 AP3 VSS132 VSS196 AW33
A32 VSS5 VSS69 AJ47 AP31 VSS133 VSS197 AW35
A36 VSS6 VSS70 AJ50 AP38 VSS134 VSS198 AW37
A40 VSS7 VSS71 AJ52 AP39 VSS135 VSS199 AW4 UC1P HSW_ULT_DDR3L
A44 VSS8 VSS72 AJ54 AP48 VSS136 VSS200 AW40 H17
A48 VSS9 VSS73 AJ56 AP52 VSS137 VSS201 AW42 D33 VSS300 H57
A52 VSS10 VSS74 AJ58 AP54 VSS138 VSS202 AW44 D34 VSS257 VSS301 J10
A56 VSS11 VSS75 AJ60 AP57 VSS139 VSS203 AW47 D35 VSS258 VSS302 J22
AA1 VSS12 VSS76 AJ63 AR11 VSS140 VSS204 AW50 D37 VSS259 VSS303 J59
AA58 VSS13 VSS77 AK23 AR15 VSS141 VSS205 AW51 D38 VSS260 VSS304 J63
AB10 VSS14 VSS78 AK3 AR17 VSS142 VSS206 AW59 D39 VSS261 VSS305 K1
AB20 VSS15 VSS79 AK52 AR23 VSS143 VSS207 AW60 D41 VSS262 VSS306 K12
AB22 VSS16 VSS80 AL10 AR31 VSS144 VSS208 AY11 D42 VSS263 VSS307 L13
AB7 VSS17 VSS81 AL13 AR33 VSS145 VSS209 AY16 D43 VSS264 VSS308 L15
AC61 VSS18 VSS82 AL17 AR39 VSS146 VSS210 AY18 D45 VSS265 VSS309 L17
AD21 VSS19 VSS83 AL20 AR43 VSS147 VSS211 AY22 D46 VSS266 VSS310 L18
AD3 VSS20 VSS84 AL22 AR49 VSS148 VSS212 AY24 D47 VSS267 VSS311 L20
AD63 VSS21 VSS85 AL23 AR5 VSS149 VSS213 AY26 D49 VSS268 VSS312 L58
AE10 VSS22 VSS86 AL26 AR52 VSS150 VSS214 AY30 D5 VSS269 VSS313 L61
AE5 VSS23 VSS87 AL29 AT13 VSS151 VSS215 AY33 D50 VSS270 VSS314 L7
AE58 VSS24 VSS88 AL31 AT35 VSS152 VSS216 AY4 D51 VSS271 VSS315 M22
AF11 VSS25 VSS89 AL33 AT37 VSS153 VSS217 AY51 D53 VSS272 VSS316 N10
AF12 VSS26 VSS90 AL36 AT40 VSS154 VSS218 AY53 D54 VSS273 VSS317 N3
C
AF14 VSS27 VSS91 AL39 AT42 VSS155 VSS219 AY57 D55 VSS274 VSS318 P59
C

AF15 VSS28 VSS92 AL40 AT43 VSS156 VSS220 AY59 D57 VSS275 VSS319 P63
AF17 VSS29 VSS93 AL45 AT46 VSS157 VSS221 AY6 D59 VSS276 VSS320 R10
AF18 VSS30 VSS94 AL46 AT49 VSS158 VSS222 B20 D62 VSS277 VSS321 R22
AG1 VSS31 VSS95 AL51 AT61 VSS159 VSS223 B24 D8 VSS278 VSS322 R8
AG11 VSS32 VSS96 AL52 AT62 VSS160 VSS224 B26 E11 VSS279 VSS323 T1
AG21 VSS33 VSS97 AL54 AT63 VSS161 VSS225 B28 E17 VSS280 VSS324 T58
AG23 VSS34 VSS98 AL57 AU1 VSS162 VSS226 B32 F20 VSS281 VSS325 U20
AG60 VSS35 VSS99 AL60 AU16 VSS163 VSS227 B36 F26 VSS282 VSS326 U22
AG61 VSS36 VSS100 AL61 AU18 VSS164 VSS228 B4 F30 VSS283 VSS327 U61
AG62 VSS37 VSS101 AM1 AU20 VSS165 VSS229 B40 F34 VSS284 VSS328 U9
AG63 VSS38 VSS102 AM17 AU22 VSS166 VSS230 B44 F38 VSS285 VSS329 V10
AH17 VSS39 VSS103 AM23 AU24 VSS167 VSS231 B48 F42 VSS286 VSS330 V3
AH19 VSS40 VSS104 AM31 AU26 VSS168 VSS232 B52 F46 VSS287 VSS331 V7
AH20 VSS41 VSS105 AM52 AU28 VSS169 VSS233 B56 F50 VSS288 VSS332 W20
AH22 VSS42 VSS106 AN17 AU30 VSS170 VSS234 B60 F54 VSS289 VSS333 W22
AH24 VSS43 VSS107 AN23 AU33 VSS171 VSS235 C11 F58 VSS290 VSS334 Y10
AH28 VSS44 VSS108 AN31 AU51 VSS172 VSS236 C14 F61 VSS291 VSS335 Y59
AH30 VSS45 VSS109 AN32 AU53 VSS173 VSS237 C18 G18 VSS292 VSS336 Y63
AH32 VSS46 VSS110 AN35 AU55 VSS174 VSS238 C20 G22 VSS293 VSS337
AH34 VSS47 VSS111 AN36 AU57 VSS175 VSS239 C25 G3 VSS294
AH36 VSS48 VSS112 AN39 AU59 VSS176 VSS240 C27 G5 VSS295 V58
AH38 VSS49 VSS113 AN40 AV14 VSS177 VSS241 C38 G6 VSS296 VSS338 AH46
AH40 VSS50 VSS114 AN42 AV16 VSS178 VSS242 C39 G8 VSS297 VSS339 V23
B AH42 VSS51 VSS115 AN43 AV20 VSS179 VSS243 C57 H13 VSS298 VSS340 E62 RC158 1 @ 2 0_0402_5% B
VSS52 VSS116 VSS180 VSS244 VSS299 VSS_SENSE CPU_VSS_SENSE 59
AH44 AN45 AV24 D12 AH16
VSS53 VSS117 VSS181 VSS245 VSS341

2
AH49 AN46 AV28 D14 16 OF 19
AH51 VSS54 VSS118 AN48 AV33 VSS182 VSS246 D18 BROADWELL-ULT-DDR3L_BGA1168 RC159
AH53 VSS55 VSS119 AN49 AV34 VSS183 VSS247 D2 @ 100_0402_1%
VSS56 VSS120 VSS184 VSS248 VSS_SENSE
AH55 AN51 AV36 D21 Length Match: No More Than 25Mil
AH57 VSS57 VSS121 AN52 AV39 VSS185 VSS249 D23 Space: More Than 25Mil

1
AJ13 VSS58 VSS122 AN60 AV41 VSS186 VSS250 D25
AJ14 VSS59 VSS123 AN63 AV43 VSS187 VSS251 D26
GND Reference
AJ23 VSS60 VSS124 AN7 AV46 VSS188 VSS252 D27
AJ25 VSS61 VSS125 AP10 AV49 VSS189 VSS253 D29
AJ27 VSS62 VSS126 AP17 AV51 VSS190 VSS254 D30
AJ29 VSS63 VSS127 AP20 AV55 VSS191 VSS255 D31
VSS64 VSS128 VSS192 15 OF 19 VSS256
BROADWELL-ULT-DDR3L_BGA1168
@
14 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 12 of 59
5 4 3 2 1
 5 4 3 2 1

UC1Q HSW_ULT_DDR3L

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4 1 @ TC71
TC70 @ 1 TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
D DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60 1 @ TC72
D
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TC73 @ 1 TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62 1 @ TC74
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 TP_DC_TEST_AV1 1 @ TC75
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW1 1 @ TC76
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 TP_DC_TEST_AW63 1 @ TC77
17 OF 19 DAISY_CHAIN_NCTF_AW63
BROADWELL-ULT-DDR3L_BGA1168
@

UC1R HSW_ULT_DDR3L

N23
RSVD42 R23
RSVD43 T23
AT2 RSVD44
RSVD35 U10
AU44 RSVD45
AV44 RSVD36
D15 RSVD37
RSVD38 AL1
RSVD46 AM11
RSVD47 AP7
F22 RSVD48
RSVD39 AU10
H22 RSVD49
RSVD40 AU15
J21 RSVD50
C RSVD41 AW14 C
RSVD51 AY14
RSVD52

18 OF 19
BROADWELL-ULT-DDR3L_BGA1168
@

UC1S HSW_ULT_DDR3L

TC96 @ 1 CFG0 AC60 AV63 1 @ TC97 CFG3 RC160 2 @ 1 1K_0402_1%

TC98 @ 1 CFG1 AC62 CFG0 RSVD_TP5 AU63 1 @ TC101
TC99 @ 1 CFG2 AC63 CFG1 RSVD_TP6
TC100 @ 1 CFG3 AA63 CFG2
TC102 @ 1 CFG4 AA60 CFG3 C63 1 @ TC103
CFG4 RSVD_TP7 CFG3
TC104 @ 1 CFG5 Y62 C62 1 @ TC105 *1: Disable
TC106 @ 1 CFG6 Y61 CFG5 RSVD_TP8 B43 1 @ TC107
CFG6 RSVD58 0: Enable, Set DFX Enabled BIT
TC108 @ 1 CFG7 Y60
TC109 @ 1 CFG8 V62 CFG7 A51 1 @ TC110
In Debug Interface MSR
TC111 @ 1 CFG9 V61 CFG8 RSVD_TP9 B51 1 @ TC112
TC113 @ 1 CFG10 V60 CFG9 RSVD_TP10
TC114 @ 1 CFG11 U60 CFG10 L60 1 @ TC115
TC116 @ 1 CFG12 T63 CFG11 RSVD_TP11
TC117 @ 1 CFG13 T62 CFG12 RESERVED N60 CFG4 RC161 2 1 1K_0402_1%
B
TC119 @ 1 CFG14 T61 CFG13 RSVD59 B

TC120 @ 1 CFG15 T60 CFG14 W23

CFG15 RSVD60 Y22
TC123 @ 1 CFG16 AA62 RSVD61 AY15 PROC_OPI_COMP RC162 2 1
CFG16 PROC_OPI_RCOMP
PROC_OPI_RCOMP
TC124 @ 1 CFG18 U63 49.9_0402_1% Width 20Mil CFG4
TC125 @ 1 CFG17 AA61 CFG18 AV62
CFG17 RSVD62 Space 15Mil *L: eDP enable
TC127 @ 1 CFG19 U62 D58 H: eDP disable
CFG19 RSVD63 Length 500Mil
RC163 2 1 49.9_0402_1% CFG_RCOMP V63 P22
CFG_RCOMP VSS342 N21
A5 VSS343
CFG_RCOMP&TD_IREF RSVD53 P20
E1 RSVD64 R20
Width 20Mil RSVD54 RSVD65
Space 15Mil D1 CFG0 RC164 2 @ 1 1K_0402_1%
J20 RSVD55
Length 500Mil H18 RSVD56 CFG1 RC165 2 @ 1 1K_0402_1%
2 1 TD_IREF B12 RSVD57
RC166 8.2K_0402_1% TD_IREF CFG8 RC167 2 @ 1 1K_0402_1%
19 OF 19
BROADWELL-ULT-DDR3L_BGA1168 CFG9 RC168 2 @ 1 1K_0402_1%
@
CFG10 RC169 2 @ 1 1K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 MCP (OTHER)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 13 of 59
5 4 3 2 1
 5 4 3 2 1

Signal voltage level = 0.675 V

PLACE TWO 4.7K RESISTORS CLOSE TO
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
Decoupling caps are needed; one 0.1μF placed close to VREF pins
U15 U16

DDRA_MA0 N3 E3 DDRA_DQ5 DDRA_MA0 N3 E3 DDRA_DQ18 Need change to 36ohm 5% +0.675VS

DDRA_DQ[63:0] 6 DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ6 DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ21
DDRA_MA2 P3 A1 DQL1 F2 DDRA_DQ0 DDRA_MA2 P3 A1 DQL1 F2 DDRA_DQ17
DDRA_MA[15:0] 6 DDRA_MA3 N2 A2 DQL2 F8 DDRA_DQ7 DDRA_MA3 N2 A2 DQL2 F8 DDRA_DQ16
DDRA_MA4 P8 A3 DQL3 H3 DDRA_DQ3 DDRA_MA4 P8 A3 DQL3 H3 DDRA_DQ22 DDRA_MA0 RD122 1 MD@ 2 36_0402_5%
DDRA_DQS[7:0] 6 DDRA_MA5 P2 A4 DQL4 H8 DDRA_DQ4 DDRA_MA5 P2 A4 DQL4 H8 DDRA_DQ23 DDRA_MA1 1 MD@ 2
RD123 36_0402_5%
DDRA_MA6 R8 A5 DQL5 G2 DDRA_DQ1 DDRA_MA6 R8 A5 DQL5 G2 DDRA_DQ19 DDRA_MA2 RD124 1 MD@ 2 36_0402_5%
D DDRA_DQS#[7:0] 6 DDRA_MA7 R2 A6 DQL6 H7 DDRA_DQ2 DDRA_MA7 R2 A6 DQL6 H7 DDRA_DQ20 DDRA_MA3 1 MD@ 2 D
RD125 36_0402_5%
DDRA_MA8 T8 A7 DQL7 D7 DDRA_DQ14 DDRA_MA8 T8 A7 DQL7 D7 DDRA_DQ28
DDRA_MA9 R3 A8 DQU0 C3 DDRA_DQ9 DDRA_MA9 R3 A8 DQU0 C3 DDRA_DQ30
DDRA_MA10 L7 A9 DQU1 C8 DDRA_DQ10 DDRA_MA10 L7 A9 DQU1 C8 DDRA_DQ29
DDRA_MA11 R7 A10/AP DQU2 C2 DDRA_DQ8 DDRA_MA11 R7 A10/AP DQU2 C2 DDRA_DQ31 DDRA_MA4 RD126 1 MD@ 2 36_0402_5%
DDRA_MA12 N7 A11 DQU3 A7 DDRA_DQ11 DDRA_MA12 N7 A11 DQU3 A7 DDRA_DQ25 DDRA_MA5 RD127 1 MD@ 2 36_0402_5%
DDRA_MA13 T3 A12/BC# DQU4 A2 DDRA_DQ12 DDRA_MA13 T3 A12/BC# DQU4 A2 DDRA_DQ26 DDRA_MA6 RD128 1 MD@ 2 36_0402_5%
A13 DQU5 B8 DDRA_DQ15 A13 DQU5 B8 DDRA_DQ24 DDRA_MA7 RD129 1 MD@ 2 36_0402_5%
DDRA_MA14 T7 DQU6 A3 DDRA_DQ13 DDRA_MA14 T7 DQU6 A3 DDRA_DQ27
DDRA_MA15 M7 A14 DQU7 DDRA_MA15 M7 A14 DQU7
NC5 +1.35V NC5 +1.35V
DDRA_MA8 RD130 1 MD@ 2 36_0402_5%
B2 B2 DDRA_MA9 RD131 1 MD@ 2 36_0402_5%
DDRA_BS0# M2 VDD1 D9 DDRA_BS0# M2 VDD1 D9 DDRA_MA10 RD132 1 MD@ 2 36_0402_5%
6 DDRA_BS0# DDRA_BS1# BA0 VDD2 DDRA_BS1# BA0 VDD2 DDRA_MA11 RD133
N8 G7 N8 G7 1 MD@ 2 36_0402_5%
6 DDRA_BS1# DDRA_BS2# M3 BA1 VDD3 K2 DDRA_BS2# M3 BA1 VDD3 K2
6 DDRA_BS2# BA2 VDD4 BA2 VDD4
K8 K8
VDD5 N1 VDD5 N1
VDD6 N9 VDD6 N9 DDRA_MA12 RD134 1 MD@ 2 36_0402_5%
DDRA_CLK0 J7 VDD7 R1 DDRA_CLK0 J7 VDD7 R1 DDRA_MA13 RD135 1 MD@ 2 36_0402_5%
6 DDRA_CLK0 DDRA_CLK0# CK VDD8 DDRA_CLK0# CK VDD8 DDRA_MA14 RD136
K7 R9 K7 R9 1 MD@ 2 36_0402_5%
6 DDRA_CLK0# CK# VDD9 CK# VDD9 DDRA_MA15 RD137 1 MD@ 2 36_0402_5%
DDRA_CKE0 K9 A1 DDRA_CKE0 K9 A1
6 DDRA_CKE0 DDRA_CKE1 CKE VDDQ1 DDRA_CKE1 CKE VDDQ1
J9 A8 J9 A8
6 DDRA_CKE1 NC2 VDDQ2 NC2 VDDQ2 DDRA_BS0# RD138
C1 C1 1 MD@ 2 36_0402_5%
VDDQ3 C9 VDDQ3 C9 DDRA_BS1# RD139 1 MD@ 2 36_0402_5%
DDRA_RAS# J3 VDDQ4 D2 DDRA_RAS# J3 VDDQ4 D2 DDRA_BS2# RD140 1 MD@ 2 36_0402_5%
6 DDRA_RAS# DDRA_CAS# K3 RAS# VDDQ5 E9 DDRA_CAS# K3 RAS# VDDQ5 E9 DDRA_CKE0 RD141
6 DDRA_CAS# 1 MD@ 2 36_0402_5%
DDRA_WE# L3 CAS# VDDQ6 F1 DDRA_WE# L3 CAS# VDDQ6 F1
6 DDRA_WE# WE# VDDQ7 WE# VDDQ7
H2 H2
VDDQ8 H9 VDDQ8 H9
DDRA_DQS0 F3 VDDQ9 DDRA_DQS2 F3 VDDQ9 DDRA_CS0# RD142 1 MD@ 2 36_0402_5%
DDRA_DQS#0 G3 DQSL DDRA_DQS#2 G3 DQSL DDRA_RAS# RD143 1 MD@ 2 36_0402_5%
DQSL# DQSL# DDRA_CAS# RD144 1 MD@ 2 36_0402_5%
DDRA_WE# RD145 1 MD@ 2 36_0402_5%
M8 +VREF_CA M8 +VREF_CA
DDRA_DQS1 C7 VREFCA H1 +VREF_DQ_DIMMA DDRA_DQS3 C7 VREFCA H1 +VREF_DQ_DIMMA
DDRA_DQS#1 B7 DQSU VREFDQ DDRA_DQS#3 B7 DQSU VREFDQ
DQSU# DQSU# DDRA_CKE1 RD146 1 MD@ 2 36_0402_5%
1 1
DDRA_CS1# RD147 1 MD@ 2 36_0402_5%
1 1
CD223 CD225
E7 B1 CD222 0.047U_0402_16V7K E7 B1 CD224 0.047U_0402_16V7K
D3 DML VSSQ1 B9 0.047U_0402_16V7K2 @ D3 DML VSSQ1 B9 0.047U_0402_16V7K2 @
DMU VSSQ2 D1 2 MD@ DMU VSSQ2 D1 2 MD@ +0.675VS
VSSQ3 D8 VSSQ3 D8
VSSQ4 E2 VSSQ4 E2
DDRA_CS0# L2 VSSQ5 E8 DDRA_CS0# L2 VSSQ5 E8
6 DDRA_CS0# DDRA_CS1# L1 CS# VSSQ6 F9 DDRA_CS1# L1 CS# VSSQ6 F9
6 DDRA_CS1# NC3 VSSQ7 G1 NC3 VSSQ7 G1
C Del CS_2(chip select: 1 per Rank) VSSQ8 G9 VSSQ8 G9 C
Del CKE_2(chip select: 1 per Rank???) VSSQ9 VSSQ9 DDRA_CLK0 RD63 1 MD@ 2 26.1_0402_1%
DDRA_ODT0 K1 A9 DDRA_ODT0 K1 A9 DDRA_CLK0# RD59 1 MD@ 2 26.1_0402_1%
J1 ODT VSS1 B3 J1 ODT VSS1 B3
NC1 VSS2 E1 NC1 VSS2 E1
VSS3 G8 VSS3 G8
VSS4 J2 VSS4 J2
RD116 1 MD@ 2 240_0402_1% L8 VSS5 J8 RD95 1 MD@ 2 240_0402_1% L8 VSS5 J8
RD118 1 MD@ 2 240_0402_1% L9 ZQ VSS6 M1 RD119 1 MD@ 2 240_0402_1% L9 ZQ VSS6 M1
NC4 VSS7 M9 NC4 VSS7 M9
VSS8 P1 VSS8 P1 +1.35V
VSS9 P9 VSS9 P9
T2 VSS10 T1 CPU_DRAMRST# T2 VSS10 T1
5,15 CPU_DRAMRST# RESET# VSS11 T9 RESET# VSS11 T9
VSS12 VSS12 DDRA_ODT0 RD117 1 MD@ 2 30_0402_1%
H5TC4G63AFR-PBA_FBGA96 H5TC4G63AFR-PBA_FBGA96
@ @

U17
U18
DDRA_MA0 N3 E3 DDRA_DQ47
DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ45 DDRA_MA0 N3 E3 DDRA_DQ52
DDRA_MA2 P3 A1 DQL1 F2 DDRA_DQ43 DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ55
DDRA_MA3 N2 A2 DQL2 F8 DDRA_DQ40 DDRA_MA2 P3 A1 DQL1 F2 DDRA_DQ49
DDRA_MA4 P8 A3 DQL3 H3 DDRA_DQ46 DDRA_MA3 N2 A2 DQL2 F8 DDRA_DQ51
DDRA_MA5 P2 A4 DQL4 H8 DDRA_DQ41 DDRA_MA4 P8 A3 DQL3 H3 DDRA_DQ53
DDRA_MA6 R8 A5 DQL5 G2 DDRA_DQ42 DDRA_MA5 P2 A4 DQL4 H8 DDRA_DQ54
DDRA_MA7 R2 A6 DQL6 H7 DDRA_DQ44 DDRA_MA6 R8 A5 DQL5 G2 DDRA_DQ48
DDRA_MA8 T8 A7 DQL7 D7 DDRA_DQ36 DDRA_MA7 R2 A6 DQL6 H7 DDRA_DQ50
DDRA_MA9 R3 A8 DQU0 C3 DDRA_DQ39 DDRA_MA8 T8 A7 DQL7 D7 DDRA_DQ59
DDRA_MA10 L7 A9 DQU1 C8 DDRA_DQ33 DDRA_MA9 R3 A8 DQU0 C3 DDRA_DQ60 +1.35V +1.35V
DDRA_MA11 R7 A10/AP DQU2 C2 DDRA_DQ34 DDRA_MA10 L7 A9 DQU1 C8 DDRA_DQ62
DDRA_MA12 N7 A11 DQU3 A7 DDRA_DQ37 DDRA_MA11 R7 A10/AP DQU2 C2 DDRA_DQ56 U15 SIDE U16 SIDE
DDRA_MA13 T3 A12/BC# DQU4 A2 DDRA_DQ35 DDRA_MA12 N7 A11 DQU3 A7 DDRA_DQ63
A13 DQU5 DDRA_DQ32 DDRA_MA13 A12/BC# DQU4 DDRA_DQ57

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
B8 T3 A2

33P_0402_50V8J

33P_0402_50V8J
DDRA_MA14 DQU6 DDRA_DQ38 A13 DQU5 DDRA_DQ58

CD231

CD232
+1.35V T7 A3 B8 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DDRA_MA15 A14 DQU7 DDRA_MA14 DQU6 DDRA_DQ61

CD198

CD199

CD200

CD201

CD202

CD203

CD204

CD205

CD206

CD207

CD208

CD209
M7 T7 A3
NC5 +1.35V DDRA_MA15 M7 A14 DQU7
NC5
1

+1.35V
RD9 B2 2 @2 2 2 2@ 2@ 2 2 2 @ 2 2 2 2@ 2@
1.82K_0402_1% DDRA_BS0# M2 VDD1 D9 B2
DDRA_BS1# N8 BA0 VDD2 G7 DDRA_BS0# M2 VDD1 D9 MD@ MD@ MD@ MD@ MD@ MD@
Trace width:20 mils DDRA_BS2# M3 BA1 VDD3 K2 DDRA_BS1# N8 BA0 VDD2 G7 @ @
Space:20mils
2

BA2 VDD4 K8 DDRA_BS2# M3 BA1 VDD3 K2

RD10 2 @ 1 +VREF_CA VDD5 N1 BA2 VDD4 K8
6 DDR_SM_VREFCA +VREF_CA 15 VDD6 N9 VDD5 N1
1 0_0402_5%
CD21 DDRA_CLK0 J7 VDD7 R1 VDD6 N9
1

B 0.022U_0402_16V7-K DDRA_CLK0# K7 CK VDD8 R9 DDRA_CLK0 J7 VDD7 R1 B

BCD@ RD11 CK# VDD9 DDRA_CLK0# K7 CK VDD8 R9
2 1.82K_0402_1% CK# VDD9 +1.35V +1.35V
For RF
1

DDRA_CKE0 K9 A1
Note: DDRA_CKE1 CKE VDDQ1 DDRA_CKE0
U17 SIDE U18 SIDE
J9 A8 K9 A1
VREF trace width:20 mils at least
2

RD12 NC2 VDDQ2 C1 DDRA_CKE1 J9 CKE VDDQ1 A8

Spacing:20mils to other signal/ planes VDDQ3 NC2 VDDQ2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C9 C1

33P_0402_50V8J

33P_0402_50V8J
24.9_0402_1%
DDRA_RAS# J3 VDDQ4 D2 VDDQ3 C9
Place near DIMM scoket

CD233

CD234
BCD@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2

DDRA_CAS# RAS# VDDQ5 DDRA_RAS# VDDQ4

CD210

CD211

CD212

CD213

CD214

CD215

CD216

CD217

CD218

CD219

CD220

CD221
K3 E9 J3 D2
DDRA_WE# L3 CAS# VDDQ6 F1 DDRA_CAS# K3 RAS# VDDQ5 E9
WE# VDDQ7 H2 DDRA_WE# L3 CAS# VDDQ6 F1
+1.35V VDDQ8 H9 WE# VDDQ7 H2 2 2 @2 2 2@ 2@ 2 2 2 @ 2 2 2 2@ 2@
DDRA_DQS5 F3 VDDQ9 VDDQ8 H9
DDRA_DQS#5 G3 DQSL DDRA_DQS6 F3 VDDQ9 MD@ MD@ MD@ MD@ MD@ MD@
1

DQSL# DDRA_DQS#6 G3 DQSL @ @

RD5 DQSL#
1.82K_0402_1% M8 +VREF_CA
MD@ DDRA_DQS4 C7 VREFCA H1 +VREF_DQ_DIMMA M8 +VREF_CA
RD6 DDRA_DQS#4 B7 DQSU VREFDQ DDRA_DQS7 C7 VREFCA H1 +VREF_DQ_DIMMA
2

1 2 +VREF_DQ_DIMMA DQSU# DDRA_DQS#7 B7 DQSU VREFDQ

6 DDR_SA_VREFDQ 1 DQSU#
2_0402_5% 1 1
1
0.022U_0402_16V7-K

1.82K_0402_1%

MD@ CD227 1
E7 B1 CD226 0.047U_0402_16V7K CD229
DML VSSQ1 0.047U_0402_16V7K2
RD7
MD@

1 D3 B9 @ E7 B1 CD228 0.047U_0402_16V7K
DMU VSSQ2 2 DML VSSQ1 0.047U_0402_16V7K2
CD3

BCD@ D1 MD@ D3 B9 @
VSSQ3 D8 DMU VSSQ2 D1 2 MD@
2

VSSQ4 E2 For RF VSSQ3 D8

2 DDRA_CS0# L2 VSSQ5 E8 VSSQ4 E2
DDRA_CS1# L1 CS# VSSQ6 F9 DDRA_CS0# L2 VSSQ5 E8
NC3 VSSQ7 G1 DDRA_CS1# L1 CS# VSSQ6 F9
1

VSSQ8 G9 NC3 VSSQ7 G1

RD8 VSSQ9 VSSQ8 G9
24.9_0402_1% DDRA_ODT0 K1 A9 VSSQ9
BCD@ J1 ODT VSS1 B3 DDRA_ODT0 K1 A9
NC1 VSS2 E1 J1 ODT VSS1 B3 +0.675VS
2

VSS3 G8 NC1 VSS2 E1 +1.35V

VSS4 J2 VSS3 G8
RD61 1 MD@ 2 240_0402_1% L8 VSS5 J8 VSS4 J2
ZQ VSS6 VSS5
(10uF_0603_6.3V)*6
RD120 1 MD@ 2 240_0402_1% L9 M1 RD93 1 MD@ 2 240_0402_1% L8 J8
NC4 VSS7 M9 RD121 1 MD@ 2 240_0402_1% L9 ZQ VSS6 M1
VSS8 NC4 VSS7

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
P1 M9
VSS9 VSS8

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
P9 P1 1 1 1 1 1 1 @ @
CPU_DRAMRST# VSS10 VSS9

CD164

CD168

CD172

CD175

CD181

CD177
T2 T1 P9 1 1 1 1 1 1
RESET# VSS11 CPU_DRAMRST# VSS10

CD176

CD178

CD180

CD183

CD182

CD179
T9 T2 T1
VSS12 RESET# VSS11 T9 @ @
VSS12 2 2 2 2 2 2
H5TC4G63AFR-PBA_FBGA96 2 2 2 2 @2 2
@ H5TC4G63AFR-PBA_FBGA96 MD@ MD@ MD@ MD@ MD@ MD@
@ MD@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 DDR3L MD A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Wednesday, May 13, 2015 Sheet 14 of 59
5 4 3 2 1
 5 4 3 2 1

DDR3 SO-DIMM B

DDR_SB_VREFDQ 6

+1.35V Swap Table

Pin
+1.35V +1.35V Pin Name Net Name
Number

1
DDRB_DQ[0..63] 6
RD114 5 DQ0 DDRB_DQ17
1.82K_0402_1% 3A@1.5V 7 DQ1 DDRB_DQ23
DDRB_DQS[0..7] 6
D RD111 For RF 15 DQ2 DDRB_DQ18 D
JDDR1
2

1 2 +VREF_DQ_DIMMB 1 2 DDRB_DQS#[0..7] 6 17 DQ3 DDRB_DQ21

2_0402_5% 3 VREF_DQ VSS_2 4 DDRB_DQ16 4 DQ4 DDRB_DQ16
VSS_1 DQ4 DDRB_MA[0..15] 6
1.82K_0402_1%

CD194

2.2U_0603_6.3V6K

CD31

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRB_DQ17 5 6 DDRB_DQ22 6 DQ5 DDRB_DQ22
DQ0 DQ5
1

DDRB_DQ23
0.022U_0402_16V7-K

1 1 7 8 1 1 1 16 DQ6 DDRB_DQ19
DQ1 VSS_4
RD115

CD33

CD34

CD35
9 10 DDRB_DQS#2 @ @ @
VSS_3 DQS0# DDRB_DQS2
18 DQ7 DDRB_DQ20
1 11 12
DM0 DQS0 10 DQS#0 DDRB_DQS#2
CD191

13 14
2 2 DDRB_DQ18 15 VSS_5 VSS_6 16 DDRB_DQ19 2 2 2 12 DQS0 DDRB_DQS2
2

BCD@ DDRB_DQ21 17 DQ2 DQ6 18 DDRB_DQ20

2 19 DQ3 DQ7 20
VSS_7 VSS_8
21 DQ8 DDRB_DQ3
CD@ DDRB_DQ3 21 22 DDRB_DQ2
DDRB_DQ5 DQ8 DQ12 DDRB_DQ4
23 DQ9 DDRB_DQ5
23 24
DQ9 DQ13 33 DQ10 DDRB_DQ6
1

25 26
RD112 DDRB_DQS#0 27 VSS_9 VSS_10 28 35 DQ11 DDRB_DQ1
24.9_0402_1% DDRB_DQS0 29 DQS1# DM1 30 CPU_DRAMRST# 22 DQ12 DDRB_DQ2
DQS1 RESET# CPU_DRAMRST# 5,14
31 32 24 DQ13 DDRB_DQ4
DDRB_DQ6 33 VSS_11 VSS_12 34 DDRB_DQ0
1 34 DQ14 DDRB_DQ0
2

DDRB_DQ1 35 DQ10 DQ14 36 DDRB_DQ7

37 DQ11 DQ15 38 CD230 Layout Note:
(10uF_0603_6.3V)*8 36 DQ15 DDRB_DQ7
BCD@ DDRB_DQ8 39 VSS_13 VSS_14 40 DDRB_DQ13 0.1U_0402_25V6
27 DQS#1 DDRB_DQS#0
DDRB_DQ10 41 DQ16 DQ20 42 DDRB_DQ12 2 EMC_NS@ Place near DIMM (1U_0402_6.3V)*8 29 DQS1 DDRB_DQS0
43 DQ17 DQ21 44
DDRB_DQS#1 45 VSS_15 VSS_16 46 (.1U_0402_10V6-K)*4 39 DQ16 DDRB_DQ8
DDRB_DQS1 47 DQS2# DM2 48
DQS2 VSS_18 DDRB_DQ9
41 DQ17 DDRB_DQ10
49 50
DDRB_DQ14 51 VSS_17 DQ22 52 DDRB_DQ11 51 DQ18 DDRB_DQ14
DDRB_DQ15 53 DQ18 DQ23 54 53 DQ19 DDRB_DQ15
55 DQ19 VSS_20 56 DDRB_DQ31 +1.35V 40 DQ20 DDRB_DQ13
DDRB_DQ27 57 VSS_19 DQ28 58 DDRB_DQ30 42 DQ21 DDRB_DQ12
DDRB_DQ26 59 DQ24 DQ29 60
DQ25 VSS_22 50 DQ22 DDRB_DQ9

CD36

CD37

CD38

CD39

CD40

CD41

CD42

CD43
61 62 DDRB_DQS#3
VSS_21 DQS3# DDRB_DQS3
52 DQ23 DDRB_DQ11
63 64
DM3 DQS3 45 DQS#2 DDRB_DQS#1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
65 66
DDRB_DQ28 67 VSS_23 VSS_24 68 DDRB_DQ29 47 DQS2 DDRB_DQS1
DQ26 DQ30 1 1 1 1 1 1 1 1
DDRB_DQ24 69 70 DDRB_DQ25
71 DQ27 DQ31 72
C VSS_25 VSS_26
57 DQ24 DDRB_DQ27 C

2 2 2 2 2 2 2 2 59 DQ25 DDRB_DQ26
DDRB_CKE0 73 74 DDRB_CKE1 67 DQ26 DDRB_DQ28
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6 69 DQ27 DDRB_DQ24
75 76
77 VDD_1 VDD_2 78 DDRB_MA15 @ BCD@ BCD@ 56 DQ28 DDRB_DQ31
DDRB_BS2# 79 NC_1 A15 80 DDRB_MA14 CD@ CD@ 58 DQ29 DDRB_DQ30
6 DDRB_BS2# BA2 A14
81 82 68 DQ30 DDRB_DQ29
DDRB_MA12 83 VDD_3 VDD_4 84 DDRB_MA11
DDRB_MA9 85 A12/BC# A11 86 DDRB_MA7
70 DQ31 DDRB_DQ25
A9 A7 62 DQS#3 DDRB_DQS#3

CD44

CD45

CD46

CD47

CD60

CD61

CD62

CD63
87 88
DDRB_MA8 89 VDD_5 VDD_6 90 DDRB_MA6 64 DQS3 DDRB_DQS3
A8 A6

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRB_MA5 91 92 DDRB_MA4
93 A5 A4 94
VDD_7 VDD_8 1 1 1 1 1 1 1 1 129 DQ32 DDRB_DQ33
DDRB_MA3 95 96 DDRB_MA2
DDRB_MA1 A3 A2 DDRB_MA0
131 DQ33 DDRB_DQ36
97 98
99 A1 A0 100 141 DQ34 DDRB_DQ39
DDRB_CLK0 101 VDD_9 VDD_10 102 DDRB_CLK1 2 2 2 2 2 2 2 2 143 DQ35 DDRB_DQ38
6 DDRB_CLK0 DDRB_CLK0# CK0 CK1 DDRB_CLK1# DDRB_CLK1 6 130 DQ36 DDRB_DQ37
103 104
6 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 6
105
VDD_11 VDD_12
106 CD@ CD@ CD@ CD@ 132 DQ37 DDRB_DQ32
DDRB_MA10 107 108 DDRB_BS1# BCD@ 140 DQ38 DDRB_DQ35
DDRB_BS0# 109 A10/AP BA1 110 DDRB_RAS# DDRB_BS1# 6
6 DDRB_BS0#
111 BA0 RAS# 112 DDRB_RAS# 6 142 DQ39 DDRB_DQ34
DDRB_W E# 113 VDD_13 VDD_14 114 DDRB_CS0# 135 DQS#4 DDRB_DQS#4
6 DDRB_W E# DDRB_CAS# WE# S0# DDRB_ODT0 DDRB_CS0# 6 137 DQS4 DDRB_DQS4
115 116
6 DDRB_CAS# CAS# ODT0 DDRB_ODT0 5
117 118
DDRB_MA13 119 VDD_15 VDD_16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 5 147 DQ40 DDRB_DQ40
DDRB_CS1# 121 122
6 DDRB_CS1# S1# NC_2 149 DQ41 DDRB_DQ43
123 124
125 VDD_17 VDD_18 126 157 DQ42 DDRB_DQ42
127 TEST VREF_CA 128 +VREF_CA 14 159 DQ43 DDRB_DQ44
DDRB_DQ33 VSS_27 VSS_28 DDRB_DQ37 146 DQ44 DDRB_DQ45
.1U_0402_10V6-K

129 130
DDRB_DQ36 131 DQ32 DQ36 132 DDRB_DQ32 148 DQ45 DDRB_DQ41
DQ33 DQ37 1 1 1
133 134 CD192 CD193 CD195 158 DQ46 DDRB_DQ46
DDRB_DQS#4 135 VSS_29 VSS_30 136 2.2U_0603_6.3V6K 1000P_0402_50V7K
DDRB_DQS4 137 DQS4# DM4 138
160 DQ47 DDRB_DQ47
CD@
139 DQS4 VSS_32 140 DDRB_DQ35 2 2 2 152 DQS#5 DDRB_DQS#5
DDRB_DQ39 141 VSS_31 DQ38 142 DDRB_DQ34 154 DQS5 DDRB_DQS5
B DQ34 DQ39 B
DDRB_DQ38 143 144
145 DQ35 VSS_34 146 DDRB_DQ45
VSS_33 DQ44
163 DQ48 DDRB_DQ52
DDRB_DQ40 147 148 DDRB_DQ41
DDRB_DQ43 DQ40 DQ45 165 DQ49 DDRB_DQ51
149 150
151 DQ41 VSS_35 152 DDRB_DQS#5 175 DQ50 DDRB_DQ50
153 VSS_36 DQS5# 154 DDRB_DQS5 177 DQ51 DDRB_DQ48
155 DM5 DQS5 156 164 DQ52 DDRB_DQ49
DDRB_DQ42 VSS_37 VSS_38 DDRB_DQ46
Layout Note: (10U_0603_6.3V)*2
157 158
Place near DIMM 166 DQ53 DDRB_DQ53
DDRB_DQ44 159 DQ42 DQ46 160 DDRB_DQ47
DQ43 DQ47 (.1U_0402_10V)*4 174 DQ54 DDRB_DQ54
161 162 176 DQ55 DDRB_DQ55
DDRB_DQ52 163 VSS_39 VSS_40 164 DDRB_DQ49
DDRB_DQ51 165 DQ48 DQ52 166 DDRB_DQ53 169 DQS#6 DDRB_DQS#6
167 DQ49 DQ53 168 171 DQS6 DDRB_DQS6
DDRB_DQS#6 169 VSS_41 VSS_42 170
DDRB_DQS6 171 DQS6# DM6 172 +0.675VS
DQS6 VSS_44
181 DQ56 DDRB_DQ62
173 174 DDRB_DQ54
DDRB_DQ50 VSS_43 DQ54 DDRB_DQ55
183 DQ57 DDRB_DQ57
175 176
DQ50 DQ55 191 DQ58 DDRB_DQ59
CD50

CD51

CD52

CD53

CD66

CD67
DDRB_DQ48 177 178
179 DQ51 VSS_46 180 DDRB_DQ56 193 DQ59 DDRB_DQ63
VSS_45 DQ60 180 DQ60 DDRB_DQ56
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRB_DQ62 181 182 DDRB_DQ61
DDRB_DQ57 183 DQ56 DQ61 184 182 DQ61 DDRB_DQ61
DQ57 VSS_48 1 1 1 1 1 1
185 186 DDRB_DQS#7 192 DQ62 DDRB_DQ58
187 VSS_47 DQS7# 188 DDRB_DQS7
189 DM7 DQS7 190
194 DQ63 DDRB_DQ60
DDRB_DQ59 191 VSS_49 VSS_50 192 DDRB_DQ58 2 2 2 2 2 2 186 DQS#7 DDRB_DQS#7
DDRB_DQ63 193 DQ58 DQ62 194 DDRB_DQ60 CD@ 188 DQS7 DDRB_DQS7
195 DQ59 DQ63 196
1 @ 2 RD20 197 VSS_51 VSS_52 198 CD@ CD@
0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
1 2 201 VDDSPD SDA 202 SMB_CLK_S3 SMB_DATA_S3 7,40
+3VS 203 SA1 SCL 204 SMB_CLK_S3 7,40
RD21 10K_0402_5% +0.675VS
VTT_1 VTT_2
2

0_0402_5%

1 1 @ 0.65A@0.75V
RD148

205 206 1
CD54 CD55 207 GND1 GND2 208 CD69
2.2U_0603_6.3V6K .1U_0402_10V6-K BOSS1 BOSS2 33P_0402_50V8J
BCD@ 2 2 @
1

LCN_DAN06-K4406-0103 2
A A
ME@

For RF

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 DDR3L SO-DIMM B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 15 of 59
2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 16 of 59
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 17 of 59
5 4 3 2 1
 5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11 OUT - GPU Core VDD PWM control signal

GPIO12 IN AC Power Detect Input (10K pull High)

Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
C ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

B
N15x Binary Straps B

+3VG_AON Other Power rail

+VGA_CORE
+3VG_AON
Physical
tNVVDD >0 Power Rail Strap Mapping
Strapping pin
+1.35VGS
Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

1. all power rail ramp up time should be larger than 40us Issued Date 2015/02/27 Deciphered Date 2014/01/21 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 18 of 60
2 1
 5 4 3 2 1

9 PCIE_CRX_GTX_N[0..3]

9 PCIE_CRX_GTX_P[0..3]

9 PCIE_CTX_C_GRX_N[0..3]
UV1A
9 PCIE_CTX_C_GRX_P[0..3]
Part 1 of 6
PCIE_CTX_C_GRX_P0 AG6 C6
D PCIE_CTX_C_GRX_N0 AG7 PEX_RX0 GPIO0 B2 D
PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7
PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9
PCIE_CTX_C_GRX_N2 AF9 PEX_RX2 GPIO4 A3
PCIE_CTX_C_GRX_P3 AG9 PEX_RX2_N GPIO5 A4
PCIE_CTX_C_GRX_N3 AG10 PEX_RX3 GPIO6 B6
AF10 PEX_RX3_N GPIO7 E9
AE10 NC81 GPIO8 F8 VGA_ALERT# A6 Symbol update to OVER
RV7 1OPT@ 2 0_0402_5% VGA_SMB_CK2 AE12 NC82 GPIO9 C5
7,44 EC_SMB_CK2 NC83 GPIO10 NVVDD PWM_VID
AF12 E7 DV1
NC84 GPIO11 NVVDD PWM_VID 58
RV9 1OPT@ 2 0_0402_5% VGA_SMB_DA2 AG12 D7 VGA_AC_DET_R 2 1
7,44 EC_SMB_DA2 NC85 GPIO12 PSI_VGA_R VGA_AC_DET 44
AG13 B4 @

GPIO
AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2
AE13 NC87 GPIO14 C3
AE15 NC88 GPIO15 D5 1 2 RV6 PSI_VGA
NC1 GPIO16 PSI_VGA 58
AF15 D4 N15SGT@ 0_0402_5%
AG15 NC2 GPIO17 C2
AG16 NC3 GPIO18 F7
AF16 NC4 GPIO19 E6
AE16 NC5 GPIO20 C4
AE18 NC6 GPIO21
AF18 NC7 A6 OVERT#
AG18 NC8 OVERT AB6
AG19 NC9 NC33
AF19 NC10
PU AT EC SIDE, +3VS AND 4.7K
AE19 NC11 PLT_RST_VGA# 1 RV174 2 0_0402_5%
NC12

.1U_0402_10V6-K
AE21 AG3
AF21 NC13 NC97 AF4 OPT@
NC14 NC98 1
AG21 AF3 CV218
NC15 NC99

2
AG22

G
NC16 @
2
+3VG_AON PCIE_CRX_GTX_P0 CV10 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P0 AC9 AE3

DACs
PCIE_CRX_GTX_N0 CV13 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N0 AB9 PEX_TX0 NC100 AE4 OVERT# 3 1
PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1 PEX_TX0_N NC101 WRST# 44

D
+3VGARST RV12 1 2 0_0402_5% CV8 OPT@ 1 2 .1U_0402_10V6-K AB10
PCIE_CRX_GTX_N1 CV9 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
PEX_TX1_N 1 QV23
PCIE_CRX_GTX_P2 OPT@ 1 2 PCIE_CRX_C_GTX_P2 AD11

PCI EXPRESS
C CV6 .1U_0402_10V6-K C
PCIE_CRX_GTX_N2 CV7 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5 CV221 2N7002KW_SOT323-3
1 PEX_TX2_N NC102
PCIE_CRX_GTX_P3 CV4 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P3 AC12 AE2 0.01U_0402_25V7K OPT@
CV11 PCIE_CRX_GTX_N3 CV5 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N3 AB12 PEX_TX3 NC103 AF2 @ 2
.1U_0402_10V6-K AB13 PEX_TX3_N NC104
2 @ AC13 NC89
AD14 NC90
AC14 NC91
NC92
5

UV2 AC15
AB15 NC93
VCC

PXS_RST# 1 AB16 NC94 B7

IN1 4 PLT_RST_VGA# AC16 NC95 I2CA_SCL A7
PLT_RST# 2 OUT AD17 NC96 I2CA_SDA
GND

IN2 AC17 NC17 C9

AC18 NC18 I2CB_SCL C8
NC19 I2CB_SDA

I2C
MC74VHC1G08DFT2G_SC70-5 AB18
2
3

@ AB19 NC20 A9
RV14 NC21 I2CC_SCL
AC19 B9
10K_0402_5% NC22 I2CC_SDA
AD20
@ NC23 VGA_SMB_CK2
AC20 D9 +3VG_AON
AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2
1

NC25 I2CS_SDA Internal Thermal Sensor

AB21
AD23 NC26
AE23 NC27
AF24 NC28 60mA
AE24 NC29 L6 +PLLVDD OVERT# RV20 1 2
AG24 NC30 CORE_PLLVDD M6 OPT@ 10K_0402_5%
AG25 NC31 SP_PLLVDD VGA_ALERT# RV23 1 2
+3VGS NC32 N6
45mA 1 2 RV24 +SP_PLLVDD OPT@ 10K_0402_5%
VID_PLLVDD OPT@
0_0402_5% VGA_AC_DET_R RV26 1 2
45mA +3VG_AON OPT@ 100K_0402_5%
CLK_PCIE_GPU AE8 PSI_VGA RV29 1 2
8 CLK_PCIE_GPU
2

CLK_PCIE_GPU# AD8 PEX_REFCLK OPT@ 10K_0402_5%

8 CLK_PCIE_GPU# PEX_REFCLK_N
RV180 CLK_REQ_GPU# AC6
2.2K_0402_5% PEX_CLKREQ_N
OPT@ 1 2 RV32 PEX_TSTCLK_OUT AF22 XTALOUT RV33 1 2

CLK
DV2 Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5%
1

2 PEX_TSTCLK_N XTAL_IN B10 XTAL_OUT

B 4 PXS_RST# PLT_RST_VGA# XTAL_OUT B
1
PLT_RST# 3 PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV21 10K_0402_5%
8,32,37,40,44 PLT_RST#
PEX_TERMP PEX_RST_N XTAL_SSIN 300ohms (ESR=0.2) Bead
1 2 RV35 AF25 C10 XTALOUT 1 OPT@ 2 RV22 10K_0402_5% Under GPU(below 150mils)
OPT@ 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF 1 2 RV175
BAT54AWT1G_SOT323-3 OPT@ 0_0402_5%
OPT@ N16V-GM-S-B1_FCBGA595 +SP_PLLVDD 1 2 LV1 +1.05VGS
OPT@ PBY160808T-301Y-N_2P

10U_0603_6.3V6M

22U_0805_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
150mA 1
CV15
1
CV16
1
CV17
1
CV18 @

2 2 2 2
OPT@ OPT@ @ OPT@

1 2 RV38
OPT@ 10M_0402_5%
YV1 30ohms (ESR=0.05) Bead
Under GPU Near GPU 1 2 RV176
XTAL_IN 1 4 OPT@ 0_0402_5%
OSC1 GND2 +PLLVDD 1 2 LV2
XTAL_OUT +1.05VGS
2 3
GND1 OSC2

10P_0402_50V8J

10P_0402_50V8J
1 1 PBY160808T-300Y-N_2P
1 1 @
CV19 CV20 CV21 CV22
OPT@ 27MHZ_10PF_7V27000050 OPT@ 0.1U_0402_10V7K 22U_0805_6.3V6M
OPT@ 2 2 OPT@
OPT@
2 2

A A

8 GPU_CLKREQ# 1 2 RV48 CLK_REQ_GPU#

OPT@
0_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 N16X_PCIE/ DAC/ GPIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

D D

UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N @ 10K_0402_5%

LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71

GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131
NC132 D1 STRAP0
STRAP0 D2 STRAP0 28
C STRAP1 C
V3 STRAP1 E4 STRAP1 28
STRAP2
V4 NC133 STRAP2 E3 STRAP3 STRAP2 28
U3 NC134 STRAP3 D3 STRAP3 28
STRAP4
U4 NC135 STRAP4 C1 STRAP4 28
T4 NC136 NC73
T5 NC137
R4 NC138 F6 1 2 RV51
R5 NC139 MULTI_STRAP_REF0_GND F4 OPT@ 40.2K_0402_1%
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND 2 RV11 1
+3VG_AON
N1
M1 NC34 @ 10K_0402_5%
M2 NC35 F12
M3 NC36 THERMDP
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA 58
M5
L3 NC43
NC44 trace width: 16mils
L4
K4 NC45 differential voltage sensing.
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA 58

J5
N4 NC49
N5 NC141 TEST
NC142
P3 AD9 TESTMODE 1 OPT@ 2 RV52
P4 NC143 TESTMODE AE5 @ 1 10K_0402_5%
B NC144 JTAG_TCK AE6 1 TV1 B
@
JTAG_TDI AF6 1 TV2
@
J2 JTAG_TDO AD6 1 TV3
@
J3 NC145 JTAG_TMS AG4 1TV4 2 RV53
NC146 JTAG_TRST_N OPT@ 10K_0402_5%

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N B12 ROM_SI TV5
ROM_SI A12 ROM_SO ROM_SI 28
ROM_SO C12 ROM_SCLK ROM_SO 28
C
ROM_SCLK ROM_SCLK 28

N16V-GM-S-B1_FCBGA595
OPT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 N16X_LVDS/ HDMI/ THERM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 20 of 60
3 2 1
 5 4 3 2 1

UV1D
Near GPU
+1.35VGS Near GPU Under GPU(below 150mils)
2000mA +1.05VGS
3.5A Part 4 of 6 Under GPU(below 150mils)
B26 AA10
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

33P_0402_50V8J
1U_0402_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_02 PEX_IOVDDQ_2

CV33

CV37

CV39

CV215
E23 AA13

1U_0402_6.3V6K

1U_0402_6.3V6K
FBVDDQ_03 PEX_IOVDDQ_3 1 1 2 1

CV25

CV26

CV27

CV28

CV29

CV30

CV31

CV32
1 2 1 1 1 1 1 1 E26 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
FBVDDQ_06 PEX_IOVDDQ_6 2 2 1 2 For RF
G13 AA20
2 1 2 2 2 2 2 2 G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 OPT@ OPT@ @
FBVDDQ_08 PEX_IOVDDQ_8 OPT@
OPT@ OPT@ OPT@ @ OPT@ OPT@ OPT@ OPT@ G15 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
D
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24 +1.05VGS D

G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25

G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26

22U_0805_6.3V6M
FBVDDQ_13 PEX_IOVDDQ_13 1

CV43
G21 AF27
L22 FBVDDQ_14 PEX_IOVDDQ_14
L24 FBVDDQ_19
L26 FBVDDQ_20 AA22 2 +3VG_AON
FBVDDQ_21 PEX_IOVDD_1 Under Near
M21 AB23
N21 FBVDDQ_22 PEX_IOVDD_2 AC24 @

.1U_0402_10V6-K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_23 PEX_IOVDD_3

CV47

CV48

CV49
R21 AD25 1 1 1

POWER
T21 FBVDDQ_24 PEX_IOVDD_4 AE26
V21 FBVDDQ_25 PEX_IOVDD_5 AE27
W21 FBVDDQ_26 PEX_IOVDD_6
FBVDDQ_27 2 2 2
OPT@ OPT@ OPT@
H24
H26 FBVDDQ_AON_1 +3VG_AON
QV24 J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 Place near balls(Under GPU) Place near GPU
+1.05VS AON7408L_DFN8-5 +1.05VGS K21 G12
FBVDDQ_AON_4 3V3_AON_2 +3VGS
RV54
1 V7 G8 +VDD33 1 2
5 S1 2 NC149 3V3_MAIN_1 G9

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
D S2 3V3_MAIN_2

CV50

CV51

CV52

CV53
3 +1.35VGS 1 1 1 1 0_0603_5%
S3 W7
NC150

G
AA6 Change RV9 to 0ohm jump
OPT@ W6 NC151 D22 FB_CAL_VDDQ 1 2 RV55

4
Y6 NC152 FB_CAL_VDDQ OPT@ 40.2_0402_1% 2 2 2 2
Reserve for GPU +1.05V NC153 @ OPT@ OPT@ OPT@
QV7 C24 FB_CAL_GND 1 2 RV56
AON6414AL_DFN8-5 FB_CAL_GND OPT@ 42.2_0402_1%

1 M7 B25 FB_CAL_TERM 1 2 RV57 CALIBRATION PIN DDR3

2 N7 NC154 FB_CAL_TERM OPT@ 51.1_0402_1%
5 3 T6 NC155
1 P6 NC156 FB_CAL_x_PD_VDDQ 40.2Ohm
CV220 NC157
Place near balls
C 0.1U_0402_16V4Z @ C
FB_CAL_x_PU_GND 42.2Ohm
4

B+ @
2 T7 +3VG_AON
R7 NC158
+5VALW NC159 Under GPU(below 150mils) FB_CAL_xTERM_GND 51.1Ohm
1 OPT@2 RV58 U6
R6 NC160 AA8

.1U_0402_10V6-K
100K_0402_5%

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
NC161 PEX_PLL_HVDD_1
1

CV55

CV56

CV57
1 AA9 1 1 1
PEX_PLL_HVDD_2

1
CV54 RV61
0.1U_0402_16V4Z 120K_0402_5% RV59 AB8
PEX_SVDD_3V3
1

D OPT@ OPT@ 470_0603_5%

1 OPT@ 2 1.05VGS_EN# 2 2 @ 2 2 2
2

RV60 G J7 OPT@ OPT@ @ +1.05VGS

120mA
2

47K_0402_5% QV8 K7 NC76 RV62

OPT@ S 2N7002KW _SOT323-3 K6 NC77 AA14 +PEX_PLLVDD 1 2 0_0603_5%
3

H6 NC78 PEX_PLLVDD_1 AA15

1U_0402_6.3V6K
.1U_0402_10V6-K

4.7U_0805_25V6-K
NC79 PEX_PLLVDD_2

CV58

CV59

CV60
J6 1 1 1
NC80
1

D D
1.05VGS_EN 2 QV9 1.05VGS_EN# 2 QV10
22,58 EN_VGA G G
2N7002KW _SOT323-3 2N7002KW _SOT323-3
@ 2 2 2
OPT@ S S OPT@ OPT@ OPT@
3

N16V-GM-S-B1_FCBGA595
OPT@
Place near balls

B B

+1.35V +1.35VGS
+1.35V TO +1.35VGS AON6414AL_DFN8-5

1
2
+3.3VS TO +3VG_AON 5 3

220U_B2_2.5VM_R15M
CV67 CV68 CV69 CV70

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
CV65 CV66

.1U_0402_10V6-K
1

1
1 1 QV14 OPT@ 1 1 1

4
+3VS +3VG_AON + RV67
470_0603_5%
@
2 2 2 2 2 2

OPT@

OPT@

OPT@

OPT@
@

2
+5VALW
S

3 1 B+
1

1
QV11 OPT@ +5VALW D
1

RV63 OPT@ 1 OPT@2 RV68 FBVDDQ_PW R_EN# 2 QV15

G

1 1 1
2

47K_0402_5% @ LP2301ALT1G_SOT23-3 CV62 RV64 CV63 100K_0402_5% G 2N7002KW _SOT323-3

CV61 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M @

1
.1U_0402_10V6-K @ @ OPT@ 1 S
2

3
RV69

6
2 2 2 D CV71 RV70
2

PXS_PW REN# 1 2 RV65 1 2 FBVDDQ_PW R_EN# 2 QV17A 0.01U_0402_25V7K 124K_0402_1%

10K_0402_5% G 2N7002KDW H_SOT363-6 OPT@ OPT@
OPT@ 2
1

2
47K_0402_5% S OPT@
OPT@

1
1

CV64 QV13 D OPT@

1

QV12 D .1U_0402_10V6-K PXS_PW REN# 2

3
2 OPT@ 2 G D
4,58 PXS_PW REN G 5 QV17B
S 2N7002KW _SOT323-3 58 DGPU_PW ROK G
@ 2N7002KDW H_SOT363-6
3

S 2N7002KW _SOT323-3
3

S OPT@

4
A A

+3VG_AON +3VGS

+3.3VS TO +3VGS
Security Classification LC Future Center Secret Data Title
RV171 1 2
0_0603_5%
Issued Date 2015/02/27 Deciphered Date 2014/01/21 N16X_Power
OPT@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 21 of 60
3 2 1
 5 4 3 2 1

D D

UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17
GND_009 GND_065 VDD_006 VDD_036

POWER
AC26 L2 L13 U15
AC5 GND_010 GND_066 L23 L15 VDD_007 VDD_035 U13

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC8 GND_011 GND_067 L25 L17 VDD_008 VDD_034 U11
AD12 GND_012 GND_068 L5 M10 VDD_009 VDD_033 T18
GND_013 GND_069 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_010 VDD_032

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV88
AD13 M11 M12 T16
AD15 GND_014 GND_070 M13 M14 VDD_011 VDD_031 T14
AD16 GND_015 GND_071 M15 M16 VDD_012 VDD_030 T12
AD18 GND_016 GND_072 M17 2 2 2 2 2 2 2 2 2 2 2 2 2 M18 VDD_013 VDD_029 T10
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
AD21 GND_018 GND_074 N12 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ N13 VDD_015 VDD_027 R15
AD22 GND_019 GND_075 N14 N15 VDD_016 VDD_026 R13
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
AE14 GND_021 GND_077 N18 P10 VDD_018 VDD_024 P18
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16
GND_023 GND_079 For RF VDD_020 VDD_022
AE20 P13 P14

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
GND_024 GND_080 VDD_021

CV89

CV90

CV91

CV92

CV213
AF1 P15 1 1 1 1 1
AF11 GND_025 GND_081 P17
GND

AF14 GND_026 GND_082 P2

AF17 GND_027 GND_083 P23
C AF20 GND_028 GND_084 P26 2 2 2 2 2 C
AF23 GND_029 GND_085 P5 OPT@ OPT@ OPT@ OPT@ @
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N16V-GM-S-B1_FCBGA595
B1 GND_034 GND_090 R18

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
GND_035 GND_091 OPT@
B11 T11
B14 GND_036 GND_092 T13
GND_037 GND_093 1 1 1 1 1 1 1 1 1 1

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102
B17 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12 2 2 2 2 2 2 2 2 2 2
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16 @ OPT@ @ OPT@ @ @ @ @ @ @
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
GND_047 GND_103 For RF
E20 U5

33P_0402_50V8J
GND_048 GND_104
CV103

CV104

CV105

CV214
E22 V11 1 1 1 1
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2 2 2 2 2
H23 GND_053 GND_109 Y23 OPT@ OPT@ @ @
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

Near GPU
AA7
GND_113 AB7
GND_114

N16V-GM-S-B1_FCBGA595
B B
OPT@

+VGA_CORE
+5VALW
1

RV173
2

470_0603_5%
RV172 @
47K_0402_5%
1 2

@
D
1

2 QV22
G
1

D
2 QV21 @ S
3

21,58 EN_VGA G 2N7002KW _SOT323-3

@ S
3

2N7002KW _SOT323-3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 N16X_+VGA CORE, GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 22 of 60
3 2 1
 5 4 3 2 1

FBA_D[0..63]
24,25 FBA_D[0..63]

24,25 FBA_DQM[7..0]
24,25 FBA_DQS[7..0]
24,25 FBA_DQS#[7..0]
CMD mapping mod Mode D
Rank0
UV1B
Address 0..31 32..63
D FBx_CMD0 CS0# D

Part 2 of 6 FBx_CMD1
FBA_D0 E18 C27 FBA_CS0# FBx_CMD2 ODT0
FBA_D1 F18 FBA_D00 FBA_CMD00 C26 FBA_CS0# 24
FBA_D2 E16 FBA_D01 FBA_CMD01 E24 FBA_ODT0 FBx_CMD3 CKE0
FBA_D3 F17 FBA_D02 FBA_CMD02 F24 FBA_CKE0 FBA_ODT0 24
FBA_D4 D20 FBA_D03 FBA_CMD03 D27 FBA_A14 FBA_CKE0 24 FBx_CMD4 A14 A14
FBA_D5 D21 FBA_D04 FBA_CMD04 D26 FBA_RST# FBA_A14 24,25
FBA_D6 F20 FBA_D05 FBA_CMD05 F25 FBA_A9 FBA_RST# 24,25 FBx_CMD5 RST RST
FBA_D7 E21 FBA_D06 FBA_CMD06 F26 FBA_A7 FBA_A9 24,25
FBA_D8 E15 FBA_D07 FBA_CMD07 F23 FBA_A2 FBA_A7 24,25 FBx_CMD6 A9 A9
FBA_D9 D15 FBA_D08 FBA_CMD08 G22 FBA_A0 FBA_A2 24,25
FBA_D10 F15 FBA_D09 FBA_CMD09 G23 FBA_A4 FBA_A0 24,25 FBx_CMD7 A7 A7
FBA_D11 F13 FBA_D10 FBA_CMD10 G24 FBA_A1 FBA_A4 24,25
FBA_D12 C13 FBA_D11 FBA_CMD11 F27 FBA_BA0 FBA_A1 24,25 FBx_CMD8 A2 A2
FBA_D13 B13 FBA_D12 FBA_CMD12 G25 FBA_W E FBA_BA0 24,25
FBA_D14 E13 FBA_D13 FBA_CMD13 G27 FBA_W E 24,25 FBx_CMD9 A0 A0
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS#
FBA_D16 B15 FBA_D15 FBA_CMD15 M24 FBA_CS1# FBA_CAS# 24,25 FBx_CMD10 A4 A4
FBA_D17 C16 FBA_D16 FBA_CMD16 M23 FBA_CS1# 25
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_ODT1 FBx_CMD11 A1 A1
FBA_D19 A15 FBA_D18 FBA_CMD18 K23 FBA_CKE1 FBA_ODT1 25
FBA_D20 B18 FBA_D19 FBA_CMD19 M27 FBA_A13 FBA_CKE1 25 FBx_CMD12 BA0 BA0
FBA_D21 A18 FBA_D20 FBA_CMD20 M26 FBA_A8 FBA_A13 24,25
FBA_D22 A19 FBA_D21 FBA_CMD21 M25 FBA_A6 FBA_A8 24,25 FBx_CMD13 WE WE
FBA_D23 C19 FBA_D22 FBA_CMD22 K26 FBA_A11 FBA_A6 24,25
FBA_D24 B24 FBA_D23 FBA_CMD23 K22 FBA_A5 FBA_A11 24,25 FBx_CMD14 A15 A15
FBA_D25 C23 FBA_D24 FBA_CMD24 J23 FBA_A3 FBA_A5 24,25
FBA_D26 A25 FBA_D25 FBA_CMD25 J25 FBA_BA2 FBA_A3 24,25 FBx_CMD15 CAS# CAS#
FBA_D27 A24 FBA_D26 FBA_CMD26 J24 FBA_BA1 FBA_BA2 24,25
FBA_D28 A21 FBA_D27 FBA_CMD27 K27 FBA_A12 FBA_BA1 24,25 FBx_CMD16 CS1#
FBA_D29 B21 FBA_D28 FBA_CMD28 K25 FBA_A10 FBA_A12 24,25
FBA_D30 C20 FBA_D29 FBA_CMD29 J27 FBA_RAS# FBA_A10 24,25 FBx_CMD17
FBA_D31 C21 FBA_D30 FBA_CMD30 J26 FBA_RAS# 24,25
FBA_D32 R22 FBA_D31 FBA_CMD31 B19 +1.35VGS FBx_CMD18 ODT1
C FBA_D33 R24 FBA_D32 FBA_CMD32 Symbol update to FBA_CMD34/35 C
FBA_D33 FBx_CMD19 CKE1

INTERFACE A
FBA_D34 T22 F22 RV121 2 @ 1 60.4_0402_1%
FBA_D35 R23 FBA_D34 FBA_CMD34 J22 RV122 2 1 60.4_0402_1%
FBA_D36 N25 FBA_D35 FBA_CMD35 @ FBx_CMD20 A13 A13
FBA_D37 N26 FBA_D36 D19 FBA_DQM0

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM0 D14 FBA_DQM1 FBx_CMD21 A8 A8
FBA_D39 N24 FBA_D38 FBA_DQM1 C17 FBA_DQM2
30ohms (ESR=0.01) Bead FBA_D40 FBA_D39 FBA_DQM2 FBA_DQM3 FBx_CMD22 A6 A6
V23 C22
FBA_D41 V22 FBA_D40 FBA_DQM3 P24 FBA_DQM4
+1.05VGS +FB_PLLAVDD FBA_D42 T23 FBA_D41 FBA_DQM4 W24 FBA_DQM5 FBx_CMD23 A11 A11
FBA_D43 U22 FBA_D42 FBA_DQM5 AA25 FBA_DQM6
200mA FBA_D44 Y24 FBA_D43 FBA_DQM6 U25 FBA_DQM7 FBx_CMD24 A5 A5
1 2 LV4 FBA_D45 AA24 FBA_D44 FBA_DQM7
HCB1608KF-300T60_2P FBA_D46 Y22 FBA_D45 F19 FBA_DQS#0 FBx_CMD25 A3 A3
FBA_D47 AA23 FBA_D46 FBA_DQS_RN0 C14 FBA_DQS#1
OPT@ FBA_D48 FBA_D47 FBA_DQS_RN1 FBA_DQS#2 FBx_CMD26 BA2 BA2
AD27 A16
FBA_D49 AB25 FBA_D48 FBA_DQS_RN2 A22 FBA_DQS#3
Place close to BGA
FBA_D50 AD26 FBA_D49 FBA_DQS_RN3 P25 FBA_DQS#4 FBx_CMD27 BA1 BA1
FBA_D51 AC25 FBA_D50 FBA_DQS_RN4 W22 FBA_DQS#5
FBA_D52 AA27 FBA_D51 FBA_DQS_RN5 AB27 FBA_DQS#6 FBx_CMD28 A12 A12
Place close to BGA Place close to ball FBA_D53 AA26 FBA_D52 FBA_DQS_RN6 T27 FBA_DQS#7
FBA_D54 W26 FBA_D53 FBA_DQS_RN7 FBx_CMD29 A10 A10
FBA_D55 Y25 FBA_D54 E19 FBA_DQS0
+FB_PLLAVDD FBA_D56 FBA_D55 FBA_DQS_WP0 FBA_DQS1 FBx_CMD30 RAS# RAS#
R26 C15
22U_0805_6.3V6M

1U_0402_6.3V6K

0.1U_0402_10V7K

FBA_D57 FBA_D56 FBA_DQS_WP1 FBA_DQS2

CV111

CV112

CV113

1 1 1 T25 B16
FBA_D58 N27 FBA_D57 FBA_DQS_WP2 B22 FBA_DQS3 FBx_CMD31
FBA_D59 R27 FBA_D58 FBA_DQS_WP3 R25 FBA_DQS4
FBA_D60 V26 FBA_D59 FBA_DQS_WP4 W23 FBA_DQS5 FBx_CMD32
2 2 2 FBA_D61 V27 FBA_D60 FBA_DQS_WP5 AB26 FBA_DQS6
FBA_D62 W27 FBA_D61 FBA_DQS_WP6 T26 FBA_DQS7 FBx_CMD33
OPT@ OPT@ OPT@ FBA_D63 W25 FBA_D62 FBA_DQS_WP7
FBA_D63 D24 FBA_CLK0 FBx_CMD34 DBG0
F16 FBA_CLK0 D25 FBA_CLK0# FBA_CLK0 24
P22 FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# 24 FBx_CMD35 DBG1
FB_PLLAVDD_2 N22 FBA_CLK1
D23 FBA_CLK1 M22 FBA_CLK1# FBA_CLK1 25
FB_VREF FBA_CLK1_N FBA_CLK1# 25
+FB_PLLAVDD
Place close to ball D18
B
1 2 CV115 H22 FBA_WCK01 C18 B

OPT@ 0.1U_0402_10V7K FB_DLLAVDD FBA_WCK01_N D17

1 2 FB_CLAMP F3 FBA_WCK23 D16
RV120 OPT@ 10K_0402_5% FB_CLAMP FBA_WCK23_N T24
FBA_WCK45 U24
FBA_WCK45_N V24
FBA_WCK67 V25
FBA_WCK67_N

N16V-GM-S-B1_FCBGA595
OPT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 N16X_MEM Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 23 of 60
3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes FBA_D[0..63] 23,25

D D

+1.35VGS
FBA_DQM[7..0] 23,25
RPV6 UV6 UV5
1 4 FBA_DQS[7..0] 23,25
2 3 +FBA_VREFCA0 +FBA_VREFCA0 M8 E3 FBA_D25 +FBA_VREFCA0 M8 E3 FBA_D8
+FBA_VREFDQ0 H1 VREFCA DQL0 F7 FBA_D28 +FBA_VREFDQ0 H1 VREFCA DQL0 F7 FBA_D12 FBA_DQS#[7..0] 23,25
1.33K_0404_4P2R_1% VREFDQ DQL1 F2 FBA_D27 VREFDQ DQL1 F2 FBA_D9
1 DQL2 DQL2
RANKA@ CV116
.01U_0402_16V7-K 23,25 FBA_A0
FBA_A0
FBA_A1
N3
P7 A0 DQL3
F8
H3
FBA_D29
FBA_D26
Group3 FBA_A0
FBA_A1
N3
P7 A0 DQL3
F8
H3
FBA_D10
FBA_D15
Group1 CMD mapping mod Mode D
23,25 FBA_A1 FBA_A2 P3 A1 DQL4 H8 FBA_D30 FBA_A2 P3 A1 DQL4 H8 FBA_D14
RANKA@
2 23,25 FBA_A2 FBA_A3 N2 A2 DQL5 G2 FBA_D24 FBA_A3 N2 A2 DQL5 G2 FBA_D13 Rank0
23,25 FBA_A3 FBA_A4 P8 A3 DQL6 H7 FBA_D31 FBA_A4 P8 A3 DQL6 H7 FBA_D11
23,25 FBA_A4 FBA_A5 P2 A4 DQL7 FBA_A5 P2 A4 DQL7 Address 0..31 32..63
23,25 FBA_A5 FBA_A6 R8 A5 FBA_A6 R8 A5
23,25 FBA_A6 FBA_A7 R2 A6 D7 FBA_D1 FBA_A7 R2 A6 D7 FBA_D17 FBx_CMD0 CS0#
23,25 FBA_A7 FBA_A8 T8 A7 DQU0 C3 FBA_D6 FBA_A8 T8 A7 DQU0 C3 FBA_D23
23,25 FBA_A8 FBA_A9 R3 A8 DQU1 C8 FBA_D2 FBA_A9 R3 A8 DQU1 C8 FBA_D18 FBx_CMD1
23,25 FBA_A9 FBA_A10 L7 A9 DQU2 C2 FBA_D5 FBA_A10 L7 A9 DQU2 C2 FBA_D20
23,25 FBA_A10 FBA_A11 R7 A10/AP DQU3 A7 FBA_D0
Group0 FBA_A11 R7 A10/AP DQU3 A7 FBA_D16
Group2 FBx_CMD2 ODT0
23,25 FBA_A11 FBA_A12 N7 A11 DQU4 A2 FBA_D7 FBA_A12 N7 A11 DQU4 A2 FBA_D21
23,25 FBA_A12 FBA_A13 T3 A12/BC DQU5 B8 FBA_D3 FBA_A13 T3 A12/BC DQU5 B8 FBA_D22 FBx_CMD3 CKE0
23,25 FBA_A13 FBA_A14 T7 A13 DQU6 A3 FBA_D4 FBA_A14 T7 A13 DQU6 A3 FBA_D19
+1.35VGS
23,25 FBA_A14 A14 DQU7 A14 DQU7 FBx_CMD4 A14 A14
+1.35VGS +1.35VGS
RPV7 FBx_CMD5 RST RST
1 4 FBA_BA0 M2 B2 FBA_BA0 M2 B2
2 3 +FBA_VREFDQ0 23,25 FBA_BA0 FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9 FBx_CMD6 A9 A9
23,25 FBA_BA1 FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA2 M3 BA1 VDD_2 G7
1.33K_0404_4P2R_1% 1
23,25 FBA_BA2 BA2 VDD_3 K2 BA2 VDD_3 K2 FBx_CMD7 A7 A7
CV216 VDD_4 K8 VDD_4 K8
RANKA@ VDD_5 VDD_5 FBx_CMD8 A2 A2
.01U_0402_16V7-K N1 N1
RANKA@ FBA_CLK0 J7 VDD_6 N9 FBA_CLK0 J7 VDD_6 N9
2 23 FBA_CLK0 FBA_CLK0# K7 CK VDD_7 R1 FBA_CLK0# K7 CK VDD_7 R1 FBx_CMD9 A0 A0
23 FBA_CLK0# FBA_CKE0 K9 CK VDD_8 R9 FBA_CKE0 K9 CK VDD_8 R9
23 FBA_CKE0 CKE VDD_9 CKE VDD_9 FBx_CMD10 A4 A4
C C
FBA_ODT0 K1 A1 FBA_ODT0 K1 A1 FBx_CMD11 A1 A1
23 FBA_ODT0 FBA_CS0# L2 ODT VDDQ_1 A8 FBA_CS0# L2 ODT VDDQ_1 A8
23 FBA_CS0# FBA_RAS# J3 CS VDDQ_2 C1 FBA_RAS# J3 CS VDDQ_2 C1 FBx_CMD12 BA0 BA0
23,25 FBA_RAS# FBA_CAS# K3 RAS VDDQ_3 C9 FBA_CAS# K3 RAS VDDQ_3 C9
23,25 FBA_CAS# FBA_W E L3 CAS VDDQ_4 D2 FBA_W E L3 CAS VDDQ_4 D2 FBx_CMD13 WE WE
23,25 FBA_W E WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1 FBx_CMD14 A15 A15
FBA_DQS3 F3 VDDQ_7 H2 FBA_DQS1 F3 VDDQ_7 H2
FBA_CLK0 FBA_DQS0 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9 FBx_CMD15 CAS# CAS#
DQSU VDDQ_9 DQSU VDDQ_9
FBx_CMD16 CS1#
1

FBA_DQM3 E7 A9 FBA_DQM1 E7 A9
RV129 FBA_DQM0 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3 FBx_CMD17
162_0402_1% DMU VSS_2 E1 DMU VSS_2 E1
RANKA@ VSS_3 G8 VSS_3 G8 FBx_CMD18 ODT1
FBA_DQS#3 G3 VSS_4 J2 FBA_DQS#1 G3 VSS_4 J2
2

FBA_DQS#0 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8 FBx_CMD19 CKE1

FBA_CLK0# DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 M9 VSS_7 M9 FBx_CMD20 A13 A13
VSS_8 P1 VSS_8 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9 FBx_CMD21 A8 A8
23,25 FBA_RST# RESET VSS_10 T1 RESET VSS_10 T1
1 2 RV130 L8 VSS_11 T9 L8 VSS_11 T9 FBx_CMD22 A6 A6
243_0402_1% ZQ VSS_12 ZQ VSS_12
RANKA@ FBx_CMD23 A11 A11

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1 FBx_CMD24 A5 A5
1

L1 B9 RV132 L1 B9
RV131 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_ODT0 10K_0402_5% L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8 FBx_CMD25 A3 A3
RANKA@ M7 NC4 VSSQ_4 E2 M7 NC4 VSSQ_4 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 FBx_CMD26 BA2 BA2
2

FBA_CKE0 VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 G1 VSSQ_7 G1 FBx_CMD27 BA1 BA1
VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 FBx_CMD28 A12 A12
1

RV133 RV134 96-BALL 96-BALL

10K_0402_5% 10K_0402_5% SDRAM DDR3 SDRAM DDR3 FBx_CMD29 A10 A10
B B
RANKA@ RANKA@ K4W 4G1646B-HC11_FBGA96 K4W 4G1646B-HC11_FBGA96
@ @
FBx_CMD30 RAS# RAS#
2

FBx_CMD31
FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF
1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV117

CV118

CV119

CV120

CV121

CV122

CV127

CV129

CV130

CV131

CV132

CV133

CV134

CV139
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
For RF
RANKA@ RANKA@ RANKA@ RANKA@ CD@ RANKA@ @ RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 DDR3 VRAM Rank0_L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 24 of 60
3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

FBA_D[0..63] 23,24

D D
+1.35VGS
FBA_DQM[7..0] 23,24
RPV8
1 4 UV8 UV7 FBA_DQS[7..0] 23,24
2 3 +FBA_VREFCA1
+FBA_VREFCA1 M8 E3 FBA_D53 +FBA_VREFCA1 M8 E3 FBA_D40 FBA_DQS#[7..0] 23,24
1 VREFCA DQL0 VREFCA DQL0
1.33K_0404_4P2R_1% CV141 +FBA_VREFDQ1 H1 F7 FBA_D55 +FBA_VREFDQ1 H1 F7 FBA_D43
.01U_0402_16V7-K VREFDQ DQL1 F2 FBA_D52 VREFDQ DQL1 F2 FBA_D41
RANKA@ DQL2 DQL2
RANKA@ FBA_A0 N3 F8 FBA_D50 FBA_A0 N3 F8 FBA_D42
2 23,24 FBA_A0 FBA_A1 A0 DQL3 FBA_D48 FBA_A1 A0 DQL3 FBA_D45
Group5 CMD mapping mod Mode D
P7 H3 Group6 P7 H3
23,24 FBA_A1 FBA_A2 P3 A1 DQL4 H8 FBA_D51 FBA_A2 P3 A1 DQL4 H8 FBA_D47
23,24 FBA_A2 FBA_A3 N2 A2 DQL5 G2 FBA_D54 FBA_A3 N2 A2 DQL5 G2 FBA_D44
23,24 FBA_A3 FBA_A4 A3 DQL6 FBA_D49 FBA_A4 A3 DQL6 FBA_D46
Rank0
P8 H7 P8 H7
23,24 FBA_A4 FBA_A5 P2 A4 DQL7 FBA_A5 P2 A4 DQL7
23,24 FBA_A5
Address 0..31 32..63
FBA_A6 R8 A5 FBA_A6 R8 A5
23,24 FBA_A6 FBA_A7 R2 A6 D7 FBA_D32 FBA_A7 R2 A6 D7 FBA_D57
23,24 FBA_A7 A7 DQU0 A7 DQU0 FBx_CMD0 CS0#
FBA_A8 T8 C3 FBA_D39 FBA_A8 T8 C3 FBA_D63
23,24 FBA_A8 FBA_A9 R3 A8 DQU1 C8 FBA_D33 FBA_A9 R3 A8 DQU1 C8 FBA_D59
23,24 FBA_A9 FBA_A10 A9 DQU2 FBA_D36 FBA_A10 A9 DQU2 FBA_D62
FBx_CMD1
L7 C2 L7 C2
23,24 FBA_A10 FBA_A11 R7 A10/AP DQU3 A7 FBA_D35 FBA_A11 R7 A10/AP DQU3 A7 FBA_D56
23,24 FBA_A11 FBA_A12 A11 DQU4 FBA_D38
Group4 FBA_A12 A11 DQU4 FBA_D61
Group7 FBx_CMD2 ODT0
N7 A2 N7 A2
23,24 FBA_A12 FBA_A13 T3 A12/BC DQU5 B8 FBA_D34 FBA_A13 T3 A12/BC DQU5 B8 FBA_D58
23,24 FBA_A13 FBA_A14 A13 DQU6 FBA_D37 FBA_A14 A13 DQU6 FBA_D60
FBx_CMD3 CKE0
+1.35VGS T7 A3 T7 A3
23,24 FBA_A14 A14 DQU7 A14 DQU7
FBx_CMD4 A14 A14
RPV9 +1.35VGS +1.35VGS
1 4 FBx_CMD5 RST RST
2 3 +FBA_VREFDQ1 FBA_BA0 M2 B2 FBA_BA0 M2 B2
23,24 FBA_BA0 FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9
1 23,24 FBA_BA1 FBA_BA2 BA1 VDD_2 FBA_BA2 BA1 VDD_2 FBx_CMD6 A9 A9
1.33K_0404_4P2R_1% M3 G7 M3 G7
CV217 23,24 FBA_BA2 BA2 VDD_3 K2 BA2 VDD_3 K2
RANKA@ .01U_0402_16V7-K VDD_4 VDD_4 FBx_CMD7 A7 A7
K8 K8
RANKA@ VDD_5 N1 VDD_5 N1
2
FBA_CLK1 VDD_6 FBA_CLK1 VDD_6 FBx_CMD8 A2 A2
J7 N9 J7 N9
23 FBA_CLK1 FBA_CLK1# K7 CK VDD_7 R1 FBA_CLK1# K7 CK VDD_7 R1
23 FBA_CLK1# FBA_CKE1 CK VDD_8 FBA_CKE1 CK VDD_8 FBx_CMD9 A0 A0
K9 R9 K9 R9
23 FBA_CKE1 CKE VDD_9 CKE VDD_9
FBx_CMD10 A4 A4
C FBA_ODT1 K1 A1 FBA_ODT1 K1 A1 FBx_CMD11 A1 A1 C
23 FBA_ODT1 FBA_CS1# L2 ODT VDDQ_1 A8 FBA_CS1# L2 ODT VDDQ_1 A8
23 FBA_CS1# FBA_RAS# J3 CS VDDQ_2 C1 FBA_RAS# J3 CS VDDQ_2 C1
23,24 FBA_RAS# FBA_CAS# RAS VDDQ_3 FBA_CAS# RAS VDDQ_3 FBx_CMD12 BA0 BA0
K3 C9 K3 C9
23,24 FBA_CAS# FBA_W E L3 CAS VDDQ_4 D2 FBA_W E L3 CAS VDDQ_4 D2
FBA_CLK1 23,24 FBA_W E WE VDDQ_5 WE VDDQ_5 FBx_CMD13 WE WE
E9 E9
VDDQ_6 F1 VDDQ_6 F1
FBA_DQS6 VDDQ_7 FBA_DQS5 VDDQ_7 FBx_CMD14 A15 A15
F3 H2 F3 H2
DQSL VDDQ_8 DQSL VDDQ_8
1

FBA_DQS4 C7 H9 FBA_DQS7 C7 H9 FBx_CMD15 CAS# CAS#

RV137 DQSU VDDQ_9 DQSU VDDQ_9
162_0402_1%
FBA_DQM6 FBA_DQM5
FBx_CMD16 CS1#
E7 A9 E7 A9
FBA_DQM4 D3 DML VSS_1 B3 FBA_DQM7 D3 DML VSS_1 B3
RANKA@ FBx_CMD17
2

DMU VSS_2 E1 DMU VSS_2 E1

FBA_CLK1# VSS_3 G8 VSS_3 G8
FBA_DQS#6 G3 VSS_4 FBA_DQS#5 G3 VSS_4 FBx_CMD18 ODT1
J2 J2
FBA_DQS#4 B7 DQSL VSS_5 J8 FBA_DQS#7 B7 DQSL VSS_5 J8
DQSU VSS_6 DQSU VSS_6 FBx_CMD19 CKE1
M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD20 A13 A13
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
23,24 FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD21 A8 A8
T1 T1
L8 VSS_11 T9 L8 VSS_11 T9
FBA_CKE1 ZQ VSS_12 ZQ VSS_12 FBx_CMD22 A6 A6
FBx_CMD23 A11 A11

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1
1

FBA_ODT1 L1 B9 RV141 L1 B9 FBx_CMD24 A5 A5

RV140 J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
243_0402_1%
NC4 VSSQ_4
RANKA@
NC4 VSSQ_4 FBx_CMD25 A3 A3
RANKA@ M7 E2 M7 E2

2
NC5 VSSQ_5 NC5 VSSQ_5
1

E8 E8 FBx_CMD26 BA2 BA2

2

RV138 RV139 VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 G1 VSSQ_7 G1
10K_0402_5% 10K_0402_5%
VSSQ_8 VSSQ_8 FBx_CMD27 BA1 BA1
RANKA@ RANKA@ G9 G9
VSSQ_9 VSSQ_9
FBx_CMD28 A12 A12
2

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD29 A10 A10
K4W 4G1646B-HC11_FBGA96 K4W 4G1646B-HC11_FBGA96
B B
@ @ FBx_CMD30 RAS# RAS#
FBx_CMD31
FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV8 SIDE +1.35VGS +1.35VGS UV7 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV142

CV143

CV144

CV145

CV146

CV147

CV152

CV154

CV155

CV156

CV157

CV158

CV159

CV164
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ CD@
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 DDR3 VRAM Rank0_H

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 25 of 60
3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 DDR3 VRAM Rank1_L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 26 of 60
3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 27 of 59
5 4 3 2 1
 5 4 3 2 1

+3VG_AON Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
OPT@ @ OPT@ @ @ STRAP1 +3VGS

1
STRAP2 +3VGS
20 STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP1 STRAP3 +3VGS
20 STRAP1
20 STRAP2 STRAP2
STRAP3 STRAP4 +3VGS
20 STRAP3
STRAP4
20 STRAP4

DEVID_SEL
2

2
Pull-up to
RV151 RV152 RV153 RV154 RV155 Resistor Values +3VGS Pull-down to Gnd
45.3K_0402_1% 45.3K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1% 0 (Default)
@ OPT@ @ OPT@ OPT@ 4.99K 1000 0000
SD03449918J
1

1
10K 1001 0001 1
15K 1010 0010
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
SD03424928J 0 (Default)
30.1K 1101 0101
SD03430128J
34.8K 1110 0110 1
SD03434828J
+3VGS 45.3K 1111 0111
C SD03445328J C

SMBUS_ALT_ADDR
0 0x9E (Default)
2

2 Physical
RV156 RV157 RV158
Strapping pin Power Rail Strap Mapping
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 1 0x9C (Multi-GPU usage)
@ OPT@ OPT@ ROM_SCLK +3VGS SMB_ALT_ADDR
1

ROM_SI +3VGS SUB_VENDOR

ROM_SO +3VGS VGA_DEVICE VGA_DEVICE
ROM_SI
20 ROM_SI ROM_SO
20 ROM_SO STRAP0 +3VGS RAM_CFG[0] 0 3D Device (Class Code 302h)
ROM_SCLK
20 ROM_SCLK
STRAP1 +3VGS RAM_CFG[1]
1 VGA Device (Default)
2

STRAP2 +3VGS RAM_CFG[2]

RV159 RV160 RV161
X76 10K_0402_1% 10K_0402_1% 10K_0402_1% STRAP3 +3VGS RAM_CFG[3]
@ @ @
STRAP4 +3VGS PCIE_MAX_SPEED
1

X76

GPU FB Memory (DDR3L) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
B H5TC4G63AFR-11C 0xE B
Hynix PU 34.8K
900MHz 256M x 16 0xE
MT41J256M16HA-093G:E 0xD
Micron PU 30.1K
N16V-GM 900MHz 256M x 16 0xD
H5TC2G63FFR-11C 0xB
Hynix PU 4.99K PU 4.99K PU 45.3K PD 45.3K PU 10K PD 4.99K PD 45.3K
128M x 16 0xB PU 20K
900MHz
MT41J128M16JT-093G 0x8
Micron
900MHz 128M x 16 0x8 PU 4.99K
K4W2G1646Q-BC1A 0x7
Samsung
900MHz 128M x 16 0x7 PD 45.3K

VRAM X76 VRAM P/N

X7606012101 SA00005SH40
Samsung

X7606012001 SA00005M120
Micron

A A

Hynix X7606012002 SA00005VS00

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2014/01/21 N16X_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 28 of 60
3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 29 of 59
5 4 3 2 1
 5 4 3 2 1

D D

UW 1

RW 2 1 2 6.2K_0402_1% RREF 1 24 VDD18 1U_0402_6.3V6K 2 1 CW 1

USB20_N3 RW 9 1 @ 2 0_0402_5% USB20_N3_R 2 RREF V18 23
9 USB20_N3 USB20_P3 USB20_P3_R DM XD_D7
RW 10 1 @ 2 0_0402_5% 3 22
9 USB20_P3 4 DP SP14 21 SD_D2_R
+3VS CARD_3V3 3V3_IN SP13 SD_D3_R
5 20
SDREG 6 CARD_3V3 SP12 19

0.1U_0402_10V7K
4.7U_0603_6.3V6K
7 SDREG SP11 18 SD_CMD_R
1 1 XD_CD# SP10
SD_W P 8 17

1U_0402_6.3V6K
CW 2 CW 3
9 SP1 GPIO0 16
1 SP2 SP9
CW 4 SD_D1_R 10 15 SD_CLK_R
2 2 SD_D0_R 11 SP3 SP8 14
LW 1 EMC@ 12 SP4 SP7 13 SD_CD#
USB20_N3 1 2 USB20_N3_R 2 SP5 SP6
1 2 25
GND
USB20_P3 4 3 USB20_P3_R
4 3 RTS5170-GRT_QFN24_4X4
EXC24CH900U_4P

CARD_3V3

FOR EMI
JREAD1
C FOR ESD Close to Connector 4 C
SD_D0_R RW 3 1 2 0_0402_5% SD_D0 VDD

.1U_0402_10V6-K
4.7U_0603_6.3V6K
EMC@ CW 5 1 2 .1U_0402_10V6-K SD_D0 7
1 1 DAT0
EMC_NS@ SD_D1 8
SD_D1_R RW 4 1 2 0_0402_5% SD_D1 CARD_3V3 CW 9 CW 10 SD_D2 9 DAT1
EMC@ CW 6 1 2 .1U_0402_10V6-K SD_D3 1 DAT2
EMC_NS@ 2 2 CD/DAT3

AZ5425-01F_DFN1006P2E2

1
SD_D2_R RW 5 1 2 0_0402_5% SD_D2 SD_CD# 11
EMC@ CW 7 1 2 .1U_0402_10V6-K DW 1 SD_W P 10 C/D

1
EMC_NS@ EMC_NS@ W/P
SD_D3_R RW 6 1 2 0_0402_5% SD_D3 Close to Connector SD_CMD 2
EMC@ CW 8 1 2 .1U_0402_10V6-K SD_CLK 5 CMD
EMC_NS@ CLK

2
SD_CMD_R RW 7 1 2 15_0402_5% SD_CMD 3 12
CW 11 1 2 5.6P_0402_50V8-D 6 VSS1 GND_1 13

5P_0402_50V8-C
EMC@ 1

2
CW 13 VSS2 GND_2
SD_CLK_R RW 8 1 2 15_0402_5% EMC@ SD_CLK EMC_NS@ DEREN_404232501111RHF_NR
EMC@ CW 12 1 2 5.6P_0402_50V8-D ME@
2
EMC@

Close to UW1 Placement SD / MMC

Close to Connector
CW11,CW12 need to change 5.6pf CAP as EMC request

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2015/12/11 Cardreader

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 30 of 60
3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 31 of 59
5 4 3 2 1
 5 4 3 2 1

D D

+3VS
+3VS_TPM
1A RTPM11 TPM@ 2 0_0603_5%
1 1
1 CTPM3
CTPM4 CTPM1 .1U_0402_10V6-K
TPM .1U_0402_10V6-K
2
10U_0603_6.3V6M
2
TPM@
TPM@ TPM@
2

C C

+3VS_TPM
UTPM1 TPM@
1 24
2 NC_1 VPS_1 10
3 NC_2 VPS_2
7 NC_3 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
SERIRQ LPC_AD0_TPM SERIRQ 9,44
6 26 RTPM6 1 TPM@ 2 0_0402_5%
NC_4 LAD0 LPC_AD1_TPM LPC_AD0 7,44
9 23 RTPM7 1 TPM@ 2 0_0402_5%
VNC_1 LAD1 LPC_FRAME#_TPM LPC_AD1 7,44
22 RTPM8 1 TPM@ 2 0_0402_5%
LFRAME# LPC_AD2_TPM LPC_FRAME# 7,44
4 20 RTPM9 1 TPM@ 2 0_0402_5%
11 GND_1 LAD2 17 LPC_AD3_TPM 1 TPM@ 2 0_0402_5% LPC_AD2 7,44
RTPM10
GND_2 LAD3 LPC_AD3 7,44
18
+3VS_TPM GND_3 25 +3VS_TPM
5 NC_11 21
NC_5 LCLK CLK_PCI_TPM 8
8 19
12 VNC_2 NC_10 15 RTPM4 1 TPM@ 2 0_0402_5%
13 NC_6 NC_9
14 NC_7 16
NC_8 LRESET# PLT_RST# 8,19,37,40,44
B ST33ZP24AR28PVSP_TSSOP28 B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 32 of 59
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

CMOS Camera
+3VS
+LCDVDD_CON
+5VS +3VS_CMOS
U5
5 1 W=60mils Need short
IN OUT J1 @ W=40mils
2 1 2

C121

C122

C123
33P_0402_50V8J
.1U_0402_10V6-K
4.7U_0603_6.3V6K
1 GND 1 2
1 1 1
C1 PCH_ENVDD 4 3 JUMP_43X39
EN FLG W=40 mils 1 1
D .1U_0402_10V6-K C3 C4 D
2 .1U_0402_10V6-K 10U_0603_6.3V6M

EMC_NS@
AP22802AW 5-7_SOT25-5 2 2 2 CD@ @
+3VS 2 2
U5 EN PIN VIH MIN 1.5V @ 0_0805_5%
2 1 R277

@
PCH_ENVDD For RF
4 PCH_ENVDD

1
R1
100K_0402_5%

2
+3VS

EMI request

2
R8 R9
100K_0402_1% 100K_0402_1% DISPOFF# INVT_PW M
+3VS

470P_0402_50V7K
C12

C13
470P_0402_50V7K
@ @

1
1 1
2

EMC_NS@ EMC_NS@
R10 EDP_AUX
4.7K_0402_5% B+ +LEDVDD EDP_AUX#
@ 2 2
2A 80 mil 0_0805_5% 2A 80 mil
1

2
2 1 R17

4.7U_0805_25V6-K
R12 1 @ 2 0_0402_5% DISPOFF# C14 R13 R15
C 44 BKOFF# C

0.1U_0402_25V6
1 1 100K_0402_1% 100K_0402_1%
C15
R14 1 @ 2 0_0402_5% ENBKL @ @

1
4 PCH_ENBKL ENBKL 44
1

2 2
R16 EMI Request JEDP1
100K_0402_5% +LEDVDD
1
CD@ 2 1
EMC@ 2
3
2

4 3
CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5 4
4 CPU_EDP_TX0+ CPU_EDP_TX0- 1 2 .1U_0402_10V6-K EDP_TX0- 6 5
C16
4 CPU_EDP_TX0- 7 6
+3VS CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8 7
4 CPU_EDP_TX1+ CPU_EDP_TX1- 1 2 .1U_0402_10V6-K EDP_TX1- 9 8
C18
4 CPU_EDP_TX1- 10 9
10
2

CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11

4 CPU_EDP_AUX CPU_EDP_AUX# C21 1 2 .1U_0402_10V6-K EDP_AUX# 12 11
R18
4 CPU_EDP_AUX# 13 12
1K_0402_5%
@ DISPOFF# 14 13
15 14
1

INVT_PW M 16 15
R19 1 2 0_0402_5% INVT_PW M 17 16
4 PCH_EDP_PW M 18 17
@
19 18
4 CPU_EDP_HPD 19
1

20
R20 21 20
+LCDVDD_CON 21
100K_0402_5% W=60mils 22
23 22
+3VS 23
43 DMIC_DATA
24
2

25 24
43 DMIC_CLK 25
26 31
27 26 G1 32
R182 1 2 0_0402_5% USB20_P5_R 28 27 G2 33
9 USB20_P5 2 0_0402_5% USB20_N5_R 28 G3
B R183 1 29 34 B
9 USB20_N5 30 29 G4 35
+3VS_CMOS 30 G5
2
W=40mils ACES_50406-03071-001
C24 ME@
0.047U_0402_16V7K
EMC_NS@ 1

EMI request

For EMI
L12 EMC_NS@
USB20_P5 1 2 USB20_P5_R
1 2

USB20_N5 4 3 USB20_N5_R
4 3
CMM21T-900M-N_4P

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 eDP/ CMOS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Monday, May 11, 2015 Sheet 33 of 59
3 2 1
 5 4 3 2 1

L2 EMC@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON
1 2

HDMI_CLK+_C 4 3 HDMI_CLK+_CON
4 3
EXC24CH900U_4P
+3VS
D EXC24CH900U_4P D
HDMI_TX0+_C 4 3 HDMI_TX0+_CON
4 3

HDMI_TX0-_C 1 2 HDMI_TX0-_CON
1 2

5
L3 EMC@

G
Q1B D3
L4 EMC@ HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX1-_C 1 2 HDMI_TX1-_CON
1 2 4 3 HDMICLK_R HDMIDAT_R 2 2 HDMIDAT_R
9 8

S
4 DDPB_CLK

D
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 2N7002KDWH_SOT363-6 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3

2
G
EXC24CH900U_4P Q1A +5VS_HDMI 5 5 6 6 +5VS_HDMI

L5 EMC@ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 6 HDMIDAT_R

S
1 2 4 DDPB_DATA

D
8
2N7002KDWH_SOT363-6
HDMI_TX2+_C 4 3 HDMI_TX2+_CON
4 3 AZ1045-04F_DFN2510P10E-10-9
EXC24CH900U_4P EMC_NS@

For EMC

C C
HDMI_CLK-_C R29 1 2 470_0402_5% +5VS +5VS_HDMI_F +5VS_HDMI
D5
HDMI_CLK+_C R30 1 2 470_0402_5% +5VS 2 F1
+3VS 1 1 2
HDMI_TX0-_C R31 1 2 470_0402_5% 3

2
D4 RB491D_SOT23-3 0.5A_8V_KMC3S050RY
HDMI_TX0+_C R32 1 2 470_0402_5% @

HDMI_TX1-_C R33 1 2 470_0402_5% @ LP2301ALT1G_SOT23-3

2
HDMI_TX1+_C R34 1 2 470_0402_5% BAT54S-7-F_SOT23-3 1 3 Q22

S
R35

1
2
Q12 D4

G
1M_0402_5%
HDMI_TX2-_C R37 1 2 470_0402_5% 1
C34

G
1

2
HDMI_TX2+_C R38 1 2 470_0402_5% .1U_0402_10V6-K

4
3
3 1
4 HDMI_HPD 46 SUSP 2

D
1

D Q13 2N7002KW_SOT323-3 RP1

2
+3VS 2
G 2N7002KW_SOT323-3 R41 2.2K_0404_4P2R_5%

1
2
20K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
R42 1 @ 2 18 HP_DET
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
4 HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 22 B
4 HDMI_CLK+ CK+ GND3
HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 23
4 HDMI_TX0- D0- GND4
8
HDMI_TX0+ C38 2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield
4 HDMI_TX0+ D0+
HDMI_TX1- C39 2 1 .1U_0402_10V6-K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
4 HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
4 HDMI_TX1+ D1+
HDMI_TX2- C41 2 1 .1U_0402_10V6-K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
4 HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
4 HDMI_TX2+ D2+
SINGA_2HE3Y37-000111F
ME@

Close to JHDMI1
D6 D7
HDMI_TX0-_CON 1 1 10 9 HDMI_TX0-_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_TX0+_CON 2 2 9 8 HDMI_TX0+_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_CLK-_CON 4 4 7 7 HDMI_CLK-_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_CLK+_CON 5 5 6 6 HDMI_CLK+_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 34 of 59
3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 35 of 59
3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 36 of 59
3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms＜spec＜100ms +3VALW_LAN +LAN_VDDREG
Need short
JL1 1 2 @ width : 40 mils RL1 1 @ 2 0_0603_5%
1 2
JUMP_43X79
D D
1 1
CL1 CL2

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K
CL4 CL5 CL6 CL7 CD@
2 2

@ 2 @ 2 2 2

Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

UL1
LAN_CLKREQ#_R RL18 2 @ 1
LAN_CLKREQ# 8,9
0_0402_5%

RL6 1 @ 2 0_0402_5% PCIE_WAKE#_R

44 LAN_WAKE#
33
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# C
AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 8
RL8 1 2 RSET 31 15
+LAN_VDD10 30 RSET REFCLK_P 14 PCIE_PTX_C_DRX_N3 CLK_PCIE_LAN 8
2.49K_0402_1%
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 9
29 13
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P3 9
28 12
+3VS +3VALW_LAN TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- 38
TL4 @ 1 25 9
LED2 MDIP3 LAN_MDI3+ 38
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 RL21 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 38
1K_0402_1% 10K_0402_5% 22 6
PCIE_WAKE#_R DVDD10 MDIP2 LAN_MDI1- LAN_MDI2+ 38
21 5
20 LANWAKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 38
@ ISOLATE#
LAN_MDI1+ 38
2

PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10

8,19,32,40,44 PLT_RST# PCIE_PRX_C_DTX_N3 PERSTB AVDD10_1 LAN_MDI0-
9 PCIE_PRX_DTX_N3 CL10 1 2 .1U_0402_10V6-K 18 2
LAN_DISABLE# PCIE_PRX_C_DTX_P3 HSON MDIN0 LAN_MDI0+ LAN_MDI0- 38
ISOLATE# 9 PCIE_PRX_DTX_P3 CL11 1 2 .1U_0402_10V6-K 17 1
HSOP MDIP0 LAN_MDI0+ 38

CL10 close to Pin18

1

PLT_RST#
RL11 CL11 close to Pin17
15K_0402_5% 1
@ CL34
.1U_0402_10V6-K
2

EMC_NS@ RTL8111GUL-CG_QFN32_4X4
2 @

100M LAN
B B

LAN_XTALI For RTL8111GUL/ RTL8106EUL (SWR mode)

@ +LAN_VDD10
YL1 LAN_XTALO RL20 1 2 0_0805_5%

1 4
OSC1 GND2 +LAN_REGOUT LL1 1 2
2 3 2.2UH_NLC252018T-2R2J-N_5%
GND1 OSC2
1 1 1 1 1 1 1 1 1
1 1
CL12 CL13 CL33 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
10P_0402_50V8J 25MHZ_10PF_7V25000014 10P_0402_50V8J .1U_0402_10V6-K
4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
2 @ 2 2 CD@ 2 2 2 2 2 @ 2 @
2 2

Close to Pin3, 8, 22, 30 Close to Pin30(Reserved)

Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 LAN_RTL8106EUL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Thursday, May 14, 2015 Sheet 37 of 59
5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
TL1 @
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0- 23 2 LAN_MDO0-
AZ3033-04F_DFN2525P10E10 37 LAN_MDI0- MX1+ TD1+
LAN_MDI2+ 7 1 LAN_MDI3+ LAN_MDI0+ 22 3 LAN_MDO0+
I/O3 I/O1 37 LAN_MDI0+ MX1- TD1-

1
6 8 21 4 MCT RL17
NC3 NC4 MCT2 TCT2 20_0603_5%

1
5 11 LAN_MDI1- 20 5 LAN_MDO1- EMC@
+3VALW_LAN VDD GND 37 LAN_MDI1- MX2+ TD2+
4 DL3

1
2
NC2 10 LAN_MDI1+ 19 6 LAN_MDO1+ PDT5061_DO-214AA
NC5 37 LAN_MDI1+ MX2- TD2-
2 EMC_NS@
NC1

2
LAN_MDI2- 9 3 LAN_MDI3- 18 7 MCT
I/O4 I/O2 MCT3 TCT3

2
DL1 EMC_NS@ LAN_MDI2+ 17 8 LAN_MDO2+
37 LAN_MDI2+ MX3+ TD3+
LAN_MDI2- 16 9 LAN_MDO2-
37 LAN_MDI2- MX3- TD3-
15 10 MCT
MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL25
37 LAN_MDI3+ MX4+ TD4+
DL2 EMC_NS@ CL32 1000P_1206_2KV7-K
LAN_MDI1+ 9 3 LAN_MDI0+ 1 LAN_MDI3- 13 12 LAN_MDO3- 0.022U_0603_50V7K EMC@
I/O4 I/O2 37 LAN_MDI3- MX4- TD4- 2 2
2 CL24 EMC@
NC1 10 68P_0402_50V8J
C NC5 C
4 EMC@ GST5009 LF
5 NC2 11 2
+3VALW_LAN VDD GND
6 8
NC3 NC4
LAN_MDI1- 7 1 LAN_MDI0-
I/O3 I/O1
AZ3033-04F_DFN2525P10E10
100M LAN CHASSIS1_GND

Place Close to TL1

JRJ1

LAN_MDO0+ 1
PR1+
LAN_MDO0- 2
PR1-
LAN_MDO1+ 3
PR2+
LAN_MDO2+ 4
PR3+
B B
LAN_MDO2- 5
PR3-
LAN_MDO1- 6
RL14 1 @ 2 0_0603_5% PR2-
LAN_MDO3+ 7
RL15 1 @ 2 0_0603_5% PR4+
LAN_MDO3- 8
RL16 1 @ 2 0_0603_5% PR4- 9
GND_1
10
GND_2

CHASSIS1_GND
Reserve for EMI go rural solution ALLTO_C100JH-10839-L CHASSIS1_GND
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 LAN_Transformer

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Wednesday, May 13, 2015 Sheet 38 of 59
5 4 3 2 1
 5 4 3 2 1

D D

+3VALW
+3VALW
Near CPU
Near GPU&VRAM

1
R36
13.7K_0402_1% R25
OPT@ 13.7K_0402_1%

2
NTC_V1

2
NTC_V2

1
PH2
100K_0402_1%_NCP15WF104F03RC PH3
OPT@ 100K_0402_1%_NCP15WF104F03RC

2
2

2
R257 R253
0_0402_5% 0_0402_5%
OPT@ @

1
C C

EC_AGND

+5VLP +5VLP for layout optimized, change the EC_AGND to GND

+5VLP

HW thermal sensor

2
C189 R252 R255
1

0.1U_0402_25V6 21.5K_0402_1% 21.5K_0402_1%

@ @
@
2

1
@
U4
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 R256 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
54 EC_ON_R OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R254 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

over temperature threshold:

B
RSET=3*RTMH B
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

FAN Conn

+5VS
JFAN1
R52 1 @ 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2
1 1 44 EC_FAN_PWM 3
C50 4 3
C49 .1U_0402_10V6-K 5 4
10U_0805_10V6K @ 6 GND1
2 2 GND2
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 39 of 59

3 2 1
 A B C D E

1 1

Mini-Express Card(WLAN/WiMAX)
+3VS Need short +3VS_W LAN
J2 @
1 2
1 2
JUMP_43X79

+3VS_W LAN

+1.5VS

1
C1107
0.047U_0402_16V4Z R80
1 2 BT_DISABLE# 2 @ 0_0603_5%
R269 1K_0402_5% JW LAN1 For RF request
1 2 @

2
3 1 2 4
1K_0402_5% 2 1 R53 BT_OFF# 5 3 4 6 +1.5VS_W LAN
9 PCH_BT_OFF# 7 5 6 8
8 W LAN_CLKREQ# 7 8
2 9 10 2
11 9 10 12
8 CLK_PCIE_W LAN# 13 11 12 14
8 CLK_PCIE_W LAN 15 13 14 16
15 16

17 18
19 17 18 20
21 19 20 22 PLT_RST# PCH_W LAN_OFF# 9
23 21 22 24 1 2 0_0402_5% PLT_RST# 8,19,32,37,44
R270 @ +3VS_W LAN
9 PCIE_PRX_DTX_N4 25 23 24 26
9 PCIE_PRX_DTX_P4 27 25 26 28
29 27 28 30 SMB_CLK_S3_R R263 1 2 @ 0_0402_5%
31 29 30 32 SMB_DATA_S3_R 1 2 @ 0_0402_5% SMB_CLK_S3 7,15
R88
9 PCIE_PTX_C_DRX_N4 33 31 32 34 SMB_DATA_S3 7,15
9 PCIE_PTX_C_DRX_P4 35 33 34 36
+3VS_W LAN 37 35 36 38 USB20_N6 9
39 37 38 40 USB20_P6 9
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
EC_TX R184 1 @ 2 0_0402_5% 49 47 48 50
44 EC_TX EC_RX R185 1 2 0_0402_5% BT_DISABLE# 51 49 50 52
44 EC_RX 51 52
53 54
53 54
2

ARGOS_MPCET-S5201-TP40
R94 ME@
100K_0402_5%
1

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 PCIe WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 40 of 59
D E
 A B C D E

+USB_VCCA

LEFT SIDE USB PORT X2 C55 1 2

+
@
220U_6.3V_M
1 1 C56 1 2
@ 1U_0603_25V6M
+5VALW +USB_VCCA C1108 C1109
U2 22U_0805_6.3V6M 22U_0805_6.3V6M C57 1 2
5 1 2 2 @ 470P_0402_50V7K
1 IN OUT 1
1
C128 2
1U_0402_6.3V6K GND JUSB1
4 3 USB_OC1# 1
2 44 USB_ON# EN FLG USB_OC1# 9 USB20_N0 R65 1 @ 2 0_0402_5% USB20_N0_R 2 VBUS
9 USB20_N0 USB20_P0 USB20_P0_R D-
1 R64 1 @ 2 0_0402_5% 3
9 USB20_P0 D+
AP22802BW5-7_SOT25-5 C140 4 5
1000P_0402_50V7K GND GND1 6
EMC_NS@ GND2 7
Low Active 2A 2 GND3 8
GND4
ALLTO_C107X3-10439-L
ME@

USB20_P0_R
+USB_VCCA
USB20_N0_R

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1

1
D9 D10 D11

1
2 2

2
L8 EMC@
USB20_N0 1 2 USB20_N0_R EMC_NS@ EMC_NS@ EMC_NS@

2
1 2

USB20_P0 4 3 USB20_P0_R
4 3
EXC24CH900U_4P
USB20_P1_R
D12 EMC_NS@
USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_N1_R

USB30_RX_R_P1 8 2 USB30_RX_R_P1

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
9 2

1
D13 D14
USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1

1
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1
EXC24CH900U_4P
USB30_RX_N1 2 1 USB30_RX_R_N1 3 3
2 1

2
8 EMC_NS@ EMC_NS@

2
USB30_RX_P1 3 4 USB30_RX_R_P1
3 4 AZ1045-04F_DFN2510P10E-10-9
L9 EMC@

3 3
For EMC
EXC24CH900U_4P
USB30_TX_C_N1 2 1 USB30_TX_R_N1
2 1
+USB_VCCA
USB30_TX_C_P1 3 4 USB30_TX_R_P1
3 4 C62 1 2
L10 EMC@ @ 1U_0603_25V6M

C63 1 2
L11 EMC@ @ 470P_0402_50V7K
USB20_P1 1 2 USB20_P1_R
1 2
JUSB2 ME@
USB20_N1 4 3 USB20_N1_R USB30_TX_P1 C64 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R68 1 @ 2 0_0402_5% USB30_TX_R_P1 9
4 3 9 USB30_TX_P1 StdA_SSTX+
1
EXC24CH900U_4P USB30_TX_N1 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R69 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
9 USB30_TX_N1 USB20_P1 USB20_P1_R StdA_SSTX-
R70 1 @ 2 0_0402_5% 3
9 USB20_P1 D+
7
USB20_N1 R71 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
For EMC 9 USB20_N1 USB30_RX_P1 USB30_RX_R_P1 D- GND_1
R72 1 @ 2 0_0402_5% 6 11
9 USB30_RX_P1 StdA_SSRX+ GND_2
4 12
USB30_RX_N1 R73 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
9 USB30_RX_N1 StdA_SSRX- GND_4
SUYIN_020053GR009M2736L
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 USB2.0/USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 41 of 59

C D E
 A B C D E F G H

SATA HDD Conn.

FOR 14"
JHDD1

1
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND_1
7 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 A+
C67 1 2 .01U_0402_16V7-K 3
7 SATA_PTX_DRX_N0 A-
4
1 SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
7 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B- JODD1
7 SATA_PRX_DTX_P0 7 B+ 1
GND_3 SATA_PTX_DRX_P1 14@ C70 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 2 GND_1
7 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1_14 RX+
14@ C71 1 2 .01U_0402_16V7-K 3
7 SATA_PTX_DRX_N1 RX-
8 4
9 V33_1 SATA_PRX_DTX_N1 14@ C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 5 GND_2
10 V33_2 7 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_14 6 TX-
+5VS +5VS_HDD 11 V33_3 7 SATA_PRX_DTX_P1 7 TX+
Need short 12 GND_4 8 GND_3
J3 @ 13 GND_5 9 DP
1 2 14 GND_6 +5V_ODD 10 +5V_1
1 2 15 V5_1 11 +5V_2
JUMP_43X79 16 V5_2 12 MD 14
17 V5_3 13 GND_4 GND1 15
18 GND_7 GND_5 GND2
19 DAS/DSS ALLTO_C185T1-11339-L
+5VS_HDD 20 GND_8 23 ME@
21 V12_1 GND1 24
22 V12_2 GND2
V12_3
1 1 1 1 1
C74 C75 C76 C77 C78 ALLTO_C166FE-12239-L
1000P_0402_50V7K .1U_0402_10V6-K 1U_0402_10V6K 10U_0805_10V6K 10U_0805_10V6K ME@
EMC_NS@ CD@ @
2 2 2 2 2

FOR 15"
2 2

For EMC SATA ODD FFC Conn

JODD2
1
+5V_ODD 2 1
3 2
SATA_PRX_DTX_P1 15@ C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 4 3
SATA_PRX_DTX_N1 15@ C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 5 4
6 5
SATA_PTX_DRX_N1 15@ C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 7 6
SATA_PTX_DRX_P1 15@ C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 8 7
+5VS +5V_ODD 9 8
Need Short 10 GND_1
J4 GND_2
1 2 ACES_51524-00801-001
1 2
ME@
10U_0805_10V6K

JUMP_43X79
.1U_0402_10V6-K

1 1

3 2 2 3
C86
C85

CD@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 42 of 59
E F G H
 5 4 3 2 1

+3VS
+3VS +3VL
RA2 1 @ 2 0_0603_5% +3.3VD
RA11 1 @ 2 0_0402_5% DVDD_IO RA43 1 @ 2 0_0603_5% AVDD_HP +5VA AVDD_HP

.1U_0402_10V6-K

.1U_0402_10V6-K
.1U_0402_10V6-K

CA11

CA12
2 2
2
+5VS CA1

RA7 1 @ 2 0_0603_5% +5VA Close to Pin3 1 1

1
D D
RA10 1 @ 2 0_0603_5% +5VD

Close to Pin7 Close to Pin28 Close to Pin24

4.7U_0603_10V6-K
.1U_0402_10V6-K
CA16 close to Pin18
2 1 CA17 close to Pin2
DA1 Close to Pin27
44 BEEP# 2
.1U_0402_10V6-K
1 2

.1U_0402_10V6-K

1U_0402_6.3V6K
PC_BEEP1 PC_BEEP

CA3
1 CA2 1 2

CA4

CA7

CA8
UA1 2 1

.1U_0402_10V6-K

2.2U_0603_6.3V6K
9 PCH_BEEP 3
RA14 2 1
HDA_RST_AUDIO# FILT_1.8V

CA5

CA6
BAT54CW_SOT323-3 10K_0402_5% 9 3
7 HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO CD@ 1 2
VDD_IO 2
2

HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2

7 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
7 HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
7 HDA_SDIN0 SDATA_IN AVDD_5V

.1U_0402_10V6-K

1U_0402_6.3V6K
HDA_SDOUT_AUDIO 4
7 HDA_SDOUT_AUDIO SDATA_OUT

CA10
CA9
2 1
PC_BEEP 10 12 SPK_L+
SPKR_MUTE# 39 PC_BEEP
SPKR_MUTE#
CX11802 LEFT+
LEFT-
14 SPK_L-

JSENSE 38 17 1 2

LINE_B_R
LINE_B_L
MIC1 RA44 2 1 2.2K_0402_5% MICBIASC 37 JSENSE RIGHT+ 15
GPIO1/PORTC_R_MIC RIGHT-
1 CA37 1 2 1U_0402_6.3V6K RA40 1 2 100_0402_5% 36 35 MICBIASC
OUTPUT 33_0402_5% 1 RA18 2 DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
33 DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
MICBIASB Close to Pin29
2 RA19 1 @ 2 DMIC_DATA_R 1 MICBIASB
A MIC GND 33 DMIC_DATA DMIC_DAT/GPIO1

4
3
C 0_0402_5%
@ 33 LINE_B_R C
.1U_0402_10V6-K PORTB_R_LINE 32 LINE_B_L RPA2
NEIM1000032_2P +5VD 1 2 11 PORTB_L_LINE
CLASS-D_REF 100_0404_4P2R_1%
CA13 30 PORTD_A_MIC
PORTD_A_MIC

1
3K_0402_1%

3K_0402_1%
13 31 PORTD_B_MIC

n
1
2
LPWR_5.0 PORTD_B_MIC

RA37

RA38
16
RPWR_5.0 25 RING2_CONN
HGNDA 1 1
EC_MUTE# RA35 1 @ 2 SPKR_MUTE# CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN
44 EC_MUTE# FLY_P HGNDB
0_0402_5% 20 CA35 CA36

2
+3.3VD

FLY_N 24 AVDD_HP 4.7U_0603_10V6-K 4.7U_0603_10V6-K

CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2 RPA3
AVEE 23 HPOUT_R 1 4 HP_OUTR
41 PORTA_R 22 HPOUT_L 2 3 HP_OUTL
GND PORTA_L
2

@ C186 1 2 .1U_0402_10V6-K
RA15 82.5_0404_4P2R_1%
5.11K_0402_1% @ C187 1 2 .1U_0402_10V6-K RPA1
PORTD_A_MIC 2 3 CA20 1 2 2.2U_0603_6.3V6K RING3_CONN
@ C188 1 2 .1U_0402_10V6-K CX11802-33Z_QFN40_5X5 PORTD_B_MIC 1 4 CA21 1 2 2.2U_0603_6.3V6K RING2_CONN
1

RA45 1 2 100_0404_4P2R_1%
5.11K_0402_1% RA1 1 @ 2 0_0402_5%
RA46 1 2
10K_0402_1% RA4 1 @ 2 0_0402_5%
PLUG_IN RA17 1 2 JSENSE JSPK1
39.2K_0402_1% RA6 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA32 SPK_L+ RA30 1 2 BLM18PG221SN1D_2P SPK_L+_CONN 1
RA36 1 2 15_0402_5% 1 CD@ 2 RA33 SPK_L- RA34 1 2 BLM18PG221SN1D_2P SPK_L-_CONN 2 1
20K_0402_1% RA9 1 @ 2 0_0402_5% EMC@ 3 2
4 G1
EMC@
RA12 1 @ 2 0_0402_5% G2

220P_0402_50V7K

220P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
CA29

CA30
ACES_50273-0020N-001
CD@ CD@ +5VD DMIC_CLK RA13 1 @ 2 0_0402_5% 2 2 1 1
on

CA31

CA32
B DMIC_DATA ME@ B
4.7U_0603_10V6-K

4.7U_0603_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
CA15

CA16

CA18

CA19

1 1 2 2
100P_0402_50V8J

100P_0402_50V8J
CA38

CA39

1 1 2 2 GND GNDA
EMC_NS@

EMC_NS@

1 1
Use 250mils wide trace bridging
EMC@ EMC@
2 2 1 1 AGND and DGND at codec
2 2
CD@ CD@

For EMI FOR ESD Close to Connector

Close to Pin11,13,16
Audio Jack JHP1

RING3_CONN 3
HP_OUTL R190 1 2 0_0402_5% A_HP_OUTL_R 1
RING3_CONN @
RING2_CONN
HDA_RST_AUDIO# A_HP_OUTL_R 5
HDA_SYNC_AUDIO A_HP_OUTR_R
HDA_SDOUT_AUDIO PLUG_IN
RA27 1 EMC_NS@2 HDA_BITCLK_AUDIO PLUG_IN 6
27_0402_5% HDA_SDIN0 7
HP_OUTR A_HP_OUTR_R
AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

R191 1 2 0_0402_5% 2 G1
RING2_CONN
CA23

CA24

CA25

CA26

@ 4
1

1
22P_0402_50V8-J

22P_0402_50V8-J
68P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

56P 50V J NPO 0402

1 1 1 1 1 C185 1 D1 D2 D24 D25 D26

1

100P_0402_50V8J

100P_0402_50V8J
CA22

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

LOTES_AJAK00XX-P001A
1 1 ME@
470P_0402_50V7K
2 2 2 2 2 2 R188 1 2 1 2 C181 A_HP_OUTL_R C182 C183
2

2
EMC@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

0_0402_5% @ @ EMC@ EMC@

A R189 1 2 1 2 C184 A_HP_OUTR_R 2 2 A
For EMI
2

0_0402_5% @ @
470P_0402_50V7K

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Codec_CX11802

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Wednesday, May 13, 2015 Sheet 43 of 59
3 2 1
 5 4 3 2 1

For EMI RE1 1 2 0_0603_5%

For ESD +3VL
PLT_RST# CLK_PCI_EC RE2 1 @ 2 10_0402_5%

RE3 1 @ 2 0_0603_5%
1 1 Close EC +3VALW
CE1 CE2 +3VALW _EC
220P_0402_50V7K 10P_0402_50V8J CE3 +3VALW _R +3VALW _R
2 EMC@ EMC_NS@ 2 1 2 VCOREVCC
RE53 1 @ 2 0_0603_5%
.1U_0402_10V6-K +3VALW _R All capacitors close to EC +3VALW _R
1 1
CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
1 1 1 1 1 1 .1U_0402_10V6-K CE5

1
+3VS +3VALW _EC CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
RE54 1 @ 2 0_0603_5% 2 EC_AGND 2 RE5
D D
@ @ 10K_0402_5%
2 2 2 2 2 2
RE6 1 @ 2 0_0402_5% EC_AGND

2
CD@ LAN_W AKE#
LAN_W AKE# 37

minimum trace width 12 mil

114
121
127
Change RE6 to 0ohm jump

12

11

26
50
92

74
3
UE1

VCORE

VCC

AVCC
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VBAT

VSTBY(PLL)
+3VS

EC_FAN_SPEED RE10 1 2 10K_0402_5%

19 W RST#
4 24
+3VALW _R 9 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PW R_LED# 45 EC_FAN_PW M RE11 1 @ 2 10K_0402_5%
9,32 SERIRQ LPC_FRAME# 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# 45
7,32 LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 VCCST_PW RGD BATT_LOW _LED# 45 LPC_FRAME# 1 2 10K_0402_5%
RE7
1 2 7,32 LPC_AD3 8 LAD3/GPM3 PWM3/GPA3 30 VCCST_PW RGD {11}
DE1 @ PWM
7,32 LPC_AD2 9 LAD2/GPM2 PWM4/GPA4 31 EC_FAN_PW M SYS_PW ROK 8 1 2 100K_0402_5%
ENBKL RE9 @
7,32 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PW M 39
RB751V-40_SOD323-2 7,32 LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 SUS_VCCP BEEP# 43
8 CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7 LAN_W AKE# SUS_VCCP 57
RE8 1 2 100K_0402_5% W RST# 14 120
15 WRST# TMRI0/GPC4 124 SUSP# +5VS +3VS
9 EC_SMI# EC_RX 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# 46,55,56,57
1 40 EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
EC_TX 17 66
40 EC_TX LPCPD#/GPE6 ADC0/GPI0 NTC_V1 39

2
CE12 PLT_RST# 22 67
8,19,32,37,40
1U_0402_6.3V6K PLT_RST# LPCRST#/GPD2 ADC1/GPI1 NTC_V2 39
23 68 BATT_TEMP RE52 RE51
2 9 EC_SCI# 126 ECSCI#/GPD3 ADC2/GPI2 69 BATT_TEMP 52
46 PCH_CMOSP GA20/GPB5 ADC ADC3/GPI3 VR_IMVP_IMON 59 0_0402_5% 0_0402_5%
70 @
IT8586E/AX ADC4/GPI4 71 VR_CPU_PW ROK
ADP_I 53
10,59

1
ADC5/DCD1#/GPI5 72 +3VALW _R
ADC6/DSR1#/GPI6

45 KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
73 EC_RTCRST#_ON
TP_CLK RE12 2 1 4.7K_0402_5%

1
KSI1 59 78
KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 RE65 TP_DATA RE13 2 1 4.7K_0402_5%
45 KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC MAINPW ON 54
C KSI3 DAC 100K_0402_5% C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81
KSI4 DAC5/RIG0#/GPJ5 ENBKL 33
KSI5 63

2
+3VALW _R KSI6 64 KSI5 85 EC_ON_GPIO RE57 2 1 0_0402_5% +5VALW
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON {54}
KSI7
36 KSI7 PS2DAT0/TMB1/GPF1 87 PBTN_OUT# 8
KSO0
RPE2 EC_SMB_CK1 PAD 1 @ KSO1 37 KSO0/PD0 GPF2 88 USB_ON# RE15 1 2 100K_0402_5%
EC_SMB_CK1 EC_SMB_DA1 IT1 KSO1/PD1 Int. K/B PS2 GPF3 TP_CLK
2 3 PAD 1 @ KSO2 38 89
1 4 EC_SMB_DA1 PAD 1 @
IT2
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA TP_CLK 45
1 IT3 40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 45
PAD @ KSO4
1 IT4 41 KSO4/PD4 96
2.2K_0404_4P2R_5% PAD @ KSO5 EXTERNAL SERIAL FLASH +3VALW _R
IT5 42 KSO5/PD5 GPH3/ID3 97
KSO6
KSO7 43 KSO6/PD6 GPH4/ID4 98 PCH_PW R_EN 46
44 KSO7/PD7 GPH5/ID5 99 ACOFF 53
KSO8
+3VS 1 45 KSO8/ACK# GPH6/ID6 PCH_PW ROK 8,10
KSI7 PAD @ KSO9 SUSP# RE18 1 @ 2 100K_0402_5%
1 IT6 46 KSO9/BUSY 101 EC_SPI_CS0#
KSI6 PAD @ KSO10
1 IT7 51 KSO10/PE NC1 102 EC_SPI_SI
RPE3 W RST# PAD @ KSO11 SUSP# RE19 1 2 100K_0402_5%
1 4 EC_SMB_CK2 IT8 KSO12 52 KSO11/ERR# NC2 103 EC_SPI_SO
EC_SMB_DA2 KSO12/SLCT SPI Flash ROM NC3 EC_SPI_CLK
2 3 KSO13 53 105 SYSON RE21 1 2 100K_0402_5%
KSO14 54 KSO13 NC4
For factory EC flash KSO14 SUS_VCCP
2.2K_0404_4P2R_5% KSO15 55 RE23 1 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW # EC_ADAPTER_R RE28 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW # 45

@ ON/OFF 110 82
EC_ON RE58 2 45 ON/OFF PWRSW# EGAD/GPE1
1 0_0402_5% 111 SM Bus 83 VDDQ_PGOOD 55
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84
52,53 EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3
52,53 EC_SMB_DA1 PECI_EC SMDAT1/GPC2
5 H_PECI RE24 1 2 43_0402_5% 117 GPIO 77
118 SMCLK2/PECI/GPF6 GPJ1 100 EC_MUTE# 43
GPG2
EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106 EC_ADAPTER_R RE25 2 @ 1 0_0402_5%
7,19 EC_SMB_CK2 EC_SMB_DA2 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 PM_SLP_S5# 8
+3VL 7,19 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 ME_FLASH 7
SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON 55
BKOFF#
CRX0/GPC0 123 BKOFF# 33 PM_SLP_S3#
RE29 1 @ 2 0_0402_5% CE21 1 2 1000P_0402_50V7K
1 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 PCIE_W AKE# 8
RE27 @
125 VSTBY0 RI1#/GPD0 21 PM_SLP_S3# 8
59 EC_VR_ON PM_SLP_S4# 8 EMC_NS@
B GPE4 RI2#/GPD1 76 SYSON CE13 1 2 1000P_0402_50V7K
B
WAKE UP TACH2/GPJ0 NOVO# 45
48
TACH1A/TMA1/GPD7 47 EC_FAN_SPEED
EC_FAN_SPEED 39 EMC_NS@
USB_ON# 33 TACH0A/GPD6 19 RE30 1 @ 2 0_0402_5% VGA_AC_DET
41 USB_ON# 35 GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 20 VGA_AC_DET 19
RTS1#/GPE5 GPIO L80LLAT/GPE7 EMC Request
93
8 EC_RSMRST# CLKRUN#/GPH0/ID0

2 Reserve for VGA_AC_DET

9 EC_LID_OUT# 128 CK32KE/GPJ7
+3VL 8 AC_PRESENT CK32K/GPJ6 Clock

RE34 1 @ 2 0_0402_5% H_PROCHOT# 5

RE35 1 2 10K_0402_5% ON/OFF 59 VR_HOT#
AVSS

@
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

RTC_RST# 7

1
RE36 1 @ 2 10K_0402_5% BKOFF# QE1 D 1
IT8586E-AX_LQFP128_14X14 H_PROCHOT#_EC 2 CE14
1

27
49
91

75
113
122

RE38 1 2 10K_0402_5% LID_SW # G 47P_0402_50V8J

@

1
2N7002KW _SOT323-3 S 2 QE3 D

3
EC_RTCRST#_ON 2
RE40 1 2 10K_0402_5% BKOFF# G
EC_AGND +3VL
S 2N7002KW _SOT323-3

3
1
RE50
for EC version update to EX, manual modify PN to FX

1
100K_0402_5%
RE42
10K_0402_5%

2
PECI_EC @ CE15 1 2 47P_0402_50V8J

2
+3VL BATT_TEMP @ CE16 1 2 100P_0402_50V8J +3VS ACIN#

+3VALW _R ACIN# @ CE17 1 2 100P_0402_50V8J

1
1 D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% ON/OFF @ CE18 1 2 1U_0402_6.3V6K CE19 2 A
.1U_0402_10V6-K G ACIN 53
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 @ 1 0_0402_5% SPI_CS0#
SPI_CS0# 7NOVO# 2 S 2N7002KW _SOT323-3

3
GPG2 RE46 2 @ 1 10K_0402_5%
EC_SPI_SI RE47 2 @ 1 0_0402_5% SPI_SI
SPI_SI 7
.01U_0402_16V7-K

when mirror, GPG2 pull high

C48

when no mirror, GPG2 pull low EC_SPI_SO RE48 2 @ 1 0_0402_5% SPI_SO

SPI_SO 7 1 RE66 1 @ 2 0_0402_5%

EC_SPI_CLK SPI_CLK Security Classification LC Future Center Secret Data Title

RE49 2 @ 1 0_0402_5%
SPI_CLK 7 @2
Issued Date 2015/02/27 Deciphered Date 2013/08/05 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 44 of 59
3 2 1
 5 4 3 2 1

ON/OFF switch +3VL +3VALW

NOVO_BTN#
K/B Connector 15"

2
R82 R83
100K_0402_5% 100K_0402_5%

2
@
SW5 KSI[0..7] JKB1

1
KSI[0..7] 44
D15
NOVO# 2 KSO[0..17] 27
44 NOVO# KSO[0..17] 44 GND1 28
EVQP7L01K SPST
1 NOVO_BTN# KSO17 26 GND2
KSO16 25 26

4
ON/OFF R85 1 @ 2 0_0402_5% 3 KSO15 24 25
KSO10 23 24
BAT54CW_SOT323-3 KSO11 22 23
KSO14 21 22
D D
KSO13 20 21
KSO12 19 20
+3VALW +3VL KSO3 18 19
KSO6 17 18
KSO8 16 17
16

2
KSO7 15
R111 R114 KSO4 14 15
100K_0402_5% 100K_0402_5% KSO2 13 14
@ ON/OFFBTN# KSI0 12 13
KSO1 11 12

1
KSO5 10 11
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF KSI3 9 10
ON/OFF 44 8 9
KSI2
KSO0 7 8
KSI5 6 7
6

2
KSI4 5
SW6 KSO9 4 5
KSI6 3 4
NOVO_BTN# ON/OFFBTN# KSI7 2 3
EVQP7L01K SPST KSI1 1 2
1
ACES_88514-02601-071

4
ME@
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
1

1
D20 D21
1

1
EMC@ EMC@
2

2
2

2
For EMC

+5VS TP_PWR TP_CLK

C R160 1 @ 2
TP/B Connector TP_DATA Hall Sensor C

2
+3VS 0_0402_5%
JTP1 DT1
R141 1 2 1
0_0402_5% TP_CLK 2 1
44 TP_CLK TP_DATA 3 2
.1U_0402_10V6-K

44 TP_DATA TP_P4_CON 4 3
1 4
@1 @1 TP_P5_CON 5
100P_0402_50V8J

100P_0402_50V8J

TP_P6_CON 6 5 7
6 GND1 8
2 GND2
C114

2 2
C115

C116

ACES_50503-0060N-001
ME@ EMC_NS@ AZC199-02S.R7G_SOT23-3

1
TP_P4_CON
For EMC
R271 1 2
0_0402_5%
TP_P5 R272 1 2 TP_P5_CON
1
0_0402_5%
TP_P6 R273 1 2 TP_P6_CON C1105
0_0402_5%
TP_LEFT Button TP_P5 TP_LEFT Button TP_P5 U14 .1U_0402_10V6-K
TP_P5 R274 1 @ 2 TP_P4_CON 1 2
1 GND
0_0402_5% C1104
TP_P6 R275 1 @ 2 TP_P5_CON 0.01U_0402_25V7K 3 LID_SW#
OUTPUT LID_SW# 44
1

5
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
0_0402_5%
TP_P6_CON 2

AZ5215-01F_DFN1006P2E2
R276 1 @ 2 SW1 SW2 R262
EVQPLHA15_4P

EVQPLHA15_4P
GND1

GND1
A1

A1
A

A
1

1
0_0402_5% DT2 DT3 1 @ 2 +VCC_LID 2
+3VL VCC
0_0402_5% D17
1

1
AH9247NTR-G1_SOT23-3
GND2

GND2

For 14" For 15"

B1

B1
B

B
2

2
14@ 15@
EMC_NS@ EMC_NS@ EMC_NS@
1 VDD 1 VDD
3

2
2 CLK 2 CLK TP_RIGHT Button TP_RIGHT Button For EMC
TP_P6 TP_P6

3 DAT 3 DAT
1

B B
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

SW3 SW4
EVQPLHA15_4P

EVQPLHA15_4P
GND1

GND1
A1

A1
A

A
1

DT4 DT5
4 GND 4 TP-L
1

1
GND2

GND2

5 TP-L 5 TP-R
B1

B1
B

B
2

14@ 15@
EMC_NS@ EMC_NS@
3

6 TP-R 6 GND
For 14" For 15"

PWR_LED# LED1 1 2 R142 1 2 1.5K_0402_5%

LED 44 PWR_LED# +5VALW
1

D16 LTW-C193TS5
AZ5425-01F_DFN1006P2E2
1

EMC_NS@
2
2

BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%

44 BATT_LOW_LED# +3VALW
LTST-C193KFKT-LC
1

D18
AZ5425-01F_DFN1006P2E2
1

EMC_NS@

A A
2
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%

44 BATT_CHG_LED# +5VALW
LTW-C193TS5
1

D19
AZ5425-01F_DFN1006P2E2
1

Security Classification LC Future Center Secret Data Title

EMC_NS@
Issued Date 2015/02/27 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn.
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Wednesday, May 13, 2015 Sheet 45 of 59
5 4 3 2 1
 A B C D E

Load Switch
+5VALW To +5VS
+3VALW To +3VS
+3VS, C173 --> 2.74ms
+5VS, C176 --> 2.03ms
1
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
R1871 2 0_0402_5% 3VSON 1
+5VALW U13 +5VS
1 14 J12 @
2 VIN1_1 VOUT1_2 13 +5VS_LS 1 2
VIN1_2 VOUT1_1 1 2
1 5VSON 3 12 C176 1 2 1000P_0402_50V7K JUMP_43X118 1
SUSP# R27 1 2 0_0402_5% 5VSON EN1 SS1
C177 +5VALW 4 11 C174 @
1U_0402_6.3V6K BIAS GND 0.1U_0402_10V7-K
+3VALW 2 3VSON 5 10 C173 1 2 2200P_0402_25V7-K 2 +3VS
1 1 EN2 SS2 J11 @
C180 C179 6 9 +3VS_LS 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K 7 VIN2_1 VOUT2_2 8 1 2
@ 2 2 @ VIN2_2 VOUT2_1 JUMP_43X118
1 1
15
C178 GPAD C175 @
1U_0402_6.3V6K
Need Short
APL3523AQBI-TRG_TDFN14_2X3 0.1U_0402_10V7-K
2 @ 2

+5VALW
+3VALW +3VALW_PCH
+5VLP
2 2
1

R278 1 2
0_0603_5%

1
R155
100K_0402_5% R161 +0.675VS
@ 100K_0402_5%
2

1
PCH_PWR_EN#_R R158 1 @ 2 100K_0402_5% PCH_PWR_EN# LP2301ALT1G_SOT23-3 Id=3.2A

2
R159

D
Q29 3 1 SUSP 47_0603_5%
34 SUSP
1

Q30 D @
PCH_PWR_EN 2 1 1
44 PCH_PWR_EN

2
G C129 C130

G
2
.1U_0402_10V6-K 0.01U_0402_25V7K

3
@ S 2N7002KW_SOT323-3 @ @ Q6A D D Q6B
3
1

2 2 2 5 SUSP
44,55,56,57 SUSP# G G
R162 PCH_PWR_EN#_R
100K_0402_5% 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6

4
@ 1
2

R163 1 2 C131
44 PCH_CMOSP
0_0402_5% .1U_0402_10V6-K
@ @

1
2
R87
100K_0402_5%
@

2
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Thursday, May 14, 2015 Sheet 46 of 59

C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3

V
PU301 PU904 +3V_PCH

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801

V
PU501
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 47 of 59
3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Friday, May 15, 2015 Sheet 48 of 59
2 1
 5 4 3 2 1

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6

1
D D

H1 H2 H3 H4 H5 H6 NH7 H8 H9 H11 H13

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_C6P5D2P3 PAD_C6P5D2P3 PAD_C6P5D2P3 PAD_C6P5D2P3 PAD_C6P5D2P3 PAD_C6P5D2P3 PAD_O2P8X3P3D2P8X3P3N PAD_C6P5D2P3 PAD_C6P5D2P3 PAD_CB6P0D3P7 PAD_CB6P0D3P7

CPU
C C

H10 H12
HOLEA HOLEA

1
NH14 H15 PAD_CT5P0B6P0D3P2 PAD_CT5P0B6P0D3P2
HOLEA HOLEA GP1 GP2 GP3 GP4
PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2
@ @ @ @
Stand Off

1
1

pad_ct6p5b5p5d2p3

1
pad_c2p8d2p8n

CHASSIS1_GND

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 Hole

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 49 of 59
5 4 3 2 1
 5 4 3 2 1

B+
+5VLP/ 100mA
Silergy
D
Silergy D

SY8208CQNC +5VALW/5A SY8868QMC

Adaptor Converter QFN10_2X2 +1.05VS/5A
FOR SYSTEM Switch Mode
EC_ON EN PGOOD ALW_PWRGD FOR VDDR
PAGE 39
SUSP# EN PGOOD

+3VLP/ 100mA
Silergy
SY8206BQNC ANPEC
Converter +3VALW/4A

FOR SYSTEM APL5930KAI-TRG_SO8 +1.5VSP/1A

EC_ON EN PGOOD ALW_PWRGD
PAGE 39 LDO
FOR VDDR
SUSP# EN PGOOD

TI +1.35V/12A
TPS51716RUKR
SYSON S5 WQFN20_3X3 Silergy
C SUSP# S3 +0.675VS/2A C
TI Switch Mode SY8032ABC
FOR DDR PGOOD SOT23-6 +1.05VSP_VGA/2A
BQ24737RGRR Switch Mode
Battery Charger FOR VDDR
EN PGOOD
Switch Mode
PAGE 46 Onsemi
CPU Core/14A/32A
NCP81101MNTXG
QFN28_4X4
Switch Mode
VR_ON
SMBus EN FOR CPU Core PGOOD VGATE
PGOOD_NB

Battery Onsemi
B
Li-ion NCP81172MNTWG B

4S1P/41WH QFN24_4X4 +VGA_CORE/31A

VIDs
Switch Mode
NVDD_PWR_EN EN FOR GPU VDDC PGOOD VGA_PWRGD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize
R&D Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 50 of 59
3 2 1
 5 4 3 2 1

@
PJ101
2 1
2 1
VIN PR9408 maybe adjust value
JUMP_43X79 +3VL PR9471 0_0603_5%
PL707 EMC_NS@ 1 2
JDCIN1 HCB2012KF-121T50_0805 @ VCCRTC
1 APDIN 1 2
1 PD707
2 PR9408 0_0603_5%
2 3 PL708 EMC_NS@ 1 2 3
3

470P_0402_50V7K

470P_0402_50V7K
4 HCB2012KF-121T50_0805 RTC_VCC
4

1000P_0402_50V7K

1000P_0402_50V7K
5 1 2 1
5 JRTC1

1
BAT_D

PC101

PC102

PC103

PC104
D For EMI request 1 1 PR9400 2 2 D
1 2
SINGA_2DC3161-000111F 2
2 3 1K_0603_5% PC2
ME@

2
G1 4 change to 1K SD01310018J BAT54CW_SOT323-3 1U_0402_10V6K
@ @ G2 1
EMC@ EMC@ ACES_50273-0020N-001

ME@

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 51 of 59
3 2 1
 5 4 3 2 1
@
PJ202
2 1
2 1
VMB
JUMP_43X79
JBATT2 ME@
SUYIN_125022HB008M200ZL PL201
1 HCB2012KF-121T50_0805
1 2 1 2
9 2 3 EC_SMCA BATT+
EMC_NS@
10 GND1 3 4 EC_SMDA PL202
11 GND2 4 5 HCB2012KF-121T50_0805
12 GND3 5 6 1 2
GND4 6 7

1
EMC_NS@
7 8

1
100_0402_1%

100_0402_1%
PC201 PC202
8

PR201

PR202
1000P_0402_50V7K 0.01U_0402_25V7K

2
D D

EC_SMB_CK1 44,53

EC_SMB_DA1 44,53
PR203
1 2
+3VALW
100K_0402_1%

PR204
BATT_TEMP_IN 1 2
10K_0402_5%
BATT_TEMP A/D
44
1

PD306
1

@
2
2

AZ5215-01F_DFN1006P2E2

C C
3

EC_SMCA
EC_SMDA Reverse PD305 For EMI request

PD305
AZC199-02S.R7G_SOT23-3
@
1

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 52 of 59
2 1
 5 4 3 2 1

B+
P2 P3
PQ309 For EMI request BATT+ PQ303 B+
PQ301 PQ302 AON7408L_DFN8-5 PL302 PR316 AO4407AL_SO8
AO4407AL_SO8 SI4483ADY-T1-GE3_SO8 PR301 0.01_1206_1% 8 1
8 1 1 8 0.01_1206_1% PL710 1 4.7UH_PCMB063T-4R7MS_5.5A_20% 7 2
7 2 2 7 HCB2012KF-121T50_0805 2 LX_CHG 1 2 CHG 1 4 6 3
6 3 3 6 1 4 1 2 5 3 5
VIN 5 5 2 3

2
2 3 EMC@ PQ311

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

0.1U_0402_25V6
0.1U_0603_25V7-M

4
@

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
4

4
2

2
AON7408L_DFN8-5 4.7_0805_5%

PC109
PC1318

PC1317
2

2
PC301 PC302 PC303 PR317

PC305

PC306

PC307

PC319

PC320
D D
PQ304 1 2 10U_0805_25V6K 10U_0805_25V6K

1
1

@ @ 4

0.1U_0603_25V7-M

1
1
PR302 LTA044EUBFS8TL_UMT3F-3 100P_0402_50V8J

16251_SN
3

2
200K_0402_5% PR303 @ PR304
200K_0402_1% @ PC317 1 2 VIN

PC308
PU911 2 1
2

3
2
1
2 OZ8682LN_QFN16_3X3

2ACOFF-1
PC321 47K_0402_1%

2
DH_CHG 680P_0402_50V7K
1P2_G2

13 14 0.47U_0603_25V6-K

1SS355_SOD323-2
HDR LX @ PR305

DISCHG_G-1
2
ICHP 5 16 DL_CHG 10K_0402_1%
ICHP LDR

2
PR312 PD301
ICHN 4 12 BST_CHG 1 2 PR306
1

1
PR315 ICHM BST 2.2_0603_5% 200K_0402_1%
P2-1 1 2 737_SDA 11 1 VCC PD303
44,52 EC_SMB_DA1 SDA VAC
2 PR313 RB751V-40_SOD323-2

1
PQ305 10_0402_5% 2 737_SCL 10 15 VDDP 2 1 PQ308B
44,52 EC_SMB_CK1 SCL VDDP

1
LTC015EUBFS8TL_UMT3F-3 PR9468 2N7002KDWH_SOT363-6

3
44 ADP_I ADP_I
P2_G1

10_0402_5% 2 IAC 7 3 IACM PC315 D PD302

IACM IAC IACM 5PACIN_N 1 2 PACIN_P
CHARGER_GND 4.7U_0603_10V6-K
3

2
2
1
0_0402_5% 2 1 PR9467 2 8 2 IACP G
COMP IACP

BASE
IACP PC318 PC1315 0_0402_5%
2N7002KDWH_SOT363-6

1SS355_SOD323-2
100P_0402_50V8J 0.47U_0402_25V6K VDDP 1 2 6 9 PACIN 1 2 ACIN 44
S

4
VDDA ACAV
6

PQ307A D PR327

1
2 PR307 PR9466 10K_0402_1%

17

6
68K_0402_1%

1M_0402_5%
G 100_0402_5% PC1316 D

1
CHARGER_GND PR9469 PC313 2 PACIN

PR347
1U_0603_25V6M

2
S 100K_0402_5% PC1319 PC324 0.1U_0603_25V7-M G
1

CHARGER_GND 1000P_0402_25V7-K 0.1U_0603_25V7-M

2
ICHP @ S PQ308A

1
2N7002KDWH_SOT363-6
P2-2

ICHN
3

PR309 D PQ307B PJ711

PACIN 1 2 5 2N7002KDWH_SOT363-6 1 2
G
PACIN_G

47K_0402_1% JUMPER
C S @ C
4

CHARGER_GND
1

PR314 PQ998 D
1 2ACOFF-1 2
44 ACOFF G
0_0402_5% VIN
S 2N7002KW_SOT323-3
3
1

PR349
1M_0402_5%

2
PD706
2

RB751V-40_SOD323-2

2 1
PR308
20_0603_5%

1
VCC

1
PC314
0.47U_0603_25V6-K

2
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 53 of 59
5 4 3 2 1
 5 4 3 2 1

B+
PJ302 1.5A
2 1 +3V_VIN
2 1

1M_0402_5%
10U_0805_25V6K
0.1U_0402_25V6
1

PR335
PC1048
D D

PC1046

PC1047
JUMP_43X79 +3VBS 1 2

2
@ 0.1U_0603_25V7-M

2
PU200
+3VALW

1
SY8286BRAC_QFN20_3X3
21

IN5

IN3

IN2

IN1

BS
GND4 PL303 PJ303
+3V_LX 6 20 +3V_LX 1 2 +3VALW _P 2 1
LX LX3 2.2UH_PCMB063T-2R2MS_8A_20% 2 1
7 19 4A
GND1 LX2 JUMP_43X79
8 18
GND2 GND3
100mA +3VLP @
+3V_PW RGD 9 17

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PG LDO

1
@

1
10 16 PR338

4.7U_0603_6.3V6K
NC1 NC3

PC1049

PC1050

PC1051

PC1052
4.7_0805_5%

OUT

NC2
EN2

EN1

PC1055
@

FF

2
2

1 2
+3V_VIN 11

12

13

14

15
PTP1@
PAD PC1106
1000P_0402_50V9-J

2
@

+3VALW_P
PR337 PR9470
1 2 EC_ON_R 1 2 +3VALW _EN
44 EC_ON
0_0402_5% 0_0402_5%
PC1057
PR341
39 EC_ON_R 1 2 1 2
1

1
PR417 @ PC1054 PR339 1000P_0402_25V7-K 1K_0402_1%
2 1 0.1U_0402_25V6 1M_0402_5%
2

44 MAINPW ON 0_0402_5%
2

C @ @ C
+3VL
2
PR429
330_0603_5% +3VLP
@ PJ304
2 1
1 1

2 1
PQ405 D
1

2 JUMP_43X39
PR427 G PC425
100K_0402_5% 2.2U_0603_10V7K @
2

@ S @
3

2N7002KW _SOT323-3
2

@
+3VALW

2
PR342
100K_0402_5%

PR343 @

1
+3V_PW RGD 1 2

B+ 0_0402_5% @
PR344
PJ305 PU201 +5V_PW RGD 1 2
2.5A +5V_VIN
2
2 1
1 5 9 PC1061 +5VALW
4 IN1 PG 1 1 2
10U_0805_25V6K

10U_0805_25V6K

+5VBS 0_0402_5% @
0.1U_0402_25V6

3 IN2 BS
1

1
PC1060

PC1059

5A
SY8286CRAC_QFN20_3X3

2 IN3
PC1058

JUMP_43X79 0.1U_0603_25V7-M PL304 PJ306

IN4 6 +5VLX 1 2 +5VALW _P 2 1
2

7 LX1 19 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@ GND1 LX2
8 20 3.3UH_PCMB063T-3R3MS_6.5A_20%
GND2 LX3

1
18 JUMP_43X79
GND3

PC1063

PC1080

PC1090

PC1091
21 PR351 PR340
PR346 GND4 14 1 2+5VALW _P 4.7_0805_5%
@

2
EC_ON_R 1 2 +5VALW _EN 12 OUT @
B +5V_VIN 11 EN1 13 0_0402_5%
B

1 2
0_0402_5% EN2 FF
15
100mA
LDO +5VLP
1M_0402_5%

10 PC1107
NC1
1

16 17 1000P_0402_50V9-J
2

NC2 VCC
1

PR348

@
@ PC1069
0.1U_0402_25V6
2

4.7U_0603_6.3V6K
2

PC1070

PC1062
1U_0603_25V6M
1

PC1072
PR350
1 2 1 2

1000P_0402_25V7-K 1K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 54 of 59
3 2 1
 A B C D

B+ @ 2A
PJ501
2 1 1.35V_B+
2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
EMC@
PC503

PC504

PC505
@
JUMP_43X79 PJ502
2 1

2
1

0.1U_0603_25V7-M 2 1 1

PU501 0_0603_5% PC506 JUMP_43X118

1 10 BST_1.35V 1 PR506 2 2 1 0.68UH_PCMB063T-R68MN_16A_20%
VIN BST PL501 PJ503
PR501 0_0402_5% 9 LX_1.35V 1 2 1.35V_L 2 1
5 CPU_DRAMPG_CNTL 1 2 S3_1.35V 16 SW 2 1 +1.35V

NB685GQ-Z_QFN16_3X3
PR503 EN1 JUMP_43X118

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@ 44 SYSON 1 2 S5_1.35V 15 13 1.35V_FB @ 220P_0402_50V7K @
EN2 FB

1
PC515

PC517

PC518

PC519
0_0402_5% 0_0402_5% 2 1 2 1

EMC_NS@
2.2_0805_5%
44 VDDQ_PGOOD 1A DIS ------10A

PR508
44,46,56,57 SUSP# 2 PR511 1 1M_0402_5% PC510
2 1 12 6 1.35V_L PR513

0.1U_0402_10V7K

0.1U_0402_10V7K
+3VALW +0.675VSP

2
PR502 100K_0402_1% PG VDDQ

2
PC501 @
DDR_3V3

PC502
3 @

2
3V3

2
@ 5

1.35V_SN

41.2K_0402_1%
1U_0402_6.3V6K
VTT

PR509
PR512

2
PC509
4

4.7_0402_5%

1200P_0402_50V7-K
1K_0402_1%
AGND

PR507 2
8

1
2 VTTS

EMC_NS@
10U_0603_6.3V6-M
2

1
PGND

PC512
7 VTTREF
VTTREF @

1
1

PC508
Mode 14 11 PJ504

1
MODE OTW# 2 1

1U_0402_6.3V6K
+0.675VSP 2 1 +0.675VS
1.35V_FB

2
2

PC511
1.35V_GND
PR504 JUMP_43X79
+3VALW

1
0_0402_5%

2
PR510
33K_0402_1%

1
1.35V_GND

2
1.35V_GND
2 2

1.35V_GND

PJ505
1 2

JUMPER
@

1.35V_GND

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 1.35VS/+0.675VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 55 of 60
C D
 A B C D

+1.5VSP +1.5VS
50mA
50mA
PJ713 PU912 PJ712
2 1 3 4 2 1
1
+3VALW 2 1 VIN VOUT 2 1
1

4.7U_0603_6.3V6K

1
2
JUMP_43X39 GND JUMP_43X39 @

PC612
5

1
1 SET PR608

2
@ SHDN 21.5K_0402_1% PC613 PC614
APL5325BI-TRG_SOT23-5 220P_0402_50V7K 1U_0603_25V6M

2
PR609 @
1 2EN_1_5VSP
44,46,55,57 SUSP# VFB=0.8V
0_0402_5%

1
PC1320 SA000067W00 PR610
.1U_0402_10V6-K 24K_0402_1%

2
@

2
2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 +1.35VS_VGA/+1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 56 of 59
C D
 5 4 3 2 1

+3VS

2
PR701
10K_0402_5%

1_05VS_PG1
5A

22U_0805_6.3V6M
22U_0805_6.3V6M

9
PJ704 PU701 PL701 PJ702 +1.05VS
2 1 1_05VS_PVIN 1 2 1_05VS_LX 1 2 2 1

0.1U_0402_25V6

PG
+5VALW 2 1 VIN LX1 2 1

1
PC1066
D D

PC702

PC701
5 0.68UH_PCMC063T-R68MN_15.5A_20%
LX2

2
JUMP_43X79 JUMP_43X79

2
@ 6 @
@ LX3 4.7_0805_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@ @

1
4 10 PR703
EN OUT

PC703

PC704

PC705

PC706
@ PR704

1SNB_1_05VS 1
1 2 1_05VS_EN

2
44,46,55,56 SUSP# 8 7
0_0402_5%

GND
SS FB

47K_0402_5%
PR994

PR705
1 2

3
44 SUS_VCCP

1
SY8868QMC_QFN10_2X2 @
0_0402_5% PC709 PC711
.1U_0402_10V6-K 0.01U_0402_25V7K PC710
1

2
@ 680P_0402_50V7K

2
@ @

PR706
1_05VS_FB 2 1
75K_0402_1%

1
PR707
100K_0402_1%
2 1 PC712
22P_0402_50V8-J

2
VFB=0.6V
Vo=VFB*(1+PR706/PR705)
C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 +1.05VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 57 of 59
3 2 1
 5 4 3 2 1

D D

+VGA_B+

+3VGS PJ710
2 1 B+
2 1

2 PR9442 JUMP_43X79
10K_0402_5% @

10U_0805_25V6K

10U_0805_25V6K
@ PD705

1
PC1295

PC1298
RB751V-40_SOD323-2

0.1U_0402_25V6
1

1
OPT@ PQ991

NVVDD PWM_VID
1 2 EN_VGA AON6372_DFN8-5

PC1255
4,21 PXS_PWREN EN_VGA 21,22

2
OPT@

2
1

1
PC1303
PR9443 PR9444 .1U_0402_10V6-K 4
100K_0402_5% 1 2 OPT@

2
@ OPT@
10K_0402_1% PR9429 PC1300 EMC_OPT@ OPT@ OPT@
2

0_0603_5% 0.22U_0603_16V7K

3
2
1
2
2 1BOOT1_2_VGA 1 2
PR9430 OPT@ OPT@
NVVDD PWM_VID 0_0402_5% PL705
19 NVVDD PWM_VID +VGA_CORE
0.24UH_PCME063T-R24MS1R145_35A_20%
PSI_VGA reserve OPT@ 1 2
19 PSI_VGA

BOOT1_VGA
1
PQ992

5
VSSSENSE_VGA AON6764_DFN8-5 OPT@

10P_0402_50V8J
20 VSSSENSE_VGA

2
VCCSENSE_VGA

PC1261
20 VCCSENSE_VGA @

OPT@
2
GPU_VID 4.7_0805_5% 1 1
C DGPU_PWROK LGATE1_VGA 4 PR9435 C
21 DGPU_PWROK
PC1258 + PC1293 + PC1297

1
1 2 @ 330U_2.5V_M 330U_2.5V_M

1
OPT@ OPT@
UGATE1_VGA 2 2

PSI_VGA
2700P_0402_50V7-K OPT@ PR9438

3
2
1
EN_VGA
13K_0402_1%
PR9460 PR9461
VREF_VGA 1 2 1 2 OPT@ SF000007300

1
PHASE1_VGA
20K_0402_1% OPT@ 20K_0402_1% OPT@ PC1296
680P_0402_50V7K

REFADJ

2
5

1
PR9464 @
0_0402_5% PR9458 PR9459

UGATE1

BOOT1
EN
VID

PSI
OPT@ 2 1 1 2 1 2
PC1301
18K_0402_1% OPT@ 2K_0402_1% OPT@ 6 20 4.7U_0603_6.3V6K
PR9447 REFADJ PHASE1
PC1259
2 1 1 2 REFIN 7 19 1 2OPT@
PC1257 REFIN LGATE1
2700P_0402_50V7-K @ +VGA_B+ 1 2 VREF_VGA8 18 PVCC_VGA 1 2
100_0402_5% VREF PVCC +5VS
OPT@ 0.1U_0603_25V7K OPT@ PR9418 0_0603_5%
OPT@ PR9465
PR9449 0.1U_0402_25V6 PC1314 1 2 OPT@ OPT@ 1 2 9 17 OPT@
0_0402_5% 2 1 2.2_0603_5% PR9457 330K_0402_5% TON LGATE2
VSSSENSE_VGA OPT@ 2 1 VSS_SEN 10 16 +VGA_B+

UGATE2
RGND PHASE2

PGOOD

BOOT2
VSNS
GND
1

PC1269

SS
1000P_0402_50V7K PU910
PR9420 @

10U_0805_25V6K

10U_0805_25V6K
2

21

11

12

13

14

15

5
0_0402_5% RT8812AGQW_WQFN20_3X3

0.1U_0402_25V6
1

1
VCCSENSE_VGA OPT@ 2 1 VCC_SEN

PC1275

PC1276
PQ993
AON6372_DFN8-5

PC1273
1000P_0402_25V7-K
BOOT2_VGA OPT@

2
1
PC1256
UGATE2_VGA 4
PR9448

2
1 2 DGPU_PWROK
+VGA_CORE
OPT@ PR9425
B B
10K_0402_5% PR9424 PC1278

3
2
1
100_0402_5% 2 1 +3VGS 0_0603_5% 0.22U_0603_16V7K EMC_OPT@ OPT@ OPT@
OPT@ OPT@ 2 1OPT@ BOOT2_2_VGA 1 2
SS time down OPT@ PL706 +VGA_CORE
0.24UH_PCME063T-R24MS1R145_35A_20%
PHASE2_VGA 1 2
PQ994 OPT@

5
AON6764_DFN8-5

1
OPT@
PR9453
4.7_0805_5% 1 1
LGATE2_VGA 4 @
+ PC1280 + PC1281

2
330U_2.5V_M 330U_2.5V_M
OPT@ @
2 2

3
2
1

1
PC1302
680P_0402_50V7K

2
@
Change PC1280 from reserve to mount
Change PC1281 from mount to reserve

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC1287

PC1288

PC1289

PC1290

PC1291

PC1292
A A

2
OPT@ OPT@ @ @ OPT@ OPT@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 2013/08/05 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 58 of 59
5 4 3 2 1
 5 4 3 2 1

CORE_GND CORE_GND

470P_0402_50V7K
1

1
PC1157

220K_0402_5%_TSM0B224J4702RE
PR9334
27.4K_0402_1%

2
2
1 PR9337 2 B+
44 VR_IMVP_IMON
165K_0402_1%

330P_0402_50V7K

68P_0402_50V8J
1

1
75K_0402_1%

2
PR9338

PH901

PC1159

PC1158
1

1
2

2
PJ708

1
D D
JUMP_43X79
PR9335

2
1 2 CPU_PH @
3A

2
140K_0603_1%

2 PR9401 1CPU_CORE
CPU_B+

1 CSCOMP

CPU_CSREF
CORE_GND
1

68U_25V_M
10_0402_1%
PC1065 PC100 PC99 PC98 PC113

CSCOMP

PC988
PR9333 +

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
16.5K_0402_1% @

CSSUM

2
1

0.1U_0402_25V6
@
PR9340 PC1171 @2

2
102K_0402_1% 1000P_0402_50V7K

5
CPU_CSREF
2
1
PR3 PC1153 PC1181 PC1172 CORE_GND
49.9_0402_1% 330P_0402_50V7K 10P_0402_50V8J CORE_GND 2.2U_0603_6.3V6K PR365
1 2 1 2 1 2 PR9341 0_0603_5%

2
1 2 CPU_HG_R 2 1CPU_HG 4 CPU_CORE
+5VS

1
PR9330 PR2 PR1 2.2_0603_5% AON6372_DFN8-5
1K_0402_1% 4.02K_0402_1% 17.4K_0402_1% PR9332 PQ40 32A

21
20
19
18
17
16
15
1 2 1 2 69.8K_0402_1% PL9

3
2
1
1 2 CPU_PH 1 2

CSCOMP

IMAX
CSSUM
IOUT

CSREF

PVCC
ILIM
CORE_GND

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PC1156 0.22UH_SPS-06CZ-R22M-V1_23A_20%

1
22 14 0.01U_0402_25V7K
ROSC VBOOT

1
23 13 TSENSE 1 2
CORE_GND PR617
COMP TSENSE CPU_LG

PC1073

PC1088

PC1089

PC1170

PC1148
24 12 4.7_0805_5%
PR9402 25 FB LG 11

2
1 2 26 DIFFOUT PGND 10 CPU_PH
12 CPU_VSS_SENSE

2
27 VSN SW 9 CPU_HG_R PC97 CPU_LG 4
VSP HG
2

0_0402_5% PC1154 28 8 1 PR80 2 1 2

VR_HOT#
VCC BST

VR_RDY
ENABLE
AON6764_DFN8-5

ALERT#
C 1000P_0402_50V7K 2_0603_5% @ @ @ @ C

1
VRMP
29 PQ39

SCLK
0.22U_0603_25V7K PC621

SDIO
1

GND 680P_0402_50V7K
10 CPU_VCC_SENSE

3
2
1
PR9145

2
1 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PC1254 @ PU908
+5VS
1
2
3
4
5
6
7
1 2 NCP81101MNTXG_QFN28_4X4
1

1
2.2_0603_5% PC242 CORE_GND

PC1164

PC1149

PC1177

PC1139

PC1160

PC1116
560P_0402_50V7-K 1U_0603_25V6M
PR9343 2 @ 1 PR9331
2

2
44 EC_VR_ON 1 2
0_0402_5% CPU_B+
PR9146
2 1 CORE_GND 1K_0402_1% For EMI request @
10 CPU_VR_ON
0_0402_5% 1 @ @
1

PC1155
PC620 0.01U_0402_25V7K
2

+1.05VS .1U_0402_10V6-K
2

@ +3VS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2

CORE_GND CORE_GND 1

1
PR9265
499_0402_1%

PC1167

PC1162

PC1165

PC1163

PC1174

PC1173
PR47 @
10K_0402_5%

2
1

44 VR_HOT# @
VR_CPU_PW ROK 10,44
10 CPU_SVID_DAT

100K_0402_1%_TSM0B104F4251RZ
10 CPU_SVID_ALERT#
PR9342
TSENSE 1 2
10 CPU_SVID_CLK CORE_GND

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
0_0402_5% 1
1

1
+

59K_0402_1%
PR9098 PR31 PC708
.1U_0402_10V6-K

PC1176

PC1178

PC1180
PR60 220U_D2_2.5VY_R6M
1

1
PC622

PH902
PR9339
75_0402_1% 130_0402_1%

2
+1.05VS 54.9_0402_1% PC626 @ 2 3
2

@ 10U_0603_6.3V6M
2

B B

2
@

PJ3
1 2

JUMPER

@
CORE_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/02/27 Deciphered Date 20140213 PWR_CPU Core

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
Date: Saturday, May 09, 2015 Sheet 59 of 59
3 2 1