A 2W, High Efficiency, 2-8GHz, Cascode HBT MMIC Power Distributed Amplifier

J.Ph. Fraysse*, J. P. Viaud**, M. Campovecchio*, Ph. Auxemery***, R. Quéré*

*IRCOM CNRS UMR n°6615 Université de Limoges, IUT 7 rue Jules Vallés 19100 BRIVE (FRANCE)
**THOMSON-CSF MICROELECTRONIQUE, 29 avenue Carnot, 91349 MASSY cedex (FRANCE)
***ums domaine de Corbeville, route départementale 128, 91401 ORSAY cedex (FRANCE)

ABSTRACT DISTRIBUTED AMPLIFIER TOPOLOGY

In this paper a new topology for wideband
power distributed amplifiers is proposed. This
topology is based on a nonlinearly optimized HBT
cascode cell. More than 2W have been measured in
the 2-8GHz frequency range with an associated
gain of 9dB and a PAE higher than 20%. Those
results have been found in good agreement with
the simulated ones.
A distributed amplifier is made up of a series of
active devices cell distributed between two
transmission lines. These cells can be constituted of a
single transistor or more complex circuits. The design
schematic of a four section HBT distributed amplifier
is given in figure 1.
Rload
U

active active active active

device device device device
INTRODUCTION cell
(1)
cell
(2)
cell
(3)
cell
(4)
In
Electronic warfare applications require wide
band MMIC amplifier where both power and high
efficiency are desired simultaneously. To realize these
applications, the HBT is an excellent candidate. Thus,
figure 1 - Schematic of power distributed amplifier
MMIC power amplifier employing GaAs HBT has got
very good power and power added efficiency The signal injected by the generator propagates
covering the 8-14GHz [1][2] 6-18GHz [3] bands. The along the input transmission line and excite the
combination techniques of these amplifiers use transistors at different phases. At the output of every
impedance transforming network adapted for these active cell, in condition of equality of phase speed,
frequency bands. But for applications which required the amplified signals add up and spread along the
wider frequency band, it is preferable to use output transmission line loaded by the load resistance
distributed topology [4][5]. (Rload).
However, the distributed amplifier performances MAIN POWER LIMITATIONS OF
(power, frequency band, gain,...) are limited by the DISTRIBUTED AMPLIFIER
characteristics of the used active cells. In this paper, a
If the characteristic impedance of the end output
solution is proposed to increase the output power and
transmission line is equal to the load impedance, the
the gain of distributed amplifier by introducing the
power delivered at the resistance is fixed by the load
cascode cell.
impedance (Rload) and the voltage amplitude (U) that
In order to demonstrate the advantage of cascode
can support the active device. The optimum output
cell for wide band power applications, a 2-8GHz HBT
power is thus :
distributed amplifier using this cell has been designed
U2
and realized with the HBTs of the UMS foundry. The P=
preliminary on wafer measurements of this amplifier 2 Rload
indicate 1.7±0.3W output power over the band with In that case, to achieve an output power of 2W in
9dB average associated gain and average power added a 50Ω resistance, the active device cell should present
efficiency ranging from 18% to 32%. a bias point equal to 14V at least.

0-7803-5687-X/00/$10.00 (c) 2000 IEEE

 With the aim of increasing the frequency band,
the output capacitance of the active device cell
shouldn't be too large. Moreover, the active device
cells gain should be high enough not to degrade the
amplifier PAE.
COMMON-EMITTER TRANSISTOR
The common emitter (CE) configuration is the
most usually active device cell used for design and
realization of HBT distributed power amplifier. But
the bias of a HBT working in X band limits the
distributed amplifier output power at about 0.5W.
CASCODE CELL
With the aim of increasing the HBT distributed
power amplifier performances, another active device
cell is investigated. The cascode cell is an attractive
cell. Indeed, the cascode configuration output voltage
is equal to the sum of the collector emitter voltage
(Vce) of the two transistors. Thus, if the two
transistors are loaded by the required impedance for
optimum power, the maximum power available at the
cascode configuration output should be twice as high
as the common emitter cell one. However, the
classical cascode configuration doesn't meet these
conditions. Indeed, in the classical configuration, the
second transistor input restricts the output voltage
excursion of the first transistor. So, it doesn't see its
optimum power load impedance. To solve this
problem, one capacitance Ca has been added in series
with the base of HBT in common base configuration
(figure 1). It allows to realize a capacitance division
with the input capacitance of this transistor. Thus, this
capacitance makes it possible to differentiate the CE
transistor output voltage from CB transistor input
voltage. In order to quantify the cascode cell
performance compared with the CE configuration
one, we considered that the transistors will operate in
class A and at the limit of saturation. In that case, the
HBT models can be reduced to linear models with a
reasonable accuracy. The only real constraint is
related to the maximum voltage Vmax and current
Imax that the transistor can support. Taking these
constraints into account, the power optimization
method of the cascode configuration consists in
modifying the capacitance Ca, the load admittance
Ych and the input power of the cascode cell to
achieve an optimum ouput power.
0-7803-5687-X/00/$10.00 (c) 2000 IEEE
This method has been applied to two HBTs of 8
fingers of 2x30µm² at 8GHz with the conditions as
follows :
Is1<180mA; Is2<180mA, Vs1<8V, Vs2<8V
A resistance (Rstab) has been placed in series
with the Ca capacitance to stabilize the cascode cell.
Figure 2 shows the dynamic load line where we
can notice that the two transistors work nearly on
their optimum. This method has been equally applied
to a common emitter configuration in keeping the
same constraints on the transistor current source. The
tables 1 and 2 present the gain and the output power
of the cascode and common emitter cells and the
values of optimized elements. These results
demonstrate that power optimized cascode cell,
compared to the common emitter configuration allows
• to increase the output voltage and power,
• to improve the gain,
• to divide by two the load reactance,
• to decrease the value of output capacitance.
The same result has been obtained for the 2-
18GHz frequency band with the same Ca capacitance.
This research work demonstrates that the cascode cell
is well adapted and presents many advantage for
design of wide band high power amplifier.
CIRCUIT DESIGN
To reduce the input capacitance of cascode cell,
a capacitance division (Cin) was employed by adding
a serie capacitance between the common emitter and
the input line. Besides, the capacitances were varied
(Cin4>Cin3>Cin2>Cin1) to compensate the loss
along the input line and equalize the input drive for
each device.
The amplifier has been optimized to obtain :
• S21>11dB
• S11<-10 dB
• equality of the input drive for each device
• optimum load for each active cell
In this optimization step, a linear model of
transistor has been used. The non linear design has
been also refined with the use of a non-quasi-static
electro-thermal HBT model [6]. The amplifier layout
is presented figure 8.
SIMULATED AND MEASURED
PERFORMANCES
The amplifier S parameter has been measured on
wafer under CW conditions. A good agreement
between measurement and simulation is obtained. The
amplifier gain is about 10dB over the band with a low
ripple (±0.4dB). A very low dispersion of the circuit
and the process can be observed. Return losses are
better than -12dB over the 3-8GHz band.
The amplifier power performances has been
evaluated on wafer under pulse condition (10µs 10%).
The output power is greater than 31.5dBm with a
power added efficiency ranging from 18% to 31%.
The maximum output power is 33dBm. Although the
biasing conditions are not optimum, these results
represent to our knowledge, the state of the art for the
compromise between output power and power added
efficiency for this frequency band. They have been
obtained at the first foundry run and without circuit
tuning. They demonstrate the cascode advantages for
wide band power amplifier. Moreover the comparison
measurements and simulations prove the validity of
used HBT model.
Preliminary tests of carrier-mounted amplifier
have shown an output power greater than 2W with an
associated gain over 9dB and a PAE higher than 20%.
The measured output power curve versus frequency
are shown in figure 9 and demonstrate the validity of
the approach adopted.
CONCLUSION
For the first time, a power distributed amplifier
using the cascode cell has been designed. The
preliminary measurements shown an output power
greater than 2W with an associated gain over 9dB
and a PAE higher than 20%. They demonstrate the
cascode advantages for wide band power amplifier.
ACKNOWLEDGMENT
The authors would like to acknowledge the
financial support of the DGA for this work

REFERENCES
[1] – F. Ali and Al [4] – J. P. Viaud and Al
"A 25 Ohm, 2W, 8-14GHz HBT Power MMIC with 20 "First Demonstration of a 0.5W, 2 To 8GHz MMIC HBT
dB Gain and 40% Power Added Efficiency" Distributed Power Amplifier Based On a Large Signal
IEEE MMWMC, pp. 113-115, 1994 Design Approach"
[2] – M. Salib and Al IEEE MTT-S Digest, pp. 893-896, 1997
"A robust 3W High Efficiency 8-14GHz GaAs/AlGaAs [5] – M. Campovecchio and al
Heterojunction Bipolar Transistor Power Amplifier" "Optimum Design of Distributed Power-fet Amplifiers.
IEEE MTT-S Digest, pp. 581-584, 1998 Application to a 2-18GHz MMIC Module Exhibiting
[3] – M. SALIB and Al Improved Power Performances"
"A 1.8W, 6-18-GHz HBT MMIC Power Amplifier with IEEE MMWMC, pp. 125-128, 1994
10-dB Gain and 37% Peak Power-Added Afficiency" [6] - J. Ph. Fraysse and al
IEEE Microwave Guided Wave Letter, vol. 3, pp. 325- "A Non-Quasi-Static Model of GaInP/GaAs HBT for
326, Sept. 1993 Power Applications "
IEEE MTT-S Digest, 1997

Cin
Vc Ps Gain Rch Cch
Ic=IcT/4
CB (mW) (dB) (Ω ) (pF)
Rstab
657 12.6 41 -0.43
Ralim table 1 - Power results of emitter common
CE Vb2

Ca
Pout Gain EC gain BC gain Rch Cch Ca1
mW (dB) (dB) (dB) (Ω ) (pF) (pF)
950 15.6 12.3 3.3 88 -0.34 0.6
figure 1. Schematic of power cascode cell table 2 - Results of cascode cell power optimization

0-7803-5687-X/00/$10.00 (c) 2000 IEEE

 IcEC, IcBC (mA) (V)
160 15
BC
EC Vce_ext_EC
10
Vce_ext_BC
80 Vout_cascode
5

0 0

-5
-80
-10

-160 -15
-8 -6 -4 -2 0 2 VceEC, VceBC (V) 0 25 50 75 time (pS)

figure 2 - Dynamic load lines figure 3 - Voltages of cascode cell

S21 (dB) S11 (dB)

12 0
sim u lation
10 -5
simulation
8 -10

6 -15

4 -20

2 -25

0 2 4 6 8 fréquence (GHz) 0 2 4 6 8 frequence (GHz)

figure 4 - Comparison between measured and figure 5 - Comparison between measured and
simulated gain simulated input reflection loss
η a j (% ) P o u t (d B m )

P i n 2 2 d B m :   s im u latio n s n m e a s u r e m e n t s
P i n 2 4 d B m : ------ sim u lations
P in 2 2 d B m :   sim u latio n s n m e a s u r e m e n ts
V c = 1 2 V , V b 2 = 7 V , IcT = 4 5 0 m A
P in 2 4 d B m : ------ sim u l a t i o n s l m e a s u r e m e n ts
V c = 1 2 V , V b 2 = 7 V , IcT = 4 5 0 m A

F r é q u e n c e (G H z ) F r é q u e n c e (G H z )

figure 6 - Comparison between measured and figure 7 - Comparison between measured and
simulated power added efficiency simulated output power
Pout (dBm)
40.00

35.00 Pin
(dBm)

30.00 05
15
20
25.00
25

20.00

15.00
Vc=13.5V, Vb2=8V
10.00
2600 3600 4600 5600 6600 frequence (Hz)

figure 9 - Preliminary measurements of carrier-

figure 8 - Power distributed amplifier layout mounted amplifier

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