910 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO.

6, JUNE 2001

A 1.25-GHz 0.35-m Monolithic CMOS PLL

Based on a Multiphase Ring Oscillator
Lizhong Sun and Tadeusz A. Kwasniewski, Member, IEEE

Abstract—A general ring oscillator topology for multiphase out-

puts is presented and analyzed. The topology uses the interpolating
inverter stages to construct fast subfeedback loops for long chain
rings to obtain both multiphase outputs and higher speed opera-
tion. There exists an optimum number of inverter stages inside a
subfeedback loop which gives the highest oscillation frequency. A
fully integrated 1.25-GHz 0.35- m CMOS phase-locked-loop clock
generator that incorporates the proposed voltage-controlled oscil-
lator topology was designed and implemented for a data trans-
ceiver. It provides eight-phase outputs and achieves RMS tracking Fig. 1. Simplified block diagram of a data transceiver.
jitter of 11 ps from a 3.3-V power supply.
Index Terms—Analog integrated circuits, clock generation, fre-
quency synthesizer, phase-locked loop.

I. INTRODUCTION

T HE phenomenal growth in information transport has

created greater demand for very high-speed integrated
circuits. Important components for the high-capacity networks
include transceivers which incorporate clock generators, Fig. 2. Functional block diagram of the PLL clock generator.
clock/data recovery circuits (CDR), multiplexers (MUX)/de-
multiplexers (DMUX) and I/O buffers. Fig. 1 shows the
clock frequency (1244.16 MHz) can be synthesized from a
simplified block diagram of a data transceiver. In the trans-
77.76 or 19.44 MHz reference clock with a corresponding
mitter, the MUX converts the internal byte-wide (parallel) data
feedback divider ratio of 8 or 32. Design considerations include
stream to a bit serial stream and drives a high-speed output
low-voltage operation, low power consumption, monolithic
buffer. In the receiver, the clock recovery circuit regenerates the
integration, low timing jitter, and good process/temperature
clock and defines the best time to sample the data in terms of
variation tolerance.
the received signal-to-noise ratio. Data is then demultiplexed.
In the next section of this paper, a general ring oscillator
The multiphase outputs from the phase-locked loop (PLL) and
topology for high-speed operation and multiphase outputs
CDR for MUX/DMUX allow the voltage-controlled oscillator
is presented and analyzed. Section III describes a four-stage
(VCO) to operate at the relative lower parallel data stream
(eight-phase) subfeedback-loop-based differential ring oscil-
rate instead of the much higher bit serial stream rate. For
lator. The PLL design and measurement results are presented
example, eight-phase 1.25-GHz clocks can be used to recover
in Section IV. Concluding remarks follow in Section V.
a serial data at 10 Gb/s for SONET systems. It has advantages
including larger VCO jitter tolerance and ease of circuit design
II. MULTIPHASE OUTPUT RING OSCILLATORS
in a low-cost digital CMOS process instead of a Si bipolar or
GaAs MESFET process. The VCO is a critical building block in PLLs. High-fre-
This paper presents a general ring oscillator topology for mul- quency and RF voltage/current controlled oscillators can be
tiphase output and high-speed oscillation. A 0.35- m CMOS implemented monolithically as LC oscillators, relaxation oscil-
PLL clock generator that incorporated the proposed VCO lators or ring oscillators. Although ring oscillators have poor
topology is designed to operate at 1.25 GHz with eight-phase phase noise characteristics compared to high- LC oscillators,
outputs. The functional block diagram is shown in Fig. 2. The they have the advantage of wider oscillation frequency range
PLL includes a phase and frequency detector (PFD), charge and a smaller die size. Ring oscillators are particularly attractive
pump, loop filter, VCO, and prescaler/divider. The output for multiphase clock signal generation required by many clock
recovery circuits and high-speed sampling systems [1], [2].
Manuscript received June 7, 2000; revised January 9, 2001. This work was For an -stage ring oscillator, the oscillation period of the
supported by NSERC and CITO in Canada. ring is , where is the delay of each inverter stage. The
L. Sun is with Lucent Technologies, Bell Labs, Allentown, PA 18103 USA. minimum delay of each stage depends on the circuit structure,
T. Kwasniewski is with the Department of Electronics, Carleton University,
Ottawa, ON K1S 5B6, Canada. process parameters, and the size of transistors. The size of tran-
Publisher Item Identifier S 0018-9200(01)04133-6. sistors affects the delay through its effect on driving strength,
0018–9200/01$10.00 © 2001 IEEE

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SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR 911

Fig. 3. General topology of ring oscillator with subfeedback loops.

Fig. 5. Block diagram of a five-stage ring oscillator with subfeedback loops

(i = =x 3 case).

Fig. 4. Redraw of Fig. 3 demonstrating the feedforward paths.

self-loading, and loading to the previous stage. The improve-

Fig. 6. Combined single-stage equivalent circuit.
ment in speed can be obtained by a circuit optimization. How-
ever, the achievable improvement in speed is limited, especially
for an oscillator with a long chain of inverters. To solve the con- of major loop inverters that the interpolating inverters
flict between speed (or tap-to-tap delay) and multiphase output, pass over. The topologies of Figs. 3 and 4 are equivalent. The
several techniques have been proposed [3]–[6]. A VCO based relation between and is .
on two-taps delay interpolating was proposed to provide large- The block diagram of a five-stage single-ended ring oscillator
range tuning without providing uniform tap-to-tap delay [3]. In is shown in Fig. 5 as an example of the topology for the
[4], a two-dimensional coupled ring oscillator was developed to (or ) case. The circuit contains a single
produce precise delays with subgate-delay resolution. Recently, slow loop and five subfeedback fast loops. Each subfeedback
a multiple-feedback-loop ring architecture was used for a three- loop contains three inverter stages. Equivalently, the circuit can
stage and four-stage ring oscillator design [5]. A single-ended also be understood as a scheme where the delay of stages is the
multiphase ring oscillator was proposed using a negative skew weighted sum of the delay through the slow path and the fast
delay scheme, suggesting an optimum skew delay of two in- path. For example, the delay from node to node is the
verter delays [6]. However, as will be shown later, the two-in- weighted sum of the slow path delay and
verter skew delay is not always the optimum for long-chain ring the fast path delay .
oscillators.
B. Model of Oscillation
A. A General Topology of Multiphase Ring Oscillators For an -stage ring oscillator in a stable oscillation mode,
Fig. 3 shows a general topology of multiphase ring oscilla- there exists a fixed phase relation between stages. Each stage
tors with subfeedback loops [7]. The nodes and their intercon- contributes a phase delay of for a total , where
nections have been correspondingly labeled. The fundamental is an odd integer with value smaller than . It represents a
idea is to use the interpolating inverters to construct inter- possible mode of oscillation. Another phase inversion required
coupled subfeedback loops. Each subfeedback loop contains an for the total phase shift of multiple of around the loop is
optimum number of inverters that keeps the circuit reliably os- provided by phase inversion in each inverter stage. For the dif-
cillating at a higher speed. The phase relationship between in- ferential ring oscillators with even number of stages, the phase
verter stages remains unchanged due to the symmetrical struc- inversion required for the total phase shift of a multiple of
ture. Thus, reduced tap-to-tap delay can be achieved. We define around the loop can be achieved by simply interchanging the
as the feedback index. It is an integer repre- differential outputs of the last inverter before feeding them back
senting the number of inverter stages in each subfeedback loop to the inputs.
(e.g., when , there are three inverters in a subfeedback To find the optimum feedback index for a long-chain ring
loop). The interpolating inverter can be incorporated into and the relative frequency variation, we model the signal path
the major loop inverter circuitry with a separate input. The in the VCO with a first-order approximation, assuming its os-
topology in Fig. 3 can be redrawn in Fig. 4 where the interpo- cillation amplitude remains small and the waveform is sinu-
lating inverters are used to construct the fast paths (short cuts). soidal-like. Fig. 6 shows a combined single-stage equivalent cir-
We define as the feed-forward index in contrast to the feedback cuit diagram. and represent the equivalent output resis-
index . It is an integer representing the number tance and the total parasitic loading capacitance at node ,

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912 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001

respectively. and represent the equivalent transconduc-

tance of the inverters in the main loop and subfeedback loop,
respectively. We define as the phase difference between two
adjacent nodes (e.g., , for and ) and
as the phase difference between node and node
. Assuming all stages are the same, we have
. Thus, the transfer function of
a single stage can be found as

(1)

According to the Barkhausen criterion of oscillation [8], the

ring oscillator would oscillate if the loop has unity voltage
gain and phase shift of or a multiple of . Although there
may exist some possible modes for long-chain ring, only those
modes with enough loop gain can sustain oscillation. Since we
want single-mode operation, loop gain should be designed to
be smaller than one for all the undesired modes. From (1), the
minimum required gain of each stage can be written as

(2)
Fig. 7. Seven-stage ring oscillator transient waveforms for different feedback
index i.
and the approximate oscillation frequency can be expressed as
C. Increasing the Oscillation Frequency
To achieve a large relative frequency increment, the interpo-
(3) lating inverters should be introduced without a significant in-
crease of the loading capacitance. Furthermore, in (4) should
where be positive. Since is fixed for an -stage ring oscillator during
stable oscillation, whether oscillation frequency is increased or
(4)
decreased depends on the feedback index , which is the number
of inverters in a subfeedback loop. The subfeedback loop can
The first term of (3) is the oscillation frequency of a con-
contain an even ( ) or odd ( ) number
ventional ring oscillator. The second term corresponds to the
of inverters. An odd number of inverters inside a subfeedback
frequency increment or decrement. Considering that an oscil-
loop has a positive value, thus increases the operating fre-
lator is a large signal nonlinear system, as the amplitude grows,
quency, while an even number ( ) causes a decrease in
transconductance degrades; furthermore, output resistance and
the operating frequency. For a long-chain ring, there exists an
capacitance deviate from their value near the quiescent biasing
optimum feedback index which gives the highest operating fre-
point. Equation (3) actually overestimates the real oscillation
quency. This can be easily confirmed with HSPICE large-signal
frequency. However, we are more interested in comparing the
transient simulations.
relative frequency improvement between different topologies
A simple single-ended inverter was used as a delay stage in
rather than calculating the absolute oscillation frequency. Equa-
the large-signal simulations. The device sizes of inverters in
tion (3) can be used to qualitatively estimate the relative fre-
the major loop are 30 m/0.6 m ( ) and 10 m/0.6 m
quency increase/decrease ( ) compared to the conventional
for pMOS and nMOS, respectively, while the device sizes
ring topology. We have
of the interpolating inverters are 15 m/0.6 m (pMOS) and
5 m/0.6 m (nMOS), respectively. The simulations were run
(5) with 0.5 m digital CMOS process parameters and a power
supply of 3.3 V for . Fig. 7 shows the
where and are the total loading capacitance of each stage oscillation waveforms for corresponding to different
for the subfeedback based topology and the conventional single values. When the subfeedback loop contains three ( )
loop topology, respectively. represents the av- or five ( ) inverters, , and the frequency is in-
erage strength of the interpolating inverters. is the operating creased compared to a conventional seven-stage single-loop
frequency for the conventional single loop topology. We have ring oscillator. However, when the subfeedback loop contains
assumed that remains the same. four ( ) or six ( ) inverters, frequency is decreased

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SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR 913

TABLE I
OSCILLATION FREQUENCY CORRESPONDING TO PARAMETERS i, , x AND
k FOR N = 7 AND 9

Fig. 9. Interpolating inverter S x

pass over three major loop inverters ( = 3
case).

Fig. 10. Combined single stage with multiple feedback.

For , improved speed is achieved when or . If

Fig. 8. Oscillation frequency versus stage number
parameter.
N with feedback index i as
two feedback indices are combined in one circuit as shown in
Fig. 10, an even higher oscillation frequency can be obtained.
This can be extended to a longer chain ring to form multifeed-
back loops, for example, combining in the nine stages
( ) ring.
It should be noted that the improved speed for a constant
output voltage swing comes at the expense of greater power
consumption due to the time overlap when both nMOS and
pMOS are on. We are more interested in power efficiency rather
than power consumption in comparison of oscillators running
at different speed. The power efficiency can be measured by
the product of the oscillation period and power consumption.
Taking as example, the period–power product for
are 13.2, 27.7, and 26.1 pJ, respectively. The conven-
tional ( ) single-ring structure has highest power efficiency
overall. Among the subfeedback-loop-based structure,
( , ) case has the highest efficiency.

due to the fact that is negative. Since for has a D. Frequency Tuning
larger value compared to that for , a higher oscillation
frequency is achieved. Table I lists the corresponding values In additional to the feature of improved speed, we observe
of the simulated oscillation frequency and parameters , , and from (3) that the oscillation frequency of an -stage ring
for and . As explained earlier, is the feedforward oscillator with a fixed feedback index can be tuned by varying
index. The positive values of and corresponding frequency any one of three parameters: loading capacitance , loading
are highlighted. resistance , and relative strength of interpolating inverters
Fig. 8 summarizes the simulation results illustrating oscilla- . Capacitive tuning has the drawback of lowering the
tion frequency versus with as a parameter. For , maximum speed of operation because the minimum value of
the highest oscillation frequency is achieved at . However, capacitor still loads the circuit. Although a resistive tuning can
for , the highest oscillation frequency is achieved at provide a large frequency variation, it causes a voltage swing
. For , we get the highest frequency at . The and voltage gain variation [9]. When transistors operating in
results confirm the prediction from the calculation of mag- the triode region are used as loading resistors, their nonlinearity
nitude. From Fig. 7 we found that although the circuit achieves degrades the common-mode noise rejection for a differential
highest speed when , it produces a sinusoidal-like wave- circuit. According to (3), the oscillation frequency of the
form when ( ). Similar phenomenon can be ob- subfeedback-loop-based ring oscillators linearly depends on
served for other values, but all corresponding to case, . When is controlled by an external voltage, the tuning
as shown in Fig. 9. Since its total power consumption is actu- range is . This tuning scheme is especially
ally lower than the case corresponding to the highest frequency, useful when loading resistors in the delay stages are imple-
a higher equivalent quality factor is expected for the mented with linear resistors (e.g., poly resistors) to improve the
case. common-mode noise rejection.

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914
Fig. 11. Eight-phase-output ring oscillator based on three-stage (i
subfeedback loops.
Fig. 12. Three-dimensional representation of the ring oscillator from Fig. 11.
Fig. 13. Phase relationship of the circuit in Fig. 11.
III. DESIGN OF AN EIGHT-PHASE-OUTPUT RING OSCILLATOR
The topology in Fig. 3 was used to design a four-stage dif-
ferential ring oscillator as shown in Fig. 11. Compared with
conventional ring oscillators, four inverters are interpolated to
construct the subfeedback loops. With feedback index ,
each subfeedback loop contains three inverters (M1–M2–S4;
M3–M4–S2; M2–M3–S1; M4–M1–S3) and is established as a
fast loop. The main feedback loop with four stages is the slow
loop. By redrawing the circuit in three dimensions as shown
in Fig. 12, the subfeedback loops can be more easily viewed
(single-ended inverters are plotted for simplicity). It should be
noted that stages in altitude and latitude are designed not to os-
cillate in a two-stage ring oscillator mode to ensure reliable os-
cillation and reduction of phase noise. Fig. 13 shows the phase
relationship of eight output signals (when matched delay stages
and loading are used). Imposing these phase relations to (3), the
minimum required dc gain is , which can be used
to calculate the initial value of transistors for design and simu-
lation. Since minimum dc gain is not related to , it is much
easier to maintain oscillation when is controlled with an ex-
ternal control signal.
A combined single delay stage of the ICO core circuit is
shown in Fig. 14. It consists of a major loop inverter and an
interpolating inverter. Fully differential inverters are used to re-
duce the sensitivity to power supply fluctuation and substrate
noise and to reduce the distortion of the duty cycle. The two
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
= 3)
Fig. 14. ICO differential stage, V –I , and bias circuit.
Fig. 15. PFD, charge pump, and loop filter.
nMOS source-coupled differential pairs share the same loads,
but have separated tail current sources. Frequency tuning can
be accomplished with controlled by a single-ended signal or
both controlled (push–pull) by a differential signal. In
this design, is connected to a proportional-to-absolute tem-
perature (PTAT) current reference and is controlled by the
charge pump/loop filter output signal through a voltage-to-cur-
rent ( – ) converter for frequency and phase locking. The os-
cillator is optimized to operate at the required output frequency
when . The – circuit is also shown in Fig. 14.
The PTAT reference circuit reduces the VCO’s sensitivity to
temperature and process variation. In the PTAT bias reference,
placing resistor to the pMOS source and tying the source
and n-well of each pMOS transistors eliminate body effect. By
connecting a diode-connected pMOS transistor in shunt with an
equal size biased pMOS transistor, the linearity of loading can
be improved [10]. 200 ppm/ C of temperature sensitivity and
6%/V of power supply sensitivity without the use of a regulator
is achieved with a good frequency control linearity.
IV. PLL DESIGN AND MEASUREMENT RESULTS
The PFD is based on a conventional three-state phase detector
(PD) shown in Fig. 15. The circuit consists of two edge-trig-
gered resettable D-flip-flops which were implemented using dy-
namic logic circuitry. In order to minimize the dead zone asso-
ciated with the three-state PFD, extra delay is introduced in the
reset path through inverters.
The charge pump and loop filter are also shown in Fig. 15.
The UP and DN signals from the PFD switch the corresponding
current sources onto node , thus delivering a charge to ad-
just up or down. Both current sources are mirrored from a
bandgap current. When neither nor is connected to ,
they are biased by the unity-gain amplifier [11]. It suppresses
SUN AND KWASNIEWSKI: MONOLITHIC CMOS PLL BASED ON A MULTIPHASE RING OSCILLATOR
Fig. 16. Die photograph of the PLL clock generator.
Fig. 17. Measurement result of the ICO (in PLL) transfer characteristic.
the charge sharing from the parasitic capacitance on node or
, thus reducing the spike on the loop filter.
The prescaler used to divide the VCO output by factor 2 is
designed using a true-single-phase clock (TSPC) D-flip-flops
[12]. The transistors’ size is optimized to achieve high-speed op-
eration. The frequency operating range of the prescaler is from
400 MHz to 3 GHz with a power consumption of 6 mW at max-
imum frequency. The divide by 8/32 divider is also based on the
dynamic flip-flops which are connected as a ripple counter and
resynchronized at the output.
The bandwidth of the PLL affects the stability, the lock-in
time, and the suppression of phase noise from the VCO. The
loop bandwidth is chosen to be 2 MHz with resistor of 40 k
and charge pump current of 20 A. and are 240 and 1 pF,
respectively.
The PLL clock generator was implemented monolithically
in a 0.35- m single-poly three-metal CMOS technology [13].
Fig. 16 shows the die photo of PLL clock generator. By varying
the input reference frequency, the ICO transfer characteristic
were measured and shown in Fig. 17. The ICO has a good con-
trol linearity. The jitter histogram of the PLL was measured with
other transceiver blocks active on chip. The tracking jitter at
1.25-GHz output is 11 ps (RMS) and 80 ps (peak-to-peak) with
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915
Fig. 18. PLL jitter histogram.
TABLE II
SUMMARY OF MEASURED PLL CLOCK GENERATOR PERFORMANCE
power consumption of 109 mW for a 3.3-V supply (Fig. 18).
Table II summarizes the measurement results.
V. CONCLUSION
A general ring oscillator topology for multiphase output has
been presented and analyzed. The topology uses the interpo-
lating inverter stages to construct fast loops for long-chain ring
oscillators to achieve both higher speed and multiphase outputs.
The analysis leads to a relationship between relative oscillation
frequency increment/decrement and the feedback index , which
is the number of inverters inside a subfeedback loop. An odd
number of inverter stages inside a subfeedback loop can increase
the operating frequency. For a long-chain ring, there exist op-
timum values which give the highest operating frequency and
highest power efficiency, respectively.
A 1.25-GHz monolithic CMOS PLL clock generator proto-
type was designed for a data transceiver. The monolithic PLL
consists of a ring oscillator, divider, PFD, charge pump, and
on-chip loop filter. The design accommodates process, supply
voltage, and temperature variations. The voltage controlled os-
cillator incorporates a four-stage differential ring structure with
subfeedback loops embedded to speed up and tune the circuit.
It has a linear control characteristics, eight-phase outputs, and
wide tuning range. The fully integrated PLL was fabricated in
a 0.35- m CMOS process, occupies an active area of 1 mm ,
and consumes about 100 mW operating from a 3.3-V supply. A
RMS tracking jitter of 11 ps was measured.
916
ACKNOWLEDGMENT
The authors would like to thank V. Lee, D. Cartina,
K. Iniewski, B. Gerson, M. Chua, R. Zavari, and Y. Xu of
PMC-Sierra, Inc., Burnaby, Canada, for their support.
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Lizhong Sun received the M.Eng. and Ph.D. degrees
in electrical engineering from McGill University,
Montreal, PQ, Canada, and Carleton University,
Ottawa, ON, Canada, in 1994 and 1999, respectively.
From 1994 to 1996, he was with OZ Optics, Carp,
ON, Canada, working on fiber optics and optoelec-
tronic components. In the summer of 1998, he was
with PMC-Sierra, Burnaby, BC, Canada, working on
CMOS phase-locked loops for frequency synthesis
and data recovery. In 1999, he joined Bell Labs, Lu-
cent Technologies, Allentown, PA, as a Member of
Technical Staff. He is currently working on high-speed analog and mixed-signal
IC design.
Tadeusz A. Kwasniewski (M’86) received the
Ph.D. and M.S. degrees from the Institute of Nuclear
Research and Warsaw University of Technology,
Poland, in 1974 and 1980, respectively.
He worked as a Research and Development
Engineer in Warsaw’s Institute of Nuclear Research
and VOEST Alpine in Austria. In 1983, he joined
Lakehead University and in 1985, Carleton Uni-
versity, Ottawa, ON, Canada. His research interests
include CMOS radio circuits and signal processing
architectures. He is currently with PMC-Sierra,
Burnaby, BC, Canada, on leave of absence from Carleton University. He is
currently working on high-speed CMOS data recovery and synthesis circuits.