Beruflich Dokumente
Kultur Dokumente
C.M.R.I.T, Bangalore
EXPT NO:1
Method 1 for 1) :
Expand the expression by multiplying the 2nd term with (C C ) and 3rd term with ( A A)
as shown below
y ABC AB (C C ) BC ( A A)
ABC ABC ABC A BC A BC.......... .1
AC ( B B ) AC ( B B ) ABC
AC AC ABC
C ( A A) ABC
C AB
BC
A
00 01 11 10
0 1 1 0
0
C
Y=AB+C
1 0 1 1 1
AB
Truth table:
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INPUTS OUTPUT
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
1
A 3
2 7408
B
1
3 Y =AB + C
2 7432
C
B 2
Y = AB + C
4
6
7
40
0
5
A
9
8 A
C 7
40
0 A
1
0
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3
1
A 7
4
02
-1
2 8 1
0
A 7
4
02
-1
5 9 1
1 1
3 3
B A 7
4
02
-
1 4 7
4
02
-
1 7
4
02
-
2 1 Y = AB + C
1
2
6 2
0 0 0
1 1
B
1 1 1 1
0 Y = AC + B
AC
Truth table:
INPUTS OUTPUT
A B C Y
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
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1
A 3
2 7408
1
7432 3 Y
=A
CB
+
2
B 1
7404
2
C
2) Realization using Universal gates:
i) WITH NAND GATES ONLY:
1
3
A 2 7400 4
6 Y= B
5 7400
+AC
B
C
ii)WITH NOR GATES ONLY:
2
7402-1 1 11
A 7402-1 13 2 5 4
3 7402-2 1 7402-2 Y= B + AC
12
3 6 Y= B
5
+AC
7402-1 4
B
6
8
7402-1 10
C
9
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0 0 0
(A + B )
Y= (A + B )( B + C)
1 0 ( B + C)
Truthtable:
INPUTS OUTPUT
A B C Y
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
1) Realization using basic gates:
1
A 3
2 7432
1
B 1
7404
2
2
7408
3 Y= (A + B )( B + C)
4
6
5 7432
C
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9
10
8 7402
C
Procedure:
1. Make connections as shown in the circuit diagram(include supply connections).
2. Apply inputs using toggle switches and verify the truth table using LEDs.
Result: Given Boolean expression is simplified and realized using logic gates and the truth
table has been verified
Conclusion: Simplifying and then realizing a given logic expression uses less number of
gates and thus helps in implementing more logic within the given area.
Probable Viva Questions:.
Boolean laws, Identities, Properties, Huntington’s postulates.
Realization of basic gates using universal gates and vice versa. Conversion of 2
input NAND into 3 input NAND and 4 input NAND gate. Decoding of the IC
number, Significance of Schottky Series.
Noise Margin, Fan out, Fan in, Propagation delay, Speed Power product.
Comparison of different Logic families, Fastest logic family, TTL Logic family.
Application of X-OR gate, realizing X-OR using minimum number of NAND
gates. Coincidence gate?
Different methods of Simplification, which method is preferred when?
State DeMorgan’s Theorem and prove them.
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EXPT NO:2
AIM: REALIZATION OF HALF/FULL ADDER AND HALF/FULL SUBTRACTOR
USING LOGIC GATES
A Sum
Half Adder
B Carry
2
7486 3 S=A B
B
1
7408 3 Co = AB
2
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4
6
7400-1
5
A S=A B
1 12
7400-1 3 7400-1 11
2 13
9
7400-1 8
10
1
Co = AB
7400-2 3
2
A
Sum
Full Adder
B
Co
Cin
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BCin
A
00 01 11 10
0 1 0 1
0 S=AB Cin + A B Cin+ ABCin + A B
Cin
= Cin(AB + A B ) + Cin ( A B + A B)
1 1 0 1 0 = Cin A B + Cin (A B)
= A B Cin
S A B Cin
Co= AB +Cin(A B)
Logic diagram of Full Adder using Basic & X-OR gates (2 Half Adders):
Block diagram:
A
Sum1 Sum
1 3
7432
Cin 2
Carry Out
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Logic diagram:
A
1
7486
3 Sum1 4
2 6
5
7486 Sum
B
Halfadder1
Halfadder2
11 4
7408
3 Carry1 7408
6
2 5
1 Carry out
3
7432
Cin 2
9
7400-1 8
10 9
8
10 7400-2
1
3
2 7400-3
Carry out
Cin
A Difference
Half
B Subtractor
Borrow
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I/P O/P
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
HalfSubtractor1
1 7404 2
1 Borrow
7408 3
2
4
7400-1 6
5
A
1 12
Difference
7400-1 3 7400-1 11
2 13
9
7400-1 8
10
1
Borrow out
7400-2 3
2
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A
D
Full
B Subtractor
Bo
Bin
Logic diagram of Full Subtractor using X-OR & Basic gates(2 Half Adders):
Block diagram:
A
Difference 1 Difference
1
3
Bin 2 7432
Borrow out
Logic diagram:
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A
1
7486 3 Difference 1 4
2 7486 6 Difference
5
B
HalfSubtractor1
HalfSubtractor2
1 7404 2
3 7404 4
1 Borrow1
7408 3 4 Borrow out
2 7408 6 1
5 7432 3
2
Bin
9
7400-1 8
10 9
7400-2 8
10
1 Borrow out
7400-3 3
2
Bin
Procedure:
1 Make connections as shown in the circuit diagram.
2 Apply inputs using toggle switches and verify the truth table using LEDs.
Result: Half adder, Full adder, Half Subtractor, Full Subtractor circuits are realized using
logic gates and the truth tables are verified.
Conclusion: Adder and Subtractor circuits are the most essential part of ALU. Workings of
these circuits at gate level are understood in this experiment.
ProbableVivaQuestions:.
Applications of Adder and Subtractor circuits.
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Definition of Half adder, Full Adder, Half Subtractor, Full Subtractor. Realizations
of the same. Derivation of truth table in each case. Obtaining the logic expression.
Realizing FA using 2 Half adders, FS using 2 Half Subtractors.
Application of X-OR gate, realizing X-OR using minimum number of NAND
gates. Coincidence gate?
EXPT NO: 3
AIM:
a. Realization of Parallel Adder/Subtractor using IC7483.
b. BCD to Excess-3 code conversion and vice versa.
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COMPONENTS REQUIRED: IC Trainer kit, IC 7483 Parallel Adder and IC7400 NAND
gate.
Cin
13 12 10 9 5 4 2 1
11 8 6 3
A3 A2 A1 A0
1 3 8 10 16 4 7 11
VCC +5V
5
7483 13
12
14 15 2 6 9
Cout
S3 S2 S1 S0
Procedure:
4 bit Binary Adder:
A3A2A1A0 = 0 1 0 0 A3A2A1A0 = 1 1 0 1
B3B2B1B0 = 1 0 0 0 B3B2B1B0 = 1 0 0 1
CoutS3S2S1S0 = 0 1 1 0 0 = (12)10 CoutS3S2S1S0 =10110=
(22)10
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Ex.1 Ex.2
A=4, B=8 A=15, B=9
D = A - B = A + (2’s Complement of B) D = A - B = A + (2’s
Complement of B)
A3A2A1A0 = 0 1 0 0 A3A2A1A0 = 1 1 1 1
B3B2B1B0 = 1 0 0 0 B3B2B1B0 = 1 0 0 1
2’Complement of B = 1’ complement of B + 1 2’Complement of B = 1’
complement of B + 1
=0111 =0110
+1 +1
2’Complement of B = 1 0 0 0 2’Complement of B = 0 1 1 1
D = A - B = A + (2’s Complement of B) D = A - B = A + (2’s
Complement of B)
= 0100 = 1111
+(1 0 0 0) +(0 1 1 1)
Cout = 0 implies that answer is negative Cout = 1 implies that answer is positive,
ignore carry
& in 2’s Complement form. & in direct form.
Answer = (- 0 1 0 0) =(-4) 10 Answer = (+ 0 1 1 0) = (+6) 10
Result: Addition and subtraction for the given numbers is performed using 7483.
Conclusion: Addition of any two 4 bit binary numbers can be performed using 7483. It is
observed that subtraction also can be performed using the adder chip itself
with the help of small additional logic.
Note: Examiner may specify the numbers.
Probable Viva Questions:
What are the different methods of representing –ve numbers, Which type is preferred and
why?
Procedure for 1’s complement method of subtraction
Procedure for 2’s complement method of subtraction
State different methods of subtraction using complementary methods
Why complementary methods are preferred?
What are the advantages of 2’s complement method?
Internal diagram of IC 7483, What is the significance of Cin and Cout pins.
Types of Adders, advantages and disadvantages of different types, Explain Look ahead
carry adder.
BCD to Excess-3 code conversion and Excess-3 to BCD code conversion:
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Truth table:
A3 A2 A1 E3A0 E2 E1 E0 Procedure:
0 0 0 0 0 0 1 1
1. Make Cin = 0 for BCD to
0 0 0 0 1 1 0 0 Excess-3 code conversion
2. 0 0 1 0 0 1 0 1 Check the output at
0 0 1 0 1 1 1 0 S3S2S1S0 for all the valid
0 0 1 code as shown in the truth
0 1 0 1 1
table.
3. 0 1 0 1 1 0 0 0 Make Cin = 1 for Excess-3 to
0 1 1 1 0 0 0 1 BCD conversion.
4. 1 1 0 Check the output at
0 1 1 1 0
S3S2S1S0 for all the valid
1 0 0 1 0 0 1 1 code as shown in the truth
1 0 0 1 1 1 0 0 table.
BCD to Excess-3 code conversion
and Excess-3 to BCD code conversion:
Logic 0 Logic 1
Cin
13 12 10 9 5 4 2 1
11 8 6 3
A3 A2 A1 A0
1 3 8 10 16 4 7 11
VCC +5V
7483 13
12
14 15 2 6 9
Cout
S3 S2 S1 S0
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EXPERIMENT NO 04
THEORY:-
BINARY TO GRAY:- The gray code is often used in digital systems because it has the
advantage that only one bit in the numerical representation changes between successive
numbers. Table shows decimal and binary codes and corresponding Gray code.
GRAY TO BINARY:-Gray codes are also called reflected codes. Gray code is an
example of unweighed code. Unweighted codes means there are no specific weights
assigned to the bit positions. BCD (8421) is an example of weighted code. Gray code can
be used to represent digital data in digital communication system. The advantage of gray
code over binary number is that a number in the gray code changes by only one bit as it
proceeds from one number to the next.
Truth Table
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
G0=B1B0+B1B0=B1 + B0
G1=B2B1+B2B1=B2 + B1
G2=B3B2+B3B2=B3 + B2
G3=B3
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B0
G0
B1
G1
B2
G2
B3 G3
B3 B2 B1 B0
G3
G2
G1
G0
TRUTH TABLE:
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G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
B0=G3 + G2 + G1 + G0
B1=G3 + G2 + G1
B2=G3 + G2
B3=G3
G0 B0
G1
B1
G2
B2
G3 B3
G3 G2 G G0
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B3
B2
B1
B0
PROCEDURE:
1. connections are made as per the circuit given
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RESULT:
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AIM: Mux/Demux, use of IC74153 and IC74139 for Arithmetic circuits and code
converters.
Theory: A digital Multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to
a single output line. The selection of a particular input line is controlled by a set of
selection lines.
General Block diagram of Mux:
I0
I1
I2
2n:1 Y
I2n - 1
S0 S1 Sn-1
SELECT
INPUTS OUTPUT
LINES
S1 S0 I3 I2 I1 I0 Y
0 0 X X X 0 0
0 0 X X X 1 1
0 1 X X 0 X 0
0 1 X X 1 X 1
1 0 X 0 X X 0
1 0 X 1 X X 1
1 1 0 X X X 0
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1 1 1 X X x 1
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E S1 S0
10
2
9
7400 7400 7400
Y=S1S0I0+S1S0I1+S1S0I2+S1S0I3
1
3
8
2
6
4 7420-1
I0 5
9
10
8
12 7420-1 1
I1 13 2
6 Y
1 4 7420-3
2 5
6
4 7420-2
I2 5
9
10
8
12 7420-2
I3 13
Procedure:
3. Make connections as shown in the circuit diagram.
4. Apply inputs using toggle switches and verify the Operation of Mux using LEDs.
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Enable Select
Outputs
lines lines Inputs
Eb Ea S1 S0 Ib3 Ib2 Ib1 Ib0 Ia3 Ia2 Ia1 Ia0 Ya Yb
1 0 0 0 X X X X X X X 0/1 Ia0 0
1 0 0 1 X X X X X X 0/1 X Ia1 0
1 0 1 0 X X X X X 0/1 X X Ia2 0
1 0 1 1 X X X X 0/1 X X X Ia3 0
0 1 0 0 X X X 0/1 X X X X 0 Ib0
0 1 0 1 X X 0/1 X X X X X 0 Ib1
0 1 1 0 X 0/1 X X X X X X 0 Ib2
0 1 1 1 0/1 X X X X X X X 0 Ib3
Ia0 6 7 Ya
Ia1 5 1C0 1Y 9 Yb
Ia2 4 1C1 2Y
Ia3 3 1C2
1C3
Ib0 10
Ib1 11 2C0
12 2C1
74153
Ib2
Ib3 13 2C2
2C3
S0 14
S1 2 A
B
Ea 1
Eb 15 1G
2G
Ea is enable input for Mux – 1 and Eb is enable input for Mux – 2. ( both are
active low).
With Ea = 0 & Eb = 1 Mux – 1 will be enabled and Mux – 2 will be
disabled.
With Ea = 1 & Eb = 0 Mux – 1 will be disabled and Mux – 2 will be
enabled.
With Ea = 0 & Eb = 0 both Mux – 1 and Mux – 2 are enabled.
With Ea = 1 & Eb = 1 both Mux – 1 and Mux – 2 are disabled.
S1, S0 are select lines common to both multiplexers.
Ia0 – Ia3 are inputs of Mux – 1 and Ya = output, Ib0 – Ib3 are inputs of Mux – 2
and Yb = output.
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1) Half Adder
I/P O/P
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Design:
Here, 2 outputs need to be generated. Sum can be generated using Mux1 and Carry
out using Mux2 of 74153. By observing the truth table we see that if S1= A and S0=B,
required output can be obtained by connecting the inputs to appropriate logic levels. For Ex.
If S1S0= AB=00, Sum=0 and Co=0, hence make Ia0=0(i.e. the value of Sum when A=0 and
B=0), Ib0=0( i.e. the value ofQo when A=0 and B=0). Similarly we get Ia1=1, Ia2=1, Ia3=0
and Ib1=0, Ib2=0, Ib3=1.
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74153
Ib3 13 2C2
2C3
B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G
Procedure:
1. Make connections as shown in the circuit diagram(Include Supply Connections).
2. Apply inputs and verify the truth table.
2) Full Adder
Design:
Here, 2 outputs need to be generated. Sum can be generated using Mux1 and Carry
out using Mux2 of 74153. Concept of VEM technique can be applied to obtain the outputs.
By observing the truth table we see that if S1= A and S0=B, required output can be obtained
by representing the Sum and Carry in terms of Cin and applying inputs in terms of Cin. For
Ex. If S1S0= AB=00, Sum follows Cin hence make Ia0=Cin and Co=0 irrespective of Cin
hence make Ib0=0. Similarly we get Ia1=Cin, Ia2=Cin, Ia3=Cin and Ib1=Cin, Ib2=Cin,
Ib3=1.
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Cin
Ia0 6 7 Ya=Sum
Ia1 5 1C0 1Y 9 Yb=Cout
Ia2 4 1C1 2Y
Ia3 3 1C2
1
1C3
7404 Logic 0 Ib0 10
Ib1 11 2C0
12 2C1
74153
Ib2
Logic 1 Ib3 13 2C2
2C3
2
B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G
Procedure:
Same as that of Half Adder.
3) Half Subtractor
Truth table for Half Subtractor:
Input
Output
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Design:
Design Procedure is similar to that of Half Adder. Solution is S1=A, S0=B, Ia0=0,
Ia1=1, Ia2=1, Ia3=0 and Ib0=0, Ib1=1, Ib2=0, Ib3=0.
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74153
Ib3 13 2C2
2C3
B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G
Procedure:
Similar to that of half adder.
4) Full Subtractor:
Truth table for Full Subtracotor:
I/p O/p
A B Bin D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Design:
Similar to that of Full adder. Solution is S1=A, S0=B, Ia0=Bin, Ia1=Bin, Ia2=Bin,
Ia3=Bin and Ib0=Bin, Ib1=1, Ib2=0, Ib3=Bin.
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Bin
Ia0 6 7 Ya=Difference
Ia1 5 1C0 1Y 9 Yb=Bout
Ia2 4 1C1 2Y
Ia3 3 1C2
1
1C3
7404 Ib0 10
Logic 1 Ib1 11 2C0
2C1
74153
Logic 0 Ib2 12
Ib3 13 2C2
2C3
2
B S0 14
S1 2 A
A B
Ea 1
Eb 15 1G
2G
Demultiplexer(Dmux):
Demultiplex means one into many. A Demultiplexer is a logic circuit with
one input and many outputs. By applying
Control signals, we can steer the input signal to one of the output lines.
IC74139 is a high speed dual 2 of 4 decoder/
Demultiplexer. The device has two independent circuits accepting two
binary weighted inputs S1,S0 and provides
four mutually exclusive active low outputs. Each decoder has an active low
enable input(E).
Y2n - 1
S0 S1 Sn-1
Y0
1:4 Y1
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DMux
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I
Y2
Y3
S1 S0
Truth Table of 1:4 DMux: Realization of 1:4 DMux Using NAND gates
S1 S0 I Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 Y0= S1 S0I
0 0 1 0 0 0 1 Y1= S1 S0I
0 1 0 0 0 0 0
Y2=S1 S0I
0 1 1 0 0 1 0
1 0 0 0 0 0 0 Y3=S1S0I
1 0 1 0 1 0 0
1 1 0 0 0 0 0
1 1 1 1 0 0 0
I S1 S0
2
7400-1 7400-1
1 9
3
2 12 8 Y0
13 7410-1 10 7400-1
3 1
4 6 3 Y1
5 7410-1 2 7400-2
9 4
10 8 6 Y2
1 7410-1 5 7400-2
1 9
2 12 8 Y3
13 7410-2 10 7400-2
Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply inputs using toggle switches and verify the operation of Dmux using LEDs.
IC 74139 – is a Dual 1:4 Dmux and can be used as a 2:4 Decoder (A Decoder will not
have data input line)
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VCC +5V
INPUTS OUTPUTS
16
En S1 S0 Y0 Y1 Y2 Y3
X/Y
Soa 2 4 Yoa
S1a 3 1 5 Y1a
1 2 6 Y2a 1 X X 1 1 1 1
Ea EN
7 Y3a
Sob 14 12 Yob 0 0 0 1 1 1 0
S1b 13 11 Y1b
15 74LS139 10 Y2b 0 0 1 1 1 0 1
Eb 9 Y3b
8 0 1 0 1 0 1 1
0 1 1 0 1 1 1
1) Half Adder
I/P O/P
A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Design:
In a decoder outputs corresponding to all possible combinations of inputs will be
available. To realize any function it is required to tap the necessary outputs and sum them.
Since 74139 is an active low output device Nand gates are preferred to realize the function.
S = ∑m ( 1, 2) = m1 + m2 = m1 . m2 and Co= m3 = m3
74LS139
A
B Y1 6
1 Y2 7
G Y3 4 Cout
7400 6
5
Procedure:
1. Make connections as shown in the circuit diagram(Include Supply
Connections).
2. Apply inputs and verify the truth table.
2) Full Adder
I/P O/P
A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Design:
First convert 2:4 decoders into 3:8 decoder and follow the design procedure of Half
adder using decoder. S = ∑m ( 1, 2, 4,7) and Co= ∑m(3, 5, 6, 7).
Circuit diagram for Full Adder using 74139:
Dept. of TCE 34
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C.M.R.I.T, Bangalore
Cin 2 4 1
3 A Y0 5 2
74LS139
Sum
B B Y1 6 6
1 Y2 7 4 7420
A G Y3 5
1
9
7404 10 Cout
8
14 12 12 7420
13 A Y0 1 13
B 74LS139 Y1 10
Y2
2
15 9
G Y3
Procedure:
Same as that of Half Adder.
Input Output
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Design:
Design Procedure is similar to that of Half Adder. D=∑m(1, 2) and Bo=m1
Circuit diagram for Half Subtractor using 74139:
1 Difference
B 2 4 7400 3
3 A Y0 5 2
74LS139
A
B Y1 6
1 Y2 7
G Y3 4 Bout
7400 6
5
Procedure:
Similar to that of half adder.
Dept. of TCE 35
LD LAB
C.M.R.I.T, Bangalore
4) Full Subtractor
Truth table for Full Subtracotor:
I/p O/p
A B Bin D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Design:
It is similar to that of Full adder. D=∑m(1, 2, 4, 7) and Bo=∑m(1, 2, 3, 7)
Bin 2 4 1
A Y0
74LS139
3 5 2 Difference
B B Y1 6 6
1 Y2 7 4 7420
A G Y3 5
9
1
10 Bout
7404 8
12 7420
14 12 13
13 A Y0 11
74LS139
B Y1 10
Y2
2
15 9
G Y3
Dept. of TCE 36
LD LAB
C.M.R.I.T, Bangalore
G2=∑m(4, 5, 6, 7) =B2
Circuit diagram for 3-bit Binary to Gray code converter using 74139:
B0 2 4 1
A Y0
74LS139
3 5 2
B1 B Y1 6 6 G0
1 Y2 7 4 7420
B2 G Y3 5
1
9
7404 10
8 G1
14 12 12 7420
13 A Y0 11 13
74LS139
B Y1 10
Y2
2
15 9
G Y3
G2
Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply the inputs and verify the truth table.
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 0 0
1 1 1 1 0 1
Dept. of TCE 37
LD LAB
C.M.R.I.T, Bangalore
B1=∑m(2, 3, 4, 5)
B2=∑m(4, 5, 6, 7) =G2
Circuit diagram for 3-bit Gray to Binary code converter using 74139:
G0 2 4 1
A Y0
74LS139
3 5 2
G1 B Y1 6 6 B0
1 Y2 7 4 7420
G2 G Y3 5
1
9
7404 10
8 B1
14 12 12 7420
13 A Y0 11 13
74LS139
B Y1 10
Y2
2
15 9
G Y3
B2
Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply the inputs and verify the truth table.
Result: Operation of Mux and Dmux and their applications in Arithmetic circuits and Code
converters has been realized.
Conclusion: It is observed that any given function can be realized very easily realized using
Mux and Dmux.
Probable Viva Questions:
1. Define Dmux
2.What is the difference between Dmux and Decoder.
3.State practical Applicationsof Dmux and Decoder.
4. Realize 3:8 decoder using 2:4 decoders.
5. Can Decoder be used as Dmux.
6. Given a logic expression which is the best method of realizing it & why?
7. Is there any significance of enable lines being active low?
8. What do you mean by Active low and Active high logic?
9. what are the different methods of indicating active low signals?
10. State different properties Binary and Gray Code.
11. What is the significance of enble inputs
12. Design 1:2 decoder
Dept. of TCE 38
LD LAB
C.M.R.I.T, Bangalore
EXPT NO: 6
A>B
A
Magnitude A=B
B Comparator A<B
INPUT OUTPUT
(A = B) = A B + A B
0 0 0 0 1 A > B =A B
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
1
3 5 6
2 A =B
7432 7404
4
B 6 A >B
3 4 5
7408
7404
2 bit comparator:
Dept. of TCE 39
LD LAB
C.M.R.I.T, Bangalore
IN P U T S OUTPUT
B1B0
A1 A0 B1 B0 A>B A<B A=B A1A0
00 01 11 10
0 0 0 0 0 0 1 00 1 0 0 0
(A = B )= (A 1 B 1 + A 1 B 1 )(A 0 B 0 + A 0 B 0 )
0 0 0 1 0 1 0 01 0 1 0 0
0 0 1 0 0 1 0 11 0 0 1 0
0 0 1 1 0 1 0 10 0 0 0 1
0 1 0 0 1 0 0
B1B0
0 1 0 1 0 0 1 A1A0
00 01 11 10
0 1 1 0 0 1 0 00 0 0 0 0
0 1 1 1 0 1 0 01 1 0 0 0 (A > B )= A 1 B 1 + A 0 B 1 B 0 + A 1 A 0 B 0
1 0 0 0 1 0 0 11 1 1 0 1
1 0 0 1 1 0 0 10 1 1 0 0
1 0 1 0 0 0 1
B1B0
1 0 1 1 0 1 0 A1A0
00 01 11 10
1 1 0 0 1 0 0 00 0 1 1 1
1 1 0 1 1 0 0 01 0 0 1 1 (A < B )= A 1 B 1 + A 0 B 1 B 0 + A 1 A 0 B 0
1 1 1 0 1 0 0 11 0 0 0 0
1 1 1 1 0 0 1 10 0 0 1 0
Dept. of TCE 40
LD LAB
C.M.R.I.T, Bangalore
A 1 A o B 1 B o
3 5 9
1
4 6 8
2
1
3
2
7 400
1 9 A > B
2 12 10 8
13 11
7 410 7410
3
4 6
5
7 410
4
6
5
7 400
1
2 12
9
10 8 A < B
13 11
7 410 7410
3
4 6
5
7 410
1
3
2
7 486
2 A = B
1
3
4
6
7402
5
7 486
A3 >B3 X X X X X X 1 0 0
A3 <B3 X X X X X X 0 0 1
A3 =B3 A2>B2 X X X X X 1 0 0
A3 =B3 A2<B2 X X X X X 0 0 1
Dept. of TCE 41
LD LAB
C.M.R.I.T, Bangalore
10 16 10 16
AO A0 A4 A0
A1 12 A1 A5 12 A1
13 13
A2 A2 A6 A2
A3 15 A3 A7 15 A3
9 B0 9 B0
B0 11 B4
B1 B1 B5
B2 14 B2 B6 11
1
B3 2 B3 7 B7 14 B1
A<B A<B B2
1 A<B A<B A<B
VCC+5V 3 A=B A=B 6 A=B
2 A=B
4 5 B3 A=B 7 A>B
A>B 8 A>B 3 A>B 8 A>B 6
7485 47485 5
Procedure:
1. Make connections as shown in the circuit diagram.
2. Apply inputs and verify the truth table.
Note: Apply inputs such that
i) A>B Ex. A=10010011, B=01111110
ii) A=B Ex. A=00010011, B=00010011, in this case output depends on
Cascading inputs of first stage
iii) A<B Ex. A=0010011, B=01111110
Result: 1-bit, 2-bit Magnitude comparator operation has been verified using logic gates.
4-bit comparator operation is verified using 7485 and also 8-bit comparison using 4-bit
comparators is performed.
Probable Viva Questions:
1. Design 1-bit magnitude comparator
2. State applications of magnitude comparator
3. What is the significance of cascading inputs in 7485.
4. What is the principle used in comparing multi bit number.
EXPT NO:7
Dept. of TCE 42
LD LAB
C.M.R.I.T, Bangalore
VC C +5V
O /P fro m 7 4 4 7 to D e c im a l
BC D I / P
7 S e g m e n ts num ber
D C B A a b c d e f g d is p la y
0 0 0 0 0 0 0 0 0 0 1 0 A
7
1 1
16
A
13
12
7
6 a
B 2 B
2 11
0 0 0 1 1 0 0 1 1 1 1 1 C
6 4 C 10
4
f b
0 0 1 0 0 0 1 0 0 1 0 2
D 8 D
2
g
4
5 B I/R B O E
9
15
1
9 e c
0 0 1 1 0 0 0 ` 0 1 1 0 3 RBI F
0 1 0 0 1 0 0 1 1 0 0 4
3
LT 8 G
14 10
d
0 1 0 1 0 1 0 0 1 0 0 5 7447 LT312 LED
0 1 1 0 1 1 0 0 0 0 0 6 Display
0 1 1 1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 0 0 0 8
1 0 0 1 0 0 0 1 1 0 0 9
Procedure:
1. Connections are made as shown in the circuit diagram.
2. Apply BCD inputs on DCBA lines using toggle switches and observe the output
on 7 segment LED display unit.
3. Observe the outputs for the remaining combinations of the 4 bit code.
Note:
LT (LAMP TEST) This is used to check the segments of LED. If it is connected
to logic zero level, all the segments of the display connected to the decoder will be
ON. For normal decoding operation, this terminal is to be connected to logic 1 level.
Dept. of TCE 43
LD LAB
C.M.R.I.T, Bangalore
One of the most commonly used device for a digital system is a set of ten switches, one for
each numeral between 0 and 9. these switches generate 1 or 0 logic levels in response to
turning them OFF or ON. When a particular number is to be fed to the digital circuit in BCD
code, the switch corresponding to that number is pressed. The IC version of this is shown in
the following figure and the truth table is also given. It has active low inputs and outputs. The
meaning of the word priority can be seen from the truth table. For example, if inputs 3 and 7
are LOW, the output will be corresponding to 7 which has the higher priority than 3, that is
highest numbered input has highest priority than the lower numbered inputs.
Dept. of TCE 44
LD LAB
C.M.R.I.T, Bangalore
VCC+5V
INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 D C B A
0 0 1 1 0
I1 11 16 x x x x x x x x
I2 12 X X X X X X X 0 1 0 1 1 1
I3 13
I4 A
74147
1 9 X X X X X X 0 1 1 1 0 0 0
I5 2 7 B
I6 3 6 C
I7 D X X X X X 0 1 1 1 1 0 0 1
4 14
I8 5
I9 X X X X 0 1 1 1 1 1 0 1 0
10
8
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1
Procedure:
1. Connections are made as shown in the circuit diagram.
2. Apply Decimal inputs using toggle switches and observe the output on LED unit.
The octal code is often used at the inputs of digital circuits that require manual entering of
long binary words. Priority encoder 74148 IC has been designed to achieve this operation. Its
logic diagram and truth table is as shown below. This circuit also has active low inputs and
outputs. The enable input and carry outputs are also active low and they are used to cascade
circuits to handle more inputs.
Dept. of TCE 45
LD LAB
C.M.R.I.T, Bangalore
INPUTS OUTPUTS
Ei I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 Gs Eo
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X X X 0 0 0 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
Dept. of TCE 47
LD LAB
C.M.R.I.T, Bangalore
EXPT NO: 8
AIM: Truth Table Verification of MS - JK FF, T – FF, D – FF
COMPONENTS REQUIRED: IC Trainer kit, IC7400 NAND gate, IC 7404 INVERTER and
IC7476 MS JK – FF.
PR
1 9 Qm 12 Qn
2 12 10 8 4 7410 11
J 7420 7420
13 11 7400 6 13
5
1
7400 3
2
CLOCK
9
3 1 7400 8 1
4 7420 6 2 7420 12 10 7410 3
K 5 13 2
Qm Qn
CR
Note: Keep pr = 1 and cr = 1 for verifying the Truth Tables of JKMS FF, T and D FFs
Dept. of TCE 48
LD LAB
C.M.R.I.T, Bangalore
T
1 9 Qm 12 Qn
2 12 10 8 4 7410 11
13 7420 11 7410 6 13
5 7400
1
7400 3
2
CLOCK
9
3 1 7400 8 1
4 6 2 12 10 3
5
7420
13
7410 2
7410
Qm Qn
CR
Input Output
Comments
CLK T Qn+1
0 X Qn No change
0 Qn No change
1 Qn Toggles
Dept. of TCE 49
LD LAB
C.M.R.I.T, Bangalore
7404
PR
2
1
2 12
9
10 8
Qm 4
12
11
Q
7420 7410 7410
14 11 6 13
7400
5
1
3
7400
2
CLOCK
9
3 1 8 1
4 6 2 12 10 7400 3
7420 7410 7410
5 13 2
Qm Qn
CR
Input Output
Comments
CLK D Qn+1
0 X Qn No change
Data
0 0
Transferred
Data
1 1
Transferred
LOGIC 1 LOGIC 1
2
T- input
2
J - input 4 PR Q 15 4 15
J Q J Q Q
PR
1 1
CLOCK CLK CLK
16 CL 14 CLOCK 16 14
K Q K Q Q
CL
K - input
Q
3 7476 7476
3
LOGIC 1 LOGIC 1
Dept. of TCE 50
LD LAB
C.M.R.I.T, Bangalore
LOGIC 1
D - input
2
4 15
J Q Q
PR
CLOCK 1
CLK
16 14
1
K Q Q
CL
7404 7476
3
LOGIC 1
2
EXPT NO: 9
Dept. of TCE 51
LD LAB
C.M.R.I.T, Bangalore
COMPONENTS REQUIRED: IC Trainer kit, IC7476 MSJK FF, IC7400 NAND gates,
IC7490 Decade counter, IC7493 Binary counter, IC74192 Decade Up-down counter and
IC74193 Binary Up-down counter.
MOD 8 UP COUNTER:
Counting Sequence:
Number of Flip Flop Outputs
Clock pulse
Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
Excitation table:
Present Next
FlipFlops States
State State
Present Next
J K Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
State State
0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 1 X
0 1 0 0 1 1 0 X X 0 1 X
1 0 X 1
0 1 1 1 0 0 1 X X 1 X 1
1 1 X 0 1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
J0 = 1 K0 = 1 J1 = Q0
1 1 X X 1 1 X 1 1 X
1 0 1 X X
Dept. of TCE 52
LD LAB
C.M.R.I.T, Bangalore
K1 = Q0 J2 = Q1Q0 K2 = Q1Q0
1 X X 1 0
X X X X 1 0 0 1 0
1
Exercise:
Dept. of TCE 53
LD LAB
C.M.R.I.T, Bangalore
Block Diagram
OUTPUTS
Q0 Q1 Q2 Q3
CLOCK B MR MR MS MS
RESET INPUTS SET INPUTS
MS1, MS2, MR1and MR2 inputs are connected to GND (Active HIGH I/O’s).
Clock input is given to Clock A
Output Q0 and Clock B are shorted so that it acts as Divide-by 10 counter with
BCD count sequence.
Verify the truth table and observe the waveforms on CRO.
Realization of MOD-6 Counter using 7490:
Clock 1 2 3 4 5 6
Clock I/P Input
5
6
4
7400 Q0
14
7
0 1 0 1 0 1 0
3
B
A
R9(2)
R9(1)
R0(2)
R0(1)
Q1
7490 0 0 1 1 0 0 0
7400
QD
QC
QB
QA
Q2
1 2 0 0 0 0 1 1 0
12
11
Q3
0 0 0 0 0 0 0
QD QC QB QA (LSB)
Truth Table:
Dept. of TCE 54
LD LAB
C.M.R.I.T, Bangalore
Input
Q3 Q2 Q1 Q0
pulses
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 0 0 0
Block Diagram
OUTPUTS
Q0 Q1 Q2 Q3
CLOCK B MR MR
RESET INPUTS
Dept. of TCE 55
LD LAB
C.M.R.I.T, Bangalore
14
12
2
1
B 1 0 0 0 1
A
MR1
MR2
10 5 7410
2 0 0 1 0
GND VCC
7493 VCC
3 0 0 1 1
4 0 1 0 0
QD
QC
QB
QA
13
1
2
5 0 1 0 1
8
12
11
1
6 0 1 1 0
13
2 12
7 0 1 1 1
QD QC QB QA (LSB) 7410 8 1 0 0 0
9 1 0 0 1
Realization of MOD-14 Binary counter using IC 7493: 10 1 0 1 0
11 1 0 1 1
Clock I/P 12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
12
14
2
16 0 0 0 0
B
A
MR1
MR2
10
GND VCC
5 7410
7493 VCC
QD
QC
QB
QA
13
1
2
8
12
11
1
2 12
13
QD QC QB QA (LSB) 7410
Input
Q3 Q2 Q1 Q0
Truth Table: pulses
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 0 0 0 0
Dept. of TCE 56
LD LAB
C.M.R.I.T, Bangalore
IC74192 is a synchronous 4 - bit decade up–down counter which can be cleared and preset to
any count.
10
15
11
Vcc
4
1 0 1 Up Count
B
A
D
C
DN
UP
CLR
LOAD
8 1 0 1 16 Down Count
GND VCC
0 074192 X X Preset
1 0 1 1 Stop Count
CO
QD
QC
BO
QB
QA
7
3
13
12
For Up Count: Give Clock only to Clock Up input (pin 5). Make Clock down input (pin 4)
logic HIGH. If the outputs QD to QA counts from 1001 to 0000, then carry is LOW. Else
carry is HIGH.
For Down Count: Give Clock only to Clock Down input (pin4). Make Clock up input (pin
5) logic HIGH. If the outputs QD to QA counts from 0000 to 1001, then borrow is LOW.
Else borrow is HIGH.
Note: The carry and the borrow outputs are normally at logic HIGH.
Carry and borrow are mainly used for cascading the counters.
Dept. of TCE 57
LD LAB
C.M.R.I.T, Bangalore
PRESET TO 5
Clock Clock 0 1 0 1 (LSB)
4 5
6 7420
2
14
15
10
11
Vcc
1
4
1
B
A
D
C
DN
UP
CLR
LOAD
8 16
GND VCC 2 4 6 8
74192
QD
QC
BO
QB
QA
7
3
13
12
1 3 5 9
Borrow Carry
QD QC QB QA (LSB)
To count from 5 to 9:
PRESET TO 8
Clock Clock 1 0 0 0 (LSB)
4 5
6 7420
2
14
10
15
11
Vcc
4
1
B
A
D
C
DN
UP
CLR
LOAD
8 16
GND VCC 2 4 6
74192
QD
QC
BO
QA
QB
7
3
13
12
1 3 5
Borrow Carry
QD QC QB QA (LSB)
Dept. of TCE 58
LD LAB
C.M.R.I.T, Bangalore
a)
14
10
15
11
Vcc
4
A
D
C
DN
UP
b)
CLR
LOAD
8 16
GND
74193
VCC Design 12 to 3 down counter using IC74193
c)
Design 15 to 6 down counter using IC74193
CO
QD
QC
BO
QB
QA
7
3
13
12
Dept. of TCE 59
LD LAB
C.M.R.I.T, Bangalore
EXPT NO: 10
AIM: STUDY OF SHIFT REGISTER IC 7495 FOR SISO, SIPO, PISO, PIPO, SHIFT
RIGHT AND SHIFT LEFT OPERATIONS.
Pin
14
1
SER
DS details
VCC
2
A
D3
3 QA
13
Q3 of
B
D2
4 QB
12
Q2 7495:
D1 C 7495 11
5 QC Q1
D
D0
QD
10
Q0
DS serial input data to be
6
M MODE right shifted
CLOCK-LEFT 9
CLK1-L
D3, D2, D1, D0 parallel data
CLOCK - RIGHT 8
CLK2-R
inputs to be loaded in to the
GND
shift reg.
7
M - Mode control.
M = 1 for loading parallel data and
to enable Clock 2.
M = 0 for enabling clock 1.
Clock 2 for loading parallel input data and for shift left of data.
Clock 1 for right shift of data.
Q3, Q2, Q1, Q0 parallel out put of the shift register.
pulses at Q0.
Parallel input parallel output (PIPO) operation:
Dept. of TCE 61
LD LAB
C.M.R.I.T, Bangalore
Serial Outputs
Clock Time input
D0 Q3 Q2 Q1 Q0
CLK2 T0 1(LSB 1
T1 0 1 0
T2 1 1 0 1
T3 1 1 0 1 1
Dept. of TCE 62
LD LAB
C.M.R.I.T, Bangalore
EXPT NO: 11
DS 1
SER
D3 2
A 13
QA
D2 3
B 12
QB
D1 4
C
7495 11
QC
D0 5
D 10
QD
TOGGLE SWITCH 6
MODE
CLOCK 9
CLK1-L
8
CLK2-R
If the serial output Q0 of the shift register is connected back to the serial input
DS, then an injected pulse will keep circulating. This is known as ring counter.
Mode control is made 1.
Parallel inputs 0001 are given to D3D2D1D0 inputs.
CLK 2 is pulsed once. Now D3D2D1D0 parallel inputs appear on QA, QB, QC, QD
lines.
CLK 1 is connected to the pulser.
Now mode control is made LOW.
When clock pulses are applied, this ‘1’ circulates around the circuit as shown.
Observe the output waveforms QA, QB, QC,QD on CRO.
Dept. of TCE 63
LD LAB
C.M.R.I.T, Bangalore
Outputs
Clock Time
QA QB QC QD
CLK2 T0 0 0 0 1
CLK1 T1 1 0 0 0
T2 0 1 0 0
T3 0 0 1 0
T4 0 0 0 1
2 1
7404
1
2 SER 13
3 A QA 12
4 B QB 11
5 C QC 10
D QD
6
9 MODE
CLK CLK1-L
8
CLK2-R
7495
clk Qa Qb Qc Qd
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0
9 1 0 0 0
Dept. of TCE 64
LD LAB
C.M.R.I.T, Bangalore
Dept. of TCE 65
LD LAB
C.M.R.I.T, Bangalore
EXPT NO: 12
Example1:
Design a sequence generator to generate the sequence S = …100010011010111…..
Here length S = 15. Hence we require at least 4 Flip Flops.
7486
2
3
1
1
SER
D3 2
A 13
QA Q3
D2 3
B 12
QB Q2
D1 4 7495
C 11
QC Q1
D0 5
D 10
QD Q0
TOGGLE SWITCH 6
MODE
CLOCK 9
CLK1-L
8
CLK2-R
Dept. of TCE 66
LD LAB
C.M.R.I.T, Bangalore
Function table:
Serial inputs Y K- MAP for Y:
Clock Q3 Q2 Q1 Q0 =
f(Q0Q1Q2Q3)
Q1Q0
1 1 1 1 1 0
Q3Q2 00 01 11 10
2 0 1 1 1 0
3 0 0 1 1 0 00 X 1 0 1
4 0 0 0 1 1
5 1 0 0 0 0 01 0 1 0 1
6 0 1 0 0 0
7 0 0 1 0 1 11 0 1 0 1
8 1 0 0 1 1
9 1 1 0 0 0 0 1 0 1
10
10 0 1 1 0 1
11 1 0 1 1 0
12 0 1 0 1 1
13 1 0 1 0 1
14 1 1 0 1 1 Expression for Y:
15 1 1 1 0 1
1 1 1 1 1 0
Y Q1Q 0 Q1Q 0
2 0 1 1 1 0 Y Q1 Q 0
3 0 0 1 1 0
.
.
15
Dept. of TCE 67
LD LAB
C.M.R.I.T, Bangalore
Example 2:
Design a sequence generator to generate the sequence S = … 1101011
Here the length of the sequence is S = 7, Hence we require at least 3 flip flops, We can
observe that here all the states are not distinct (i.e., the states are repeating) Therefore, N
= 3 Flip Flops are not sufficient, We assume N = 4 and prepare the truth table for the
sequence generator. Starting state Q3, Q2, Q1, Q0 is 1110.
7410
1 2 13
12
1
SER
D3 2
A 13
QA Q3
D2 3
B 12
QB Q2
D1 4 7495
C 11
QC Q1
D0 5
D 10
QD Q0
TOGGLE SWITCH 6
MODE
CLOCK 9
CLK1-L
8
CLK2-R
Serial inputs Y
Clock Q3 Q2 Q1 Q0 =
f(Q0Q1Q2Q3)
1 1 1 1 0 1
2 1 1 1 1 0
3 0 1 1 1 1
4 1 0 1 1 0
5 0 1 0 1 1
6 1 0 1 0 1
7 1 1 0 1 1
01 X 1 1 X
Expression for Y:
11 X 1 0 1
Y Q3 Q1 Q 0
Y Q3Q1Q 0
10 X X 0 1
Dept. of TCE 68
LD LAB
C.M.R.I.T, Bangalore
APPENDIX 1
IC 7408 V
C
VCC
1 14
14 VCC
13 1
2
12 2 13
3
11 3 12
4
10 4 11
5
9 5 10
6
7 6 9
8
GND GND 7 8
NAND GATE (TWO INPUT) IC 7400 EXOR GATE IC7486
IC 7400 IC 7486
1 14 VCC
1 14 VCC
13
2
2
12 13
3 3 12
11
4 4
10 11
5
5 10
9 9
6 6
7 8 GND
GND 7 8
Dept. of TCE 69
LD LAB
C.M.R.I.T, Bangalore
OR GATE 1
14 VCC
2
IC 7432
13
3 12
4
11
5
6 10
9
7
GN 8
D
1 14 VCC
IC 7402
2 13
3 12
4
11
5 10
6 9
GN 7 8
D
Dept. of TCE 70
LD LAB
C.M.R.I.T, Bangalore
5 11
10
6 9
GN 8
7
D
4 12
5 11
10
6 9
7 8
GND
1 16
B3 VCC
2 15
A<B_IN A3
7476
3 14
2
A=B_IN B2
4 13
4 15 A>B_IN A2
PRE
J Q
5 7485 12
1 A>B A1
CLK
6 11
16 14 A=B B1
K Q
7 10
CLR
A<B A0
8 9
GND B0
3
Dept. of TCE 71
LD LAB
C.M.R.I.T, Bangalore
1 14
1 14 CKB CKA
I/P B I/PA
2 13
2 13
R1 NC R01 NC
3 12 3 12
R2 QA R02 QA
4
NC
7493
QD
11 4 11
NC 7490 QD
5 10 5 10
VCC GND
VCC GND
6 9
NC QB 6 9
R91 QB
7 8
NC QC 7 8
R92 QC
1 Segment E
10 9 8 7 6 2 Segment D
6 3 Common Cathode
a
4 Segment C
b 5 DIP (Dual In Package)
f g 6 Segment B
7 Segment A
e c 8 Common Cathode
9 Segment F
d 10 Segment G
1 2 3 4 5
5
1 4 VCC 16
2 5 7 NC 15
3 6 4 D 14
4 7 1 3 13
5 8 4 2 12
6 C 7 1 11
7 B 9 10
8 GND A 9
Dept. of TCE 72
LD LAB
C.M.R.I.T, Bangalore
VCC
GND
P1 VCC
1 16
8
Q1 P0 P0 Q0
16
2 15 15 3
Q0 CLR P1 Q1
3 14 1 2
Clk-DN 74192 Borrow P2 Q2
4 13 10 6
74193
P3 Q3
Clk-UP Carry 9 7
5 12
Clk-UP Carry
Q2 Load 5 12
6 11
Clk-DN Borrow
Q3 P2 4 13
7 10
14
11
GND P3
8 9
Load
CLR
Pin details of 74192 IC Shift Register
14
6
VCC
1 MODE
9 SER
8 CLK1
2 13
3 A QA
B
7495 QB
12
4 11
5 C QC 10
D QD
7 GND
U1
16
3
I3A
VCC
4
I2A
MUX1
5 7
I1A ZA
1
INB OUTE
9 1
A4 SUM1
9 4-1
6
I0A
2 10 2 10
INC OUTD SUM3 A1 1
EA
3 11 3 11
LT OUTC A3 B1
10
74153
4 12 5 12 I0B
BI/RBO OUTB VCC GND
7483A
7446
5 13 4 13 11 9
RBI OUTA B3 C0 I1B ZB
6 14 6 14 12 MUX2
IND OUTG SUM2 C4 I2B
7 15 7 15 13 4-1
INA OUTF B2 SUM4 I3B
8 16 8 16 15
GND VCC A2 B4 EB
GND
S0
S1
14
Dept. of TCE 73
LD LAB
C.M.R.I.T, Bangalore
VIVA-VOCE QUESTIONS
1. Mention the difference between Analog and Digital Signals. Give Ex.
2. What is an Analog circuit and digital circuit. Give Ex.
3. What is positive logic and negative logic?
4. What is a Gate? Name different types.
5. Give Ex. For Basic Gates.
6. Why NAND and NOR gates are called universal gates?
7. Mention the merits of using Digital Systems.
8. What is truth table?
9. Name different types of Logic families.
10. What is the difference between Algebra and Boolean algebra?
11. State De-Morgan’s theorems.
12. For a gate with N inputs, how many combinations of inputs are possible?
13. What is Inhibit or disable condition of a gate? How it is achieved.
14. Why Semiconductor devices are preferred for making digital switches instead of relays
and mechanical switches?
15. What are the advantages of ICs over discrete circuits?
16. Why Schottky diodes are preferred than PN junction diodes in digital circuits
17. What are the differences between Linear and Digital ICs?
18. What are the methods to represent negative numbers in digital systems
19. Why Binary number system is used in digital systems
20. Define the terms Fan out, Fan in, Propagation delay, Noise margin w.r.t logic gates.
21. Define the term figure of merit of a digital IC.
22. What is tri-state logic?
23. Name the different types of TTL ICs available
24. Which type of Logic family is faster?
25. Give the typical values of Fan in, Fan out, Propagation delay, Power dissipation in TTL
gates.
26. Explain the meaning the symbol used in 74 series TTL ICs
27. What is half adder and full adder. Why it is called so?
28. What are the applications of half adder and full adder?
29. Why subtractor IC is not available?
30. What is meant by a 7 segment LED display?
31. Which are the different types of LED displays?
32. Mention the common anode and common cathode display numbers?
33. Mention the different types of displays?
34. What are the difference between LED display and LCD display?
35. Explain the importance of BI/RBO, RBI and LT in 7447 decoder chip
36. What do you mean by dp in the display?
37. What do you mean by decoder/driver?
38. Mention the applications of LED and LCD displays
39. What is the difference between MUX and Encoder?
40. What is the type of display device used in your calculator?
41. What is the difference between Demux and decoder?
42. Why 2:4 decoder is sometimes called as a 1-of-4 decoder?
43. What is multiplexer?
44. What is de multiplexer?
45. Is the display device used in a digital wristwatch is LED or LCD? Why?
46. Mention the application for MUX and DEMUX?
Dept. of TCE 74
LD LAB
C.M.R.I.T, Bangalore
72. Write the transistor version circuit diagram for TTL NOT gate IC
73. Write the internal block diagram for four-bit full adder chip?
74. Which code is called reflected or cyclic or unit-distance code?
75. Which code is called self-complementing code?
76. Where we use Excess-3 codes?
77. Why code conversion is required?
78. What is Ring counter?
79. What is Johnson counter?
80. Which counter is called twisted ring counter or switch-tail counter or moebious counter?
81. Which codes using in the k-map to represent the blocks?
82. Mention the application for Ring counter and Johnson counters?
83. State distributive law, commutative law and associate law with examples?
84. What is don’t care condition means?
85. How many states are possible in 4-bit ring counter and 4 bit Johnson counters?
86. What is o/p frequency of 4-bit ring counter and 4 bit Johnson counters?
87. Where do we use down counter?
88. Where do we use counters?
89. What is strobe?
90. What are the various methods used for triggering flip-flops?
91. What is meant by active low and active high?
92. Differentiate between S-R, J-K and M/S J-K flip-flops?
93. Differentiate T Flip flop and D flip-flop
94. Write down the internal block diagram for IC 7490?
95. How do you represent –5 and +5 in binary form?
Dept. of TCE 75
LD LAB
C.M.R.I.T, Bangalore
96. Which codes are called weighted codes and which codes are called weighted codes?
97. What are pre-settable counters? What are the applications?
98. What is the use of Tcu and Tcd pins in IC 74193?
99. What is a multivibrator circuit? Classify.
100. Why IC 555 is called timer chip.
101. Mention the features of IC 555
102. What is the use of RESET pin in IC 555?
103. Why a diode is connected in parallel with R B in symmetrical Astable multivibrator
circuit.
104. Can we make RA = 0 for getting 50% duty cycle in Astable mode? Justify your answer.
105. Why a 0.01f capacitor is connected at pin 5 of IC 555? Can we replace with any
other value?
106. Mention some of the applications of IC 555 used as Astable and Monostable
multivibrator circuits.
107. What are the applications of Magnitude comparators?
108. What is the significance of cascading inputs?
109. Why cascading inputs A=B is made 1, A<B and A>B is made 0
110. What is a shift register? Classify.
111. Name different modes of operations of shift registers.
112. What is sequence generator? Name different types. Mention the applications of
sequence generators.
113. Write the block diagram of sequence generator Ckt.
114. What is priority encoder? Mention the applications of priority encoder.
115. What is the difference between encoder and priority encoder?
Dept. of TCE 76