DDR 2

DDR2 SDRAM DIMM 240 pin · AllPinouts https://allpinouts.org/pinouts/connectors/memory/ddr2-sdram-dimm-240...
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01 Mar 1998
DDR2 SDRAM DIMM 240 pin
DDR: Double Data Rate

DIMM: Dual Inline Memory Module
SDRAM: Synchronous Dynamic Random Access Memory,
Synchronous to Positive Clock Edge.
PIN CONFIGURATIONS (Front side / back side)
Front Back
Pin Symbol
1 VREF
2 VSS
3 DQ0
4 DQ1
5 VSS
6 DQS0#
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Front Back
7 DQS0
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8 VSS
Pinouts
9 DQ2
About
10 DQ3
11 VSS
12 DQ8
13 DQ9
14 VSS
15 DQS1#
16 DQS1
17 VSS
18 RESET#
19 NC
20 VSS
21 DQ10
22 DQ11
23 VSS
24 DQ16
25 DQ17
26 VSS
27 DQS2#
28 DQS2
29 VSS
30 DQ18
Note: Pin 196 is NC for 512MB, or A13 for 1GB and 2GB; pin 54 is NC
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for 512MB and 1GB, or BA2 for 2GB.
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Pin Descriptions
Pinouts Pin numbers may not correlate with symbols; refer to Pin Assignment
table above for more information.
About
Pin Numbers Symbol Type Description
On-Die Termination: ODT

(registered HIGH) enables
termination resistance internal to
the DDR2 SDRAM. When
enabled, ODT is only applied to
195 ODT0 Input
each of the following pins: DQ,
DQS, DQS#, RDQS, RDQS#,
CB, and DM. The ODT input will
be ignored if disabled via the
LOAD MODE command.
Clock: CK and CK# are

differential clock inputs. All
address and control input
signals are sampled on the
185, 186 CK0, CK0# Input crossing of the positive edge of
CK and negative edge of CK#.
Output data (DQs and
DQS/DQS#) is referenced to the
crossings of CK and CK#.
Clock Enable: CKE (registered

HIGH) activates and CKE
(registered LOW) deactivates
clocking circuitry on the DDR2
SDRAM. The specific circuitry
52 CKE0 Input
that is enabled/disabled is
dependent on the DDR2
SDRAM configuration and
operating mode. CKE LOW
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provides PRECHARGE
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POWER-DOWN and SELF
Pinouts REFRESH operations (all device
About banks idle), or ACTIVE
POWERDOWN (row ACTIVE in
any device bank). CKE is
synchronous for POWER-
DOWN entry, POWER-DOWN
exit, output disable, and for
SELF REFRESH entry. CKE is
asynchronous for SELF
REFRESH exit. Input buffers
(excluding CK, CK#, CKE, and
ODT) are disabled during
POWER-DOWN. Input buffers
(excluding CKE) are disabled
during SELF REFRESH. CKE is
an SSTL_18 input but will detect
a LVCMOS LOW level once
VDD is applied during first
power-up. After Vref has become
stable during the power on and
initialization sequence, it must
be maintained for proper
operation of the CKE receiver.
For proper self-refresh operation
VREF must be maintained to this
input.
Chip Select: S# enables

(registered LOW) and disables
(registered HIGH) the command
193 S0# Input decoder. All commands are
masked when S# is registered
HIGH. S# provides for external
rank selection on systems with
4 of 10 6/18/2018, 8:27 AM
multiple ranks. S# is considered

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part of the command code.
Pinouts
RAS#, Command Inputs: RAS#, CAS#,
About 73, 74, 192 CAS#, Input and WE# (along with S#) define
WE# the command being entered.
Bank Address Inputs: BA0Â–

BA1/BA2 define to which device
bank an ACTIVE, READ,
WRITE, or PRECHARGE
54 (2GB), 71, BA0, BA1, command is being applied.
Input
190 BA2 (2GB) BA0Â–BA1 define which mode
register including MR, EMR,
EMR(2), and EMR(3) is loaded
during the LOAD MODE
command.
Address Inputs: Provide the row

address for ACTIVE commands,
and the column address and
auto precharge bit (A10) for
Read/ Write commands, to
57, 58, 60, select one location out of the
61, 63, 70, A0Â–A12 memory array in the respective
176, 177, (512MB) bank. A10 sampled during a
179, 180, A0Â–A13 Input PRECHARGE command
182, 183, (1GB, determines whether the
188, 196 2GB) PRECHARGE applies to one
(1GB, 2GB) device bank (A10 LOW, device
bank selected by BA0Â–
BA1/BA2) or all device banks
(A10 HIGH). The address inputs
also provide the op-code during
a LOAD MODE command.
3, 4, 9, 10, DQ0Â– Data Input/Output: Bidirectional

I/O
12, 13, 21, DQ63 data bus.
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22, 24, 25,

Home
30, 31, 33,
Pinouts 34, 39, 40,
About 80, 81, 86,
87, 89, 90,
95, 96, 98,
99, 107, 108,
110, 111, 116,
117, 122,
123, 128,
129, 131,
132, 140,
141, 143,
144, 149,
150, 152,
153, 158,
159, 199,
200, 205,
206, 208,
209, 214,
215, 217,
218, 226,
227, 229,
230, 235, 236
6, 7, 15, 16, Data Strobe: Output with read

27, 28, 36, data, input with write data for
DQS0Â–
37, 45, 46, source synchronous operation.
DQS8,
83, 84, 92, Edge-aligned with read data,
DQS0#Â–
93, 104, 105, center aligned with write data.
DQS17#,
113, 114, I/O DQS# is only used when
DM0Â–
126, 135, differential data strobe mode is
DM8
147, 156, enabled via the LOAD MODE
(DQS9Â–
165, 203, command. Input Data Mask: DM
DQS17)
212, 224, 233 is an input mask signal for write
125, 134, data. Input data is masked when
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DM is sampled HIGH along with

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that input data during a WRITE
Pinouts access. DM is sampled on both
About edges of DQS. Although DM
146, 155,
pins are input-only, the DM
164, 202,
loading is designed to match that
211, 223, 232
of DQ and DQS pins. If RDQS is
disabled, DQS0Â–DQS17
become DM0Â–DM8 and
DQS9#Â–DQS17# are not used.
42, 43, 48,

49, 161, 162, CB0Â–CB7 I/O Check Bits.
167, 168
Parity bit for the address and

68 PAR_IN Input
control bus.
Parity error found on the

55 ERR_OUT Output
address and control bus.
Serial Clock for Presence-

Detect: SCL is used to
120 SCL Input synchronize the presence-detect
data transfer to and from the
module.
Presence-Detect Address
Inputs: These pins are used to
101, 239, 240 SA0Â–SA2 Input
configure the presence-detect
device.
Serial Presence-Detect Data:

SDA is a bidirectional pin used
119 SDA I/O to transfer addresses and data
into and out of the presence-
detect portion of the module.
Asynchronously forces all

18 RESET# Input
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registered outputs LOW when

Home
RESET# is LOW. This signal can
Pinouts be used during power up to
About ensure that CKE is LOW and
DQs are High-Z.
53, 59, 64,

67, 69, 172,
178, 184, VDD Supply Power Supply: 1.8V ±0.1V.
187, 189,
197,
51, 56, 62,

72, 75, 78,
170, 175, VDDQ Supply DQ Power Supply: 1.8V ±0.1V.
181, 191,
194,
1 VREF Supply SSTL_18 reference voltage.
2, 5, 8, 11,
14, 17, 20,
23, 26, 29,
32, 35, 38,
41, 44, 47,
50, 65, 66,
79, 82, 85,
88, 91, 94,
97,100, 103,
VSS Supply Ground.
106, 109,112,
115, 118,
121, 124,
127, 130,
133, 136,
139, 142,
145, 148,
151, 154,
157, 160,
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163, 166,
Home
169, 198,
Pinouts 201, 204,
About 207, 210,
213, 216,
219, 222,
225, 228,
231, 234, 237
Serial EEPROM positive power

238 VDDSPD Supply
supply: +1.7V to +3.6V.
19, 54
(512MB,
1GB), 76, 77, No Connect: These pins should
NC -
102, 171, 196 be left unconnected.
(512MB),
173, 174,
137, 138,
RFU — Reserved for future use.
220, 221
References
Micron: DDR2 SDRAM (PDF link)
Category:Memory Connectors
DEC DLV11-J Serial DDR SDRAM DIMM 184 Pin
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DDR2 SDRAM DIMM 240 pin · AllPinouts https://allpinouts.org/pinouts/connectors/memory/ddr2-sdram-dimm-240...

DDR2 SDRAM DIMM 240 pin

DDR: Double Data Rate

PIN CONFIGURATIONS (Front side / back side)

for 512MB and 1GB, or BA2 for 2GB.

Pin Numbers Symbol Type Description

On-Die Termination: ODT

Clock: CK and CK# are

Clock Enable: CKE (registered

Pin Numbers Symbol Type Description

Chip Select: S# enables

Pin Numbers Symbol Type Description

multiple ranks. S# is considered

Bank Address Inputs: BA0Â–

Address Inputs: Provide the row

3, 4, 9, 10, DQ0Â– Data Input/Output: Bidirectional

Pin Numbers Symbol Type Description

22, 24, 25,

6, 7, 15, 16, Data Strobe: Output with read

Pin Numbers Symbol Type Description

DM is sampled HIGH along with

42, 43, 48,

Parity bit for the address and

Parity error found on the

Serial Clock for Presence-

Serial Presence-Detect Data:

Asynchronously forces all

Pin Numbers Symbol Type Description

registered outputs LOW when

53, 59, 64,

51, 56, 62,

1 VREF Supply SSTL_18 reference voltage.

Pin Numbers Symbol Type Description

Serial EEPROM positive power

DEC DLV11-J Serial DDR SDRAM DIMM 184 Pin

© 1998-2018 – Nicola Asuni - Tecnick.com - All rights reserved.

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