Design, Implement and Test a Signed

Eight-Bit Booth Encoded Multiplier

Anwesh Mohanty, 170070009
April 19, 2019

1 Overview of the experiment

To design a 8-bit signed booth encoded multiplier using only structural
VHDL. The RTL and gate level simulations are carried out using Model-
sim and tested using a tracefile.

2 Algorithm
Algorithm Overview: In booth encoding, we reduce the number of partial
products by multiplying 2 bits at a time. Let the multiplicand be A and the
multiplier be B. We multiply A with two bits of B at a time. Depending
on the two bits being 00,01,10 and 11, the product will be 0, A, 2A and
3A. Generating partial products of 0 and A is straightforward. 2A can be
generated as 4A-2A and 3A can be generated as 4A-A. 4A can generated by
adding 1 to the next two bits of the multiplier (i.e. B). 2A can generated by
left shifting all bits of A by one place.
Main Algorithm: Consider two bits of the multiplier in every step starting
from LSB. If 00 do nothing, for 01 add A, for 10 subtract 2A and ask next
group to add 4A, and for 11 subtract A and ask next group to add 4A. The
next group looks at the more significant bit of the previous group and adds
1 to the multiplier accordingly.

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 Current 2-bits Multiplier Previous MSB Increment Final Multiplier
00 0 0 0 0
01 +1 0 0 +1
10 -2 0 0 -2
11 -1 0 0 -1
00 0 1 +1 +1
01 +1 1 +1 +2
10 -2 1 +1 -1
11 -1 1 +1 0

Table 1: Summary of the basic operations

3 Experiment setup
The following VHDL files were designed for the assignment:
Bit adder.vhdl
booth.vhdl
DUT.vhdl
Gates.vhdl
left shift.vhdl
left shift2.vhdl
Testbench.vhdl

4 Circuit Implementation
4.1 Bit Adder-Subtractor
The bit adder can perform both addition and subtraction of two 16 bit num-
bers depending on the control input (Cin ) i.e. if Cin is 0 then addition is
done else subtraction. It performs twos complement subtraction. Each of
the 16 sub-blocks of the circuit consists of a full adder and a combination of
gates to calculate the twos complement if required for subtraction.
The netlist for the bit adder is:

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Figure 1: Bit adder-subtractor used in Booth multiplication

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4.2 Left-Shifter
Two left shifters are implemented for 16 bit numbers. Left shift.vhdl shifts
the corresponding input by 1 bit and Left shift2.vhdl shifts it by 2 bits.
Multiplication by 2 corresponds to shifting by one bit and by 4 corresponds
to shifting by two bits. Each sub-block consists of a 2-to-1 multiplexer which
just shifts the bits.
The netlist for the one bit left shifter is:

Figure 2: One bit left shifter used in Booth multiplication

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4.3 Gates
Gates.vhdl contains all the basic gates(AND,OR,NOT,NOR,XOR,NAND),
2-to-1 multiplexer, 4-to-1 multiplexer, half adder and full adder constructed
using gates.

4.4 Booth Encoder

Booth.vhdl implements the booth encoding algorithm described above. It
uses all the above subcomponents.
The netlist for the booth encoder is:

Figure 3: Netlist of Booth encoder

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5 Observations and Scrrenshots

Figure 4: Compilation Success

Figure 5: RTL transcript

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Figure 6: Waveforms obtained in RTL simulation

Figure 7: Gate level simulation transcript

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Figure 8: Waveforms obtained in Gate level simulation