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FSC LCD Backlight Inverter IC Solution

Lighting Product Line


Power Conversion

www.fairchildsemi.com
FSC Product Line - up

Features
Generation Products Description Status
Vcc (V) Dimming Soft Start OLP OLR(=OVP) SCP Vout(Max) Iout(Max)

FAN7547A 1Ch. Buck-Royer 6 ~ 30 Analog, Burst O O O X Vcc 0.2A S


0G
FAN7548 2Ch. Buck-Royer 9 ~ 30 Analog, Burst O O O X 13.5V 0.2A S

FAN7311/A/B P-N Full Bridge 5 ~ 25.5 Analog, Burst O O O X 8.5V 0.2A S


1st G
FAN7314/A P-N Half Bridge 5 ~ 25.5 Analog, Burst O O O X 8.5V 0.2A S

FAN7313 Push-Pull 4.5 ~ 25.5 Analog, Burst O Internal (4) O O 6V 0.5A S

FAN7316 N-N Half Bridge 4.5 ~ 24 Analog, Burst O Internal (4) O O 6V 0.5A S
2nd G
FAN7317 P-N Full Bridge 6 ~ 24 Burst O Internal (4) Internal (4) SLP 6V 0.2/0.3A S

FAN7318 P-N Half Bridge 6 ~ 30 Analog, Burst O Internal (4) Internal (4) SLP 8V 0.3/0.4A D (P12)

3rd G FAN7320 H/B Switch Integration 9 ~ 25.5 Analog, Burst O Internal (4) Internal (4) SLP Ron=30mΩ S

2
Product Introduction

- FAN7313 (Push-pull) / FAN7316 (N-N Half-Bridge)


- FAN7317 (Full-Bridge)

New Product
- FAN7318

3
FAN7313/6 Key Features

• Reduce external components


 Wide Input Voltage Range : 4.5 ~ 25.5V (FAN7313),4.5 ~ 24V(FAN7316)
 Integrated OLP circuit

• Various Protection
 OLP, OLR, SCP, TSD, Soft-start, Arc Protection

• Design flexibility
 Selectable Dimming Polarity
 N-N Half-bridge & Push-pull topology
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 4.5 ~ 24V

4
Reduce External Components

• Wide Input Voltage Range : 4.5 ~ 24V


 Can use common Vcc with IC input voltage
 1 TR, 1 Zenor D, 2 Resister
IC_Vcc

• Integrated OLP Circuit REF OLP circuit

 No need open lamp detection circuit IC_OLP

 Reduce Feedback rectifier diode


 1 TR, 5 Diode (3 BAV55,2 BAV70)
5 Capacitor, 1 Resister (@ 4Lamp)

5
Reduce External Components

FAN7316 – N-N Half-Bridge


F1

FUSE C1 C2
220u 1u C3
1u

OLP3 OLP4 OLR 0 0 0 TX1 LTM190EX 1


1
0 0 0 M1 C4 10u CN1
CCFL
C6 2
2
SN1 DN1
R2 R3 1
0.1u 1
100k 100k C5 R1 C7 10u
10n 27k GN1 DN1 C9 CN2
D2 C8 5p CCFL
0 BAV70 5p 2
0 2
OL R

VS

VB
OL P3

OL P4

SCP
RT
BCT

OUTH

VIN
SN2 DN2
OLP1 OLP2
FAN7316

GN2 DN2 R4 C10 R5 C11


IC1

1k 4.7n 1k 4.7n
D1
FDS6990A
D1N4148
R6 R7
OUTL
BDIM

ADIM

VREF
OL P1

OL P2

GND
CMP

0 0 0 0
ENA

D3 680 680
FB

BAV70

0 0
R8 R9 C12
100k 100k 33n 0

R22
0 C13
1u TX2 1
R13 100k 1
CN5 100k C23 R23 CN4
OLP1 OLP2 0
10n N.C. CCFL
1 REF 2
2 2
14V
3 1
4 R12 0 0 1
5 R10 75k CN3
6 12k D4 C15 C16 CCFL
7DIM( 0~3.3V) 0 BAV70 5p 5p 2
8 2
9ON/OFF
OLR OLP3 OLP4
10 C14 R11
10n 9.1k R14 C18 R15 C19
C24 R18 1k 4.7n 1k 4.7n
?? 4.7n 100k
0 R20 0 0 R16 R17

10k
C17
Can delete this 0 0
0 0 0 0 D5
BAV70
680 680

Can delete this external 10n

external IC - Vcc
R21
0 0

OLP detection circuit 0


regulation circuit
C20
1n
R19
10k
10k

REF OLP circuit


0 0
IC_OLP
BOM
Dual N MOS 1
Control IC 1
IC_Vcc

6
Reduce External Components

FAN7314 – P-N Half-Bridge F1

FUSE C22
220u C25 C27
1u 1u
25V or 35V
CN5 C26 1n
0 IC1 FAN7314 0 0 0
1 M1
2 14V R6 82k
3
4 OLP RT1 RT 0 SN DN
5
6 OUTB
7 OLR OUTB
GN DN
8 R24 R25 C7 10u
9
10
ON/OFF
10k
ENA OUTA
OUTA
SP DP
LTM190EX
C1 0.22u C6 10k
C28 TX1 1
12505WR-10 10n 0 S_S VIN 0 GP DP HOT
1u
C8 10u CN1
0 FDS8958A CCFL
0 0 GND PGND 0 J1 2
C2 1u M2 COLD
0
DIM( 0~3.3V) REF 1
0 REF OUTC HOT
0 CN2
SN DN
R2 CCFL
R4 56k ADIM OUTD 2
0 COLD
22k R7 0 C5 220p GN DN C10 C11
R27 15p 15p
BDIM CT 0
R5 27k SP DP
OLP1 OLP2
C21 R3 10k
10n 18k EA_IN RT 0
C3 C4 GP DP
EA_OUT BCT 0 FDS8958A D4 D6 D7
0 0 4.7n 4.7n OLR BAV70 C14 C30 BAV99 BAV99
R26 12n R13 12n R17 R16
RT 1k 1k 1k 1k
R8 R15
FB
100k 10k 0 0 0 0 0 0 0 0
R9
9.1k
FB
TX2 1
OLR 0 HOT
CN3
R14 CCFL
REF 100k 2
OLP1 OLP2 COLD
1
R1 R22 R23 HOT
OLP 330k 0 10k 10k CN4
0 CCFL
C12 C13 2
D11 15p 15p COLD
C9 BAW56
1u Q1
KST2222
OLP3 OLP4
OLP3 OLP4 C19 C20
D1 2.2n 2.2n
BAW56 R20 R21
10k 10k D3 D8 D9
0 0 OLR BAV70 BAV99 BAV99
R12 C29 R11 C15 R18 R19
D10 1k 12n 1k 12n 1k 1k
BAW56
0

C18 C17 0 0 0 0 0 0 0 0
2.2n 2.2n

0 0
FB

FAN7316 – N-N Half-Bridge F1

FUSE C1
220u
C2
1u C3
1u

OLP3 OLP4 OLR 0 0 0 TX1 LTM190EX 1


1
0 0 0 M1 C4 10u CN1
CCFL
C6 2
2
SN1 DN1
R2 R3 1
0.1u 1
100k 100k C5 R1 C7 10u
10n 27k G N1 DN1 C9 CN2
D2 C8 5p CCFL
0 BAV70 5p 2
0 2

OLR

VS

VB
OLP3

OLP4

SCP
BCT

RT

OUTH

VIN
SN2 DN2
OLP1 OLP2

FAN7316
G N2 DN2 R4 C10 R5 C11

IC1
1k 4.7n 1k 4.7n
D1
FDS6990A
D1N4148
R6 R7

OUTL
BDIM

ADIM

VREF
OLP1

OLP2

GND
CMP
0 0 0 0

ENA
D3 680 680

FB
BAV70

0 0
R8 R9 C12
100k 100k 33n 0

R22
0 C13
1u TX2 1
R13 100k 1
CN5 100k C23 R23 CN4
OLP1 OLP2 0
10n N.C. CCFL
1 R EF 2
2 2
14V
3 1
4 R12 0 0 1
5 R10 75k CN3
6 12k D4 C15 C16 CCFL
7D IM( 0~3.3V) 0 BAV70 5p 5p 2
8 2
9ON/OFF
OLR OLP3 OLP4
10 C14 R11
10n 9.1k R14 C18 R15 C19
C24 R18 1k 4.7n 1k 4.7n
?? 4.7n 100k
0 R20 0 0 R16 R17
0 0 0 0 D5 680 680
0 0 BAV70
10k
C17
10n R21
0 0

10k
0 C20 R19
1n
10k

0 0

7
Key Features

• Reduce external components


 Wide Input Voltage Range : 4.5 ~ 24V
 Integrated OLP circuit

• Various Protection
 OLP, OLR, SCP, TSD, Soft-start, Arc Protection

• Design flexibility
 Selectable Dimming Polarity
 N-N Half-bridge & Push-pull topology
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 4.5 ~ 24V

8
Various Protection

1.25V +
DRV 6V VREF
ENA -
Internal

UVLO
200k Voltage

VIN +
VIN Reference
Protection Protection
UVLO 4.5V -
UVLO

SCP Description
Arc 3V
+

-
+

- 2V
SCP
Item Condition
Timer

+ 16 switching
cycles @ Normal TSD 150oC
0.25V
1.75V - 1.5s @ Strike

OLR VREF
-
Protection
2V +
Short Circuit
Disable @ Striking

TSD
VB
SCP > 2V (@ SCP)
+

FAULT
BDIM
OLR
1) ADIM>3.5V(hys. 0.5V) : Negative BDIM
FAULT
Protection
3V OUTH
2) ADIM<3.5V : Positive Controller VBURST

max. 2V
BCT/FT
VS
min. 0.5V Drivers
VREF
0.45*Va + Input
Control
OUTL Open Lamp
- Logic
VSS_STK
GND
OLR Regulation
> 1.75V (@ OLR)
FB - Output
2V + Control
ADIM + Logic
Va
1.5s @ Strike max. 2V
Error Amp.
10ms @ Normal
min. 0.5V
CMP OSC RT
VSS_STK

VSS_STK
Fstrike: Fnormal = 1.3:1
Arc Arc Protection > 3V (@ OLR)
OLP1 - - OLP3

1.5V + + 1.5V

OLP2 - - OLP4
Open Lamp
1.5V + + 1.5V OLP Protection
< 1.5V (@ OLP)

Thermal Shut
OLP TSD Down
150oC (@ Tj)

9
Key Features

• Reduce external components


 Wide Input Voltage Range : 4.5 ~ 24V
 Integrated OLP circuit

• Various Protection
 OLP, OLR, SCP, TSD, Soft-start, Arc Protection

• Design flexibility
 Selectable Dimming Polarity
 N-N Half-bridge, Push-pull topology, P-N Half-bridge, P-N Full-bridge
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 4.5 ~ 24V

10
Design Flexibility

Selectable Dimming Polarity


1) Positive burst dimming polarity @ ADIM < 3.0V 1) Positive burst dimming polarity
Positive dimming polarity
3.3V
Positive dimming polarity
2V
DIM Positive dimming polarity
BDIM 0V
Transconductance
BCT 0.5V Amplifier
2V Lamp
- current
ADIM
3.0V ADIM + 2V sense
0V + ADIM
CCMP REF
Lamp 0V
current CMP
6V
0V DIM
OUTH
Lamp
6V current
OUTL 0V

2) Negative burst dimming polarity @ ADIM > 3.5V 2) Negative burst dimming polarity
Negative dimming polarity
Negative dimming polarity 3.3V
2V
DIM
BDIM
0V
Negative dimming polarity
BCT 0.5V
2V
ADIM
3.5V
ADIM Transconductance
0V DIM
Amplifier
Lamp
Lamp
current
0V - current
CMP + 2V sense
6V
0V + ADIM
OUTH CCMP
Lamp
REF
6V
current
OUTL 0V

11
Design Flexibility

N-N Half-bridge Application Push-pull Application


F1
F1

FUSE C1 C2
220u 1u C3
FUSE C1 C2
220u 1u C3
1u 1u

LTM190EX
OLP3 OLP4 OLR
LTM190EX
OLP3 OLP4 OLR 0 0 0 TX1 0 0 0 0 0 0 TX1
1 0
1 R28 R29 1
HOT
0 0 0 M1 C4 10u CN1 33 33
CCFL CN1
35001WR-02A
C6 2 R2 R3 C5 R1 2
2 COLD
SN1 DN1 100k 100k 10n 27k
R2 R3 1 C24 C25
0.1u 1
100k 100k C5 R1 C7 10u 2.2n 2.2n
10n 27k GN1 DN1 C9 CN2
D2 C8 5p CCFL
0 M1 1
BAV70 5p 2 HOT

OUTH
BCT/F T

RT

SCP
0

OLR

VIN
VS

VB
OLP3

OLP4
2
OL R

VS

VB
OL P3

OL P4

SCP
BCT

RT

OUTH

VIN

SN2 DN2 C9 CN2


0

FAN7316
OLP1 OLP2 SN DN C8 15p 35001WR-02A
FAN7316

15p 2
COLD

IC1
GN2 DN2 R4 C10 R5 C11
IC1

1k 4.7n 1k 4.7n GN DN D2 OLP2


C22 BAV70 R5 OLP1
D1

OUTL

VREF
OLP1

OLP2

BDIM

ADIM
FDS6990A

CMP

GND
R4 C10 1k C11

ENA
D1N4148 0 330p
DN 1k 10n 10n

FB
SN
R6 R7
OUTL
BDIM

ADIM

VREF
OL P1

OL P2

GND
CMP

0 0 0 0
ENA

D3 680 680
FB

BAV70 CN5 GN DN
0 0 0 0 D3
1 C12 HUFA76413DK8 BAV70
0 0 2 14V 33n R6 R7
3 R8 R9 680 680
R8 R9 C12 4
100k 100k 33n 0 100k 100k 0
5 C13
6 1u
R22 7 DIM( 0~3.3V) 0 0
0 C13 8
1u TX2 1 9 ON/OFF 0 0
R13 100k 1 10 R22 TX2
CN5 100k C23 R23 CN4 1
OLP1 OLP2 0 HOT
10n N.C. CCFL
1 REF 2 12505WR-10 OLP1 OLP2 47k CN4
2 REF C23 R23 35001WR-02A
2 14V 0 R13 10n 100k 2
3 1 10K COLD
4 R12 0 0 1
R12
5 R10 75k CN3 R10 56k 0 0
6 12k D4 C15 C16 CCFL 22k
7DIM( 0~3.3V) 0 BAV70 5p 5p 2
2 1
8 HOT
9ON/OFF C14 R11 CN3
OLR OLP3 OLP4
10 C14 R11 10n 18k C15 C16 35001WR-02A
10n 9.1k R14 C18 R15 C19 15p 15p 2
C24 R18 1k 4.7n 1k 4.7n COLD
?? 4.7n 100k D4 OLP4
0 0 OLR BAV70 C19 OLP3
0 R20 0 0 R16 R17 R20 R14 C18 R15 10n
0 0 0 0 680 680
C21 R18 1k 10n 1k
D5
0 0 BAV70 10k 4.7n 100k
10k
C17 C17
10n R21 10n 0 0 0 0 D5
0 0 0 0 BAV70
0 R16 R17
10k R21 680 680
0 C20 R19
1n 8.2k
10k 0 0
C20 R19
1n
10k
0 0
0
0

P-N Half-bridge Application P-N Full-bridge Application


F1
F1
FUSE

2
C1 C6 M1
FUSE C1 C2 220u C3 220u C25 ZD1 R30
220u 1u C3 1u 1u 6.8V 10k 0
1u SN DN
LTM190EX

1
R26 C22 C4 10u
OLP3 OLP4 OLR 0 0 M3 0 TX1 LTM190EX 1
OLP3 OLP4 OLR 0 0 0 0 C2
1u 100R
GN DN
T1 1
1
1 0 0 0 0 0.1u C7 10u CN1
0 0 0 0 SN C4 10u CN1 D1 35001WR-02A
0 SP DP 2
DN 35001WR-02A 0 2
2
2 R2 R3 1
GN 100k 100k C5 R1 GP DP 1
R2 R3 1
1 10n 27k BAV99 C9 CN2
100k 100k C5 R1 R27 FDS8958A D2 C8 3p 35001WR-02A
10n 27k SP C7 10u C9 CN2 BAV70 3p 2
DP D2 C8 5p 35001WR-02A 2

OUTH
BCT

RT

SCP
OLR

VIN
VS

VB
OLP3

OLP4
0 BAV70 5p 2 100R
2

FAN7313
OUTH
BCT

RT

SCP

R33
OLR

VIN

R24 Q1 GP
VS

VB
OLP3

OLP4

10k R4 C10 R5 C11 OLP1 OLP2


750R 2N2222

2
OLP1 OLP2
FAN7313

IC1
10k 2.2n 10k 2.2n
FDD8424H R4 C10 R5 C11 ZD2 M2
6.8V R31
IC1

1k 4.7n 1k 4.7n

OUTL
0

VREF
OLP1

OLP2

BDIM

ADIM
CMP

GND
10k 0 R6 R7

ENA

1
0 0 0 0 D3 680 680

FB
SN DN
R26 Q2 R28 C24 BAV70
OUTL

VREF
BDIM

ADIM
OLP1

OLP2

CMP

GND

1k 2N2907 R6 R7
ENA

0 0 0 0 D3 680 680
FB

GN DN
BAV70 100R 0.1u 0 0
0 R8 R9 C12 0 D6
M2 0 0
100k 100k 33n SP DP
2N7002
R8 R9 C12 R25 0 R22
100k 100k 33n 0 GP DP
BAV99 T2 1
R13 100k R29 FDS8958A 1
0 R22 0R CN5 OLP1 OLP2 100k C23 R23 C13 CN3
TX2 1 10n N.C. 1u 100R 35001WR-02A
1 1 REF 2
R13 100k 2 13.5V R34 2
CN5 OLP1 OLP2 100k C23 R23 C13 0 CN4 3 1
0 0 0 10k 1
10n N.C. 1u 35001WR-02A 4 R12
1 REF 2 5 R10 75k CN4
2 14V 2 6 12k D4 C15 C16 35001WR-02A
3 1 7DIM( 0~3.3V) 0 BAV70 3p 3p 2
0 0 0 1 8 R32 2k 2
4 R12
5 9ON/OFF
R10 75k CN3 10 C14 R11 OLR
6 12k D4 C15 C16 35001WR-02A OLP3 OLP4
7DIM( 0~3.3V) 0 BAV70 5p 5p 2 10n 9.1k R14 C18 R15 C19
8 2 C24 R18 10k 2.2n 10k 2.2n
9ON/OFF
12505WR-10 4.7n 100k
10 C14 R11 OLR OLP3 OLP4 0 0 0
R20 0 0 0 0 R16] R17
10n 9.1k R14 C18 R15 C19 0 0
D5 680 680
C24 R18 1k 4.7n 1k 4.7n 10k
BAV70
12505WR-10 4.7n 100k C17
10n R21 20k 0 0
0 R20 0 0 R16 R17
0 0 0 0 D5 680 680
0 0 BAV70 0
10k C17 C20 R19
1n R24 20k
10n R21 0 0 10k

10k 0 0
0 C20 R19
1n
10k

0 0

12
Design Flexibility

Analog & Burst Dimming


Negative dimming polarity
2V
1.25V +
DRV 6V VREF BDIM
ENA -
Internal BCT 0.5V
200k Voltage
VIN Reference
VIN +
ADIM
UVLO
3.5V
UVLO 4.5V -

+ + SCP

3V - - 2V
Timer Lamp 0V
+ 16 switching current
cycles @ Normal TSD 150oC
0.25V
1.75V - 1.5s @ Strike 6V

OLR VREF OUTH


-
Protection
2V +
Disable @ Striking VB
6V
+

FAULT
FAULT
BDIM OUTL
1) ADIM>3.5V(hys. 0.5V) : Negative BDIM 3V OUTH
2) ADIM<3.5V : Positive Controller VBURST

max. 2V
BCT/FT
VS
min. 0.5V Drivers
VREF
0.45*Va + Input
Control
OUTL
- Logic
VSS_STK
GND

Burst Dimming
FB

ADIM
Va
2V
-
+
+
1.5s @ Strike
Output
Control
Logic
max. 2V
Negative dimming polarity
Error Amp.
10ms @ Normal 3.3V
min. 0.5V
CMP OSC RT
VSS_STK
DIM
Fstrike: Fnormal = 1.3:1
VSS_STK 0V

2V
OLP1 - - OLP3

1.5V + + 1.5V ADIM


0V

Analog Dimming
OLP2

1.5V
-

+
-

+ 1.5V
OLP4

CMP
0V

Lamp
current
0V

13
Design Flexibility

PWM dimming by external pulse signal


This method can be applied to FAN7313, FAN7316 application

9uA 2V -
Ich

+ S
SET
Q External
BCT pulse signal
R CLR Q
18uA -
Idch

0.5V +

BDIM
BCT
Comparator
-
Burst signal
to Error Amp.
External
BDIM + Burst signal
Pulse Signal
to Error Amp.

14
Design Flexibility

Wide Input Voltage Range : 4.5 ~ 24/25.5V


F1

FUSE C1 C2
220u 1u C3
1u

OLP3 OLP4 OLR 0 0 0 TX1 LTM190EX 1


1
0 0 0 M1 C4 10u CN1
CCFL
C6 2
2
SN1 DN1
R2 R3 1
0.1u 1
100k 100k C5 R1 C7 10u
10n 27k G N1 DN1 C9 CN2
D2 C8 5p CCFL
0 BAV70 5p 2
0 2
OLR

VS

VB
OLP3

OLP4

SCP
RT
BCT

OUTH

VIN
SN2 DN2
OLP1 OLP2
FAN7316

G N2 DN2 R4 C10 R5 C11


IC1

1k 4.7n 1k 4.7n
D1
FDS6990A
D1N4148
R6 R7
OUTL
BDIM

ADIM

VREF
OLP1

OLP2

GND
CMP

0 0 0 0
ENA

D3 680 680
FB

BAV70

0 0
R8 R9 C12
100k 100k 33n 0

R22
0 C13
1u TX2 1
R13 100k 1
CN5 100k C23 R23 CN4
OLP1 OLP2 0
10n N.C. CCFL
1 R EF 2
2 2
14V
3 1
4 R12 0 0 1
5 R10 75k CN3
6 12k D4 C15 C16 CCFL
7D IM( 0~3.3V) 0 BAV70 5p 5p 2
8 2
9ON/OFF
OLR OLP3 OLP4
10 C14 R11
10n 9.1k R14 C18 R15 C19
C24 R18 1k 4.7n 1k 4.7n
?? 4.7n 100k
0 R20 0 0 R16 R17
0 0 0 0 D5 680 680
0 0 BAV70
10k
C17
10n R21
0 0

0
Can delete this C20 R19
10k

external IC - Vcc
1n
10k

0 0

regulation circuit

IC_Vcc

15
FAN7317 Key Features

• Reduce external components


 Wide Input Voltage Range : 6.0 ~ 24V
 Integrated OLP circuit
 Integrated OLR circuit
 Integrated P-MOS driving circuit

• Various Protection
 OLP, OLR, SLP, CMP-high, FB-high,
TSD, Soft-start, Arc Protection

16
FAN7317 Key Features

• Reduce external components


 Wide Input Voltage Range : 6.0 ~ 24V
 Integrated OLP circuit
 Integrated OLR circuit
 Integrated P-MOS driving circuit

• Various Protection
 OLP, OLR, SLP, CMP-high, FB-high, TSD, Soft-start, Arc Protection

• Design flexibility
 Selectable Dimming Polarity
 N-N Half-bridge & Push-pull topology
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 4.5 ~ 24V

17
Reduce External Components

• Wide Input Voltage Range : 6.0 ~ 24V


 Can use common Vcc with IC input voltage
 1 TR, 1 Zenor D, 2 Resister IC_Vcc

• Integrated OLP Circuit REF OLP circuit

 No need open lamp detection circuit IC_OLP

 Reduce Feedback rectifier diode


 1 TR, 5 Diode (3 BAV55,2 BAV70)
5 Capacitor, 1 Resister (@ 4Lamp)

• Integrated OLR Circuit


 No need open lamp regulation circuit
 No need feedback diode
 2 Capacitor, 4 Diode (BAV70)
3 Resister (@ 4Lamp)

• P-MOS Driving Circuit Vcc


 2 Zenor D, 2 Capacitor, 2 Resistor
IC _ Output
for P-driving P-MOSFET Gate

18
Reduce External Components

F1

R1 FUSE C1 1
220u C2 C3 HOT
10k 1u 1u C4 CN1
CN2 0 0 0 0 5p CCFL
C5 2
1 10n REF OLR4 OLP4 0 0 0 COLD
2 13V OLP3 OLR3 OLR1 OLP1
3 C7 R4 C8 R5 C9 C10
4 0 R2 4.7n 1.4M 1u 100k 220p 33n TX1 R3 C6 R6
5 R7 56k 10k 3.3n 470
6 22k
7 BDIM(0~3.3V)
8
9 ON/OFF 0 0 0

BDIM
OLR4

OLP4

OLP3

OLR3
CT
BCT

REF(5V)
10 1

CMP

ENA
C11 R8 HOT
10n 18k M1
C12 CN3
12505WR-10 5p CCFL
2
0 0 0 0 SN DN
COLD
OLR2 OLP2
IC1 GN DN R9 C14 R10

OUTD

OUTC

OUTA

OUTB
OLP1

OLR1

OLP2

OLR2
C13 10u 10k 3.3n 470

GND
FAN7317

VIN
SP DP
R11 C15 10u 0 0 0
10k
GP DP TX2 1
HOT
C16 FDS8958A C17 CN4
1u 5p CCFL
2
OLP1 OLR1 OLP2 OLR2 COLD
0 0 OLR3 OLP3

M2 R12 C18 R13


10k 3.3n 470

0 SN DN
0 0 0
1
GN DN
HOT
C19 CN5
5p CCFL
SP DP 2
R14 COLD
10k OLR4 OLP4
GP DP
R15 C20 R16
FDS8958A 10k 3.3n 470

0 0 0

Can delete this


Can delete this external Can delete this external Can delete this
external IC - Vcc
OLP detection circuit P-MOSFET driving circuit OLR circuit
regulation circuit
REF OLP circuit

IC_OLP Vcc

IC _ Output
IC_Vcc for P-driving P-MOSFET Gate

19
Key Features

• Reduce external components


 Wide Input Voltage Range : 4.5 ~ 24V
 Integrated OLP circuit

• System Reliability with Various Protection


 OLP, OLR, SLP, CMP-high, FB-high, TSD, Soft-start, Arc Protection

• Design flexibility
 Selectable Dimming Polarity
 N-N Half-bridge & Push-pull topology
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 4.5 ~ 24V

20
Various Protection

Protection Protection
TSD Description
Item Condition
Arc
Short Lamp
SLP Protection
< 0.3V (@ OLR)

OLR / SLP Open Lamp


OLR Regulation
> 2.0V (@ OLR)

CMP-high Arc Arc Protection > 3V (@ OLR)


Protection
Comparator high
CMP-High protection
> 3V (@ CMP)

UVLO FB-High
Feedback high
> 3.5V (@OLP)
protection

FB-high OLP
Open Lamp
< 1/0.5V (@ OLP)
Protection
Protection
Thermal Shut
TSD Down
150oC (@ Tj)
OLP

21
Key Features

• Reduce external components


 Wide Input Voltage Range : 4.5 ~ 24V
 Integrated OLP circuit

• Various Protection
 OLP, OLR, SLP, CMP-high, FB-high, TSD, Soft-start, Arc Protection

• Design flexibility
 P-N Half-bridge, P-N Full-bridge
 PWM dimming by external pulse signal
 Wide input voltage range : 6.0 ~ 24V

22
Design Flexibility

PWM dimming by external pulse signal


This method can be applied to FAN7313, FAN7316 application

9uA 2V -
Ich

+ S
SET
Q External
BCT pulse signal
R CLR Q
18uA -
Idch

0.5V +

BDIM
BCT
Comparator
-
Burst signal
to Error Amp.
External
BDIM + Burst signal
Pulse Signal
to Error Amp.

23
Design Flexibility

Wide input voltage range 6 ~ 24V


F1

R1 FUSE C1 1
220u C2 C3 HOT
10k 1u 1u C4 CN1
CN2 0 0 0 0 5p CCFL
C5 2
1 10n REF OLR4 OLP4 0 0 0 COLD
2 13V OLP3 OLR3 OLR1 OLP1
3 C7 R4 C8 R5 C9 C10
4 0 R2 4.7n 1.4M 1u 100k 220p 33n TX1 R3 C6 R6
5 R7 56k 10k 3.3n 470
6 22k
7 BDIM(0~3.3V)
8
9 ON/OFF 0 0 0

BDIM
OLR4

OLP4

OLP3

OLR3
CT
BCT

REF(5V)
10 1

CMP

ENA
C11 R8 HOT
10n 18k M1
C12 CN3
12505WR-10 5p CCFL
2
0 0 0 0 SN DN
COLD
OLR2 OLP2
IC1 GN DN R9 C14 R10

OUTD

OUTC

OUTA

OUTB
OLP1

OLR1

OLP2

OLR2
C13 10u 10k 3.3n 470

GND
FAN7317

VIN
SP DP
R11 C15 10u 0 0 0
10k
GP DP TX2 1
HOT
C16 FDS8958A C17 CN4
1u 5p CCFL
2
OLP1 OLR1 OLP2 OLR2 COLD
0 0 OLR3 OLP3

M2 R12 C18 R13


10k 3.3n 470

0 SN DN
0 0 0
1
GN DN
HOT
C19 CN5
5p CCFL
Can delete this R14
10k
SP DP

OLR4 OLP4
2
COLD

GP DP

external IC - Vcc FDS8958A


R15
10k
C20
3.3n
R16
470

regulation circuit 0 0 0

IC_Vcc

24
New Product Introduction

- FAN7318 P-N Half Bridge Solution

25
FAN7318 Key Features

• Reduce external components


 Wide Input Voltage Range : 6.0 ~ 30.0 V
 Integrated OLP circuit
 Internal OLR circuit
 Internal feedback circuit
 Internal P-MOS driving circuit

• Various Protection
 OLP, OLR, SLP, OVP, COMP-Hi, Feedback-Hi, TSD, Soft-start

• Design flexibility
 Adjustable Striking & Protection delay time
 DCR mode operation
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 6.0 ~ 30V

26
Reduce External Components
Vcc

• Wide Input Voltage Range : 6.0 ~ 30V Device Unit Price


 Can use common Vcc with IC input voltage TR 2 $0.014
 1 TR, 1 Zenor D, 2 Resister IC-Vdd
ZD 1 $0.007
BAV D 9 $0.063
• Integrated OLP Circuit IC_OLP
OLP 2
Capacitor 6 $0.012
 No need open lamp detection circuit OLP 1

Resistor 12 $0.005
 1 TR, 3 Diode (BAW56) OLP 3 OLP 4

5 Capacitor, 5 Resister (@ 4Lamp) Total 30 $0.101

• Integrated OLR Circuit OLR 1 OLR 2

 No need open lamp regulation circuit


 2 Capacitor, 2 Diode (BAV70) IC_OLR
OLR 3 OLR 4

4 Resister (@ 4Lamp)

FB 1 FB 2

• Integrated Feedback rectifier diode


 4 Diode (BAV99) (@4Lamp) FB 3 FB 4

IC_FB

Vcc

• P-MOS Driving Circuit


 1 Zenor D, 1 Capacitor, 1 Resistor
P-MOSFET
IC_ P Out Gate

27
Reduce External Components
CN2
T1 HOT
F1 C4
OLP1
OLR1 COLD
C3
C1 C2 C6
R2 R3
OLP1 OLR1 OLP2 OLR2 OLP3 OLR3 OLP4 OLR4
C12

CN3
C7
HOT

SN DN C13

20

19

18

17

16

15

14

13

12

11
CN1 OLP2
OLR2 COLD
GN DN

OLP1

OLR1

OLP2

OLR2

OLP3

OLP3

OLP4

OLR4

VIN

OUTA
1 C14
C9
2 SP DP R6 R7
3
R11
4 ADIM GP DP
5
6
7
C22 R17
FAN7318 M1 CN4
8
HOT

TIMER

OUTB
9

ADIM

BDIM
CMP

GND
IC1

ENA
REF

BCT
10 REF C16

CT
OLP3
BDIM

OLR3 COLD
R8

10
C19
1

9
R9
R12 R13

C15 R10
R5 R14
CN5
C5 C11 C10 C17 C18 HOT

C20
OLP4
ON/OFF R1 OLR4 COLD

C21
R15 R16
C8

FB 1 FB 2 Vcc
IC_OLP OLR 1 OLR 2 Vcc
OLP 2
OLP 1

IC_OLR
OLR 3 OLR 4 FB 3 FB 4
OLP 3 OLP 4

IC_FB IC-Vdd
P-MOSFET
IC_ P Out Gate

28
Reduce External Components

FAN7314 – P-N Half-Bridge F1

FUSE C22
220u C25 C27
1u 1u
25V or 35V
CN5 C26 1n
0 IC1 FAN7314 0 0 0
1 M1
2 14V R6 82k
3
4 OLP RT1 RT 0 SN DN
5
6 OUTB
7 OLR OUTB
GN DN
8 R24 R25 C7 10u
9
10
ON/OFF
10k
ENA OUTA
OUTA
SP DP
LTM190EX
C1 0.22u C6 10k
C28 TX1 1
12505WR-10 10n 0 S_S VIN 0 GP DP HOT
1u
C8 10u CN1
0 FDS8958A CCFL
0 0 GND PGND 0 J1 2
C2 1u M2 COLD
0
DIM( 0~3.3V) REF 1
0 REF OUTC HOT
0 CN2
SN DN
R2 CCFL
R4 56k ADIM OUTD 2
0 COLD
22k R7 0 C5 220p GN DN C10 C11
R27 15p 15p
BDIM CT 0
R5 27k SP DP
OLP1 OLP2
C21 R3 10k
10n 18k EA_IN RT 0
C3 C4 GP DP
EA_OUT BCT 0 FDS8958A D4 D6 D7
0 0 4.7n 4.7n OLR BAV70 C14 C30 BAV99 BAV99
R26 12n R13 12n R17 R16
RT 1k 1k 1k 1k
R8 R15
FB
100k 10k 0 0 0 0 0 0 0 0
R9
9.1k
FB
TX2 1
OLR 0 HOT
CN3
R14 CCFL
REF 100k 2
OLP1 OLP2 COLD
1
R1 R22 R23 HOT
OLP 330k 0 10k 10k CN4
0 CCFL
C12 C13 2
D11 15p 15p COLD
C9 BAW56
1u Q1
KST2222
OLP3 OLP4
OLP3 OLP4 C19 C20
D1 2.2n 2.2n
BAW56 R20 R21
10k 10k D3 D8 D9
0 0 OLR BAV70 BAV99 BAV99
R12 C29 R11 C15 R18 R19
D10 1k 12n 1k 12n 1k 1k
BAW56
0

C18 C17 0 0 0 0 0 0 0 0
2.2n 2.2n

0 0
FB

FAN7318 – P-N Half-Bridge F1


T1
C4
OLP1
CN2
HOT

OLR1 COLD
C3
C1 C2 C6
R2 R3
OLP1 OLR1 OLP2 OLR2 OLP3 OLR3 OLP4 OLR4
C12

CN3
C7
HOT

SN DN C13

20

19

18

17

16

15

14

13

12

11
CN1 OLP2
OLR2 COLD
GN DN

OLP1

OLR1

OLP2

OLR2

OLP3

OLP3

OLP4

OLR4

VIN

OUTA
1 C14
C9
2 SP DP R6 R7
3
R11
4 ADIM GP DP
5
6 C22 R17 M1 CN4
7
8
HOT

TIMER

OUTB
9

ADIM

BDIM
CMP

GND
IC1

ENA
REF

BCT
10 REF C16

CT
OLP3

BDIM
OLR3 COLD
R8

10
C19

9
R9
R12 R13

C15 R10
R5 R14
CN5
C5 C11 C10 C17 C18 HOT

C20
OLP4
ON/OFF R1 OLR4 COLD

C21
R15 R16
C8

29
FAN7318 Key Features

• Reduce external components


 Wide Input Voltage Range : 6.0 ~ 30.0 V
 Integrated OLP circuit
 Internal OLR circuit
 Internal feedback circuit
 Internal P-MOS driving circuit

• Various Protection
 OLP, OLR, SLP, OVP, COMP-Hi, Feedback-Hi, TSD, Soft-start

• Design flexibility
 Adjustable Striking & Protection delay time
 DCR mode operation
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 6.0 ~ 30V

30
FAN7318 Application Circuit

Vcc = 15V, P-N Half Bridge


Lamp Current = 7.0mA
Fm : 46.5KHz
Fstr : 65KHz
Fbus: 320Hz
Vstr : Over 1700V
Panel : M220EW01 (AUO 22”)

31
Various Protection
O : Over / U : Under
SLP
OLR1 Min.
Delay
+
TIMER Protection
Protection Description Time
OLR2
Max. -
3V/1V Condition
Full Wave
Recifier
OVP OLP
Protection @ striking/normal
@ 1uF
High_FB
OLR3 TSD 150oC Short Lamp U 0.3V @
High_CMP
SLP 20mS
OUTA
Protection OLR (min.)
OLR4 TSD Output Driver

OLR / FB OUTB
OLR
Open Lamp
U 2V (@ OLR)
- Regulation
Open Lamp Regulation 2V +

Over Voltage O 1.4V (@


Oscillator OVP 20mS
Control
Protection OLR)
Logic
CT -

GND Open Lamp U 0.7/0.5V (@


CMP +
OLP 1.5/0.5S
COMP-Hi Protection OLP)
- UVLO 5.5V

ADIM + + VIN
+ Comparator
- 3.5V -
High_CMP
O 3.5V (@
- 1.35V
CHP High 1.5/0.5S
+
ENA CMP)
Protection
+
High_FB
3.5V -
OLP1 Voltage Reference
REF Feedback 80uS
& Internal Bias
O 3.5V (@
FHP High
OLP2
Full or Half
FB-Hi protection
OLP) @50KHz
Wave
Rectifier
OLP3 -
BCT
- Thermal O 150oC (@
0.7V/0.5V +
OLP
TSD
Shut Down Tj)
+
BDIM
OLP4

OLP
32
Soft Start

 Soft start operated by BCT waveform

Normal Mode Burst Dimming Mode

CMP
BCT
Frequency
I Lamp

33
Open Lamp Protection

 Open Lamp Protection delay time is adjusted by C timer (@1uF)


 Open Lamp Protection disable for DCR Mode by ENA voltage
Normal Operation (ENA < 2.1V) OLP Disable (ENA > 2.5V)

OLP1

OLP2

OLP3

OLP4

Lamp 1 Open

Protection Condition
OLP delay time ≈ 500mS OLP <0.7/0.5V

OLP1

Timer

OLP3

OLP4

Lamp 1 Open

34
Short Lamp Protection

 Short Lamp Protection delay time is adjusted by C timer (@ 1uF)


 Short Lamp Protection disable for DCR Mode by ENA voltage

Normal Mode (ENA < 2.1V) SLP Disable ENA > 2.5V

OLR

Timer

Lamp Current

Protection Condition
SLP delay time ≈ 20mS
OLR <0.3V

35
Open Lamp Regulation & OVP

 OLR Voltage regulated at 2V


 Over Voltage Protection delay time is adjusted by C timer (@1uF)

Error Amp Source Current Change


to protect overshoot Timer ≈20mS
 22uA OLR<1.4V
 3.2uA OLR>1.4V ≈1.4V
 0uA OLR>2.0V
OLR

CMP Slope Change

@ Normal Mode
CMP
≈1.4V
Disabled
OLR CMP
≈2.0V
Timer

OLR

@ Striking Mode

@ Striking Mode

36
CMP (Error Amp. Output) High Protection

 CMP High Protection operated over 3V


 CMP High Protection delay time is adjusted by C timer (@1uF)
 CMP source current decreases from 22uA to 3.2uA for CMP high protection disable
Normal Mode CMP-Hi P Disable

VIN

CMP
2.5V

Timer

Primary
Current

1.0MΩ 1 TIMER OLP1 20


CMP Hi P delay time ≈ 500mS 2 CMP OLR1 19

3 ADIM OLP2 18

4 CT OLR2 17

CMP-Hi Protection Disable Method

37
Feedback High Protection

 Feedback High Protection operated over OLP 3.5V


 Feedback High Protection delay time is decided by 8 cycle 3.5V OLP Voltage

Normal Mode (Disable @ Striking Mode)

CMP
3.5V

OLP

BCT

8 Cycle ≈ 80uS @ 50Khz main frequency

38
Key Features

• Reduce external components


 Wide Input Voltage Range : 6.0 ~ 30.0 V
 Integrated OLP circuit
 Internal OLR circuit
 Internal feedback circuit
 Internal P-MOS driving circuit

• Various Protection
 OLP, OLR, SLP, OVP, COMP-Hi, Feedback-Hi, TSD, Soft-start

• Design flexibility
 Adjustable Striking & Protection delay time
 DCR mode operation
 Analog & Burst dimming
 PWM dimming by external pulse signal
 Wide input voltage range : 6.0 ~ 30V

39
Adjustable Protection Delay & Striking Time

 Protection Delay Time  Striking Time

Striking off
OLP1
50μA 2μA
On @ High_CMP, OLP 4 Output
On @ OVP, SLP
Pulses
OLP2 Counter
+ Min. & Max.
Protection TIMER Detector OLP
/Full Wave
Rectifier
-
3V/1V 1μF
OLP3
OLP min.
@ striking/normal - 150μs
Delay
0.7V/0.5V +
Clear all protection condition Striking/normal
OLP4

dt = Cdv/I dt = Cdv/I

OVP, SLP dt = 1u / 50u = 20mS OLP dt = 1u X 3 / 2u = 1.5S (Striking)


OLP, High_CMP dt = 1u / 2u = 0.5S (Normal) T strike off = t OLP + 4 OLP out
dt = 1u X 3 / 2u = 1.5S (Striking) = 1.5 + 40u (@ fmain = 50KHz)
≈ 1.5S

40
DCR Mode Operation

 DCR Mode Operated by ENA voltage (> 2.5V)


 Minimum lamp current = 0mA (Open lamp protection disabled)
 Open lamp protection operated by Over Voltage Protection (OLRv>1.4V, Tdelay = 20mS @ 1uF Ctimer)

DCR Mode Operation OLP Disable @ OLP condition Over Voltage Protection @ OLP condition
@ Normal Mode
OLP1
Timer
OLP2 ≈1.4V
CT
OLP3 OLR
BDIM 0% 100%
OLP4 /5mS
CMP
0mA I Max ≈20mS
ILamp
Lamp1 Open No Protection Lamp Open

/1S @ Striking Mode

OLP1
CMP
Timer ≈2.0V
Timer
OLP3 OLR

OLP4 /500mS

(Test condition : OVP disable) Disabled

41
Analog & Burst Dimming

 Analog Dimming  Burst Dimming


Negative Error Amp.
ADIM Analog +
Dimming
Vref
1.16V=1.34V*0.87 Linear region
-
1.34V 0.67V=1.34V*0.50
0~4V
1.16V
0.67V

0.5V 1.86V
Polarity : Negative Polarity : Negative
ADIM OLP max.

CMP CMP
ADIM=0V ADIM=1V BCT BCT
BDIM BDIM
ILamp ILamp =1.8V =1.7V
= 12mA = 9mA Ilamp Ilamp
=1.67mA =3.01mA
Duty : 20% Duty : 30%

CMP CMP
ADIM=1.5V ADIM=2V BCT BCT
ILamp ILamp BDIM BDIM
= 6mA = 5mA =1.6V =1.5V
Ilamp Ilamp
=3.88mA =4.54mA
Duty : 40% Duty : 50%

CMP CMP
ADIM=2.2V ADIM=2.5V
BCT BCT
ILamp ILamp BDIM BDIM
= 5mA = 5mA =1.0V =0.95V
Ilamp Ilamp
=5.67mA =5.99mA
Duty : 70% Duty : 75%

42
Burst Dimming by external Pulse signal

 Burst Dimming implemented by external Pulse signal

Polarity : Negative Polarity : Positive


External
pulse signal
External
pulse signal

External Pulse Signal

-
BCT Ref. BCT
-
BCT BDIM disable @ striking BDIM
disable @ striking
External Pulse Signal
BCT +
+
BDIM BDIM

Burst signal
Burst signal
to Error Amp.
to Error Amp.

BDIM BDIM

BCT BCT

I Lamp
I Lamp

43
Product Roadmap - Backlight

2007 2008 2009 2010 2011

RGB 3Ch. FAN7344 RGB LED FAN7344X

8Ch WLED FAN7342 WLED FAN7342X


LED

• Channel Optimization
• High efficiency

8Ch WLED FAN7343 WLED FAN7343X

Super IP Solution
P.P. FAN7313 P.P FAN7319 P.P. FAN733X
MOS Integrated (4Lamp) MOS Integrated Customer optimized

N-N HB FAN7320 N-N HB FAN732X N-N HB FAN732X


CCFL

P.P. FAN7313A P.P. FAN733X


Low Cost (2 Lamp)
P-N HB FAN7318A

Protection Integrated P-N HB FAN7318

P-N FB FAN7317

N-N HB FAN7316

44