Volume 4

MECL INTEGRATED CIRCUITS

Series A

• Technical Information
• MECL 10,000
• MECL III
• Phase-Locked Loop Components
 frECHNICAL DATA]

MECL GENERAL INFORMATION

•
MECL SELECTOR GUIDES

MECL 10,000 Series

MECL III MC1600 Series

•
COMPATIBLE CIRCUITS

PHASE-LOCKED LOOP COMPONENTS

•
MIL-M-38510 PROGRAM

•
 THE
SEMICONDUCTOR
DATA LIBRARY
SERIESA
VOLUME IV prepared by
Technical I nformation Center

MECL INTEGRATED CIRCUITS

This book presents technical data for a broad line of MECL integrated circuits. Com-
plete specifications for the individual monolithic circuits in the most popular MECL
families are provided in the form of data sheets. In addition, selector guides are included
to simplify the task of choosing the best combination of circuits for optimum system
archi teet ure .
The information in this book has been carefully checked and is believed to be reliable;
however, no responsibility is assumed for inaccuracies. Furthermore, this information
does not convey to the purchaser of microelectronic devices any license under the patent
right of any manufacturer.

Series A
© MOTOROLA INC., 1974
"All Rights Reserved"

Printed in U.S.A.
MECL, MECL I,MECL II, MECL III, MECL 10,000, MTTL,
MTTL III, and MDTL are trademarks of Motorola Inc.
 CONTENTS

NUMERICAL INDEX . ....................... ii

GENERAL INFORMATION . .................. 1·1
HIGH SPEED lOGICS . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Definitions and Abbreviations . . . . . . . . . . . . . . . . 1-10
TECHNICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
OPERATIONAL DATA . . . . . . . . . . . . . . . . . . . . . . . . 1-20
SYSTEMS DESIGN CONSIDERATIONS . . . . . . . . . . . . 1-23
Package Outl ine Dimensions . . . . . . . . . . . . . . . . .1-32
APPLICATION NOTE ABSTRACTS . . . . . . . . . . . . . . . 1-34
MECL SELECTOR GUIDES . .................. 2-1
MECl II MC1000/MC1200 Series . . . . . . . . . . . . . . . . . 2-3
M ECl III MC1600 Series . . . . . . . . . . . . . . . . . . . . . . 2-5
MECl 10,000 Series . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
MECL 10,000 Series DATA SHEETS . ........... 3-1
MECL III MC1600 Series DATA SHEETS .. ...... 4-1
COMPATIBLE CiRCUITS ..... ................ 5-1
PHASE-LOCKED LOOP COMPONENT .......... 6-1
DATA SHEETS
MIL-M-38510 PROGRAM . .................... 7-1
 NUMERICAL INDEX

DEVICE PAGE DEVICE PAGE

MC1543L 5-3 MC10160 3-121

MC1648 4-3 MC10161 3-125
MC1650 4-10 MC10162 3-129
MC1651 4-10 MC10163 3-133
MC1654 4-23 MC10164 3-141
MC1658 4-26 MC10165 3-146
MC1660 4-30 MC10166 3-150
MC1662 4-34 MC10168 3-154
MC1664 4-38 MC10171 3-157
MC1666 4-42 MC10172 3-161
MC1668 4-47 MC10173 3-165
MC1670 4-52 MC10174 3-170
MC1672 4-60 MC10175 3-173
MC1674 4-64 MC10176 3-177
MC1678 4-68 MC10177 3-180
MC1688 4-72 MC10178 3-183
MC1690 4-75 MC10179 3-186
MC1692 4-81 MC10180 3-191
MC1694 4-85 MC10181 3-195
MC7900C 5-9 MC10182 3-199
MC10100 3-3 MC10193 3-133
MC10101 3-5 MC10195 3-204
MC10102 3-8 MC10197 3-207
MC10103 3-11 MC10210 3-210
MC10104 3-13 MC10211 3-212
MCl 01 05 3-16 MC01212 3-214
MC10l06 3-19 MC10216 3-217
MC10107 3-22 MC10231 3-221
MCl 01 09 3-25 MC10287 3-225
MC10110 3-28 MC10501 3-232
MC10111 3-31 MC10502 3-235
MC10113 3-34 MC10504 3-238
MC10114 3-36 MC10505 3-241
MC10115 3-39 MC10506 3-244
MC10116 3-42 MC10507 3-247
MC10117 3-45 MC10509 3-250
MC10118 3-48 MC10514 3-253
MC10119 3-51 MC10515 3-256
MC10121 3-54 MC10516 3-259
MC10123 3-57 MC10517 3-262
MC10124 3-59 MC10518 3-265
MC10125 3-62 MC10519 3-268
MC10128 3-65 MC10521 3-271
MC10129 3-71 MC10524 3-274
MC10130 3-75 MC10525 3-277
MC10131 3-79 MC10530 3-280
MC10132 3-83 MC10531 3-284
MC10133 3-88 MC10533 3-288
MC10134 3-92 MC10535 3292
MC10135 3-97 MC10536 3-296
MC10136 3-101 MC10537 3-303
MC10137 3-107 MC10541 3-308
MC10138 3-111 MC10560 3-312
MC10141 3-114 MC10561 3-316
MC10153 3-118 MC10562 3-321

ii
NUMERICAL INDEX(continued)

DEVICE PAGE DEVICE PAGE

MC10564 3-326 MC12060 6-42

MC10571 3-331 ~1C12061 6-42
MC10572 3-335 MC12560 6-42
MC10574 3-339 MC12561 6-42
MC10575 3-343 MCM7001 L 5-18
MC10579 3-347 MCM10140 3-370
MC10580 3-352 MCM10142 3-370
MC10581 3-356 MCM10143 3-374
MC10616 3-362 MCM10144 3-379
MC10631 3-366 MCM10145 3-383
MC12000 6-12 MCM10147 3-387
MC12012 6-23 MCM10148 3-370
MC12040 6-38 MCM10150 3-391
 GENERAL
INFORMATION
 MECL GENERAL INFORMATION
Table of Contents

PAGE
SECTION I: HIGH SPEED LOGICS
MECL Products .. 1-4
Family Comparison tables .. 1-5
MECL in Perspective 1-6
MECL Applications .. 1-6
Considerations for High Speed Logic Design .. 1·7
MECL Circuit Description .. 1-8
Variations among MECL Families 1-9
Definitions, Symbols, and abbreviations. 1-10

SECTION II: TECHNICAL DATA

General Characteristics and Specifications 1-12
Maximum Ratings. 1·12
Noise Margin 1-12
Maximum Ratings (table! 1-13
Logic Levels (table! 1-13
Logic Level variations - tables and graphs. 1-13
AC or time Parameters. 1·17
Variations in ac parameters (graphs! 1-17
Package Dimensioned Drawings. 1·32

SECTION III: OPERATIONAL DATA

Power supply considerations .. . 1-20
Loading characteristics . . . . . . 1·21
AC variations with loading (graphs! 1-22
Unused MECL inputs .. 1-23

SECTION IV: SYSTEM DESIGN CONSIDERATIONS

Thermal Management. .. 1-23
Thermal Data (tables! .... 1-24
Mounting and heat sinks for MECL III 1-24
Compatibility among MECL Families .. 1-26
Interfacing MECL to slow logic 1-27
Circuit Interconnections . . . . . 1-28
Clock Distribution . . . . . . . . . . . . . . 1-29
System Design - Summary Recommendations . . . . . . . . . . . 1-31

SECTION V: MECL LITERATURE

Application Note abstracts .. 1-34
Supplementary Literature . . . . . . . . . . . . . . . . . . . 1-37
MECL System Design Handbook - contents 1-38

1-3
 GENERAL INFORMATION
SECTION I: HIGH SPEED LOGICS
For the purposes of this discussion, high speed
logic has either or both of two characteristics:
a) toggle rates over 50 MHz
b) gate propagation delays under 6 ns
Only two types of standard high speed logic
integrated circuits are commonly available in the
marketplace: Schottky·clamped TTL logic (TTL·S),
and non·saturating emitter·coupled logic (ECL).
Schottky·clamped TTL logic is similar to conven·
tional TTL logic in its circuit configuration and
operating characteristics. Conventional TTL is a
saturated form of logic; that is, during turn·on, both
the emitter·base and collector·base junctions of a
transistor are forward biased, causing an accumula·
tion of charged carriers in the base regions. Then,
when the transistor is turned off, this charge must
discharge through the collector. The finite time
required for this charge to dissipate causes a delay in
turning the transistor off. This "storage time" delay is
an integral part of all saturated logic forms. Schottky·
clamped TTL logic reduces storage time by means of
Schottky·diodes between base·collector junctions.
These diodes tend to keep the transistor out of
saturation, but they also tend to increase the input
capacitance of the Schottky·clamped transistor. Thus,
while the speed of TTL·S is greater than that of TTL,
due to a reduction in storage time, it is limited by the
RC time constant of the transistor input.
Emitter·Coupled Logic, being non·saturating by
design, completely avoids transistor storage time and
its attendent speed limitation without the tradeoffs
inherent in TTL·S. Gate delays of less than a
nanosecond and operating frequencies approaching a
gigahertz are currently feasible, and even these are
not ultimate limits.
MECL PRODUCTS
Motorola offers four ECL logic families under its
MECL trademark: MECL I, MECL II, MECL III, and
MECL 10,000.
The MECL I family, introduced by Motorola in
1962, was the first monolithic integrated circuit line
of emitter·coupled logic. Its propagation delay time
of 8 ns and toggle rate of 30 MHz, though no longer
considered state of the art, still places it above the
speed capabilities of most saturated logic lines. It is
still being produced in quantity for use in existing
equ ipment designs, but several features of the more
advanced MECL II, III, and MECL 10,000 families
favor the use of these families in new designs.
In 1966, Motorola introduced MECL II with gate
propagation delays of 4 ns, and flip·flop toggle rates
1-4
of over 70 MHz. Speeds were later increased first to
120 MHz (typical) for the MC1027/MC1227 J·K
flip·flop circuit, and then to 180 MHz (min.) for
the MC1034 type 0 flip·flop.
Complex functions became available in MECL II
when production capabilities shifted toward more
complicated circuits. The family now has adders, data
selectors, multiplexers, decoders, and a gas display
tube decoder/driver.
Continuing development of MECL made possible
an even faster logic family. As a result, MECL III was
introduced in 1968. Its 1 ns gate propagation delays
and greater than 500 MHz flip·flop toggle rates
remain the industry leaders. For the moment, the
very high speed capabilities of MECL III appear to
have outstripped the general speed requirements of
today's computer systems, however they are being
utilized extensively in special high·speed sections of
computers and high speed test and communication
equipment. Motorola is continuing to develop and
expand this product line.
For general purpose computer applications, trends
in large high·speed systems showed the need for an
easy·to·use logic family with propagation delays on
the order of 2 ns. To match this requirement, the
MECL 10,000 Series was introduced in 1971.
An important feature of MECL 10,000 is its
compatibility with MECL III to facilitate using both
families in the same system. A second important
feature is its significant power economy - MECL
10,000 gates use less than one·half the power of
MECL III or high speed MECL II gates. Finally, low
gate power and advanced circuit design techniques
have permitted a new level of complexity for MECL
circuits. For example, complexity of the MC10181
four bit arithmetic unit compares favorably to that of
any bipolar integrated circuit on the market.
The basic MECL 10,000 Series has recently been
expanded by a subset of devices with even greater
speed. This additional series provides a selection of
MECL 10,000 logic functions with flip·flop repetition
rates up to 200 MHz min. The MECL 10,200 Series is
meant for use in critical timing chains, and for clock
distribution circuits. MECL 10,200 parts are other·
wise identical to their 10,000 Series counterparts
(subtract 100 from the MECL 10,200 part number to
obtain the equivalent standard MECL 10,000 part
number).
Although the basic design of all MECL families is
the same, there are differences other than the speed
and power capabilities. Comparisons of the key
characteristics of each family are given in the tables
of Figure 1.
 MECL FAMILY COMPARISONS

MECL 10,000
10,100 Series 10,200 Series
Feature MECLI MECL II 10,500 Series 10,600 Series MECL III

1. Gate Propagation Delay 8 ns 4 ns 2 ns 1.5 ns 1 ns

2. Gate Edge Speed 8.5 ns 4 ns 3.5 ns 2.5 ns 1 ns
3. Flip-Flop Toggle Speed (min) 30 MHz 165 MHz 125 MHz 200 MHz 500 MHz
4. Gate Power 31 mW 22mW 25mW 25mW 60mW
5. Speed-Power Product 250 pJ 88 pJ 50 pJ 37 pJ 60 pJ
6. Transmission Line Capability No On Some Devices Ves Ves Ves
7. Wire-Wrap Capability Ves Ves Ves Ves No
8. Output Pulldown Resistors Ves Optional No No No
9. Input Pulldown Resistors No No 50 k!1 50 k!1 2 k!1 & 50 k!1

FIGURE la - GENERAL CHARACTERISTICS

Ambient Temperature Range MECLI MECL II MECL III MECL 10,000

aOc to +75°C (commercial) MC350 MC1000 - -

-30°C to +85°C (industrial) - - MC1600F .L MECL 10,100
MECL 10,200
-55°C to +125°C (military) MC300 MC1200 . MECL 10,500
MECL 10,600

FIGURE lb - OPERATING TEMPERATURE RANGE

*Planned for selected devices.

Package Style MECL III MECL 10,000

--
Ceramic Flat Pack_ (Hermetic) Ves Ves

Ves
Plastic DIP (selected types) Ves

Ceramic DIP (Hermetic) Ves Yes

(For package dimensions see page 32)
FIGURE 1c - PACKAGE STVLES

1-5
 MECL IN PERSPECTIVE

CMOS (quiescent dissipation)

60 80
50
~r5d~f==t==F=t~--+--t
t + , , l--+-++1 1
. ~
54L/~4~ - t--,--,-
.
40 - + - - 70
30 I! ~ -t 1 I IJM~CLIIIII
E
> 20
I I __ consta~t 5? pJ Lone } __ t--+--+-H-~ 60

~
Gi I I 93LOO ,:' 18060 E 50
54LS/~4LS! 154/14 TT\~
"0
o I
o 10
.~
• -l-t--'-+~i'd-H+
~ 40
o
g' 7.0
0. - - .---t---+--+--+'r+-1~-t+--:::'::;'~;:':"'+--I-~H-I
"-
• 30
1./r;lJCLI
K5.0 :0
<!l
./ MECL 10,000
20
"
.~ 3.0
> 10
IITI
ECL
I i
I- 2.0 rm
10 100
Frequency (MHz)

--
1.0
2 3 4 567 10 70100 FIGURE 2b - POWER DISSIPATION
versus FREQUENCY (MECL versus TTL-SI
nW Power dissipation (mW/gate)

FIGURE 2a - SPEED-POWER CHARACTERISTICS

OF MAJOR LOGIC LINES

MECL IN PERSPECTIVE Wide Variety of Functions, including complex

In evaluating a logic line, speed and power
requirements are the obvious primary considerations.
In Figure 2, today's major logic families are compared
on the basis of these characteristics. But these are
only the start of any comparative analysis. While the
chart clearly shows that MECL and other ECL-type
families are without peer in the speed category, with
low power levels that rival some of the TTL lines,
there are a number of other characteristics that make
MECL highly desirable for systems implementation.
Among these:
Complementary Outputs cause a function and its
complement to appear simultaneously at the device
outputs, without the use of external inverters. It
reduces package count by eliminating the need for
associated invert functions and, at the same time, cuts
system power requirements and reduces timing dif-
ferential problems arising from the time delays
introduced by inverters.
High Input Impedance and Low Output Imped-
ance permit large fan out and versatile drive char·
acteristics.
Insignificant Power Supply Noise Generation, due
to differential amplifier design which eliminates
current spikes even during signal transition period.
Nearly Constant Power Supply Current Drain
simplifies power-supply design and reduces costs.
Low Cross-Talk due to low-current switching in
signal path and small (typically 850 mV) voltage
swing, and to relatively long rise and fall times.
functions facilitated by low power dissipation
(particularly in MECL 10,000 series). A basic MECL
10,000 gate consumes less than 8 mW in on-chip
power in some complex functions.
Wide Performance Flexibility due to differential
amplifier design which permits MECL circuits to be
used as linear as well as digital circuits.
Transmission Line Drive Capability is afforded by
the open emitter outputs of MECL devices. No "Line
Drivers" are listed in MECL families, because every
device is a line driver.
Wire-ORing reduces the number of logic devices
required in a design by producing additional OR gate
functions with only an interconnection.
Twisted Pair Drive Capability permits MECL
circuits to drive twisted-pair transmission lines as long
as 1000 feet.
MECL APPLICATIONS
The graduated speed ranges of the various MECL
Families satisfy a great many digital system require-
ments. MECL 10,000 is a general-purpose, high-speed
logic family specifically designed for smaller digital
systems and peripherals as well as large computers.
MECL III is recommended where its exceptionally
high speed can buy needed system performance. It is
used frequently in counter pre-scalers, high-speed
digital communication systems, VHF phase-locked
loops, high-speed digital processors, and high-speed
timing chains in computers.

1-6
 The compatibility among MECL families pro-
vides a bridge between system performance and
system cost. Thus, the many functions and complex
circuit members of the MECL 10,000 Line can be
conven iently mixed with the very-high-speed functions
of MECL III, in judicious combinations for system
optimization.
BASIC CONSIDERATIONS FOR HIGH SPEED
LOGIC DESIGN
High-speed operation involves only four considera-
tions that differ significantly from operation at jow
and medium speeds:
1. Time delays through interconnect wiring, which
may have been ignored in medium-speed systems,
become highly important at state-of-the·art speeds.
2. The possibility of distorted waveforms due to
reflections on signal lines increases with edge speed.
3. The possibility of "crosstalk" between adjacent
signal leads is proportionately increased in high speed
systems.
4. Electrical noise generation and pick-up are
more detrimental at higher speeds.
In general, these four characteristics are speed- and
frequency-dependent, and are virtually independent
of the type of logic employed. The merit of a
particular logic family is measured by how well it
compensates for these deleterious effects in system
applications.
The interconnect-wiring time delays can be
reduced only by reducing the length of the inter-
connecting lines. At logic speeds of two nanoseconds,
an equivalent "gate delay" is introduced by every
foot of interconnecting wiring. Obviously, for func-
tions interconnected within a single monolithic chip
the time delays of signals travelling from one function
to another are insignificant. But for a great many
externally interconnected parts, this can soon add up
to an appreciable delay time. Hence, the greater the
number of functions per chip, the higher the system
speed. MECL circuits, particularly those of the MECL
10,000 Series are designed with a propensity toward
complex functions to enhance overall system speed.
Waveform distortion due to line reflections also
becomes troublesome principally at state-of-the-art
speeds. At slow and medium speeds, reflections on
interconnecting lines are not usually a serious
problem. At extreme speeds, however, line lengths
can approach the wavelength of the signal and im-
properly terminated lines can result in reflections
that will cause false triggering (see Figure 3). The
solution, as in RF technology, is to employ "trans-
mission-line" practices and properly terminate each
signal line with its characteristic impedance at the end
of its run. The low-impedance, emitter-follower out-
puts of MECL circuits facilitate transmission-line
practices without upsetting the voltage levels of the
system_
The increased affinity for crosstalk in high·speed
circuits is the result of very steep leading and trailing
edges (fast rise and fall times) of the high-speed
signal. These steep wavefronts are rich in harmonics
that couple readily to adjacent circuits. In the design
of MECL 10,000, the rise and fall times of the gate
waveforms have been deliberately slowed. This reduces
the affinity for crosstalk without compromising other
important performance parameters.
From the above, it is evident that the MECL logic
line is not simply capable of operating at high speed,
but has been specifically designed to reduce the
problems that are normally associated with high-
speed operation.

-~··8"--

--~-8"-

+--
I I
Receiving Gate
I
~
n
I,
n"
I
High ~
1Jv..,..J
~S!
VTT"" -2 Vdc

I
F- RL - Zo

H:9h

I
, Receiving Gate
(
·· Input A
I
:,
:
V
Input A

·, ;. \
I
, Low
,
·.." f\
Low
.h
~ v 1
J I
FIGURE 3b - PROPERLY TERMINATED
FIGURE 3a - UNTERMINATED TRANSMISSION LINE TRANSMISSION LINE
(No Ground Plane Used) (Ground Plane Added)

1-7
 GATE CIRCUIT
Multiple Oift~.nti.1
Input' Amplifier
~ ~
-+_VC_t-
~---v,...-----'
INPUTS
FIGURE 4 - MECL GATE STRUCTURE AND SWITCHING BEHAVIOR
CIRCUIT DESCRIPTION
The typical MECL circuit, Figure 4, consists of a
differential-amplifier input circuit, a temperature and
voltage compensated bias network, and emitter-
follower outputs to restore dc levels and provide
buffering for transmission line driving. High fan-out
operation is possible because of the high input
impedance of the differential amplifier input and the
low output impedance of the emitter follower out-
puts. Power-supply noise is virtually eliminated by
the nearly constant current drain of the differential
amplifier, even during the transition period. Basic
gate design provides for simu Itaneous output of both
the OR function and its complement, the NOR
function.
Power-Supply Connections - Any of the power
supply levels, VBB, VCC, or VEE may be used as
ground; however, the use of the VCC node as ground
results in best noise immunity. In such a case: VCC =
0, VBB = -1.15 to -1.3 V (depending on the specific
MECL family), VEE = -5.2 V.
System Logic Specifications - The output logic
swing of 0.B5 V, as shown by the typical transfer
characteristics curve, varies from a LOW state of VL =
-1.75 V to a HIGH state of VH = -0.9 V with respect
to ground. (These logic levels are valid for the MECL
10,000 and MECL III families. MECL I and II logic
levels differ slightly.)
Positive logic is used when reference is made to
logical "D's" or "l's." Then
"0" = ~1.75 V = LOW
typical
"1" = -0.9 V = HIGH
Circuit Operation - Beginning with all logic inputs
LOW (nominal -1.75 V), assume that 01 through 04
GATE TRANSFER CURVES
Bies Complementary -0.800
Network Output, Hlth (-O.9 V typ.)
~ ;---"-.. I---~-"----/I--
-::::~:
-1.200
C2 VBS - -1.29 V
Low(-1.75 V typ_)
·1.800
-1.400 -1.200
Input Voltage (Volt,)
A
B~A+B+C+O
C A+8+0+C
o
GATE SYMBOL
are cut off because their P-N base-emitter junctions
are not conducting, and the forward-biased 05 is
conducting. Under these conditions, with the base of
05 held at -1.29 V by the VBB network, its emitter
will be one diode drop (0.8 V) more negative than its
base, or -2.09 V. (The 0.8 V differential is a
characteristic of this P-N junction.) The base-to-
emitter differential across 01 - 04 is then the
difference between the common emitter voltage
(-2.09 V) and the LOW logic level (-1.75 V) or 0.34
V. This is less than the threshold voltage of 01
through 04 so that these transistors will remain cut
off.
When anyone (or all) of the logic inputs are
shifted upward from the -1.75 V LOW state to the
-0.9 V HIGH state, the base voltage of that transistor
increases beyond the threshold point and the transis-
tor turns on. When this happens, the voltage at the
common-emitter point rises from -2.09 V to -1.7 (one
diode drop below the -0.9 V base voltage of the input
transistor), and since the base voltage of the fixed-
bias transistor (05) is held at -1.29 V, the base-
emitter voltage of 05 cannot sustain conduction.
Hence, this transistor is cut off.
This action is reversible, so that when the input
signal(s) return to the LOW state, 01 - 04 are again
turned off and 05 again becomes forward biased. The
collector voltages resulting from the switching action
of 01 - 04 and 05 are transferred through the output
emitter-follower to the output terminal. Note that
the differential action of the switching transistors
(one section being off when the other is on) furnishes
simultaneous complementary signals at the output.
This action also maintains constant power supply
current drain.
'-8
 MECL I MECL II
.,t;.'
Dittar• Diff.rential Bia.
Amplifier Vee Inputs Amplifier Network Follower Outputs
,--"--.. ~~~~
Vee
270 300

290

NOR
OR

1.18k 2k 2.30k RL RL

A
v
VARIATIONS AMONG MECL FAMILIES Inputs

The basic gate circuits of the four MECL families

are illustrated in Figure 5. From these diagrams, it is
evident that some variations were employed as
technology advanced. The first of these is that the
bias driver for the MECL I Line is not included on the
chip, whereas all subsequent lines have this as an MECL III
internal feature. Emitter
Follower
DIfferentIal
Second, most corresponding resistor values differ MultIple t "puts Ampllf,er Network Outputs

among all MECL Lines. This difference is necessary to

achieve the varying speed and power improvements of
100
the different lines. Of course, speed is not determined
by resistor values alone. Transistor geometries, while
not represented on a schematic, are a major deter·
minant. The transistor geometries in conjunction with
the resistor values provide the speed and power
characteristics of the different families.
Third, it will be noted that MECL 10,000 and 36' 2k 1958

MECL III gates are supplied with base pull-down

resistors (Rp = 50,000 m in each of the input
transistors while the other two families are not. These
resistors provide a path for base leakage current to
unused input bases, causing them to be well turned
off. Where these resistors are not used, any unused
inputs must be externally tied to a suitable negative
potential, e.g., VEE. MECL 10.000
A final significant difference among the families Multiple D,fferentIal Bias
EmItter
FOllower
is in the output circuits. MECL I circuits normally are Input$ AmplifIer Network Outputs

~~~r---"-.
supplied with output pull·down resistors on the chip.
MECL II circuits can be obtained with or without
output resistors. MECL III and MECL 10,000 circuits
have open outputs.
The use of on·chip output resistors has both
advantages and limitations. On the plus side is the
obvious advantage that fewer external components
are required. On the minus side is the fact that
wire·ORing capability with on·chip pulldown resistors
is limited. Moreover, with open outputs the designer
can choose both the value and location of his
termination to meet the system requirements. And
finally, the use of external resistors reduces on·
chip heating and power dissipation, allowing more FIGURE 5 - BASIC GATE DIAGRAMS FOR
complex LSI and increasing chip life and reliability. THE MECL FAMILIES

'-9
 DEFINITIONS OF LETTER SYMBOLS AND ABBREVIATIONS
Current:
Base leakage current of a MECL expander
input when at VEE.
ICC Total power supply current drawn from
the positive supply by a MECL unit under
test (IC on older data sheets).
ICBO Leakage current from input transistor on
MECL devices without pulldown resistors
when test voltage is applied.
ICCH Current drain from VCC power supply
with all inputs at logic HIGH level.
ICCL Current drain from VCC power supply
with all inputs at logic LOW level.
ICEX Collector cut·off current (VCE
VBE(off) as specified). For a MECL gate
expander, this term signifies the total
collector leakage current when all inputs
are at the negative supply potential.
Voltage:
VBB Reference bias supply voltage.
Base·to-emitter voltage drop of a tran-
VBE
sistor at specified collector and base
currents.
VCB Collector-to-base voltage drop of
transistor at specified collector and base
currents.
Vce General term for the most positive power
supply voltage to a MECL device (usually
ground, except for translator and inter-
face circuits).
"CC1 Most positive power supply voltage (out-
put devices). (Usually ground for MECL
and
devices.)
VCC2 Most positive power supply voltage Icur-
rent switches and bias driverllusually
ground for MECL devices).

Total power supply current drawn from a
MECL test unit by the negative power
supply.
Forward diode current drawn from an
input of a saturated 10gic·to·MECL trans·
lator when that input is at ground
potential.
Current into the input of the test unit
when a maximum logic HIGH (VIH max)
is applied at that input.
HIGH level node input current into an
input node with a specified HIGH level
(V I H max) logic voltage appl ied to that
node. (Same as lin for positive logic.)
LOW level node input current. The cur·
rent flowing into an input node with a
specified LOW level IV I L min) logic
voltage applied to that node.
Load current that is drawn from a MECL
circuit output when measuring the output
HIGH level voltage.
*IOH HIGH level output current: the current
flowing into the output, at a specified
HIGH level output voltage.
*IOL LOW level output current: the current
flowing into the output, at a specified
LOW level output voltage.
lOS Output short circuit current.
lout Output current (from a device or circuit,
under such conditions mentioned
context).
Reverse current drawn from a transistor
input of a test unit when VEE is applied
at that input.
ISC Short·circuit current drawn from a trans·
lator saturating output when that output
is at ground potential.
Most negative power supply voltage for a
circuit (usually -5.2 V for MECL devices).
Input voltage for measuring IF on TTL
interface circuits.
Input logic HIGH voltage level (nominal
value).
*VIH max Maximum HIGH level input voltage: The
most positive lIeast negative) value of
high-level input voltage, for which
operation of the logic element within
specification limits is guaranteed.
Input logic HIGH threshold voltage level.
VIHA min Minimum input logic HIGH level (thres-
hold) voltage for which performance is
specified.
'VIH min Minimum HIGH level input voltage: The
least positive (most negative) value of
HIGH level input voltage for which opera-
tion of the logic element within specifica-
tion limits is guaranteed.
VIL Input logic LOW voltage level (nominal
value).
'VI L max Maximum LOW level input voltage: The
most positive (least negative) value of
LOW level input voltage for which opera-
tion of the logic element within specifica-
tion limits is guaranteed.
V I LA I nput logic LOW threshold voltage level.
VILA max Maximum input logic LOW level (thres-
in
hold) voltage for which performance is
specified.
'VIL min Minimum LOW level input voltage: The
least positive (most negative) value of
LOW level input voltage for which opera-
• JEDEC, EIA, NEMA standard definition

1-10
 tion of the logic element within specifica- t-+ Propagation Delay, see Figure 12.
tion limits is guaranteed_ tpd Propagation delay, input to output from
the 50% point of the input waveform at
Yin I nput voltage (to a circuit or device\-
tx±y± pin x (falling edge noted by - or rising
V max Maximum (most positive) supply voltage, edge noted by +) to the 50% point of the
permitted under specified set of output waveform at pin y (falling edge
conditions. noted by -, or rising edge noted by +\- (Cf
'VOH Output logic HIGH voltage level: The Figure 12.)
voltage level at an output terminal for a Output waveform rise time as measured
t x+
specified output current, with the from 10% to 90% or 20% to 80% points
specified conditions applied to establish a on waveform (whichever is specified) at
HIGH level at the outpuL pin x with input conditions as specified.
VOHA Output logic HIGH threshold voltage
t x- Output waveform fall time as measured
leveL
from 90% to 10% or 80% to 20% points
VOHA min Minimum output HIGH threshold voltage on waveform (whichever is specified) at
level for which performance is specified. pin x, with input conditions as specified.
VOH max Maximum output HIGH or high-level f tog Toggle frequency of a flip-flop or
voltage for given inputs. counter device.

VOH min Minimum output HIGH or high-level volt- fshift Shift rate for a shift register.
age for given inputs. Te mperature:
'VOL Output logic LOW voltage level: The tstg Maximum temperature at which device
voltage level at the output terminal for a may be stored without damage or
specified output current, with the performance degradation.
specified conditions applied to establish a
TJ Junction (or die) temperature of an inte-
LOW level at the outpuL
grated circuit device.
VOLA Output logic LOW threshold voltage leveL
Am bien t (environment) temperature
VOLA max Maximum output LOW threshold voltage existing in the immediate vicinity of an
level for which performance is specified. integrated circuit device package.
VOL max Maximum output LOW level voltage for Thermal resistance of an IC package,
given inputs. junction to ambienL
VOL min Minimum output LOW level voltage for °JC Thermal resistance of an IC package,
given inputs. junction to case.

VTT Line load-resistor terminating voltage for LFPM Linear feet per minute.
outputs from a MECL device.
Thermal resistance of an IC package, case
VOLS1 Output logic LOW level on MECL 10,000 to ambient.
line receiver devices with all inputs at
VEE voltage leveL (This parameter is only Miscellaneous:
valid for devices on whose data sheets it is eg Signal generator inputs to a test circuit_
specified).
TPin Test point at input of unit under test.
VOLS2 Output logic LOW level on MECL 10,000
TP out Test point at output of unit under test.
line receiver devices with all inputs open.
(This parameter is only valid for devices O.U.T. Device under test.
on whose data sheets it is specified). Zout Output impedance.
Time Parameters: 'PO The total dc power applied to a device,
not including any power delivered from
t+ Waveform rise time (LOW to HIGH), 10%
the device to a load_
to 90%, or 20% to 80%, as specified.
Load Resistance.
t- Waveform fall time (HIGH to LOW), 90%
to 10%, or 80% to 20%, as specified. Terminating (load) resistor.

tr Same as t+ Rp An input pull-down resistor (i.e., con-

nected to the most negative voltage).
tf Same as t-
t+- Propagation Delay, see Figure 12. • JEOEC, EIA, NEMA standard definition

1-11
 SECTION II - TECHNICAL DATA
GENERA L CHARACTERISTICS and
SPECIFICATIONS
(See pages 7 and 8 for definitions of symbols and
abbreviations)
In subsequent sections of this Data Sook, the
functional blocks of all four MECL lines are iden-
tified and characterized. Complete data sheets are
provided for each of the functions in the MECL II,
MECL III, and MECL 10,000 families'. To make
these data sheets as useful as possible, and to avoid a
great deal of repetition, the data that is common to
all functional blocks in a line is not repeated on each
individual sheet. Rather, these common char-
acteristics, as well as the application information
that applies to each family, are discussed in this
section.
In general, the common characteristics of major
importance are:
Maximum Ratings, including both dc and ac
characteristics and temperature limits;
Transfer Characteristics, which define logic levels
and switching thresholds;
AC Parameters, such as propagation delays, rise
and fall times and other time dependent char-
acteristics.
In addition, this section will discuss general lay-
out and design guides that will help the designer
in building and testing systems with MECL circuits.
LETTER SYMBOLS AND ABBREVIATIONS
Throughout this section, and in the subsequent
data sheets, letter symbols and abbreviations will be
used in discussing electrical characteristics and
specifications. Recently, these symbols have been
under scrutiny by various industry organizations,
resulting in a number of additions and changes. The
symbols used in this book, and their definitions, are
listed on the preceeding two pages.
MAXIMUM RATINGS
The dc limit parameters beyond which the life of
the devices may be impaired are given in the
following table in Figure 6 for all MECL families. In
addition, the table provides certain ac parameter
limits which, if exceeded, will not destroy the devices,
but could degrade the performance below that of the
guaranteed specifications.
"'Complete data sheets for MECL I functions are not included
because this line is recommended only for replacement
purposes. However, such data sheets are available and can be
obtained by contacting your nearest Motorola
representative.
1-12
MECL TRANSFER CURVES
For MECL logic gates, the dual (complementary)
outputs must be represented by two transfer curves:
one to describe the OR switching action and one to
describe the NOR switching action. A typical transfer
curve and associated data for all MECL families is
shown in Figure 7a.
It is not necessary to measure transfer curves at all
points of the curves. To guarantee correct operation
it is sufficient merely to measure two sets of min/max
logic level parameters.
The first set is obtained by applying test voltages,
VI L min and VIH max (sequentially) to the gate
inputs, and measuring the OR and NOR output levels
to make sure they are between VOL max and VOL
min, and VOHmax and VOHmin specifications.
The second set of logic level parameters relates to
the switching thresholds. This set of data is
distinguished by an "A" in symbol subscripts. A test
voltage, VILA max, is applied to the gate and the
NO Rand 0 R outputs are measured to see that they
are above the VOHA min and below the VOLA max
levels, respectively. Similar checks are made using the
test input voltage VIHA min.
The result of these specifications insures that:
a) The switching threshold ('" VSS) falls within
the darkest rectangle; i.e. switching does not begin
outside this rectangle;
b) Quiescent logic levels fall in the lightest shaded
ranges;
c) Guaranteed noise immunity is met_
Figure 7b shows guaranteed 25 0 C logic level limits
and switching thresholds for each of the MECL fami-
lies, along with typical HIGH and LOW logic levels.
Of additional interest are the variations of these
parameters at Ii mit temperatures. These are given in
the tables of Figure 8, for the MECL II, III, and
10,000 families.
All of these specifications assume -5.2 V power
supply operation. Operation at other power-supply
voltages is possible, but will result in further transfer
curve changes. Transfer characteristic data obtained
for a variety of supply voltages are shown in Figure
9. The table accompanying these graphs indicates the
change rates of output voltages as a function of
power supply voltages.
Variations in logic swing amplitude for MECL II,
III, and 10,000 are shown in Figure 10.
NOISE MARGIN
"Noise margin" is a measure of a logic circuit's
resistance to undesired switching. MECL noise margin
is defined in terms of the specification points
surrounding the switching threshold. The critical
parameters of interest here are those designated with
A. Limits beyond which device life may be impaired:
FamilY
Characteristic Symbol Unit ~~~------~M~E~C~L~II~A~~M~E~C~L~I~II~--7M=E~C~L~10~.~OOO~'
'MECL I
Power Supply Voltage (VCC = 0) VEE Vdc -10toOV -10toOV -8 to 0 V -8 to 0 V
B.... Input Voltage (VCC = 0) Vin Vdc 0'0 VEe o to Vee o to vee o to VEE
Output Source Current
Continuous
10 mAde {
<20 <20 <40 <so
Surge <100
-55 to +'50 MC1000 -55 to +150 -55 to +150·
Storage Temperature T stg °c
{ -55 to +150
MC1200
-55 to +150
-55 to +160··

Junction Operating Temperature' TJ °c MC1000<150 < 165t < 165tt

MC1200 < 175

,::.~.:::"~ rn~~ d"'-:d 1

B.
MC-JOO MC1000 MCl600
urn.., : . : -55'0+125 o to +75 -30 to +85 -30 to +85·
MC350 MC1200
o to +75 -55'0 +125 -55 to +125··
AC Fan-in (Expandable gates) m <:;18 QO
AC Fan-out ~15 ~15
DC Fan-out <:;70
Power Supply Regulation ±10%
1 Case must be 'MC10, 100, MC10,200 Except MC1666-MC1671 < 1450 C
< 150 0 C. .. MClO.500. MC10,600 < 150°C
tt Plastic Package
FIGURE 6 - MAXIMUM RATINGS

-----~t--
---'-
Gate Output
(measured test limits)
VOH max

VOH min
0810

0960
I

I} Hogh
State
i 0980 I

I VOL max
1630
1.650 I
} Low
State
VOL min 1.850
T~st Conditions 25° C
VIL min
VEE
50H matched
5.2V

Inputs and outputs

Gatel"pu,
(Applied test voltage)
} - !.... V 88:;:::; 1.29V
(Switching Threshold)

FIGURE 7a - MECL TRANSFER CURVES IMECL 10000 example)

and SPECIFICATION TEST POINTS MECL 10.000

(1)<ll 10.100(1) 10,500 @

Inputs Outputs MECLI MECL II MECLIII 10,200 (J) 10,600

VIL min Vee @) -1.850 -1.850 -1.850

VIH max 0 -0.700 -O.8lO -0.810 -0.720
VOL min -1.750 -1.800 ·1.850 -1.850 -1.850
VOL max -1.465 -1.500 -1.620 -1.650 -1.620
VOH min -0.795 -0.850 ® -0.960 -0.960 -0.930
VOH max -0.690 -0.700 -0.810 -0.810 -0.720
VILA max - -1.350 -1.485 -1.475 -1.475
VIHA min - 1.025 -1.095 -1.105 -1.105
VOLA max - - -1.600 -1.630 -1.600
VOHA min - -0.980 -0.980 -0.950

With suitable inputs:

Typical Output HIGH State -0.75 -0.75 -0.900 -0.900 -0.825
Typical Output LOW State -1.55 -1.58 -1.750 -1.750 -1.725
Nominal VSS -1.15 -1.175 -1.290 -1.290 -1.290
(Switching Threshold)

CD Stabilized temperature, with ~ 500 Ifpm air flow. OJ L package outputs terminated General Conditions:
through 50 n resistor to -2.0 V. VEE = -5.2 V
~ MC1660DILpackage_ VCC = ground
@ MC10101 example. TA = 25°C
@) See individual data sheets for VI L min.
@ 100 n load to -2.0 V, stabilized temperature with ;;'500 Ifpm air flow.

FIGURE 7b - MECL LOGIC LEVEL SPECIFICATIONS (volts) 2SoC

1-13
 TRANSFER DATA FOR TEMPERATURE VARIATIONS

FIGURE 8-
TYPICAL
TRANSFER
CHARACTERISTICS
ASA au TP U T va L T AG E - 1 350f---+--+--+l'N'1f---+-+-
FUNCTION (VOL TS)
OF
TEMPERATURE
(see tables below
for data)

16 -14 -1 2 -10

INPUT VOLTAGE (VOLTS)

MECL 10,000 FAMILY

S . _{10,100 S . __ {lO,SOO
eroes 10,200 eroes 10,600
(MC10l0l) (MC10501)
Parameter (volts) -30°C +85 OC -55°C +125 OC

VIH max & VOH max -0.890 -0.700 -0.830 -0.580

VOH min -1.060 -0890 -1.080 -0.825
VOHA min -1.080 -0.910 -1.100 -0.845
VIHA min -1.205 -1.035 -1.255 -1.000
VILA max -1.500 -1.440 -1.510 -1.400
VOLA max -1.655 -1.595 -1.635 -1.525
VOL max -1.675 -1.615 -1.655 -1.545
VIL min & VOL min -1.890 -1.825 -1.920 -1.820
'Outputs loaded 50 n to -2.0 V. • 'Outputs loaded 100 n to -2.0 V.

MECL III (e.g. MC1660) FAMILY

Compatible with MECL 10,000

DIP and Flat Package

Parameter (volts) _30 o C +850 C
VIH max -0.875 -0.700
VOH max ·0.875 -0.700
VOH min -1.045 -0.890
VOHA min -1.065 ·0.910
VIHA min ·1.180 ·1.025
VILA max -1.515 -1.440
VOLA max -1.630 -1.555
VOL max ·1.650 -1.575
VIL min & VOL min 1.890 -1.830
Note: Outputs loaded 50 n to ·2.0 V.

MECL II FAMILY
Parameter (Volts) -55°C OOC +75°C +125°C

VIH max -0.825 -0.740 -0.615 -0.530

VOH max -0.825 -0.735 -0.615 -0.530
VOH min -0.990 -0.895 -0.775 -0.700
VIH min -1.165 -1.070 -0.950 -0.875
VIL max -1.405 -1.350 -1.260 -1.205
VOL max -1.580 -1.525 -1.435 -1.380
VOL min -1.890 -1.830 -1.760 -1.720
VIL min <VEE <VEE <VEE <VEE
Note: Noise margin = 175 mV.

1-14
 TRANSFER DATA FOR POWER SUPPLY VARIATIONS
_ +0.2 +0.2
;;;
t!!oJ -0.2
50!1 Load I-
oJ
50!1 Load
-0.2
-...g
0
~ -0.6
-0.6
...
" -1.0
C)

-
0( -1.0 0(
~E =-3.6V-
I-
oJ
o -1.4
/I 'JVEE' -J.6V I-
oJ
0 -1.4 \ \\ _ -<I.4V~
> 1j-4.4V > \ \ ...... ~.2V
.
5
5
-1.8

-2.2
5.2 V
6.0 V .j
j -1.8

-2.2
\. -6.0V- ~
o -7.0 V o -7.0 V
~ -2.6 T A = 25°C
,
;. -2.6
TA = 2SoC
> -3.0 I .: -3.0
-3.2 -2.B -2.4 -2.0 -1.6 -1.2 -O.B -0.4 0 -3.2 -2.B -2.4 -2.0 -1.6 -1.2 -O.S -0.4 0

Vin.INPUT VOLTAGE (VOLTS! Vin.INPUT VOLTAGE (VOLTS!

FIGURE ge - MECL 111/10,000 "OR" FIGURE 9b - MECL 111/10,000 "NOR"

;;; -0.7 u; -0.7

~ -0.9 I I iff I-
oJ -0.9
o
~
I I /I ~ VE~=~3.0~_ 0
~ -1.1
...
C)
-1.1
J Y. i"- 3.6 It w
<.:>
0( -1.3 <t -1.3
I- ~ 4.4 V I-
oJ
oJ
o -1.5 0 -1.5
> I'-- 5.2 V >
)
..55 -1.7
"- -6.0V ......
I-
::l

::l
-1.7

-1.9
-1.9
o I-- "~-7.0 V TA :::z +25 0 C 0
; -2.1 50 -2.1

>0 -2.3
~~ -B.OIV > -2.3
-1.B -1.4 -1.0 -0.6 -0.2 0 -l.B -1.4 -1.0 -0.6 -0.2 0
Yin. INPUT VOLTAGE (VOLTS! Vin. INPUT VOLTAGE (VOLTS)

FIGURE 9c - MECL II "OR" FIGURE 9d - MECL II "NOR"

Voltage MEClll MECl10,OOO" MEClll1

~VOH/~VEE 0.015 0.016 0.033
~VOl/~VEE 0.230 0.250 0.27
~VBB/~VEE 0.115 0.148 0.14
"and subsets: 10,200; 10,500; 10,600.
FIGURE 9a - LEVEL CHANGE RATES

LOGIC SWING VARIATIONS WITH TEMPERATURE AND SUPPLY VOLTAGE

1.60

~ 1.44 50 n 'to -2 J
oJ
o 1.28
~ ......,:::,;;
C) 1.12
....-::::: ~
Z ".
i 0.96
.......-:: ~
III
Beoe ...
rP'
!:1 0.80
~~
C)

g 0.64
.
>0. 0 .48 ~ ~
'-Jooe

~ 25°C
0.32
-3.6 -4.4 -5.2 -6.0 -6.8
VEE. SUPPLY VOLTAGE (VOLTS!
0.2 '--_'--_-1._ _......._ _'--_ _......._ _-"
-3.0 -3.8 -4.4 -5.2 -8.0 -7.0 -8.0
VEE. SUPPL.Y VOL. TAOE (VOLTS)
FIOURE 10. - MECL II FIOURE 1Gb - MECL 111/10.000

1-15
 --------Jr+·1.475 ·1.105 1l.V = High .Noise {
VOHA min
Margm
V,HA min
1High
JSt8te
VOHA min ------t.o ·0.980

VILAmax
.6. = Low Noise {
V Margin
VOLA max
VOLA max ·1.630
Gate , Low
Output
i State NOISE
MARGIN COMPUTATIONS
Gate
Input
V,LA max V,HA min
Guaranteed
Vas (switching threshold)
Worst·Case de Typical de
SPECIFICATION POINTS FOR Family Noise Margin Noise Margin
DETERMINING NOISE MARGIN MECL II 0.175/0.150' 0.250/0.200'
All MECL 10.000 0.125 0.210
~ MECL III 0.115 0.200
~~ 01 L and Flat Package

ELEMENT 2 NOISE MARGIN MEASUREMENT *Depending on part type. See selector gUide or data sheet.
POINTS FOR MECL GATES MECL NOISE MARGIN DATA'

FIGURE 11

the "A" subscript (VOHA min, VOLA max, VIHA
min, V ILA max) in the transfer characteristic curves.
Guaranteed noise margin (NM) is defined as
follows:
NMHIGH LEVEL = VOHA min' VIHA min
NMLOW LEVEL = VILA max' VOLA max·
To see how noise margin is computed, assume a
MECL gate drives a similar MECL gate, Figure 11.
At a gate input (point B) equal to VI LA max, MECL
gate #2 can begin to enter the shaded transition region.
This is a "worst case" condition, since the VOLA
max specification point guarantees that no gate can
enter the transition region before an input equal to
VI LA max is reached. Clearly then, VI LA max is one
critical point for noise margin computation, since it is
the edge of the transition region.
To find the other critical voltage, consider the
output from MECL gate #1 (point A). What is the
most positive value possible for this voltage (consider·
ing worst case gate specifications)? From Figure 11 it
can be observed that the VOLA max specification
insures that the LOW state OR output from gate 1
can be no greater than VOLA max.
Note that VOLA maxis more negative than VILA
max. Thus, with VOLA max at the input to gate #2,
the transition region is not yet reached. (The input
voltage to gate #2 is still to the left of VI LA max on
the transfer curve.)
In order to ever run the chance of switching gate
#2, we would need an additional voltage, to move the
input from VOLA max to VI LA max. This con·
stitutes the "safety factor" known as noise margin. It
can be calculated as the magnitude of the difference
between the two specification voltages, or for the
MECL 10,000 levels shown:
NMLOW = VILA max' VOLA max
= ·1.475 V· (·1.630 V)
= 155 mV.
Similarly, for the HIGH state:
NMHIGH = VOHA min' VIHA min
= ·0.980 V . (·1.105 V)
= 125 mV
Analogous results are obtained when considering
the "NOR" transfer data.
Note that these noise margins are absolute worst
case cond itions. The lesser of the two noise margins is
that for the HIGH state, 125 mV. This then,
constitutes the guaranteed margin against signal
undershoot, and power or thermal disturbances.
As shown in the table, typical noise margins are
usually better than guaranteed - by about 75 mV.
Noise margin is a dc specification that can be
calculated, since it is defined by specification points
tabulated on MECL data sheets. However, by itself,
this specification does not give a complete picture
regarding the noise immunity of a system built with a
particular set of circuits. Overall system noise im·
munity involves not only noise·margin specifications,
but also other circuit·related factors that determine
how difficult it is to apply a noise signal of sufficient
magnitude and duration to cause the circuit to
propagate a false logic state. In general, then, noise
immunity involves line impedances, circuit output
impedances, and propagation delay in addition to
noise·margin specifications. This subject is discussed
in greater detail in Application Notes AN·298 and
AN·592.

1-16
AC OR TIME PARAMETERS "conditions" associated with a particular parameter
Time dependent specifications are those that may differ among logic families, the common MECL
define the effects of the circuit on a specified input waveform and propagation delay terminology are
signal, as it travels through the circuit. They include depicted in Figure 12. Specific rise, fall, and prop-
the time delay involved in changing the output level agation delay ti mes are given on the data sheet
from one logic state to another (t+; t-). In addition, for each specific functional block, but like the
they include the ti me required for the output transfer characteristics, ac parameters are temperature
of a circuit to respond to the input signal, des· and voltage dependent. Typical variations for the
ignated as propagation delay. Since this terminol· MECL families are given in the curves of Figure 13.
ogy has varied over the years, and because the

Undershoot
Overshoot
50% t~~~~~~~~~~~~~.~i~~~~~~~H~i:9h~L~evel
1 VIHA
VILA
VBB
V out OR
Undershoot t Low Leval

~
MECL WAVEFORM TERMINOLOGY -+
t+-

~
o% V out NOR 50%

~
o%
Vout 10% Vout 20%
• Designated tpd· on older data sheets
t-- t+ t- - t+ •• Designated tpd+ on older data sheets
t- = tf t+ = tr t- .,. tf t+ "'" tr
MECL II, III RISE AND FALL TIMES MECL 10,000 RISE AND FALL TIMES MECL PROPAGATION DELAY

FIGURE 12

2.6 2.S
] 2.5 ~ I-sol n LJad to l -2.0 ~
I _1+B5°
Jc >
c
2.4 t - - t-so1n LO~d '°1_2 .0 Y
> OR ..: 85°C
..: 2.4
.J
~ SOcj
:::;.. _30 0 c
.J
w
2.3
r- ./ -I
~ 2.3 0 2.2 NJA
I
Z I-- 25°,:1

-
~ 2.2 2.1 o
_30 e
~ 2.1
l 9
....
.......
. / 8Soe

-- 250~1
..: 2.0
..: 8Soe
r- OA V
~ 2.0
t
1-
t---
NOR
r::-- ..... 30°C
sOei
..
C>
..: 1.9
I-- __ 30°C

a:
CL
1.9
1.8
--- I-- -~ .
0
a:
1.8
1.7
1.7 :.. 1.6
~ 1.6 t 1.S
-3.6 -4.4 -5.2 -6.0 -6.8 -3.6 -4.4 -S.2 -6.0 -6.8
VEE. SUPPLY VOLTAGE (VOLTS) VEE. SUPPLY VOLTAGE (VOLTS)
• Formerly designated tpd- • -Formerly designated tpd+
FIGURE 13a - TYPICAL PROPAGATION DELAY t··- FIGURE 13b - TYPICAL PROPAGATION DELAY t++--
versus VEE and TEMPERATURE (MECL 10,000) versus VEE and TEMPERATURE (MECL 10,000)

+-2.~
- r
3.9 5.2
.n
~I n
50 Load to -2.0 V

- r--
3.8 5.0 L10ad V
~
NOR
J I
85 0
..
- r--
3.7 4.8
w """'=:::I:::::::
t::i- T8s oe
~ 3.6 soc!
~
4.6
w I--- _30°C -..,J25Oe
::; 3.5 w 4.4
::; NiA
1· 30oe
~ 3.4 ~ 4.2
.J
.J 3.3
i'-.. w
4.0
I I
.....: J'-.. !!? ......... I
a: r--.. I
3.2
" r-:h. 3.8 OA
3.1
3.0
2.9
---
r- -+-
--.-. -
8Soe
r---,~soei
1--..L'300e
t
3.6
3.4
3.2
~ t-- - I -
-I-

1
8SoC
25°C,
1.30°9
-3.6 -4.4 -S.2 -6.0 -6.8 -3.6 -4.4 -5.2 -6.0 -6.8
VEE. SUPPLY VOLTAGE (VOLTS) VEE,SUPPLY VOLTAGE (VOLTS)

FIGURE 13c - TYPICAL FALL TIME (90%to 10%) FIGURE 13d - TYPICAL RISE TIME (10%to 90%)
_sus TEMPERATURE and SUPPLY VOLTAGE _SUI TEMPERA TUR E and SUPPLY VO L TAG E
(MECL 10,100) (MECL 10,100)

1·17
 TYPICAL DELAY TIMES FOR MECL II FAMILY

7.S r--.,.---r-----,--~---_._--___, 20

- Input tT .. t- • 5.0 ns
Input t+ "" t-: 5.0 ns I.
V
Fen-out = 1 -;;
5. 5. Fen-out ... 1
"' +12SoC w +1250~ -..........
+750~~
~
j: 6.0 ~-+----I---
>
«
+7S o C
"''"'+--'::O'......~£...-.---l
>
«
~
j:
10
+2S0C,
OoC
t-YJ'-... /
-' -' -SSoC "- ")(. /
w w
"'- "- 7'
"
C C 7.0
~5.0r---1-----1-----~~~~~·--~~~---1 Z f' /
a ....,
j:
« ~5.0 / ,""X 'V/
" .."«c i
/ A ~
~4.0~~~~~~~~~::::~::::::~~~~ a:
Q. 3.0
./
...v ~ ~
~-
+
3.0~ __ ~ ____ ~ ____ ~ ____-,-______ ~ ____--,
t;. 2.0 I
-3.0 -3.6 -44 -S.2 -6.0 -1.0 -8.0 -3.0 -3.6 -4.4 -5.2 -6.0 - 7.0 -8.0
VEE. SUPPLY VOLTAGE (VOLTS) VEE. SUPPLY VOLTAGE (VOL TS)
• Formerly d •• ignated tpd- •• F orm.rly desinated tpd +

FIGURE 138 - TYPICAL PROPAGATION DELAY FIGURE 131 - TYPICAL PROPAGATION DELAY
t- -* versus TEMPERATURE and t++** versus TEMPERATURE and
SUPPLY VOLTAGE (MECL II) SUPPLY VOLTAGE (MECL II)

11 7.0.----,----,-----,---,----,-----,
Input t+ = t- =5.0 ns Input t+ = t- = 5.0 ns
10 Fan-out = 1
I

.
.£
9.0 +12SoC
I

+75 0 C
w S.O +2Soe
:!
;:: 7.0 oOe
..J -SSoC
..J
6.0
...<a:
~ 5.0

4.0

3.0
-3.0 -3.6 -4.4 -S.2 -6.0 -7.0 -S.O 2~3L.0----3~.~6---~4~.4~--~5~.~2----6~.~0-----~7~.0~---~S.0
VEE. SUPPLY VOLTAGE (VOLTS) VEE. SUPPLY VOLTAGE (VOLTS)

FIGURE 13g - TYPICAL FALL TIME FIGURE 13h - TYPICAL RISE TIME
(90% to 10%) versus TEMPERATURE and (10%to 90%) versus TEMPERATURE and
SUPPLY VOLTAGE (MECL II) SUPPLY VOLTAGE (MECL II)

1-18
 TYPICAL DELAY TIMES FOR MECL 10,000 FAMILY

2.6 3.4
1010 n Ll.d to ~2.0 V~C 100ln LO~d to -J.o Vd~ 1+1250~
"0
7.4
NOR
"
o
3.2
>
«
..J
w
I'---t-.,
>
«
u! 3.0
N6R
1
0
z
2.2
........ o
~
/
Q
....
«
2.0

r-- ~
...... "'-- j:
«
(!)
2.8

2.6
/ /1
_55°C

"""
t:l
«
"- 1.B ........
+12SoC
~ lL /
+250~
0 ........",., o 2.4
II:
"- ~ II:
"-
........... ~V .;j5 C
0
1
-650~-

-
1.6
2.2
f--'
1.4 J +
!. 2.0
V
-3.6 -4.4 -5.2 -6.0 -6.8 -3.6 -4.4 -5.2 -6.0 -6.8
VEE. SUPPLY VOLTAGE (VOLTS) VEE,SUPPLY VOLTAGE VOLTS
-Formerly des;gnated tpd- •• Formerly designated tpd+

FIGURE 131 - TYPICAL PROPAGATION DELAY FIGURE 13i - TYPICAL PROPAGATION DELAY
t--* versus VEE and TEMPERATURE t++** venus VEE and TEMPERATURE
(MECL 10,500) (MECL 10,500)

1.9 2.2
L~.d V~c ri
'"
NOR 1cio n to 1_ 2 .0 '00 Load Ito -2.ci Vd c
1.8
I 2. 1

~
0 1.7
r----. 0 r- 1
+125 0 C - 2.0
l""- t'-....
-............
~
UJ NOR
r--........
"'"f',.'\
:;;
j: 1.6 ~ 1.9
..J
..J
r-... ~ UJ
~
« ~ 1.8 -55°C
u.
.!.
1.5
~
-550~-
+2SOC
II: r-- r-- ....... ~-
+12SoC

1.4 t 1.7 t-- I

+25 0 C -

1.3
-3.6 -4.4 -5.2 -6.0 -6.8
1.6
-3.6 -4.4 -5.2 -6.0
1 -6.8
VEE,SUPPLY VOLTAGE (VOLTS) VEE,SUPPLY VOLTAGE (VOLTS)

FIGURE 13k - TYPICAL FALL TIME FIGURE 131 - TYPICAL RISE TIME (20% to 80%) versus
(80% to 20%) versus TEMPERATURE and TEMPERATURE and SUPPLY VOLTAGE
(MECL 10,500) (MECL 10,500)

SETUP AND HOLD TIMES

The tsetup and thold times are two ac specifi- The thold is similarly defined to be the time after the
cations which can be confused unless clearly defined. Clock transition that Data must remain to insure that
For MECL devices, tsetup is defined as the time bistable outputs retain their state.
(50% - 50%) before a Clock transition that Data must In specifying devices, Motorola establishes and
be present for a bistable circuit to "recognize" the guarantees values for tsetup and thold. The limits for
incoming Data. tsetup and thold insure proper logical function of
bistable circuits, but do not guarantee that prop-
50%
agation delay or noise specifications wi II be met under
D - - -J all conditions when operating near the limits. For
MECL bistable circuits, proper device operation
50%
c---4--..J usually occurs with Data present for somewhat less
tsetup time than that specified for tsetup and thold.

1-19
 SECTION III - OPERATIONAL DATA

POWER SUPPLY CONSIDERATIONS Output Terminating

Transistor Resistor
MECL circuits are characterized with the VCC Power Power
point at ground potential and the V EE point at -5_2 Terminating Dissipation Dissipation
V_ While this MECL convention is not necessarily Resistor Value (mWI (mWI
mandatory, it does result in maximum noise im- 150 ohms to -2.0 Vdc 5.0 4.3
munity _ This is so because any noise induced on the 100 ohms to -2.0 Vdc 7.5 6.5
VEE line is applied to the circuit as a common-mode 75 ohms to -2.0 Vdc 10 8.7
signal which is rejected by the differential action of 50 ohms to -2.0 Vdc 15 13
the MECL input circuit_ Noise induced into the Vee 2.0 k ohms to VEE 2.5 7.7
line is not cancelled out in this fashion_ Hence, a good 1.0 k ohm to VEE 4.9 15.4
system ground at the Vce bus is required for best 680 ohms to VEE 7.2 22.6
noise immunity_ 510 ohms to VEE 9.7 30.2
Power supply regulation of 10% or better is 270 ohms to VEE 18.3 57.2
recommended_ The -5.2 V power supply potential 82 ohms to Vee and 15 140
130 ohms to VEE
will result in best circuit speed. Other values for VEE
may be used. A more negative voltage will increase
FIGURE 14 - TYPICAL POWER DISSIPATION
noise margins at a cost of increased power dissipation. IN OUTPUT CIRCUIT WITH EXTERNAL
A less negative voltage will have just the opposite TERMINATING RESISTORS
effect.
On logic cards, a ground plane or ground bus
system should be used. A bus system should be wide
enough to prevent significant voltage drops between system designer can compute total package power for
supply and device and to produce a low source his particular termination technique by adding, IE x
inductance. 5.2 + Output Device Power. Some of the devices in
Although little power supply noise is generated by the MECL I, II, and III Lines include on-chip
MECL logic, power supply bypass capacitors are output pulldown resistors, so that adding termina-
recommended to handle switching currents caused by tion power has already been accomplished. None of
stray capacitance and asymmetric circuit loading. A the devices in the MECl 10,000 Series incorporate
parallel combination of a 1.0 /--IF and a 100 pF internal output pulldown resistors.
capacitor at the power entrance to the board, and a The omission of these resistors permits the use of
0.01 /--IF low-inductance capacitor between ground external terminations designed to yield best system
and the -5.2 V line every four to six packages, are performance. To obtain total operating power dissipa-
recommended. tion of a particular functional block in a system, the
Most MECL 10,000 and MECL III circuits have dissipation of the output transistor, under load, must
two Vec leads. Veel supplies current to the output be added to the specified power dissipation of those
transistors and VCC2 is connected to the circuit logic circuits without internal termination.
transistors. The separate VCC pins reduce cross· The table in Figure 14 lists the power dissipation
coupling between individual circuits within a package in the output transistors plus that in the external
even when the outputs are driving heavy loads. terminating resistors, for the more commonly used
Circuits with large drive capability, similar to the termination values and circuit configurations. To
MC10ll0, have two Vee1 pins. The Vee pins should obtain true package power dissipation, one output-
be connected to the ground plane or ground bus as transistor power-dissipation value must be added to
close to the package as possible. the specified package power dissipation for each
All MEeL II, MEeL III, and MECL 10,000 devices external termination resistor used in conjunction with
have their own internal temperature and power-volt- that package. To obtain system power dissipation, the
age-compensated bias voltage sources. stated dissipation in the external terminating resistors
For further discussion of MECL power supply must be added as well. Unused outputs draw no
considerations to be made in system designing, see power and may be ignored.
MECL System Design Handbook, Ch. 5. The power dissipation of MEel functional blocks
varies with both temperature and VEE. Typical
POWER DISSIPATION variations are shown in Figure 15. The graph is
The power dissipation of MEeL functional blocks normalized so that it applies to all MEeL lines. The
is specified on their respective data sheets. This reference temperature is 25°C and the reference
specification does not include power dissipated in the power is obtained by multiplying the typical IE value
output devices due to output termination. The (total power supply drain current specified on the

'-20
 +1.0
3.0

J. - Lv
Vee - -5.2 V

'- ;;;
+0.5
~ "2.5 ......
;::-
<•
L.!!
=~ 2.0
I -7.0 V
r-- o
2!
w

"~
o

r +126 0 C
'0&
I:~
W 0

~ ~1.5 1 - o
>
-0.5
~ /-
2SOC

"-Issoc ,
....
- r
L •
6.0 V ~ -1.0 VOH

~L
~
+~2S0C
Q '
wi
~.::
I :0
H
"
..J 1.0 5.2 V 0_1.5 25°C
.. >
:l~ -4~4 V
; / ~ 5SoC
0:- >. VOL I
Q
VOL
Z 0.6 3.6V_
- -2.0
I
3.0 V -2.5 I (10 m •• j

o
-55 -25 o +25
I
+75 +125
+5.0 - 5.0 - 10 -15 - 20 - 25 -30 35 - 40
LOAD CURRENT (mAl
T A. AMBIENT TEMPERATURE CDC)
FIGURE 168 - MECL II TYPICAL OUTPUT VOLTAGES
FIGURE 15 - NORMALIZED POWER DISSIPATION versus LOAD CURRENT and TEMPERATURE
+1. 0
versus TEMPERATURE and SUPPLY VOLTAGE
Vee = -5.2 V

+0.
•
~...
data sheet) by VEE (5.2 V). For those devices where o
only the maximum value of IE is specified on the ~
w
data sheet, nominal power dissipation is approximate· "«~ +7SoC

Iy 80% of that calculated with the I E (max) o

>
-0. 5
~r-- VOH
/ VOI C

specification. to- -1.0

~r-L- ---; V
:0 v H
~
LOADING CHARACTERISTICS :0
o -1. S
1.<= .Loc
.... OOC
The differential input to MECL circuits offers :0
o
several advantages. Its common-mode·rejection :> -2.0 v L"":: F=
feature offers immunity against power-supply noise (10 m . . )
-2.5
injection, and its relatively high input impedance +5.0 5.0 10 15 20 25 30 35 40
makes it possible for any circuit to drive a relatively LOAQ CURRENT (mAl

large number of gate inputs without deterioration of FIGURE 16b - MECL II TYPICAL OUTPUT VOLTAGES
vemls LOAD CURRENT and TEMPERATURE -
the guaranteed noise margin. Hence, dc fan·out with O·C I!o +75·C
MECL circuits does not normally present a design
problem.
The specified dc loading factors (the number of
gate inputs of the same family that can be driven by a
circuit output) for MECL I and MECL II families is
25. For MECL 10,000, it is 90; and for MECL III, it
1-... 301-----i>--~'"
is 70 or 7, depending on the input impedance of the 520~~~~~~+-~~-4~-*---*---+f-~
circuit (whether the system is implemented with
high-impedance or low-impedance devices).
Graphs showing typical output voltage levels as a
function of load current for MECL II, III, and 10,000
are shown in Figure 16. These graphs can be used to (LOAD LINES FOR TERMINATION TO VEE (-5.2 Vdcl250C

determine the actual output voltages for loads 50

exceeding normal operation.

While dc loading causes a change in output voltage
40
JI
LHA J••-vlA
~
VOH min I
levels, thereby tending to affect noise margins, ac VOH m~x J I
I
VOl
rna. l J0"L
moo

~ 1I /
200 Ohms I I
loading increases the capacitances associated with the I I
circuit and, therefore, affects circuit speed. The effect
of fan-out on MECL II speed is shown in the graphs
of Figure 17.
10
JOOOh~'
1K Ohm.
J
1
I I
I -
For MECL 10,000 and MECL III, best a :----2K Ohm.
o ·0.5 1.0 1.5 2.0
performance at fan-outs greater than 10 and 6, VOUTCVOL TS)

respectively, will occur with the use of transmission FIGURE 16c- OUTPUT VOLTAGE LEVELS
lines. versus DC LOADING, MECL III and MECL 10,000

1-21
 10
,n'put t1 = t· = 5.0 n.
Vee >= -5.2 V
I. .l 35

30 -
I~putt1 '" t· :. 50
Vee = ·5.2 V
~s
(Single PulldOl/lln Resistor)
I
/
VV
,/
8.0
l125l\ I
125°C ........ ,"

~ ~~~
2.

c ]
'5OC ........
I
2 SoC-..
'" ~ ~ ~
IY
~
~ E
20

~~~
,: 6.0
,......,::;:f:::::::;-- - ,: 1:7
~
ii' --=="
;::;;-. ".....
1./ / ;;;
~ 15

~~
~
~
:::;0- ;::;-55 0
\ "- ·5SoC

r
t-
I ooJ ./ 10 ./.. I r--
~
~~
4.0 c

I
5.0
,
2.0 I
10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF) LOAD CAPACITANCE tpF)
6 8 10 12 14 16 18 20 6 8 10 12 14 16 18 20
FAN·aUT FAN-OUT

FIGURE 17a - MEeL" RISE TIME versus FIGURE 17b - MEeL " FALL TIME versus
LOADING and TEMPERATURE LOADING and TEMPERATURE,
(Single Pull-down Resistod
10
tn~ut t+l= t. =150 n1
Vee'" -5.2 v
]
w 8.0 20~-+--~--+-~---+--~--r-~---b~
~
~

> . ~
~

>

--- i~
~
I-- ~

-
.J
w 6.0 ~ 15~~--~--~--~-+~-p~+-~~~~~
0 I-- f.- I-:::::: o
Z
-\ f.--
""
~
~ 40

I"""" ('-- o( 551°C

~
0 ,"-- 2SoC
~

-
20
: \ ,lsoC I _
-
'-rOCI
o °0~-'~0~~2~0~3~0~~40~~5~0~~60~~'~0~~~~~1~00
o ,a 20 30 40 50 60 70 aD 90 '00
LOAD CAPACIT ANCE (pF) LOAD CAPACITANCE
6 B 10 12 14 16 18 20 6 8 10 12 14 16 18 20
FAN·OUT FAN·OUT

FIGURE 17c - MEeL" PROPAGATION DELAY t++ FIGURE 17d - MEeL" PROPAGATION DELAY t--
versus LOADING and TEMPERATURE versus LOADING and TEMPERATURE
3.0 6.5
] 2',8 r-- ~o n Lood I J J ] 6.0 -150 n l LOad l
; 2. 6
I I
t++
~ 5.5
~
IoU 2.4 ~ 5.0

~ 2. 2
I .J
.J 4.5 -?
.;-
g 2.0
I

t--
I I
,
~
~

0
4.0 - -;.- V
f--:
~ , z 3.S

-
1.8
:
o
1.6
1
I
I j i
~
w
!!!
a:
3.0 <:::
~ 2.5
1.4
I I .. 2.0
I
I I I I I t 1.5 I
2.0 4.0 6.0 B.O 10 12 14 16 18 20 2.0 4.0 6.0 8.0 10 12 14 16 18 20
FANOUT (NUMBER OF GATE INPUTS) FANOUT (NUMBER OF GATE INPUTS)

FIGURE 188 - MEeL 10,000 GATE PROPAGATION FIGURE 18b - MEeL 10,000 RISE and FALL TIME
DELAY TIME versus FANOUT (Fanout-at End of 14" (10% to 90%1 versus FANOUT (Fanout at End of 14" 50 n
50 n Matched Transmission Linel Matched Transmission Linel

The propagation delay and rise time of a driving Co is the normal line capacitance, and Cd is the
gate are affected very little by capacitance loading distributed capacitance due to loading and stubs off
along a matched parallel-terminated transmission line_ the line_
However, the delay and characteristic impedance of Maximum allowable stub lengths for loading off of
the transmission line itself are affected by the a MECL 10,000 transmission line vary with line
distributed capacitance. Signal propagation down the impedance_ For example, with Zo = 50 ohms,
line will be increased by a factor,...; 1 + Cd/Co. Here maximum stub length would be 4_5 inches (1.8 in. for

'-22
MECL III). But when Zo = 100 ohms, the maximum
allowable stub length is decreased to 2.8 inches (1.0
in. for MECL III).
The input loading capacitance of a MECL 10,000
device is 2.9 pF (e.g. MC10l09). Therefore it is
recommended that non·transmission-line environment
fanout be limited to a maximum of 10 loads, due to
line delay increases which limit system speed.
The input loading capacitance of a MECL III logic
function is 3.3 pF. Therefore it is recommended
that non·transmission·line environment fanout be limi·
ted to a maximum of 6 loads.
Shown in Figure 18 are the effects of fanout on
MECL 10,000 time parameters.
UNUSED MECL INPUTS
The input impedance of a differential amplifier, as
used in the typical MECL input circuit, is very high
when the applied signal level is low. Under low·signal
conditions, therefore, any leakage to the input
capacitance of the gate could cause a gradual build·up
of voltage on the input lead, thereby adversely
affecting the switching characteristics at low repeti·
tion rates.
For MECL I and MECL II circuits, the gate inputs
are essentially open. In use, therefore, any unused
inputs should be tied to a negative potential for
SECTION IV - SYSTEM DESIGN CONSIDERATIONS
THERMAL MANAGEMENT
Circuit performance and long-term circuit reo
liability are affected by die temperature. Normally,
both are improved by keeping the IC junction
temperatures low.
Electrical power dissipated in any integrated cir·
cuit is a source of heat. This heat source increases the
temperature .of the die relative to some reference
point, normally the ambient temperature of 25°C in
still air. The temperature increase, then, depends on
the amount of power dissipated in the circuit and on
the net thermal resistance between the heat source
and the reference point.
the average temperature at the junction is a
function of the system's ability to remove heat
generated in the circuit - from the junction region to
the. ambient environment. The basic formula for
converting power dissipation to estimated junction
temperature is:
TJ = TA + Po (/lJC + /lCA) (1)
or
(2)
where
T J = junction temperature
T A = ambient temperature
Po = calculated power dissipation
1-23
reliable system operation. Most devices can use VEE
as the input return, but control inputs of series
reliable system operation. Most devices can use
VEE as the input return, but control inputs of
series gated devices such as the MC1019, MC1021,
MC1028, MC1035, MC1038, MC1045, and MC1066
should be returned to the VOL level. This protects
against voltage buildup on the unused inputs and
assures that noise immunity depends only on those
inputs actively used.
All single·ended input MECL 10,000 and MECL III
circuits contain input pull·down resistors between the
input transistor bases and VEE. As a result, unused
inputs may be left unconnected (the resistor provides
a sink for ICBO leakage currents, and inputs are held
sufficiently negative that circuits will not trigger due
to noise coupled into such inputs).
Input pull·down resistor values for the MECL III
high·impedance circuits and all MECL 10,000 devices
are typically 50 kn and are not to be used as
pull-down resistors for preceding open·emitter out·
puts.
Several MECL 10,000 devices don't contain input
pull·downs. Examples are the differential line reo
ceivers, MC10115 and MC10116. If a single dif·
ferential receiver of either device type is unused, one
input of that receiver must be tied to the VBB pin
provided, and the other input goes to VEE.
/I JC = thermal resistance, junction to case
/lCA = thermal resistance, case to ambient
/I JA = thermal resistance, junction to ambient
Only two terms on the right side of equation (1)
can be varied by the user - the ambient temperature,
and the device case·to-ambient thermal resistance,
/lCA. (To some extent the device power dissipation
can be also controlled, but under recommended use
the VEE supply and loading dictate a fixed power
dissipation.) Hence, both system air flow and the
MECL package mounting technique affect the
thermal resistance term.
OJA _ °CIWatt
°JC -
IStillAir) °CIWatt
Package Worst Case Typicat Worst Case
Ceramic Flat Pack 210 .166 60
(Cerflat) 1I4x 1/4
(Gold Eutectic Die Bond)
Plastic Dual-In-line, 150 100 70
14 lead or 16 lead
(Gold Eutectic Die Bond)
Ceramic Dual-in-Line 150 100 50
14 or 16 lead
(Gold Eutectic Ole BondI
Ceramic Dual-ln·Line
24 Lead 45' 10'
Plastic Dual-I n-Lme
24 Lead 65··
"Data for 8200 SQ. mil die SIZe
0·500 If pm air flow
FIGURE 19"':" WORST CASE AND TYPICAL THERMAL
RESISTANCE RATINGS FOR SELECTED Ie PACKAG ES
 • 1200r---,---,---,---,----r--, Internally, thermal resistance of an integrated
~ A '" Ceramic Flat Package circuit is a function of the package material and size,
@:: 1000k--:-+- B -= Pla,tic Package.
and of the method used in bonding the IC die to the
3: C = Ceramic Dual In-Line
E package. For some standard IC packages, the worst·
case and typical thermal resistance values are given in
the table in Figure 19. In Figure 20, this basic data is
converted into a graph showing the maximum power
dissipation allowable at various ambient temperatures
for circuits mounted in the various packages, taking
into account the maximum permissible junction
temperature for devices packaged in plastic or ceramic.
These measurements are taken in still air.
O~_~_~~~~_~_~~~
25 50 75 100 The effect of air flow over the packages on 8 JA is
T A. Ambient Temperatur. (oC) illustrated in the graph of Figure 21 for two different
FIGURE 20 - AMBIENT TEMPERATURE mounting methods. This driven air flow reduces the
DERATING CURVE thermal resistance of the package, therefore per·
mitting a corresponding increase in power dissipation
without exceeding the maximum permissible junction
temperature.
As an example of the use of the information
above, the junction temperature for a quad MECL
100r---r--,r--,---.--~--r-~
Z A)(is 10,000 gate loaded with ·four SO ohm loads can be
calculated. Typical total power dissipation (including
a load) for this quad gate is 164 mW. Assume for this
thermal study that air flow is 500 linear feet per
minute and that the device is soldered into a printed
circuit board. From Figure 21, curve #2, 8JA is
SOoCIW. With T A (air flow temperature at the device)
equal to 2SoC, the following junction temperature
results:
TJ = PD 8 JA + T A
TJ = (0.164 W) (SOoCIW) + 2SoC = 33.2 °c
Under the above operating conditions the MECL
AlA FLOW (LFPM)
10,000 quad gate has its junction elevated above
Package Tvpe - 1S-Lead Black CeramIc ambient temperature by only 8.2°C.
Dissipation Le .... el - 200 mW
Air Flow - Z-Axis 2SoC· Ellen though devices on a printed circuit board
Method - Calibrated Diode may each have different power dissipations, all will
Package Mounting #1 Barnes Socket
#2 Printed Circuit Board have the same input and output levels provided that
4" )( 6" .Ie 0.062" - 2 oz. Cu.
each is subject to identical air flow and the same
• x-axis air flow lowers 8 JA by SoC per watt. ambient air temperature. This eases design, since the
FIGURE 21 - TYPICAL THERMAL RESISTANCES FOR only change in levels between devices is due to the
16-PIN BLACK CERAMIC DUAL IN·LINE PACKAGES
increase in ambient temperature as the air passes over
the devices, or differences in ambient temperature
between two devices.

MOUNTING and HEAT SINK SUGGESTIONS for

Pack_ Ambient Condition 9JA MECL.III
Stud Copper heat si nk 37°C/W typ
With large subnanosecond logic systems, the use of
Dual I n·Line ;;. 500 linear fpm blown air SOoC/W typ multilayer printed circuit boards is recommended.
Low Power
Such boards permit better ground planes and shorter
Dual In·Line Mounted in heat sink 35°C/W max
High Power and interconnection runs than single·layer boards and also
(PD>500mW) 500 linear fpm blown air allow better use of stripline techniques.
or MECL III circuits have an average power dissipa·
Mounted in heat sink
and
tion of approximately 60 mW per logic gate. Ade·
on printed circuit ground quate cooling should be provided to insure that
plane using termal paste device junction temperatures do not exceed 110°C.
FIGURE 22 - THERMAL CONDITIONS FOR The dc data sheet specifications for MECL III are
DC SPECIFICATIONS - MECL III given for an operating temperature range from -300 C

'·24
to +850 C for the conditions described in the table thermal conduction and mechanical strength. Also,
of Figure 22. mounting holes for low power devices may be
The designer may want to use MECL III under counter sunk to allow the package bottom to contact
conditions that vary from those given. The main the heat plane. This technique used along with
restriction facing the designer is that a few high power thermal paste will provide good thermal conduction.
dual in·line parts' dissipating typically 900 mW under Printed channeling is a useful technique for con-
load require heat sinking to assure a 0 JA .;;; 350 C/W duction of heat away from the MECL dual in-line
which will keep iunction temperature below 1100 C. package when the device is soldered into a printed
The .Iow-power dual in-line parts may be used circuit board. As illustrated in Figure 23, this heat
without air and with higher 8JA. However, the dissipation method could also serve as VEE voltage
designer must bear in mind that junction tempera- distribution or as a ground bus. The channels should
tures will be higher for higher 8 JA, even though the terminate into channel strips at each side or the rear
ambient temperature is the same. Higher junction of a plug-in type printed circuit board. The heat can
temperatures will cause logic levels to shift. then be removed from the circuit board, or board
As an example, a 450 mW device operated at 8 JA slide rack, by means of wipers that come into thermal
= BO°CIW shows a HIGH logic level shift of about contact with the edge channels.
17.5 mV above the HIGH logic level when operated
with a 8JA = 50°CIW (level shift = 6TJ X 1.3
mVtC).
If logic levels of individual devices shift by
different amounts (depending on PD and 8 JA). noise
margins are somewhat reduced. Therefore, the system
designer must layout his system bearing in mind that
the mounting procedures to be used should minimize
thermal effects on noise margin.
The following sections on package mounting and
thermal characteristics are intended to provide the
Top View
designer with sufficient information to insure good
noise margins and high reliability in MECL III system
use.
Spacing (Inchs,)
Ceramic Dual In-Line Package, Case 620 Cy Cz
Pac:kage Cx
MECL III low-power devices are specified with Ceramic 0.9 0.2 0.5
Dual-In-Line
OJA typically 50o CIW, and the high-power units (PD Flat 0.4 0.08 0.45
> 500 mW} with 8JA equal to 35°CIW maximum. To
aid the designer in using the "L" (ceramic dual in-line}
package, curves and data showing thermal character- Side View
istics of the package are provided in Figure 21.
The use of multi-layer printed circuit boards is
recommended to provide both a ground plane and a FIGURE 230 - TYPICAL MECL IIilMECL 10,000
CIRCUIT BOARD SPACING
good thermal path for heat dissipation. Also, a
mUlti-layer board allows the use of microstrip line
techniques to provide transmission line inter-
connections.
Two-sided printed circuit boards. may be used
where board dimensions and package count are small.
If possible, the VCC ground plane should face the
bottom of the package to form the thermal con-
duction plane. If signal lines must be placed on both
sides of the board, the VEE plane may be used as the
thermal plane, and at the same time may be used as a
pseudo ground plane. The pseudo ground plane
becomes the ac ground reference under the signal
lines placed on the same side as the VCC ground
plane (now on the opposite side of the board from
the packages). thus maintain ing a' microstrip signal
FIGURE 23b - CHANNEL/WIPER HEAT SINKING ON
line environment. DOUBLE LAYER BOARD USED WITH MECL III
Two-ounce copper board i.s recommended for
°i.e. MC1654. MC167B. MC1694, etc.

1-25
 For the high-power devices requiring (}JA of
less than 350 C/W, a suitable heat sink is the
IERC-LlC-214A2WCB shown in Figure 24. The heat
sink should have a minimum of 500 Ifpm blown air
or be mounted directly on the copper ground plane
(using silicone paste) if used in still air, to meet the
350 C/W maximum rating. (See IERC Data Sheet for
lIC-214A2WCB.) The heat sink shown allows easy
access to the dual in·line IC pins for connection to
Microstrip line.

Air Flow
The majority of MECl III users employ some
form of air-flow cooling. As air passes over each
device on a printed circuit board, it absorbs heat from
each package. This heat gradient from the first
package to the last package is a function of the air
flow rate and individual package dissipations. Figure
25 provides gradient data at power levels of 200 mW.
250 mW, 300 mW, and 400 mW with an air flow rate
of 500 Ifpm. These figures show the proportionate
increase in the junction temperature of each dual
in-line package as the air passes over each device. For
higher rates of air flow the change in junction
temperature from package to package down the air
stream will be lower due to greater cooling.
(For further discussion of Thermal Management in
MECl systems, see MECl System Design Handbook,
Ch.6.)
FIGURE 24 - MECL III HIGH-POWER DUAL IN-LINE
PACKAGE MOUNTING (With Heat Sink, in 500 Ifpm of Airl

COMPATIBILITY AMONG MECL FAMILIES

Power Dissipation Junction Temperature Gradient
(mWI (OC/Package I MECL circuits are designed to interface with each
200 0.4 other over a power supply voltage range of ±10%
250 0.5 from the nominal -5.2 V without loss of noise margin
300 0.63 (other than that due to reduced signal swing at low
400 0.88
voltage). However, if two circuits are at different
Devices mounted on 0.062" PC board with Z aXIs spacing of
0.5". Air flow is 500 'fpm along the Z axis. supply voltages or on the same power supply with a
FIGURE 25 - THERMAL GRADIENT OF
voltage offset between circuits, there will be a
JUNCTION TEMPERATURE predictable loss of noise margin.
U6-Pin MECL Dual In·Line Packagel The MECL 10,000 logic family was designed to be
directly level compatible with the MECL III logic
family in dual in-line packages. The MECL II family
MECL II' MECL 10.000
has somewhat higher output levels but is compatible

~
6n orMECLII'
with the faster MECl 10,000 and MECL III inputs
when MECL II is loaded with the resistor pair, shown
1.5 k
in Figure 26. The resistor combination insures full
MECL 10000 VEE noise margin in the logic LOW level. An alternate
or MECL "' MECL II approach is to use a single 510 ohm resistor to VEE

~
on the MECl II output, but some loss of noise margin
takes place. Conversely, lightly loading the MECL
10,000 or MECL III outputs with a 1.5 kD resistor
• no internal 1.5 kn pulldown resistor
raises the output logic levels to meet MECL II
requirements. MECL II will operate directly with
FIGURE 26 - INTERFACING MECL II TO
MECL 10,000 and MECL III, but there is a loss of
MECL III OR MECL 10,000 noise margin (at the interface point only).

'-26
INTERFACING MECL to SLOWER LOGIC TYPES

~
MECL circuits are interfaceable with most other
logic forms. For MECLlMTTLlMDTL interfaces, when
MECL is operated at the recommended -5.2 volts and
·5.2 V (a)
TTL/DTL at +5 V supply, currently available trans-
lator circuits, such as MC10124 and MC10125, may

~
be used.
For systems where a dual supply (-5.2 V and + 5
V) is not practical, a discrete-component translator
can be designed. For details, see MECL System ·2.0 V (b)

Design Handbook, Ch. 8. Such circuits can easily be

~
made fast enough for any available TTL.
MECL also interfaces readily with MOS. With
Rp
CMOS operating at +5 V, any of the MECL to TTL
translators works very well. On the other hand, ·5.2 V (c)
CMOS will drive MECL directly when using a FIGURE 27 - PULL-DOWN RESISTOR TECHNIQUES
common -5.2 V supply. P-channel MOS, operating
with a negative supply, requires simple translators to
power and load requirements (see MECL System
equalize the differing logic levels.
Design Handbook, Ch. 3). Power may be saved by
Specific circuitry for use in interfacing MECL
connecting pull-down resistors in the range of 50
families to other logic types is given in detail in
ohms (100 ohm minimum for MC10,500 and
Chapter 8 of the MECL System Design Handbook.
MC10,600 Series parts) to 150 ohms, to -2.0 Vdc, as
Complex MECL 10,000 functions are presently shown in Figure 27(b). Use of a series damping
available to interface MECL 10,000 with MOS resistor, Figure 27(c), will extend permissible lengths
logic, MOS memories, TTL tri-state circuits, and
of unmatched-impedance interconnections, with
IBM bus logic levels.
some loss of edge speed.
CIRCUIT INTERCONNECTIONS With proper choice of the series damping resistor,
line lengths can be extended to any length', while
Though not necessarily essential, the use of multi-
limiting overshoot and undershoot to a predeter-
layer printed circuit boards offers a number of
mined amount. Damping resistors usually range in
advantages in the development of high-speed logic
value from 10 ohms to 150 ohms, depending on the
cards. Not only do multi-layer boards achieve a much
line length, fanout, and impedance. The open emitter-
higher package density, interconnecting leads are kept
follower outputs of MECL III and MECL 10,000 give
shorter, thus minimizing propagation delay between
the system designer all possible line driving options.
packages. This is particularly beneficial with MECL
III which has relatively fast (1 ns) rise and fall times.
Moreover, the unbroken ground planes made possible I----tpd - - - - - l

with multi-layer boards permit much more precise

B
control of transmission line impedances when these
are used for interconnecting purposes. Thus multi-
layer boards are recommended for MECL III layouts
and are justified when operating MECL 10,000 at top
circuit speed, when high-density packaging is a
requirement, or when transmission line interconnects
are used.
Point-to-point back-plane wiring without matched
line terminations may be employed for MECL inter-
FIGURE 29. - PARALLEL TERMINATED LINE
connections if line runs are kept short. At MECL II
speeds, this applies to line runs up to 12 inches, for

~r=:) Rlf.~D-
MECL 10,000 up to 8 inches, and for MECL III up to
1 inch (maximum open wire lengths for less than 100
mV undershoot!. But, because of the open-emitter =::J--)
outputs of MECL 10,000 and MECL III circuits, Zo
R2
pull-down resistors are always required. Several ways
of connecting such pull-down resistors are shown in ·5.2 V
Figure 27.
fiGURE 29b - PARALLEL TERMINATION -
Resistor values for the connection in Figure 27 (a)
THEVENIN eQUIVALENT
may range from 270 ohms to 2 kn depending on • Limited only by line attenuation and
bandwidth characteristics.

1-27
 ~:t--c;= Ap
l VEE
c "':+-r'L~-_-_-_-_~-_-_"i______.J 50%
FIGURE 30 - SERIES TERMINATED LINE
One major advantage of MECL over saturated
logic is its capability for driving matched-impedance
transmission lines. Use of transmission lines retains
signal integrity over long distances. The MECL III and
MECL 10,000 emitter·follower output transistors will
drive a 50·ohm transmission line (100 ohms or greater
for MECL 10,500 and MC10,BOO Series) terminated
to ·2.0 Vdc. This is the equivalent current load of 22
mA in the HIGH logic state and B mA in the LOW
state.
Parallel termination of transmission lines can be
done in two ways. One, as shown in Figure 28(a),
uses a single resistor whose value is equal to the
impedance (Zo) of the line. A terminating voltage
(VTT) of ·2.0 Vdc must be supplied to the
terminating resistor.
Another method of parallel termination uses a pair
of resistors, Rl and R2. Figure 28(b) illustrates this
method. The following two equations are used to
calculate the values of R 1 and R2:
Rl = 1.B Zo
R2=Rl'Zo
Rl + Zo
Another popular approach is the series·termi nated
transmission line (see Figure 29). This differs from
parallel termination in that only one·half the logic
swing is propagated through the lines. The logic swing
doubles at the end of the transmission line due to
reflection on an open line, again establishing a full
logic swing.
To maintain clean wave fronts, the input im·
pedance of the driven gate must be much greater than
the characteristic impedance of the transmission line.
This condition is satisfied by MECL circuits which
have high impedance inputs. Using the appropriate
terminating resistor (RS) at point A (Figure 29), the
reflections in the transmission line will be terminated.
The advantages of series termination include ease
of driving multiple series·terminated lines, low power
consumption, and low cross·talk between adjacent
lines. The disadvantage of this system is that loads
may not be distributed along the transmission line
due to the one·half logic swing present at inter·
mediate points.
'-28
FIGURE 31 - TWISTED PAIR LINE DRIVER/RECEIVER
For board to board interconnections, coaxial cable
may be used for signal conductors. The termination
techniques just discussed also apply when using coax.
Coaxial cable has the advantages of good noise
immunity and low attenuation at higR frequencies.
No significant performance degradation occurs for
lengths up to 20 feet for MECL III, and up to 50 feet
for MECL 10,000.
Twisted pair lines are one of the most popular
methods of interconnecting cards or panels. MECL
complementary outputs are connected to one end of
the twisted-pair line, and a differential line receiver to
the other as shown in Figure 30. RT is used to
terminate the twisted pair line. The 1 to 1.5 V
common-mode noise rejection of the line receiver
ignores common·mode cross-talk, permitting multiple
twisted pair lines to be tied into cables. MECL signals
may be sent very long distances (> 1000 feet) on
twisted pair, although line attenuation will limit
bandwidth, degrading edge speeds when long line runs
are made.
-D ~ <r-----~::::
rAp Card C
?---EI:=::=}----r_- Card A
. . . r_+_-
Zo
'--~=~=}-- Card B
Zo
~-c::===}-""""f__t_i~-C8I'd c
Zo
*Multiple output gate eg MC10110 VTT
FIGURE 32 - PARALLEL FAN·OUT TECHNIQUES
If timing is critical, parallel signal paths (shown in
Figure 31) should be used when fanout to several
cards is required. This will eliminate distortion caused
by long stub lengths off a signal path.
Wirewrapped connections can be used with both
MECL II and MECL 10,000. For MECL III, the fast
edge speeds (1 ns) create ~ mismatch at the wirewrap
 Refer to MECL System Design Handbook, Ch. 3
for a full discussion of the properties and use of these
lines.

FIGURE 32 - PC INTERCONNECTION
LINES FOR USE WITH MECL
connections which can cause reflections, thus reducing
noise immunity. The mismatch occurs also with
MECL II and MECL 10,000, but the distance between
the wire·wrap connection and the end of the line is
generally short enough so the reflections cause no
problem.
Series damping resistors may be used with wire·
wrapped lines for both MECL II and MECL 10,000 to
extend permissible backplane wiring lengths. Twisted
pair lines may be used for even longer distances across
large wirewrapped cards. The twisted pair gives a
CLOCK DISTRIBUTION
Clock distribution can be a system problem. Where
large high-speed clock networks are required, a
balanced twisted-pair line is recommended for clock
distribution. A gate such as the MC100l/MC1201,
together with the MC1020/MC1220 Quad Line
Receiver make an excellent combination for distri-
buting the clocking throughout a system. (See the
MC1020/MC1220 data sheet for further detail.) This
method allows control of clock skew time and offers
1.0 V, or better, noise immunity regardless of line
length.
At MECL 10,000 speeds, either coaxial cable or
twisted-pair line (using the MC10l0l and MC10115)
can be used to distribute clock signals throughout a
system. Clock line lengths should be controlled and
matched when timing could be critical. Once the
clocking signals arrive on card, a tree distribution
should be used for large-fan outs at high frequency.
An example of the application of this technique is
shown in Figure 33.
Fan-Out = 4 Each

more defined characteristic impedance (than a single

wire), and can be connected either single-ended, or
differentially using a line receiver.
The recommended wirewrapped circuit cards have
a ground plane on one side and a voltage plane on the
other, to insure a good ground and a stable voltage Off
source for the circuits. In addition, the ground plane Card

near the wirewrapped Iines lowers the impedance of

those lines and facilitates terminating the line.
Finally, the ground plane serves to minimize crosstalk
between parallel paths in the signal lines. Point-to-
point wire routing is recommended because crosstalk
will be minimized and line lengths will be shortest.
Commercial wire-wrap boards designed for MECL
10,000 are available from Augat Inc.

Microstrip and Stripline

Microstrip and stripline techniques are used with
printed circuit boards to form transmission lines.
Microstrip consists of a constant-width conductor on
one side of a circuit board, With a ground plane on
the other side (shown in Figure 32.) The char·
acteristic impedance is determined by the width and
thickness of the conductor, the thickness of the
circuit board, and the dielectric constant of the
circuit board material.
Stripline is used with multilayer circuit boards as
shown in Figure 32. Stripline consists of a constant-
width conductor between two ground planes. FIGURE 33 - 64 FANOUT CLOCK OISTRIBUTION

'-29
 Because of the very high clock rates encountered
in MECL III systems, rules for clocking are more
rigorous than in slower systems.
The following guidelines should be followed for
best results:
A. On-card Synchronous Clock Distribution via
Transmission Line
1. Use the NOR output in developing clock chains
or trees. Do not mix OR and NOR outputs in
the chain.
2. Use balanced fanouts on the clock drivers.
3. Overshoot can be reduced by using two parallel
drive lines in place of one drive line with twice
the lumped load.
4. To minimize clock skewing problems on
synchronous sections of the system, line delays
should be matched to within 1 ns.
5. Parallel drive gates should be used when
clocking repetition rates are high, or when high
capacitance loads occur. The bandwidth of a
MECL III gate may be extended by paralleling
both halves of a dual gate. Approximately 40 or
50 MHz bandwidth can be gained by paralleling
two or three clock driver gates.
6. Fanout limits should be applied to clock
distribution drivers. Four to six loads should be
the maximum load per driver for best high
speed performance. Avoid large lumped loads at
the end of lines greater than 3 inches. A lumped
load, if used, should be four or fewer loads.
7. For Wire-OR (emitter dotting), two-way lines (a
A' B
... : - A I B + C t D
A7"B,CIO
c
D C'D
FIGURE 34a - USE OF WIRE-OR AND
COMPLEMENTARY OUTPUTS
Family Number **
MECL II" 15
MECL 10,000 10
MECL III 6
"Devices without Internal pull-down resistors.
.. *DC limiting case; not AC recommended.
FIGURE 34b - RECOMMENDED MAXIMUM
NUMBER OF GATES TO BE WIRE-ORed
'-30
bus) are recommended. To produce such lines,
both ends of a transmission line are terminated
with l00-ohms impedance. This method should
be used when Wire-OR connections exceed 1
inch apart on a drive line.
B. Off-Card Clock Distribution
1. The OR/NOR outputs of an MC1660 may be
used to drive into twisted pair lines or into flat,
fixed-impedance ribbon cable. At the far end of
the twisted pair an MC1692 differential line
receiver is used. The line should be terminated
with two Zo/2 ohm resistors as shown in Figure
31. This method not only provides high speed,
board-to-board clock distribution, but also
provides system noise margin advantages. Since
the line receiver operates independently of the
VBB reference voltage (differential inputs) the
noise margin from board to board is also
independent of temperature differentials.
2. MECL III clock distribution to MECL II logic
elements can be done one of two ways:
a. Use the 0 R/NOR outputs or Q/G outputs to
drive the twisted pair as previously dis-
cussed. Receive differentially with the
MECL " line receivers (MC1D2D, MC1D35,
or MC1066).
b. Use any MECL III single-rail output to drive
MECL II logic, but lightly load the MECL III
element (1.5 kn to -5.2 volts) and maintain
the interface lead length under 1 inch total
(see Figure 26).
Channel A Channel B
• Matched 50-ohm coax
•• 0.' IJ,F -decouples fixture
• • • 25 J..I.F -dampens supply
var iations
·Coax
+2.0 V -3.2 V
Vee VEE
FIGURE 35 - MECL TEST SETUP
LOGIC SHORTCUTS
MECL circuitry offers several logic design con-
veniences. Among these are:
1. Wire·OR (can be produced by wiring MECL
output emittc~s together outside packages).
2. Complementary Logic Outputs (both OR and
NOR are brought out to package pins in most cases).
An example of the use of these two features to
reduce gate and package count is shown in Figure 34a.
The connection shown saves fOllr 2-input gates and
two inverters over non-ECl type logic designs.
Wire-ORing also permits direct connection of MECl
gates to busses (MECl System Design Handbook, Ch.
4).
Propagation delay is increased approximately 50
ps per wire-OR gate. The table in Figure 34b lists
maximum numbers of gates possible for wire-OR
without materially affecting system performance.
The use of a single output pulldown resistor is
recommended per wired-OR, to economize on power
dissipation. However, the use of two pulldown
resistors per wired-OR can improve fall times and be
used for double termination or busses.
Wire-OR should be done between gates on the
same board, but the output of wire-OR
combination may go off board. Short on-card inter-
connects are recommended.
TESTING MECl 10,000 and MECL III
To obtain results correlating with Motorola circuit
specifications certain test techniques must be used. A
schematic of a typical gate test circuit is shown in
Figure 35.
A solid ground plane is used in the test set up, and
capacitors bypass VCC1, VCC2, and VEE pins to
ground. All power leads and signal leads are kept as
short as possible.
The sampling 'scope interface runs directly to the
50-ohm inputs of Channel A and B via 50-ohm
coaxial cable. Equal-length coaxial cables must be
used between the test set and the A and B 'scope
inputs. A 50-ohm coax cable such as RG 58/U or
RG188A/U, is recommended.
Interconnect fittings should be 50 ohm GR, BNC,
Sealectro Conhex, or equivalent.
The pulse generator must be capable of 2.0 ns rise
and fall timesforMECl 10,000 and 1.5nsforMECl
III. In addition, the generator voltage must have an
offset to give MECl signal swings of ±400 mV about
a threshold of +0.7 V when VCC = +2.0 V and VEE =
-3.2 V. (T A = 25°C.)
The power supplies are shifted +2.0 V, so that the
device under test has only one resistor value to load
into - the precision 50-ohm input impedance of the
sampling oscilloscope. Use of this technique yields a
close correlation between Motorola and customer
testing. The positive supply (VCC) should be de-
coupled from the test board by R.F. type 25 j.LF
capacitors to ground. The VCC pins are bypassed to
ground with 0.1 j.LF, as is the VEE pin.

SYSTEM CONSIDERATIONS, A SUMMARY OF RECOMMENDATIONS

MECL II MECL 10,000 MECL III

Power Supply Regulation 10% or better 10% or better 10% or better
On-Card Temperature Gradient Less Than 25°C Less Than 25°C Less Than 25°C
Maximum Non-Transmission Line 12" 8" I"
Length INo Damping Resistor)
Unused Inputs Connect to VEE' Leave Open Leave Open
PC Board Standard 2-Sided or Standard 2-Side<J or Multilayer
Multilayer Multilayer
Special Cooling Requirements No No No
Bus Connection Yes Yes Yes
Capability (Wire·OR) (Wire·OR) (Wire-OR)
MSI/LSI Parts Yes Yes Yes (MSI)
Maximum Twisted Pair Length Limited by Cable Response Limited by Cable Response Limited by Cable Response
(Differential Drive) Only,. Usually> 1000' Only, Usually> 1000' Only, Usually> 1000'
The Ground Plane to Occupy >25% >50% >75%
Percent Area of Card
Wirewrap may be used Yes Yes Not recommended
Compatible with MECL 10,000 With proper I ntertace - Yes

*Some devices may not be connected to VEE; see specific data sheet Information.

1-31
 PACKAGE OUTLINE DIMENSIONS

A letter suffix to the MECL logic function part number is used to specify the package style (see drawings below).
See appropriate selector guide for specific packaging available for a given device type.

F SUFFIX L SUFFIX
CERAMIC PACKAGE CERAMIC PACKAGE
CASE 607·04 CASE 620

MILLIMETERS INCHES
Mil IMETERS DIM MI. MA' MIN MA.
DIM ...... MAlt NOTES:
A 19.05 19.81 Q.150 0.780
A
C
D
f
S.10 S.!!!
076
0.250.41
0.08 015
203
•
C
6.22
4.116
6.98
.111
0.245 0.215
0.160 0._
1 lEADS WITHIN 0.13 mm (O.DOS) RADIUS
OF TAUE POSITION AT SEATING PLANE
2 AT MAXIMUM MATERIAL CONDITION'
0 0.38 0.51 0.015 0.020
Ii

..
1 2165C
013 089
, ''"
•
G
1.40 1.85
2.54 ISC
o.os. 0....
o.l00RSC
PKG. INDEX: NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT'
3 DIM "t" TO CENTER OF LEADS
H 0.51 1.14 0.020 0.045
181(1 J 0.20 0.30 0.008 0.012 WHEN FORMED PARALLEL'
O.2!'!
K 3.18 4.06 0.125 0.160
1.62 OJOO 0 L 1.31 7.87 0.31
- ",
M
• 0.51 '"
1.02 0.020 0.040

L SUFFIX
L SUFFIX
CERAMIC PACKAGE
CERAMIC PACKAGE
CASE 632-02
CASE 623

.
~ .~
1 ~
-1l-oJ f

r- A-L.l [L
~-1c

DIM
M lIMET RS
MI. MU .,. INCME
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L 7.62 SSC
PARALLEl. M 15"
2. LEADS WITHIN 0.13 mm M 0.51 0.76
(0.005) RADIUS OF TRUE P 8.25
POSITION AT SEATING
PLANE AT MAXIMUM NOTE, OIMENSION "L" TO CENTER OF
MATERIAL CONDITION.
(WHEN fORMED PARALLEL) LEAOS WHEN FO RMED PARALLEL.

'-32
 PSUFFIX PSUFFIX
PLASTIC PACKAGE PLASTIC PACKAGE
CASE 646 CASE 649

MllllMETlRS iNCHt$
DIM MIN MAX MI' MAX NOTES
1 LlAOSWITHINO 13mm
A 18.16 18.80 0.715 0740
•
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610
4.06
660
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CASE 690·05
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 1S.80 19.23 0.740 0.757
C 2.79 3.S1 0.110 0.150
0 0.41 0.51 0.016 0.020
F 1.14 1.52 0.04 .06(1
G 2.54 sse O.IIM sse
H 0.33 0.S9 0.013 0.035
J 0.20 0.30 0.008 0.012
K 3.56 4.06 0.140 0.160
L 762 sse 0.300 sse
M 10" 10'
N 0.76 1.14 0.030 0.045
NOTES.
I. LEADSWITHtN 0.13 mm !0.0051 RAOIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION.

1-33
 SECTION V - MECL LITERATURE
Application Note Abstracts
AN-417A
"ICCrystal Controlled Oscillators"
Crystal controlled square wave oscillators can be used
as clock drivers, harmonic sources for frequency
markers, in frequency synthesizers, frequency com-
parators, etc_ It is difficult to obtain high frequency
square waves due to the long propagation delays of
most integrated circuits_ MECL 10,000 circuits with 2
ns propagation delays eliminate this problem_ This
note describes square wave oscillator circuits with
crystal control that are capable of output frequencies,
inverted and non-inverted, up to 200 MHz_
AN-418
"High Speed Monostable Multivibrators
Design with MECL Integrated Circuits"
This note describes two configurations of monostable
multivibrators using the MC1023 clock driver and a
delay element_ Operating frequencies in excess of 70
MHz and pulse widths of 4 nanoseconds are possible.
Methods of obtaining the predetermined delay are
also discussed.
AN-487
"A High-Speed Ripple-Through
Arithmetic Processor"
A simple, systematic building block approach for
designing a high-speed, ripple-through arithmetic
processor is described. Using only gates and full
adders, ultra-high speed multiplication, division,
square root extraction, addition, and subtraction may
be performed. Several variations of an arithmetic
processor design are detailed and comparisons of
speed and package count using the MECL and MDTL
logic in l4-pin, l6-pin, 24-pin, 32-pin, and 64-pin
packages are given.
AN-488
"High-Speed Addition
Using Lookahead Carry Techniques"
The use of the lookahead carry principle to increase
the operating speed of adder systems is described.
Several adders of different sizes using variations of
lookahead carry are developed and the logical
implementation of these using the MTTL III and
MECL II logic families is given.
AN-496-A
"Error Detection and Correction
Using Exclusive-OR Gates and Parity Trees"
The availability of Exclusive-OR gates and parity
trees allows digital system designers to use error
detection and correction codes to improve their
system reliability and maintainability without the
major cost penalty that has existed in the past. Use of
1-34
(Application notes are available from Motorola Inc.
at P.O. Box 20924, Phoenix, Arizona 85036)
Exclusive-OR gates and parity trees available in the
MRTL, MTTL, MOTL, and MECL families to design
simple parity and single error Hamming parity detec-
tion and correction circuits is discussed.
AN-504
"The MC1600 Series MECl III Gates"
This application note explains the basic operation of
the various gates available in the MECL III logic
family. Typical operating characteristics are included
as an aid to the designer of high-speed logic along
with recommended layout, breadboarding, and test-
ing procedures. This note will also provide the
designer with some insight into the overall capabilities
of this logic line as they apply to this application.
AN-532-A
"MTTL and MECl
Avionics Digital Frequency Synthesizer"
This application note discusses several approaches
that illustrate applications of complex digital inte-
grated circuits directed toward avionics frequency
synthesizers. The techniques presented point out the
simpliCity with which both MTTL and MECL digital
integrated circuits can be used to produce frequency
synthesis for avionic communications.
AN-534
"Com mutating Filter Techniques"
This note describes the design and construction of
commutating (digital) filters using Motorola MECL II,
MTTl III and MC7400 digital integrated circuits. A
short section on commuting filter theory is included
along with examples of filters and their responses.
AN-536
"Micro-T Packaged Transistors
for High Speed logic Systems"
Integrated circuits have become the first thought of
most designers faced with a digital problem. For
specialized needs such as extremely high speed, high
speed with minimum power dissipation, or unusual
logic functions, however, discrete transistors in the
ultra-small Micro-T package may prove advantageous.
AN-553
"A New Generation of
. Integrated Avionic Synthesizers"
The need to generate signals of a multitude of
different frequencies for avionic systems has resulted
in complex solutions in the past. With the introduc-
tion of certain standard product integrated circuits,
frequency synthesis using digital phase locked loop
techniques presents a more practical solution. Several
different types of servo phase locked loop systems are

APPLICATION NOTE ABSTRACTS(continuedl
discussed and a practical design example is given.
Results of design examples are presented along with
possible applications.
AN-556
"Interconnection Techniques
for Motorola's MECl 10,000 Series ECl"
This application note describes some of the charac-
teristics of high speed digital signal lines and gives
wiring rules for MECl 10,000 emitter coupled logic.
The note includes discussions of printed circuit board
interconnects, board-to-board interconnects, and
wirewrapping techniques.
AN-565
"Using Shift Registers
as Pulse Delay Networks"
This note discusses a high-speed clocked shift register
using MECl 10,000 flip-flops and employed as a
digitial incremental delay. The register may be
clocked with a frequency division counter to accom·
plish delay with increments as small as 7.5 ns. The
circuit, as developed, may be used for timing basic
computer decisions or as an adjustable digital delay
fine for pulses.
AN-566
"High Speed Binary Multiplication
Using the MC10181"
With a MECl 4-bit arithmetic unit you can reduce
both package count and interconnections in a ripple
multiplier and achieve very fast multiply times.
AN-567
"MECl Positive and Negative logic"
Either positive or negative logic assignments may
prove convenient to the MECl system designer. This
note describes the equivalences between the two
approaches and providing guides for converting
between them.
AN-579
"Testing MECl 10,000
Integrated logic Circuits"
Circuit testing techniques become increasingly im-
portant as circuit speeds approach and exceed the 2
ns range. With MECl 10,000 and MECl III circuits it
is possible to exploit their 50-ohm output drive
capability to obtain highly accurate test data. This
application note describes techniques for testing
MECl 10,000 circuits for laboratory evaluation, and
discusses key parameters which should be measured
during incoming inspection rapid testing_
'-35
(Application notes are available from Motorola Inc.
at P.O. Box 20924, Phoenix, Arizona 85036)
AN-581
"An MSI 500 MHz Frequency
Counter Using MECl & MTTl"
The design of an MSI a-digit lED readout 500 MHz
counter using MECl III, MECl 10,000 and TTL is
discussed. Described are two prescalers using MECl,
along with the designs for two input amplifiers. A
unique time-base controller is also shown for
providing a multiphase clock to the counter.
AN-583
"A MECl 10,000 Main Frame
Memory System Employing Dynamic
MMOS RAMS"
Thi.s application note describes the construction of a
dynamic MOS random access memory system that
employs MECl 10,000 for the memory control logic.
Considered in detail are the memory organization,
layout rules, interfacing, and generation of the
needed control signals.
AN-584
"Programmable Counters Using the
MC10136 and MC10137 MECl 10,000
Universal Counters"
This application note describes operation of two
MECl 10,000 Universal counters, and their use in
high speed programmable counters. Circu it diagrams
and waveform traces are included.
AN-592
"AC Noise Immunity of MECl 10,000
Integrated Circuits"
This application note discusses ac noise immunity as
it relates to MECl systems. Test circuits for measuring
ac noise immunity are shown, and results to be
expected for typical MECl 10,000 circuits are
presented.
AN-700
"Simulate MECl System Interconnections
With A Computer Program
Circuit interconnections are an important part of
system design when using high speed logic circuits.
The design of interconnecting paths affects both sys-
tem speed and system accuracy. This application note
describes the use of a computer program to simulate
interconnections for high speed digital systems.
AN-701
'-Understanding MECl 10,000 DC and AC
Data Sheet Specifications"
The dc and ac specifications for emitter-coupled logic
are somewhat different than those for saturated logic.
This application note describes the specifications
found on a MECl 10,000 data sheet and provides
information for understanding these specifications for
persons unfamiliar with emitter-coupled logic.
 (Application notes are available from Motorola
APPLICATION NOTE ABSTRACTS (continued)
at P.O. 60·x 20924, Phoenix, Arizona 85036)

AN-709
"MECL 10,000 Arithmetic Elements
MC10179, MC10180, MC10181"
The MECL 10,000 arithmetic functions include a
4-bit arithmetic unit, a dual adder/subtractor, and a
lookahead carry block. This application note describes
the devices and shows their operation in large system
configurations.

AN-720
"Interfacing With MECL 10,000"
This article describes some of the MECL circuits used
to interface with signals not meeting MEGL input or
output requirements. The characteristics of these cir-
cuits such as; input impedance, output drive, gain,
and bandwidth allow the system designer to use these
parts to optimize his system. MEGL interface circuits
overcome a problem area of many system designs,
which is the efficient coupling on non-compati-
ble signals.

AN-726
"Bussing With MECL 10,000
Integrated Circuits"
High speed data bus lines are an important part of
modern computer systems. Features of the MEG L
10,000 family allow construction of data busses in a
transmission line environment. This application note
describes some of the guidelines to consider when
designing high speed bus lines and shows how the
MG10123 can be used for maximum bus performance.

1-36
SUPPLEMENTARY LITERATURE
1. "The Case for Emitter·Coupled Logic," by
Anthony A. Vacca, ELECTRONICS, April 26,
1971.
2. "Low Power ECL Bids for TTL Applications,"
by Ed Tynan, ELECTRONIC PRODUCTS, May
17,1971.
3. "High·Speed Translators Simplify ECL/TTL
Interface ," by Bill Blood, COMPUTER
HARDWARE, July 15, 1971.
4. "Speedup in ECL," by John Rhea,
ELECTRONIC NEWS, September 13,1971.
5. "Generate Stable High·Frequency Signals With
Digital Mixers and Phase Locked Loops," by R.
Treadway and l. J. Reed, ELECTRONIC
DESIGN, January 6, 1972.
6. "ECL vs. Schottky," Special Report by John
Rhea, ELECTRONIC NEWS, March 13, 1972.
7. "ECL Gates Stretch Oscillator Range," by W.
Blood, ELECTRONICS, March 13, 1972.
B. "ECL - Who's Leading the Band?" by Sheldon
Edelman, THE ELECTRONIC ENGINEER,
April 1972.
9. "ECL Arithmetic Unit Performs High·Speed
Binary Multiplication," by Tom Balph, EDN,
May 1, 1972.
10. "Measure Frequency and Propagation Delay with
High Speed ECL Circuits," by William R. Blood,
Jr., EDN, July 1, 1972.
11. "Use ECL 10,000 Layout Rules to Help Solve PC
Board I nterconnections, Part I," by Tom Balph,
ELECTRONIC DESIGN, August 17, 1972.
12. ibid, Part II, ELECTRONIC DESIGN, September
2,1972.
13. "ECL/MOS for Optimum Minicomputer
Systems," by P. Breedlove, COMPUTER
DESIGN, August 1972.
14. "Testing MECL 10,000 - What it Takes to Get
High on Speed", by Bill Blood, ELECTRONIC
PRODUCTS, November 20, 1972.
'·37
15. "Boost Counting Speed to 110 MHz with ECL
Universal Counters", by Tom Balph and Howard
Gnauden, ELECTRONIC DESIGN, April 1, 1973.
16. "Digital Alphabet Spells Change in IC Usage" by
Ed Tynan, ELECTRONIC BUYERS NEWS,
October 2, 1972.
17. "ECL Shift Registers make Versatile Pulse Delay
Networks", by Jon DeLaune, EDN, October15,
1972.
lB. "Testing MECL 10,000 - What it Takes to Get
High on Speed," by Bill Blood, ELECTRONIC
PRODUCTS, November 20, 1972. (AN·579)
19. "Blend ECL and TTL ICs to Obtain High Fre·
quency Counter Circuits," by Jon DeLaune,
ELECTRONIC DESIGN, March 15, 1973, page
112.
20. "Leapfrog Ahead with Standard Family MSII
LSI," by Bob Cushman, Special Features Editor,
EDN, April 5, 1972, page 30.
21. "Positive versus Negative Logic," by Tom Balph,
Electronic Products Magazine, August 21, 1972.
22. "Improve Fast·Logic Designs," by Bill Blood,
Electronic Design, May 10, 1973.
23. "Use ECL for Your High·Speed Design - Part I,"
by lloyd Maul, EDN, July 20, 1973.
24. "ECL 10,000 Layout and Loading Rules -
Part II," by lloyd Maul, EDN, August 5, 1973.
25. "Interface TTL Systems With ECL Circuits," by
George Adams, EDN, September 5, 1973.
26. "MECL 10 K Reliability Evaluation," by Paul
Greer, Electronic Buyers' News, November 26,
1973.
27. "Make Sure Your Logic Keeps Pace With Mem·
ory Cycle Times" by Dick Brunner, EON,
January 20, 1973.
2B. "Increasing Minicomputer Speed With Emitter·
Coupled Logic" by Jon DeLaune, COMPUTER
DESIGN, February 1974.
Contents of the MECL SYSTEM DESIGN
HANDBOOK (206 pages):

CHAPTER 1 - MECL Families CHAPTER 6 - Thermal Considerations

The Basic MECL Gate MECL Integrated Circuit Heat Transfer
Noise Margin MECL DC Thermal Characteristics
MECL Circuit Types Heat Dissipation Techniques
MECL Flip-Flops Mounting Techniques
Operation of Flip-Flop
CHAPTER 7 - Transmission Line Theory
MECL Family Comparison
Transmission Line Design Information, With
Examples
CHAPTER 2 - Using MECL
Signal Propagation Delay for Microstrip and Strip
MECL II Design Rules
Lines With Distributed or Lumped Loads
A_ Logic Design Considerations
Microstrip Transmission Line Techniques,
B_ System Layout Considerations
Evaluated Using TOR Measurements, with
C_ Circuit Board Layout Techniques
Examples
D_ Backplane Wiring
The Effect of Loading on a Parallel-Terminated
E_ System Considerations
Transmission Line, With Examples
MECL 10,000 Design Rules Analysis: Series Terminated Lines Compared to
A_ General Considerations Parallel Terminated Lines, With Example
B_ Printed Circuit Card Layout Techniques Analysis of Series Damping Terminations
C_ Power Supply Bypassing on Circuit Cards Bibliography
D_ Backplane and Loading Considerations
E_ System Distribution and Grounding CHAPTER 8 - MECL Applications
F_ Loading Rules for MECL 10,000 Counters
MECL III Design Rules Shift Registers
A Circuit Card Layout Adders
B_ Transmission Line (Microstrip Line) Code Converters
C_ On-Card Clock Distribution via Transmission Memories
Lines Oscillators
0_ Off-Card Clock Distribution One-Shot Mu Itivibrators
E_ Testing MECL III Linear Applications
Translators
CHAPTER 3 - Printed Circuit Board Connections
Transmission Line Geometries CHAPTER 9 - AC Noise Immunity
Basic Transmission Line Operation Introduction
Unterminated Lines Test Circuits
Series Damped and Series Terminated Lines Test Conditions
Parallel Terminated Lines Test Results
Transmission Line Comparison Conclusions
Wirewrapped Cards CHAPTER 10 - MECL 10,000 For Military
Applications
CHAPTER 4 - System Interconnections Fanout
Connectors Termination and Interconnect Techniques
Coaxial Cable Power
Differential Twisted Pair Lines and Receivers Noise Margin
Ribbon Cable AC Performance
Schottky Diode Termination
Parallel Wire Cables APPENDIX I - MECL Hardware and Components
Twisted Pair Cable, Driven Single-Ended

CHAPTER 5 - Power Distribution

System Power Calculations
Power Supply Considerations
System Power Distribution
Motorola's MECL System Design Handbook may be
Backplane Power Distribution
purchased for $2.50 per copy. Copies may be obtained
On-Card Power Distribution by sending check or money order payable to Motorola
VTT Termination Voltage Distribution Inc., at P. D. Box 20924, Phoenix, Arizona 85036.

'-38
 INTEGRATED CIRCUITS
SELECTOR GUI DES

2-1
 INTEGRATED CIRCUITS
MC1000 Series (0 to +750
C)
MC1200 Series (-55 to +1250 C)

The MECL II series of monolithic integrated logic circuits presents the system FEATURES
design engineer with an integrated circuit family designed to permit system imple- • Propagation typically 4 ns
mentation with the fewest possible number of individual units. This approach offers per logic decision
cost savings, reduced power supply requirements, smaller physical size and high • Excellent noise immunity
reliability.
characteristics
MECL II circuits feature the fastest propagation delay times with commensurate • Simultaneous OR/NOR
rise and fall times of any family of integrated circuits. This feature plus the constant outputs
current feature of MECL imposes fewer restrictions on design, layout and system • High fan-in and fan-out
fabrication than any other high·speed family. capabi Iities
• Internally temperature
compensated

FSUFFIX
CERAMIC PACKAGE
CASE 1107 LSUFFIX
CERAMIC PACKAGE
CASE 832
LSUFFIX TO-ll11 PSUFFIX
CERAMIC PACKAGE PLASTIC PACKAGE
CASE 620 CASE 1148

F SUFFIX
- ."''"OX
PLASTIC PACKAGE
CASE 6411
CERAMIC PACKAGE
CASE 650

FUNCTIONS AND CHARACTERISTICS (VCC =0 VEE = -52 V TA = 25 0 CI

Loading Propo- Power
Factor gation Dissipation
Typo CD Each Dolay mW
Function -55 to +1250 C o to +75 0 C Output ns typ typ/pkg Caso

Single 6-lnput Gate, 3 OR Outputs w/Pulldowns MC1201F,L MC1001P 25 4.0 115 607,632,646
3 NOR Outputs w/Pulidowns
Dual4-lnput Gate, 2 OR Output's w/Pulidowns MCI204F.L MC1004P 25 4.0 95 607,632,646
2 NOR Outputs w/Pulidowns
Dual 4-1 nput Gate, 2 OR Outputs w/o Pulldowns MC1206F,L MC1D06P 25 4.0 45 607,632,646
2 NOR Outputs w/o Pulldowns
Triple 3·lnput Gate, 3 NOR Outputs w/Pulidowns MC1207F,L MC1007P 25 4.0 110 607,632,646
Quad 2-lnput Gate, 4 NOR Outputs w/Pulidowns MC1210F,L MC10l0P 25 4.5 115 607.632,646
Quad 2-lnput Gate, 2 NOR Outputs w/Pulldowns MC1211F,L MC10llP 25 4.5 95 607,632,646
2 NOR Outputs w/o Pulldowns
<D Type numbers With F suffiX use Case 607 or 650, Type numbers With L suffiX use Case 632 or 620 as Indicated.
Type numbers with P suffix use Case 646 or 648 as indicated.

2-3
~ rn ~ [1 00 LOGIC DIAGRAMS

FUNCTIONS AND CHARACTERISTICS (VCC = 0, VEE = -5.2 V, TA = 25 0 CI

loading Propa- Pow ..

Type <D Factor gat ion Dissipation
Each Dolay mW
Function -55 to + 125°C o to + 75°C Output nstyp typ/pkg ea..
Quad 2-lnput Gate, 4 NOR Outputs w/o Pulldowns MC1212F,L MC1Q12P 25 4.5 65 607, 632, 646
AC Coupled J-K Flip-Flop (85 MHz typ) MC1213F,L MC1Q13P 25 6.0 125 607, 632, 646
Dual R-S Flip-Flop (Positive Clock) MC1214F,L MC1014P 25 6.0 140 607, 632, 646
Dual R-S Flip-Flop (Negative Clock) MC1215F,L MC1015P 25 6.0 140 607, 632, 646
Dual A-S Flip-Flop (Single Rail) MC1216F,L MC1016P 25 6.0 140 607, 632, 646
Level Translator (Saturated Logic to MECL) MC1217F L MC1017P 251MECLI 15 105 607, 632, 646
Level Translator (MECL to Saturated Logic) MC1218F,L MC1018P 71DTLI 19 55 607, 632, 646
Full Adder MC1219F,L MC1019P 25 3.0 to 8.0·· 145 607, 632, 646
Quad Line Receiver MCl220F,L MC1020P 25 4.0 115 607, 632, 646
Full Subtractor MC1221F,L MC1021P 25 4.0 to 1,·· 145 607, 632, 646
Type 0 Flip-Flop MCl222F,L MC1022P 25 8.0 110 607, 632, 646
Dual 4-lnput OR/NOR Clock Driver MC1223F,L MC1023P 25 2.0 250 607, 632, 646
Dual 2-lnput Expandable Gate MC1224L 1'.1Cl024P 25 4.0 95 632,646
Dual 4 and 5-lnput Expander MCl225F,L MC1025P - - - 607, 632, 646
Dual 3-4-lnput Transmission Line and Clock Driver- MCl226F,L MC1026P 25 2.0 140 607, 632, 646
AC Coupled J·K Flip·Flop (120 MHz typ) MC1227F,L MC1027P 25 4.0 250 607, 632, 646
Dual 4-Channel Data Selector MC1228F ,L MC1028P 25 5.0 170 620, 648, 650
Quad Exclusive OR Gate MC1230F,L MC1030P 25 5.0 130 607,632,646
Quad Exclusive NOR Gate
100-MHz AC Coupled Dual J-K Flip-Flop . MC1231F,L
MC1232F ,L
MC1233F ,L
MC1031P
MC1032P
MC1033P
25
25
5.0
4.5
130
180
607, 632, 646
620,648, 650
Dual A-S Flip-Flop (Single Rail, Negative Clock) 25 6.0 140 607,632,,646
Type 0 Flip-Flop MC1234F,L MC1034P 25 4.0 185 607, 632, 646
Triple Line Receiver MC1235F,L MC1035P 25 5.0 140 607, 632, 646
16-Bit Coincident Msmory MC1236F,L MC1036P 5 17 250 607, 632, 646
16-Bit Coincident Memory w/o Pulldowns MC1237F,L MC1037P 5 17 250 607,632,646
Quad Level Translator (MECL to Saturated Logic) MC1239F ,L MC1039P 71DTLI 12 200 620, 648, 650
Quad Latch MC1240F,L MC1040P 25 8.0 250 607,632,646
Decoder - Display Driver MC1245F,L MC1045P - - 178 620, 648, 650
Quad 2-lnput AND Gates MC1247F,L MC1047P 25 5.0 130 607, 632, 646
Quad 2-lnput NAND Gates MC1248F,L MC1048P 25 5.0 130 607,632,646
Dual Full Adder MC1259F ,L MC1059P 25 9.0 375 620, 648, 650
Quad 2-lnput NOR Gate MC1262F ,L MC1062P 25 2.0 320 620, 648, 650
Quad 2-1 "put NO R Gate MC1263L MC1063P 25 2.0 320 632,646
Triple Line Receiver MC1266F,L MC1066P 25 2.0 350 607, 632, 646
Quad MTTL to MECL Translator With Strobe
Quad MECL to MTTL Translator
With Totem-Pole Outputs
. MC1267F ,L

MC1268F,L
MC1067P

MC1068P
1

10(MTTL)
5.0

5.0
300

340
620, 648, 650

620, 648, 650

Quad Latch MC1270F,L MC1070P 25 8.0 200 607, 632, 646

CD Type numbers with F suffix use Case 607 or 650, Type numbers with L suffix use Case 632 or 620 as indicated_
Type numbers with P suffix use Case 64~ 648 as indicated.
tNot recommended for new designs
-Noise Margin = 150 mV
- -Propagation delay time is dependent on data path, see data sheet for details.

2-4
 INTEGRATED CIRCUITS
MC1600 Series (-300 e to +85 0 C)

The requirement for digital systems with ever higher MECL III circuit design is similar to that used in the
performance has increased the need for high-speed inte- popular MECL 10,000 family. In the MECL III line, as
grated circuits_ The industry has recognized that the only well as MECL 10,000, advanced processing techniques are
economical way to obtain high operating system speed is employed and the capability for driving low-impedance
through the use of emitter-coupled logic_ Motorola offers terminated lines is provided. MECL III is recommended
a state-of-the-art, emitter-coupled logic family with sub- for new designs.
nanosecond propagation delays - MECL III.
GENERAL FEATURES
• Gate Switching Speeds of 1.0 ns typical
• Capability of Driving Terminated Lines with Impedance as Low as 50 Ohms
• Flip-Flop Toggle Rate Greater Than 500 MHz
• Operation with Unused Inputs Left Open
• Multilayer Metalization for economy
• New Packages with Improved Electrical and Thermal Characteristics
• Compatibility with MECL 10,000 Series
'SUFFIX L SUFFIX
• Counting Speeds to above 1 GHz PLASTIC PACKAGE CEFtAMIC PACKAGE
CASE 646 CASE 632

FUNCTIONS AND CHARACTERISTICS (VCC = 0 VEE

Function
PSUFFIX
PLASTIC PACKAGE
CASE 648

Type CD
-300 to +8s"C
=
CERAMIC PACKAGE

Loading Factor #
Each Output
CASE 6Q7

Prapogetion Dolay
5IH>hm Load
nstyp
-
-5 2V TA = 250 C unless otherwise noted)
Power Dissipation
(No Load)
mW
typfpkg
L SUFFIX
CERAMIC PACKAGE
CASE 6:Z0

Coso
Voltage Controlled Oscillator MC1648 - "225 MHz typ 150 607,632,646
Dual AID Comparator MC1650 70 3.5 275 620,650
Dual AID Comparator MC1651 70 3.0 275 620,650
Binary Counter MCI654 70 "325 MHz typ 750 LL/ 620
Voltage-Controlled Multivibrator MC1658 70 "150 MHz tvP 125 620,648,650
Dual4-lnput ORINOR Gate MCI660 70 1.1 120 620,650
Quad 2-1 nput NOR Gate MCI662 70 1.1 240 620,650
Quad 2-lnput OR Gate MCI664 70 1.1 240 620,650
Dual Clocked R-S Flip-Flop MCI666 70 1.8 220 620,650
Dual Clocked Latch MCI668 70 1.8 220 620,650
Mester-Slave Type D Flip-Flop MC1670 70 "350 MHz typ 220 620,650
Triple 2-1 nput Exclusive OR Gate MCI672 70 1.3 220 620,650
Triple 2-lnput Exclusive NOR Gete MC1674 70 1.3 220 620,650
Bi-Quinary Counter MC1678 70 "350 MHz tvP 750 L.LJ 620
Dual 4-5-lnput ORINOR Gate MC1688 70 0.8 125 650
UHF Pre",sler Type D Flip-Flop MC1690 70 -500 MHz min 200 620,650
Quad Line Receiver MC1692 70 1.1 220 620,650
4-8it Shift Register MC1694 70 "325 MHz typ 750 LL/ 620
1 GHz Divide-By-Ten Counter MC1696 - ·1 GHzmin 650 650

CD L suffix denotes Dual In-Line Ceramic Package, F suffix denotes Ceramic Flat Package, P suffix denotes Dual In-Line Plastic Package.
Ii.e., MCI600L = Ceramic Dual In-Line Package, MCI600F = Ceramic Flat Packege, MCI600P = Plastic Dual In-Line Package).
U-' Requires Heat Sink - IERC-LIC-214A2WCB or equivalent.
-Toggle Frequency
#DC Loading F actors are based on:
1. Full load output current, IL = -25 mAdc max
2. Maximum input current, lin = 350 "Adc

2-5
~ rn (S ~ DOD LOGIC DIAGRAMS

Numbers at ends of terminals denote pin numbers for L package (Case 620 unless noted
as Case 632) and P pecka99 (Case 646 unless noted as Case 648). CASE VCC VEE
Pin No. Pin No.
Numbers in parenthesis denote pin numbers for F package (Case 650 unless noted as Case 607).
650 4,5 12
620 1,16 8
See individual drawing
for devices withoth.rC .....

GATES------------------------------~----------~

MCl660 MC1662 MCl664

Dual 4-lnput ORINOR Gat. Quad 2-lnput NOR Gat. Quad 2-lnput OR Gat.

4~
.~ 4~
(81 (81 (81
5 B X 3 B 2 (61 (61
(91 (7J (91 5 (91 5 B 2
6 C y 2

~~3
(101 (61 (101
6~
(101
7 0 (71 01
(11 I (111 (111 7 3

(14110~ (141
10~ 14 (21
(141
10~ (21
(15111 14 (21 (151 11 (151 11 14
(161 12 15 (31 (161
12~ (31
(161
12~ 15 (31
(1113 (11 13 15 (11 13

----
= A+8+C+O
X
= A+B+C+O X
- -
A+B
Y = X = A+B

tpd '" 0.9 ns typ (SlO-ohm load) tpd == 0.9 ns typ (510-ohm load) tpd == 0.9 ns typ (S10-ohm load)
1.1 ns typ (50-ohm load) 1.1 ns typ (50-ohm load) 1.1 ns typ (50-ohm load)
Po == 120 mW typ/pkg (no loed) Po = 240 mW typ/pkg (no load) Po == 240 mW typ/pkg (no load)

MC1672 MC1674 MCl688

Triple 2·lnput Exclusive OR Gate Triple 2-lnput Exclusive NOR Gate DuaI4-5·lnput
ORINOR Gate

(81
(91

(16113~
3~2
5 B
(61
(81
(91
3
5 8
2
(61
(
(101
(111
81
(91
3=t= (71
(61

(16113~

""¥
14 (21 (101 6 8 14 (21
(101 6
(141
(141
11~ 15 (31
(141
11~
7 B 15 (31 (151
(21
(111 7 (111 (31
(161
X=AeS+AeB X=AeB+AeEi (11

tpd'" 1.1 ns typ 15l0-ohm load) tpd = 1.1 ns typ (510·ohm load) tpd = 0.8 ns tvp
"" 1.3 ns typ (50-ohm load) = 1.3 ns type (50-ohm load) Po = 125 mW tYP/pkg (No Load)
Po = 220 mW typ/pkg Po = 220 mW typ/pkg

2·6
LOGIC DIAGRAMS (continued)

FLiP-FlOPS------------------------.
MC1SSS MC1SS8
Dual Clocked R-S Flip-Flop Dual Clocked latch

(9) 5~a 2 (6) (::)) : g s :2 (6)

(11) 7 C
(8) 4 R a 3 (7) (111 7 C R a 3 (7)

(8) 4
(16)12~a 15(3)
(14)
(1113
9 C
R a 14(2) «116:):~gs
~ 15 (3)

(14) 9 C A a 14 (2)

(1) 13

tpd == 1.6 nstyp (5l0-ohm load)

== 1.8 ns typ (50-ohm load)
Po = 220 mW typ!pkg (no-load)
tpd == 1.6 ns typ (S10-ohm load)
= 1.8 ns tvp (50-ohm load)
PO::: 220 mW tvp/pkg (no-load)

MC1S70 MC1S90
Master·Slave Tvpe 0 Flip-Flop UH F Prosealar Typo D Flip-Flop

(9) 5 S------,

(11) 7 C1
(11) 7 C1 2 (6)
a 2 (6) (14) 9 C2
(14) 9 C2

(15) 11 01
(15) 11 0 Q 3 (7) 3 (7)
(16) 1202

(8) 4 A-------'

fTog == 350 MHz typ fTog = 500 MHz min

Po = 220 mW typ/pkg (no load) PO;' 200 mW tvp/pkg (No Load)

2-7
LOGIC DIAGRAMS (continued)

COUNTERS
MCI654
Binary Counter

50 3 00 5 51 7 01 6 52 9 02 11 53 14 03 12

o· Q'
AT AT
Clock 1 15 C1
Clock 2 C2 a C Q
A

Reset 10

00 4 03 13

·po = 750 mW typ/pkg

Operating Frequency'" 325 MHz typ

• Requires special heat sink IERe Lie 214A2WCB or equivalent.

MC1678
BI-Quinary Counter

SO 14 ao 13 51 10 Q1 11 52 3 02 4 53 7 03 6

Clock 15 C1
A

Reset 9 o----J---~-t==t==:::!=~==E===~~-J
aD 12 C2 2 03 5

·po = 750 mW typ

Toggle Frequency = 350 MHz typ

• Requires special heat sink IERe Lie 214A2WCB or equivalent.

2-8
LOGIC DIAGRAMS (continued)

COUNTERS (cant.) - - - - - - - - - - - - - - - - - - - - - - - ,

MC1696
l-GHz Divide-By-Ton
Counter

11 ao 10 Q2

vee1 = Pin 4
VCC2'" Pin 5
VEE1 = Pin 13
VEE2"" Pin 12
Bia. POint'" Pin 1•

o a o a
710 Out
Clock 16

....- - - - - - - j c ceQ
Enable 2 A A A

ftog = 1.2 GHz tvp

Po = 650 mW tvp/pkg (No Load)
Output Rise and Fall Times = '.0 ns (20% to 80%)
-This bias point permits capacitive decoupling for
a c performance enhancement.

SHIFT REGISTER'------------------~
MCl694
4-Bit Shift Registo,

FLIP-FLOP TRUTH TABLE

INPUTS UTPU
D C R S an 50 aD 51 01 52 a2 53 a3
0 0 0 0 °n_1 2 13 10 12 3 4 6 5
0 0 0 0 1
0 0 1 0 0
0 0 1 1
0 1 0 0 0 01 14
0 1 0 1 1 02 15
0 1 1 0 0
0 1 1 1
1 0 0 0 °n_1
1 0 0 1 1
1 0 1 0 0 Clock
1 0 1 1 Reset 9
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1
·Output State
Undefined
Total Power Dissipation =< 750 mW typ/pkg
Shift Frequency"" 326 MHz typ

2·9
LOGIC DIAGRAMS (continued)

MULTIVIBRATOR-----........, OSCILLATOR------_
MCI668 MC1648
Voltage-Controlled Emitter Coupled Oscillator
Muhivibrator

Co
~~;~~g <>-114--......- 0

Vcx 2 a 6

Bias Filter 12

Input Filter 13 4

Vee =: Pins 1, 14
VEE = Pins 7,8

veel = Pin 1
VCC2 = Pin 5 Operating Frequency = 225 MHz typ
VEE=PinS Po z: 150 mW typ!pkg
(+5.0 Vdc Supply)
Operating Frequency"" 150 MHz typ L, C, Co are external components.
Po = 125 mW typ!pkg Co is a varactor diode.

COMPARATOR------------- RECEIVER------------------
MCI660 MC1692
MC16S1 Quad Line Receiver
Dual AID Comparator

v,.
6~O
(10)
(6) 00
(9) 5 - 02
(8) 45~ 2 (6)
(9)~
c. (8) 4 C a 3 (7) 00
67~.
(111 3 (7)
(10)~
:~::~~~14 (2) 01 (14)10~ 14 (2)
(15) 11

Cb(I)13~'5 (3) 01 (1l12~

(16) 13
15 (3)

~9(13)
tpd = 3.5 ns typ (MC1650)
Vss
3.0 ns typ (MC16S1)
Po = 330 mW tvp/pkg (No load)

Vee = +5.0 V -= Pin 7,10· (11), (14) tpd 0.9 ns typ (SlO-ohm load)
=
VEE = -5.2 V = Pin 8 (12) '.1 ns typ (50·ohm load)
Gnd = Pin I, 16 (4) (5) Po = 220 mW typ/pkg (No load)

2·10
 MECL 10.000 SERIES

INTEGRATED CIRCUITS FROM MOTOROLA

MC10,100/10,200 Series (-30 to +850 C)
MC10,500/10,600 Series (-55 to +1250 C)

MECL 10,000 has an excellen t speed-power product,
has relatively slow rise and fall times, and transmission·
line drive capability. The combination of versatile logic
functions and the 2.0 ns propagation delay make MECL
10,000 a versatile family for data handling and processing
systems.
Circuit design with MECL 10,000 is unusually con·
venient. The differential amplifier input and emitter·
follower output permit high fanout, the wired·OR option,
and complementary outputs. MECL III is directly com·
patible with MECL 10,000, and can be used to extend the
speed capability of the MECL 10,000 series.

L SUFFIX P SUFFIX
Cf::AAMIC PACKAGE Pl-ASTIC PACKAGE
CASE 648

~
PSU'FI'
'. .. PL.ASTIC PAC!<::AGE F SUFFIX
t CASE 649
CERAMIC PACKAGE

_;i" i
CASE 652

FUNCTIONS AND CHARACTERISTICS (Vcc' 0 VEE' -52 V TA' 25°C)

Propagation Power Dissipation
TypoG) Delay mW
Function -30 to +850 C -55 to +125 0 C nstyp typ/pkg* Case

Quad 2-lnput NOR Gate With Strobe MC10l00 - 2.0 100 620
Quad ORINOR Gate MC10l0l MC10501 2.0 100 620,648,650
Quad 2-lnput NOR Gate MC10l02 MC10502 2.0 100 620,648 ,650
Quad 2-lnput OR Gate MC10l03 - 2.0 100 620
Quad 2-lnput AND Gate MC10l04 MC10504 2.7 140 620,648,650
Triple 2-3-2-lnput ORINOR Gate MC10l05 MC10505 2.0 90 620.648,650
Triple 4-3-3-lnput NOR Gate MC10l06 MC10506 2.0 90 620,648,650
!riple 2-lnput Exclusive OR/Exclusive NOR MC10l07 MC10507 2.5 110 620,648,650
DuaI4-5-lnput OR/NOA Gate MC10l09 MC10509 2.0 60 620,648,650
Ouar3-lnput 3-0utput OA Gate MC10l10 - 2.4 160 620,648
Dual 3-lnput 3-0utput NOR Gate MC10111 - 2.4 160 620,648
Qued Exclusive OR Gate MC10113 - 2.5 175 620
Triple Line Receiver MC10114 MC10514 2.4 145 620,648,650
Q.uad L.ine Receiver MC10115 MC10515 2.0 110 620,648,650
Triple Line Rac&iver MC10116 MC10516 2.0 85 620,648,650
Duel2·Wide 2·3·lnput OR·AND/OR·AND· MC10117 MC10517 2.3 100 620,648,650
INVERT Gete
Dual 2-W'ida 3-lnput OR-AND Gate MC10118 MC10518 2.3 100 620,648,650
4-Wldo 4,3·3·3·lnput OR·AND Gate MC10119 MC10519 2.3 100 620,641.;650
:4--Wlde OR-AND/OR-AND-INVEAT Gate MC10121 MC10521 2,3 100 620,648,650
T .. iple 4-3-3-lnput Bus Driver MC10123 - 3.0 310 620
Quad MTTL to MECL Translator MC10124 MC10524 3.5 380 620,648,650
Quad MECL to MTTL Translator MC10125 MC10525 4.5 380 620,648,650
Dual MECL to MOS Translator MC10127 - - - 620
BUI Driver MC10128 - 12.0 700 620
Quad a us Receiver MC10129 - 10.0 750 620
Dual Latch MC10130 MC10530 2.5 155 620,648,650
Dua' Type 0 Master-Slave Flip-Flop MC10131 MC10531 f'" 160 MHz 235 620,648,650
Dual Multiplexer With Latch and Common Reset MC10132 - 3.0 225 620,648
Quad Latch MC10133 MC1Q533 4.0 310 620,648,650
Multiplexer with Latch MC10134 - 3.0 225 620,648
Dual J-K Master-Slave Flip-Flop MC10135 MC10535 f 140 MHz 280 620,648,650
Universal Hexadecimal Counter MC10136 MC10536 f - 150 MHz 625 620,650

CD L suffix denotes Dual In-Une Ceramic Package. P suffix denotes Dual In-Une Plastic Package, F suffix denotes flat package
(i .••• MC10100L ~ C.ramic Dual In-Line Package. MC10l00P:: Plastic Dual In-Line Package and MC10500F "" Ceramic Flat Package,)

-External Load Power not included.

2-11
~ ~ ~ [110.000 LOGIC DIAGRAMS
Numbers In parenthesis denote pin numbers for F package (Case 650).

FUNCTIONS AND CHARACTERISTICS (continued)

TypeQ) Propagati on Power Dissipation

Delay mW
Function -30 to +850 C -55 to + 125°C ns typ typ/pkV' C ....
Universal Decade Counter MC10137 MC10537 f'" 150 MHz 625 620,650
Bi-Quinary Counter MC10138 - f::::: 150 MHz 370 620
64-Bit Random Acces. Memory (900) MCM10140 - tAccess'" 15 (max) 420 620,690
Four-Bit Universal Shift Register MC10141 MC10541 f = 200 MHz 425 620,648,650
64-Bit Random Accesl Memory (50 fl) MCM10142 - tAccess - 10 (max) 420 620
8)( 2 Multiport Regilter File (RAM) MCM10143 - tAccess::: 10 610 623
2S6-Bit Random Access Memory MCM10144 - t Access == 30 (max I 420 620,690
64-Bit Regilter Fila (RAM) MCM10145 - tAces" = 10 625 620
128-Bit Random Access Memory MCM10147 - tAccess = 12 (max) 420 620
64-Bit Random Access Memory (50 fl) MCM10148 - tAecass = 15 (max) 420 620
1 024-Bit Programmable Read Only Memory MCM10150 - tAccess::: 20 - 690
Quad Latch MC10153 4.0 310 620
12-Bit Parity Generator-Checker MC10160 MC10560 5.0 320 620,648,650
Binary to 1-8 Decoder (LOW) MC10161 MC10561 4.0 315 620,648,650
Binary to 1-8 Decoder (High) MC10162 MC10562 4.0 315 620,648,660
Error Detection-Correction Circuit MC10163 - 5.0 520 620
S-Line Multiplexer MC10164 MC10564 3.0 310 620,648,650
a-Input Priority Encoder MC10165 - 7.0 545 620,648
5-Bit Magnitude Comparator MC10166 - 6.0 440 620
Quad Latch MC10168 - 3.0 310 620
Dual Binarv To 1-4 Decoder (Low) MC10171 MC10571 4.0 325 620,648,650
Dual Binary To 1-4 Decoder (High) MC10172 MC10572 4.0 325 620,648,650
Quad 2-lnput Multiplexer/Latch MC10173 - 2.5 275 620,648
Dual 4 To 1 Multiplexer MC10174 MC10574 3.5 305 620,650
Quint Latch MC10175 MC10575 2.5 400 620
Hex "0" Malter-Slave Flip-Flop MC10176 - f = 250 MHz 460 620
Triple MECL to NMOS Tranllator MC10177 - - 1.0W 620
Binary Counter MC10178 - f : 150 MHz 370 620
Look-Ahead Carry Block MC10179 MC10579 3.0 (Cn,P) 4.0 (G) 300 620,648,650
Dual High Speed Adder/Subtractor MC10180 MC10580 4.6 360 620,648,650
4-Bit Arithmetic Logic Unit/Function Generator MC10181 MC10581 See Logic Oiag. 600 623,649,652
2-Bit Arithmetic Logic Unit/Function Generator MC10182 - See Logic Dieg. 575 620
Error Detection-Correction Circuit MC10193 - 7.5 520 620
Hex Inverter/Buffer MC10195 - 2.0 200 620
Hex "AND" Gate MC10197 - 2.8 200 620
High Speed Dual 3-lnput 3-0utput OR Gat. MC10210 - 1.5 160 620
High Speed Dual "3-lnput 3-0utput NOR Gate MC10211 - 1.5 160 620
High Sp.ed Dual 3-lnput 3-0utput OR/NOR Gate MC10212 - 1.5 160 620
High Speed Triple Line Receiver MC10216 MC10616 1.8 100 620,648,650
High Speed Dual Type 0 Matter-Slave Flip-Flop MC10231 MC10631 f - 225 MHz 270 620,648,650
High Sp. . d 2 x 1 Bit Array Multiplier Block MC10287 - - 400 620

CD L .ufflx denotel Dual In-Line Ceramic Package, P suffix denotes Dual In-Line Plastic Package, F suffix denotes flat package
(I.e., MC10100L" Ceramic Dual In-Une Package, MC10100P '"' Pla.tlc Dual In-Line Package and MC10500F "" Ceramic Flat Package.)
-Load Power not included

2-12
LOGIC DIAGRAMS

CASE VCCl VCC2 VEE

620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

GATES-----------------------------------------,
MCl0l00 MC10l0l MCl0l02
Quad 2-lnput NOR Gate MC10&01 MC 1 0&02
With Strobe Quad OR/NOR Gate Quad 2-lnput NOR Gate

4
2 (8) 4 . . .,,---d. . .---- 2 (6) (8)
(9)~
45~ .2 (6)
-"-~--- 5 (9)

6 (11 ) 7 --I-...,--...d/JI_"---- 3 (7) (10)6~

t---L____- ......---- 6 ( 1 0) (11)7~3(1)

(14) 10~1-...'--...d/JI_"----14 (2) (14)10~
10 14 (2)
14 t---L~- ......---- 11 (15) (15) 11
11 (1) 13 ~I-...,--...d/JI_"---- 15 (3) (16) 12~15 (3)
12 (16) 12 9 (13) (1)13~9(13)
15
13

Po = 25 mW typ/gate (No Load) Po = 25 mW typ/gate (No Load) Po =- 25 mW typ/gate (No Load)

tpd = 2.0 ns typ tpd = 2.0 ns typ tpel =
2.0 ns typ

MC10l03 MCl0l04 MCl010&

Quad 2·lnput MC10504 MC 10505
OR Gate Quad 2-lnput AND Gate Tripi. 2-3-2 Input OR/NOR Gate

4-----,=C>-- (8)4~
(9)5~2(G)
_

(814~3(7)

:c>--- 3
(10)G~
(11)7~3(1)

(14)10~ _
(9)5~2(6)

[13)9~ 6 (10)

;~ ____~::~~': ('5),,~'4(2) (14) 10 7 (11)

(15) 11
(IG)12~9(13)
(1)13~'4(2)
(')'3~'5(3)
10
11 :C>--'4 (IG) 12~15[3)

Po = 25 mW typ/gate (No Load) Po = 35 mW typ!gate (No Load) Po 230 mW tvp/gate (No Load)
tpd :::: 2.0 ns typ tpd - 2.7 nstyp tpet '"" 2.0 nl typ

MC10l06 MC10107 MC10l09

MC10506 MC10507 MC10&09
Triple 4-3-3-lnput NOR Gate Triple 2-lnput Exclusive Dual 4-5-lnput
OR/Exclusive NOR OR/NOR Gat.

(::::~3(7)
A
[8)4~2161
19)5~317)
Y : : :~3
[10) 6 2
[7)
[6)

(11)7~ (13) 9~11 (15)

111) 7

;:::,:~
(11)7~'O(14)
(t3)9~
(14) 10 2 (G) (2)'4~12(16) 14 12)
(15) 11
(15) 11 (3)15~13(1) 15 13)
(I G) 12
(lG)12~ (1) 13
(1) 13 15 (3)
(2) 14
z~ IA_S)+ (A_B)
Y =- LA. • HI + (A. BI

Po = 30 mW typ!gate (No Load) Po = 110 mW typ/pkg (No Load) Po - 30 mW typ/gete (No Load)
tpd = 2.0 ns typ tpd = 2.5 ns typ tpel • 2.0 ns typ

2-13
LOGIC DIAGRAMS (continued)

GATES(continuedl - - - - - - - - - - - - - - - - - - - - - - - - - - - - " " "

MC10110 MC10lll
MC10210 MC10211
Dual 3-lnput 3-Output Dual 3-1 nput 3-0utput
OR Gate NOR Gate

5~~
6
7
4

'~~''2 ~
'2
9 13
" 13
10 14
14 11

Po'"" 160 mW tvp/pkg (No Load) Po = 160 mW ryp!pkg (No Load)

MC101'O MC1D111
tpd "" 2.4 ns typ tpd "" 2.4 ns 'tYP
MC1021D MC1D211
tpd = 1.5 ns typ tpd"" 1.5 ns typ

MC10113 MC10l17
Quad Exclusive MC10517
OR Gete DU81 2-Wido 2-3-1 nput
OR-AND/OR-AND-INVERT
E 9 Gate

2 (8) 4
(91 5
, r -___ " 3 (7) y = (A + B) • (e + 0 + E)
6 2 (6) X = (A + B) • (e + 0 + E)
3
(101 6
(11\ 7
10
14
11 (13) 9

12 Po = 100 mW tYP/pkg (No Load)

(14) 10
15 tpd = 2.3 ns typ
13 (15) 11
L-_r---"_ _ 14 (2)
.--, J - - 1 5 (3)
Po'" 175 mW typ!pkg (No Load) (16) 12
tpd = 2.5 nl typ (1) 3

MC10l19
MC10118
MC10519
MC1OS18
4-Wide 4-3-3-3 Input
Duel2-Wide 3-lnput OR-AND-Gate
OR-AND Gete
(7) 3
(7) 3 (B) 4
(8) 4 (9) 5
(9) 5 (10) 6
2 (6) (11) 7
(10) 6
(11) 7 (13) 9
(13) 9 (14) 10 2 (6)
(14) 10
(15) 11
(15) 11 (16) 12
15 (3)
(16) 12 (1) 13
(1) 13 (2) 14
(2) 14 (3) 15

• Collector Dot ·Collector Dot

PO:::: 100 mW typ!pkg (No Load) Po = 100 mV typa/pkg (No Load)
tpd - 2.3 ns tYP tpd:::O 2.3 ns typ

2·14
LOGIC DIAGRAMS (continued)

MC10196
MC10121 Hex In_tw/Buffer
MC10621
4-Wida
A
OR-AND/OR-AND-INVERT a
Gate B

:::;--~~~---------,
(10) 6
- - - 1 . _____- - - - , 6

1111 7 -~.,-...,o_--I----~ 4
(13)9

2(7)
114110
3(6)
13
(15)11 10
116112 ---"'---------.,

14
(1) 13 -~'''o_--l----­ 11
(2)14
(3) 1 5 ----,L -------

IS
12

Po ~ 200 mW typ/pkg INo Load)

Po: 100 mW typ/pkg INo Load)
tpd '" 2.3 ns typ tpd ::: 2.8n.
typ

MC10197
Hex AND Gate

MC10212
High Speed Duol 3-lhput
3-0utput OR/NOR Gote

- 4
6
5~:
7 --
2

~
'2
10 ____ -+___"o.L.-'i------ 13 9 13
10 14
11 .

VCC1 - 1,15
VCC2: 16
12----- .,...----- 15 VEE :8
PO:: 160 mW typ/pkg (No Load)
Po'" 200 mW typ/pkg (No Load) tpd;;:: 1.5 nl typ (All Outputs Loaded)
tpd :: 2.8 n. typ

2-15
LOGIC DIAGRAMS (continued)

TRANSLATORS==~------------------------------
MC10124 MC10125 MC10127
MC 10525 MC10525 Dual MECL to MOS Translator
Quad MTTL to MECL Translator Quad MECL to MTTL Translator

(6)2~
(9) 5 4(8) (7)3~418)
(10) 6 2(6) (10)6~_
III) 7 3 (7) (11)7~519)

(14) 10
1(5)

12(16)
15 (3)
(14)10~
(15)11~12116)

(2)14~
12
11
=t>--j1.- 14

(15) 11 13(1) (3)'5~'311) 13

, , 9

~'(5)
14(2) ....../'.r~
Vee = Gnd:= Pins 1, 2, 15.16
Vse
VEE=Pin8
Po = 380 mW typ/pkg (No Load) VSS:= Pins 7, 9
Po = 380 mW tvp/pkg (No Load)
tpd = 3.5 os typ
tpd "" 4.5 01 typ (50% to
~1.5 Vdc out)

RECEIVE RS=====______---------------------=
MC10114 MC10115 MCl0116, MCl05l6
MC105l4 MC10515 MC102l6, MC106l6
Triple Line Receiver Quad Line Receiver Triple L ina Receiver
le)4~216)
le)4~
(8)4~216)
(9)5~216) (9)5~317)
(9)5~317) (13)9~6110)
(11)7~
(13)9~6110)
(10)6~317) (14)10~7111)
(14)10~7111) (16)12~1412)
(14)10~
(16) 12~14(2)
(15)11~'412) 1')13~'513)
(1)13~'513) ~"1'6)
(1)13~
~11(15) (16)12~'513)
MCIOl16, MCI0516 Vss
Po = 85 mW typ!pkg (No Load)
VSS
'v--
SS
9(13 )
tpd "" 2.0 ns typ
tpd "" 2.4 nstyp (Single Ended Input) MCI0216, MCI0616
tpd "" 2.0 ns typ (Differential Input) PO"" 110 mW typ/pkg (No Load) Po ~ 100 mW typ/pkg INo Load)
Po "" 145 mW typ/pkg (No Load) tpd = 2.0 ns typ tpd = 1.8 ns typ
MC10129
Quad Bus Receiver
1400

1501

Po'"' 750 mW tvp/pkg (No Load)

tpd = 1001 typ

302

034

Hyster•• i.
Control 50-------'
Clock 11 u - - - - - - - '
R.MtIOo------~-~
Strobe 12

2-16
LOGIC DIAGRAMS (continued)

FLiP-FLOPS--------------------,
MC10131,MC10631
MC10231,MC10631
Duo! Type D M..ter·S!..,.
Flip-Flop

R-8 TRUTH TABLE

51 (9) 5---------------.
R S Q n +l
L L an
01 (11) 7----..-ot 2 (6) L H H
GEl (10) 6 H L L
H H N.D.
3 (7)
N.D. "" Not Defined
MC10131. MC10531
Rl (8) 4-+-------' Po = 235 mW typ/pkg (No Load)
f = 160 MHz typ
Cc (13) 9
MC10231. MC10631
R2 (1) 13--+------------. CLOCKED TRUTH TABLE
PO::: 270 mW typ/pkg (No Load)
f'" 225 MHz typ c 0 Q n +l
14 (2) L rp an
H L L
GE2 1'5)"---~__/ H H H

02 (14) 10-----.ao.t 15 (3) lP = Don't Care

C = GE + CC'

52 (16) 12 - - - - - - - - - '

MC10135 MC10176
MC10535 H.x "D" M.st ..·S.... Flip-Flop
Duol J·K M.st.r-S ....
Flip·Flop
2 00

R-S TRUTH TABLE

51 (9) 5 3 01
R S °n+1
Jl (11) 7 2(6) L L an
L H H
Kl(10) 6 3(7) H L L 4 02 CLOCKE.D TRUTH TABLE
H H N.D. C 0 Q n +l
Rl (8) 4 rp
C(13) 9
N.D. '" Not Defined L On
CLOCK J·K TRUTH TABLE" H' L L
52(16)12 13 03
K Q n +l H' H H
J2(14)10 15(3)
L L an (/> == Don't Care.
H L L • A clock H is 8 clock
14(2) 14 Q4
K2(15)11 L H transition from 8 low
H
to a high state.
H H Q n
R2 (1) 13
·Output states change on
positive transition of clock 15 Q5
for J-K input-condition
present.

Po = 280 mW tvp/pkg (No Load) Po '" 460 mW typ!pkg (No Load)

f tog '" 140 MHz typ f tog ::: 150 MHz typ

2-17
LOGIC DIAGRAMS (continued)

DRIVER------------------------------------------~

MCl0123 MC10128
Tripi. 4-3-3 Input Bu.s Driver Bus Driver

Dl

01
Clock

Reset "",,rl...,...---'

':~2
11~
Disable 1 o-';~-+---+-'
Disable 2 0--'''-1-+---+..,
D2
12~ 15
13
14

Stro~~--------~
Po - 310 mW typ/pkg (No Load) Control 2
tpd = 3.0 ns typ Po = 700 mW typ/pkg (No Load)
tpd = 12 ns typ

PARITY CHECKER - - - - - - - - - - - - - - - - - - - - - .
(7) 3
MC10160
MC10560
(B) 4
12-Bit Parity Generator-Checke,
(9) 5 INPUT OUTPUT
(10) • Sum of
(11) 7 High Level Pin 2
Inputs
(13) 9
2 (6) Even
(14)1. Low
(15)11 Odd High
(16)12
(1) 13
PD - 320 mW fVP!pkg (No Load)
(2)14 tpd .. 5.0 ns typ
(3) 15

ENCODER-----------------------------------~
MC10165
8-lnput
Priority Encoder
TRUTH TABLE
DATA INPUTS OUTPUTS
Vee 11 - _ 1 6 Vee 2
DO Dl D2 D3 D4 D5 D6 D7 03 02 01 00
012- - 1 5 02
H <P <P <P <P <P <P <P H L L L
003- - 1 4 03
L H <P <P <P <P <P <P H L L H
e4- - 1 3 D2 L L H <P <P <P <P <P H L H L
D05- - 1 2 D5 L L L H <P <P <P <P H L H H
L L L L H <P <P <P H H L L
D76- - 1 1 D4
L L L L L H <P <P H H L H
D17- - 1 0 D3 L L L L L L H <P H H H L
VEEB- -9 D6 L L L L L L L H H H H H
L L L L L L L L L L L L
tI>,. Don't Care
Po - 545 mW typ/pkg
tpd ,. 7.0 ns typ (Oat. to Output)

2-18
LOGIC DIAGRAMS (continued)

DECODERS---------------------------------------
MC10161 MC'10162
MC10561 MC10562
Binary To 1-8 Decoder Binery To 1-8 Decod.
(Low) (High)
EO 2::[:;E4::::::~
E115 EO 2::[:;E4::::::~
6 00 E115 6 00
5 01 5 01
4 02 4 02
A 7 A 7
3 03 3 03
13 04 13 04
B 9 B 9
12 05 12 05
1106
1106
C 14 10 07
C 14 10 07

TAUTHTABLE TRUTH TABLE

~~:~i; INPUTS OUTPUTS

INPUTS OUTPUTS

r;:, ~o C B A 00 Q1 Q2 Q3 Q4 05 06 Q1 Eo E.
L L
c
L
•
L
A
L
aD Q1 Q2 Q3 04
H L L L L
as
L
06 07
L L
L L L L.L L H H H H H H H
L L H H L H H H H L L l L H L ... L L L L L L
L H L H H L H H H H H L L L H L L L H L L L L L
L L H H L L L H H L L L H L L L L
L L H H H H L L L H L L L l L L H L L L
L L H l H L L L L L H L L
LLHHLH
L L H H L L L L L L L H L
LLHHHHHHHHHHL
(f)d>¢JIPHHHHHHHH L L H H H L L L L L L L H

H " '" (/) H

H

•
"
H
•• •" •• L
L
l
L
l
L
L
L
L
L
L
L
L
L
L
L

!) Don t Care
Po 315 mW typ/pkg (No Load)
c
Po - 315 mW tvp/pkg (No Load)
tpd ... 4.0 n. typ
tpd - 4.0 ns typ

MC10171 MC10172
Dual Binary To 1·4 Dacoder Dual Binery To 1-4 Decoder
(Low) (High)

10 003 10 00 3

'II 002 11 00 2

12 00 1 12 00 1
A 9
13 00 0 13 00 0

3 01 3
B 7
3 01 3
4 01 2
4 01 2
E 15 5 01 1
6 01 1
5 01 0
El 2
6 01 0

TRUTH TABLE
TftUTHTAR.E
ENABLE INPUTS INPUTS OUTPUTS
• f. Eo A
• a. 0 all 0.2 0.3 000 00' 002 003
E
L
EO
L
••
L
A
L
•
l
0.0
l
011
H
0'2
H
013
H
000
L
00.
H
002
H
003
H
l
L
H
H
H
H
l
L
L
H
H
L
L
H
L
L
L
L
H
L H
L L
L
L
L
L L L L H H L H H H L H H L H H H L L L H L L L H L
L L L H l H H L H H, H L H L H H H H L L L H L L L H
L L l H H H H H L H H H L L L H L L L L L L H L L L
L L H L L H H H H L H H H L H L L L H L L L L L L L
L
H
H

• • • •
L L L L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
• • • • L L L L L L L L

•• Don't c.,. . - Oont Cere

Po - 325 mW typ/pkg(No Load) Po - 325 mW typ/pkg (No LOIld)

tpd - 4.0 nl typ !pet ~ 4.0 no typ

2-19
LOGIC DIAGRAMS (continued)

DATA SELECTORS/MULTIPLEXERS-----------
MC10132 MC10134
Dual Multiplex .. With Dual Multiplexer with latch

Al1~
Latch and Common R_t
A06~
011 4 r---
~2 01
~
A"'--U-
011 4 r---
~2 01
----:l

*
012 5
CEO 10
Cc 7
~3 (11 012 5
CEO 10
R 6
~3 01
j ~1502 Cc 7
eEl 9
T ~
021 13 :i ~'5 02

~
eEl 9
021 13

~-
~'4Q2
02212
-,402
TRUTH TABLE 022 12

R 0 C CE Ontl TRUTH TABLE

<I> L L L L C AO 011 012 On+ 1

L L L H an = 225 L L L L
Po mW typ/pkg <I> Po = 225 mW typ/pkg
L L H L an (No Load) L L H <I> H (No Load)
L L H H an tpd = 3.0 ns typ L H <I> L L tpd = 3.0 ns typ
<I> H L L H L H <I> H H
L H L H an H <I> <I> <I> On
L H H L an
rJ> = Don't Care
L H H H an
H H L
c= Ce + Cc
<I> <I>
rJ> - Don't Care

MCtOt64 MCl0173
A (11) 7 L MCt0564 Quad 2-lnput
B(13)9~ B-Lin. Multiplexer Multiplexer/Latch

C(14)10~ S.'.ct9~
Enable (6) 2
===\ -;
15 (3) Z
0006 ~- 100
XO (10) 6

Xl (9) 5
~ ;- 0015
-0
X2(B)4
=\ ;- ~= 201

X3 (7) 3
H r P.o = 310 mW typ/pkg
0104

J=< ~
X4 (15)11
~ ;- tpd'" 3.0
(No Load)
ns typ/pkg
0113

R ;- ~;= ~ 15 02
X5 (16) 12 02013

X6 (1) 13
-B )"
02112
~
-L./
'------='=\ ;-
X7 (2) 14
TRUTH TABLE
~:= 1403

~
03011
ADDRESS INPUTS
ENABLE C B A Z
03110
~
'--
L L L L XO Clock 7 -
L L L H Xl
L L H L X2 TRUTH TABLE
L L H H X3
SELECT CLOCK OOn+l
L H L L X4
L H L H xs H L 000 Po = 275 mW typ/pkg
L H H L X6 (No Lo.ad)
L L 001
L H H H X7 tpd ~ 2.5 n. typ
<I> H aO n
H <I> ~ ~ L
• - Don't Cere q, = Don't Car •

2-20
LOGIC DIAGRAMS (continued)

DATA SELECTORS/MULTIPLEXERS
(continuedl
MC10174 MCl0l.
MC10674 MCl0530
Dual 4 to 1 Multiplex .. Quell l.8teII
XO (7) 3 - - - - - - ' 51 (9) 5

Xl (9) 5----H--,.-{~
01(11) 7 2 (6)
X2 (8) 4 ----H::8~ 2 (6) Z
CEI (10) 6
X3 (10) 6 -----1-t-b8~ 3 (7)

A (11) 7
Al (8) 4
8 (13) 9 C (13) 9
Po ~ 305 mW tvp/pkg A2 (1) 13
(No Load)
YO (1) 13 ----+++1-1.____
14 (2)
Y 1 (15) 11 ----+-=H:....::{____
15 (3) W CE2 (15) 11
Y2(16) 12'----F=f=L-/ 02 (14) 10 15 (3)
Y3 (14) 10---===L____
S2 (16) 12
TRUTH TABLE
TRUTH TABLE
ENABLE ADDRESS INPUTS OUTPUTS D C CE °n+1
E B A Z W L L L L
H <I> <I> L L
H L L H
L L L XO YO
Yl <I> L H an
L L H Xl
L H L X2 Y2 <I> H L an
L H H X3 Y3 q, H H an
I'/> = Don't Care cp - Don t Care.

MC10175
MC10575
LATCHES----------' Quint Latch
00I0---~ 1400
MC10133 MC10153
MC10533 Quad Latch
Quad Latch
003------"'! 003,------Ai,nn~~~
01 12 -----t--t'"1 15 01
2 00 2 00

GO 5 , - - - - - [ - - - -.......,-,
6 01 6 01 02 13 ----t---+-1 2 02
01 7----4--~~~
CE4
03 9 -----+--t"i t 3 03

11 02 11 02
9 45 ----t-l''''I 404
CO 6
C17
15 Q3 15 03 Aesat 11----+-~

Po::: 310 mW typ/pkg (No Load) Po::: 310 mW typ/pkg (No Load) Po = 400 mW typ/pkg (No Load)
tpd "" 4.0 ns typ tpd = 4.0 ns typ tpd = 2.5 ns typ
TRUTH TABLE TRUTH TABLE TRUTH TABLE
"G C D Q n +1 "G C D Q n +l 0 CO C1 Reset a n+1
H q, <I> L H q, q, L L L L L
L L <I> an L H q, an H L L L H
L H L L L L L L <I> H <I> L an
L H H H L L H H q, q, H L an
tP c Don t Care I'/> '" Don't Care
q, H <I> H L
C=Cc+ce C '" Cc + CE <I> q, H H L

2·21
LOGIC DIAGRAMS (continued)

SHIFT REGISTERS----------------~
MC10141
MC10541
Four-Bit Universe. Shift Register
(1) 13
I TRUTH TABLE
OL SELECT OUTPUTS
( (8) 4-C aD f---14 (2)
SI S2 OPERATING MODE OOn+l 0l n+l 02n +l 03n+l
(16) 1 2 - DO
l L Parallal Entry DO 01 02 03
(15) 1 1 - 01 al f---15 (3)
L H Shift Right- aln Q2 n a3 n DR
(13) 9 - 02
(10) 6 - 03 a2 f - - - 2 (6)
H L Shift Left- Dl aO n aln a2n
(14) H H Stop Shift aO n aln a2n a3"
1 0 - SI
(11) 7 - S2 (7) • Outputs .. exist after pulse appear, at "c" input with input condition.
a3 - 3
DR as .hown. (Pulse "" Positive tran.ition of clock Input).

(9) 5 I Po "" 425 mW tvp/pkg

fahift" 200 MHz typ

ERROR DETECTION-CORRECTION
MC10163. MC10193
Error Detection-C orraction
Circuit

MC10163 LOGIC DIAGRAM MC10193 LOGIC DIAGRAM

81 Bl 7
B2 6 B2 6
15 POA )-f---15P4
B412 _B412
B711 B711
3 P3 )-t---3P3

-B5 4
B6 5
Jl5 4
B6 5
2 P5
2 POB
BO 9
B310 -BO 9
B310

) - - - - 1 4 PI > - - - - 1 4 PI

> - - - - 1 3 P2 >----13P2

IBM CODE MOTOROLA CODE

POA = Bl, B2, B4, B7 PI = Bl, B3, B5, B7
POB = 80, B3, B5, 86 P2 = B2, B3, B6, B7
PI = Bl, B3, B5, 87 P3 = B4, B5, B6, B7
P2 ;c 82, 83, 86. B7 P4 = 81, 82, 84, B7
P3 = B4, B5, B6, B7 P5 = Byt. (BO, 1,2,3,4,5,6,7)
..
Po = 520 mW tvp/pkg (No Load) Po = 520 mW typ/pkg (No load)
tpd:: 5.0 ns tvp tpd"" 7.5 ns typ (Pin 7 to Pin 2)

2-22
LOGIC DIAGRAMS (continued)

COUNTERS--------------------------------------~
MC10136
MC10536

(14)10-
- Cin 00 r-14 (2)
Universal Hexadecimal
Counter
SEQUENTIAL TAUTH TABLE'
(1)13- C
r-15 (3)
DO 01
INPUTS OUTPUTS
(16)12-
(15)11- 01 CMrV Clock Carry
02 r-- 2 (6) 5' 52 DO O. 02 03 ;;; ao o. 02 03 0,;
(10) 6 - 02 L H H H H
(9) 5 - 03 03 r-- 3 (7)
H •• •• •• H H

(13) 9 - 51 L H
• • •
(11) 7 -
-
S2 C out r-- 4 (8) H
H •• •• •• •• H
H
H
H
H
H
H
H

FUNCTION SELECT TABLE

L
H
L H • • • •
H L L
H
H
H
H
H
L
H
L

51 52 Operating Mode
H
H
L
L •• •• •• L L
Pr..., (ProGram) L
L •• •• •• L
H
L
H

DlICr.mant (Count Cown)

HOLd (Stop Cound
(/) "" Don't care.
'Truth table shows logic states assuming inputs vary in sequence
Po = 626 mW typ/pkg (No Load) shown from top to bottom.
f count -150MHztyp •• A clock H is defined as a clock input transition from a low to
a high logic level.

MC10137
.-- U River ..1 Decade
10-C;n 00-14 Counter SEaUENTIAl TRUTH TABLE'
INPUTS OUTPUTS
~~=~O 01-15 5iTV Clock ~
51 52 00 01 02 03 iii' CXI at 02 OJ OUt
1 1 - 01 02-2
H H H L
6 - 02
•• ••• ••
••"
5-03 03-3 H H H
9-51 H
• • H L

••• ••• • ••
L H H
7 - 52 C ou, - 4

••• •• •
L H H
~
H H L L H

fUNCTION SELECT TABLE

H
L
H
L H
• H• L
•
H
H
L
H L
L
L
H

H L
51 52 Operating Mode H L H L L
H L L L

Incramant (Count Up)

OllCremant (Count Down)
q, = Don't care.
Hold (Stop Count)
-Truth table shows logic states assuming inputs vary in sequence
shown from top to bottom.
Po = 625 mW typ/pkg (No Load)
_. A clock H is defined as a clock input transition from a low to
f eount "" 150 MHz tvp
8 high logic level.

MC10138 MC 1 0178
12-Cl 0 0 r - 15 Bi-au inary Count. Binary Counter
9-R 01r-13
7-C2 02r- 4
11-50 03r-- 2 11-50 00-15 TRUTH TABLE
10-51 00r-14 7 - 51 01-13
INPUTS OUTPUTS
6 - 52 03r-- 3 6-52 02-4 R 50 5. 52 S3 Cl C2 co 01 02 OJ
5 - 53 03-2
*- •• ~•• I. \,1
5-53 L L
12-Cl 00-'4 H H
L H'
LJ H H
L
L L NoCounl
COUNTER TRUTH TABLES ;O-C2 03-3 L L
9- R
BI·QUlNARY BCD
(Clock conneettd to C2 IClock connected to Cl
.nd 03 connecttd to C1) and CO connected to C2) Po = 370 mW 'YP/pkg
L
(No Load) L
COUNT 01 02 00 ao COUNT ao O. Q2 00 1'og - 150 MHz (Typ) L
0
1
2
L
L
H
,
0
2
L
L
L
L L
3 H 3
•6
L
L
L
L
L
H
L
H
L
L
H
H
L
.L

,
6 H L
H ] L
H
H
H
H
H
L
L
L

8 H H H L L H
• L L H H L H ~ - Oon't Care
Clock tran,itlon from VI L to VI H
Po "" 370 mW typ/pkg (No Load) may be applied to C 1 or C2 or both
f tog "" 150 MHz typ for .ame effect.

2-23
LOGIC DIAGRAMS (continued)

ADDER AND ARITHMETIC FUNCTIONS-----------.

MC11l179
Look-Ahead Carry Block

G3 5

P3 13
G2 9 J ./~ ~3 C n +4

P2 12 ~"
--L/
~2 GG
-= =:::; ./

Cn II ~
>-
'"
./ 15 PG
Po: 300 mW tvp/pkg
tpd "" 3.0 ns typ (Carry, Propagate)
4.0 ns typ (Generata)
Gl 7

PI 10
GO 4
) 6 C n +2

~
PO 14

MC10180 MC10181
MC10580 MC10581
Dual High Speed 4-Bit Arithmetic Logic
AddarlSubtr.ctor Unit/Function Generator

(11) 7
..... SelA 50 ......... 15 (3) (19) 13
(13) 9
... Sala SO .........2 (6) (21) 15
(9) 5
... AO
= 360 mW typ/pkg
(23) 17

~
Po
(10) 6 BO (20) 14
(8) 4 .... Cin C out .........3 (7)
r
tpd (typ)
50 51 52 53
Cin to C out = 2.2 ns (3) 21------ AO FO - 2 ( B )

_ ...
L-........
SalA 51 ~14(2)
AO to SO = 4.5 ns
AO to C out = 4.5 ns (2) 20------ BO
(24) lB------ Al
Fl - 3 ( 9 )

...... Sala 51 ~1(5) (1) 19------ Bl F2 - 7 ( 1 3 )

-
(IS) 11 Al (22) 16------ A2
F3 - 6 ( 1 2 )
(14) 10 Bl (17) 11------ B2
(16) 12 Cin
C out ~13(1) (16)10-- A3 GG - 4 ( 1 0 )
(15) 9------ B3
PG -8(14)
Positive Logic Only ( 4 ) 2 2 - - Cn
A': A 0SoIA: A (!)SoIA (5)23--M C n +4 - 5 ( 1 1 )
B' ~ B 0 SOla= B (!) Sola
FUNCTION SELECT TABLE

SoiA SelB Function Po ~ 600 mW typ/pkg (No Load)

'pd (typ), A1 to F -6.5 n.
H H S - A plu. B
C n to C n + 4 - 3.1 nl
H L S - A minus B A1 tOPG'"'6.0nl
L H S'" B minus A A 1 to GG ,.. 4.5 nl
L L S - 0 minus A minus B A1 to C n +4'" 5.0"s

2-24
LOGIC DIAGRAMS (continued)

ADDER AND ARITHMETIC FUNCTIONS ( c o n t i n u e d ) - - - - - - - - - - - ,

MC10182
2-Bit Arithmetic Logic
Unit/Function Generator

9----------,

10-----,

SO SI
13 cn
Po = 575 mW tvp/pkg (No Load)
FO 4
AO tpd (typ) A 1 to F '" 7.5 ns
F1 14 C n to C n +2:: 2.7 ns
A 1 to PG '"' 6.5 ns
6 BO
PG 15 A 1 to GG : 5.5 ns
Al toC n +2= 7.0ns
12 Al GG 3

C n +2
11 Bl
M

MCl0287
HighS.... d
2 X 1 Bit Array Multiplier

CO 9
aO 6
aO' 7
2 SO

4 Po'" 400 mW typ/pkg (No Load)

bO
C, tpd: (Outputs loaded 1 kfl to Vee)
bO° 5 co to C2 1.7nstyp
MO
aO to C2 2.8
aO to SO 2.7
bO to SO 3.'

a' " 5'

aO to 51 3.9
bO to 51 4.4
al' '0
MO to 5'8.7
b' '3
'5 C2
"51' 12
M' '4 Vee'" Pin 16
VEE=Pin8

2-25
LOGIC DIAGRAMS (continued)

MEMORIES
MCM10143 MCM10145
8 x 2 Multiport Register 64·8it Register File
File (RAM) (RAM)

Read Enable
4
6
BO REB
Chip Enable
B, 2 3
OB,

{
5
B2 10 CE

,......
9 AO 00
Write Enable WEO 9
10 AI
Data DO 3 Lines
14 aBO A2
6 01
AO Data
Address 15 Data A3
AI Output 5 Output
Lines 13 DO Lines
Lines 15
A2 22 4 02
8 OC, 01
Write Enable WE, 0 ... '"."" { 11
11 Lines 02
Data 0, 12 14
17 03 _ 0 3
Co 21 WE
OCO
16
C, 13
18 _ Clock Write Enable
C2 REC
20 19
Read Enable - - - - - - - '
Clock - - - - - - - - - - ' Vee:::: Pin 16
tpel: VEE=Pin8
Clock to Data out = 5 ns (typ) Veca :::: Pin 1
I Read Selected) Veel = Pin 23
Address to Data out = 10 ns (typ) Vee = Pin 24
Po = 625 mW typ/pkg (No Load)
(Clock High) Vee = Pin 12 Access Time:::: 10 ns typ
Read Enable to Data out = 3.5 ns (typ)
(Clock high, Addresses present)
PO::: 610 mW typ/pkg (No Load)

MCM10140 (90 {"I)

MCM10142 (50 fl)
MCM10148 (50 {"I)
64-Bit Random Access Memory
Address Inputs

The Chip is enabled

when EEl and C E 2
inputs are at positive
Po:::: 420 mW typ!pkg logic "0"
tAccelS = 15 nl (maxI MCM10140, MCM10148
:::: 10 nl (max) MCM10142

CEI
CE2

Data Out

Data In O-:-=---------j
Write o-----------i

2·26
LOGIC DIAGRAMS(continued)

MEMORIES (continued) - - - - - - - - - - - - - - - - - - - - - - - ,

MCM10144
D out GE1 CE2 CE3 256 Bit Random
A ..... M.mory
1,5 Is is i7

~
Data Out Chip
Buffer Enable

Sense

AO------1~ r
Amplifier
J r-L-- Vee = Pin 16

----2
.. "
~ :& i . r-;-;;-
VEE:: Pin 8
tAcces. = 30 ns (max) (Addrellinputs)

·. -1
A' ,,::: WE

J-
32 x 8 c ,
A2~
•
•
0
u Memorv Cell
«III
,';0
'ON Array
!E
";: nI
A3~ «~ ~:; ~Din
i
l
,,~
0
A4~~ - TRUTH TABLE
B;, Add,." Buffe,/
1/8 Decoder
J MODE INPUT OUTPUT
CE WE Din °out
['0 [" ['2 Write "0" L L L L

AS AS A7 Write "1" L L H L
Read L H <I> a
Disabled H

tP "" Don't Care

<I>
" L

MCM10147
Chip Enable 128 Bit Random
Chip Enable A ..... M.mory

14[ 1,3
4 CE2
3 A, AO eEl

Address

( 5
6

'0
2

7
A2
A3
A4
AS
AS Q~OatBOut

TRUTH TABLE
11
Data Input D MODE INPUT OUTPUT
WE
CE' CE2 WE D a
Read/Write 12 j Writ. "0" L L L L L
Enable
Writ."," L L L H L
R.ad L L H a
Disabled H L 4>
'"
4> L
L H 4> 4> L
Po = 415mW tvp/pkg (No Load)
(Access = 10 ns typ (Address Inputs) <P = Oo~·tC ...

2·27
LOGIC DIAGRAMS(continued)

MEMORIES (continued) - - - - - - - - - - - - - - - - - - - - - - - ,

MCM10160
1024·Bit Pr .... mmabl.
Road Only Memory
A3 •

A410

Input 32.32
A5 • Arr.y.nd
A.lOdated Drivers

A. 5

., 1

AO 4

., , Output
Oecoder

., 3

CE 13----------------------------~+_----~~~----~~----__,

Dout3 Doutl OoutO

COMPARATOR------------------------------~
MC10166
5-Bit M..,ituda
Comparator
TRUTH TABLE A4 9
84 10
Inputs Outputs A3 12
E A I B A<B A>B 83 11
2 A> 8
H X I X L L A2 13
Word A = Word B 82 14
L L L
Al 6
L Word A > Word B L H
81
L Word A < Word B H L AD 5 3 A<8
80 4
E 15
Po = 440 mW typ/pkg (No Load)
tpd = Data to output 6.0 ns tvp
E to output 2.5 ns typ

2·28
 INTEGRATED CIRCUITS
MECL 10.000 SERIES

3-1
 MECL 10,000 series
, QUAD 2-INPUT NOR GATE
WITH STROBE

MC10l00

Advance In~orIDatton
The MC10l00 is a quad NOR gate. Each gate has 3
inputs, two of which are independent and one of which is
tied common to all four gates. Input pulldown resistors
eliminate the need to tie unused inputs to a voltage
supply. Open emitter outputs permit wire-ORing and
direct connection to busses.
Po - 25 mW typ/gote (No Load)
tpd~ 2.0 n. typ

POSITIVE LOGIC NEGATIVE LOGIC

4 4
2 2
6 5

6 6
3 3
7
9 Vee1 - Pin 1 9
10 VCC2 :II: Pin 16 10
14 VEe· Pin 8 14
11 11

12 12
16 15
13 13
2-4+"5+9 2- 'i"i"'"5i9

SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS @l250 C

Input
Co..
Vin

25;
m
v e e1 '" vCC2
+2.0 Vdc

o~
r-----.., ",F
V out

COOK
PROPAGATION DELAY

Pulse Generator

Input Pulse
t+ == t- == 2.0 ±. 0.2 ns
(20 to 80%1

V out
--.j....o"T-
All input and output cables to the
scope are equal lengths of 50-ohm VEE = -3.2 Vdc
coaKia' cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.

Unused outputs connected to

a 50-ohm resistor to ground.

5O~hm termination to
ground located in each
scope channel input.

SH General Information Section for packaging and maximum ratlngl.

This II advance information and specifications are subject to change without notice.

3-3
 ...o...:s::
ELECTRICAL CHARACTERISTICS
Eaeh MECL 10,000 series circuit has been
(")
designed to meet the de specifications
shown in the test table, after thermal equi-
librium has been established. The circuit is o
in a test socket or mounted on a printed o
circuit bo ..d and transverse air flow greater
than 500 linear fpm is maintained. Outputs 8::I

-
are terminated through a S().ohm resistor to 5
.....
-2.0 volts. Test procedures are shown for 6 3 ::I
4 g§2
c:
1~
only one input and one output. The other L SUFFIX CD
inputs and outputs are tested in the same
manner. 14 CERAMIC PACKAGE ~
11 CASE 620
12 15
13

TEST VOLTAGE VALUES

CVolts)
@THt
T emp8fatur. VIHmax VILmin VIHAmin VILAmax VEE
I
-lOGe -0.890 -1.890 -1.205 -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
T8SoC -0.700 -1.825 -1.035 -1.440 -5.2
MC10100L Test Limits
w Pi"
TEST VOLTAGE APPLIED TO
~ Under -lOoC +250 C +85 oC PINS LISTED BELOW: CVCC)
Characteristic Symbol Test Min Ma. Min Typ Ma. Min Ma. Unit VIHmax VILmin VIHAmin VILAmax VEE Gnd
Power Supply Drain Current IE 8 - - - 21 26 - - mAde - - - - 8 1,16
Input Current linH 4· - - - 245 - - J.lAde 4· - - - 8 1,16
9 - - - - 470 - - J.lAde 9 - - - 8 1,16
linL 4· - - 0.5 - - - - J.lAde - 4· - - 8 1,16
Logic "1" Output Voltage VOH 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc - - - - 8 1,16
14 -1.060 -0.890 -0.960 -- -0.810 -0.890 -0.700 Vdc - - - - 8 1,16
Logic "0" Output Voltage VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 4,5.9 - - - 8 1,16
14 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 9,10,11 - - - 8 1,16
Logic "1" Threshold Voltage VOHA 2 -1.090 - -0.980 - - -0.910 - Vdc - - - 9 8 1,16
- -
t t
3 -1.090 -0.980 - - -0.910 - - - 9
14 -1.090 - -0.980 - - -0.910 - - - - 9
15 -1.090 - -0.980 - - -0.910 - - - - 9
Logic "0" Threshold Voltage VOLA 2
3
14
-
-
-
-1.655
-1.655
-1.655
-
-
-
-
-
-
-1.630
-1.630
-1.630
-
-
-
-1.595
-1.595
-1.595
Vdc

t
-
-
-
-
-
-
-
9
9
9
-
-
-
•
8 1,16

Switching Times
15 - -1.655 - - -1.630 - -1.595 - 9 -
Pul.ln Pulse Out
+
-3.2 V
+
+2.0 V
(50-ohm load)
Propagation Delav t4+2- 2 - - - 2.0 - - - ns - - 4 2 8 1,16
t4-2+ 2 - - - - - - - -
Rise Time
120% 10 80%1
Fall Time
C20% 10 80%)
'2+

'2_
2

2
-

-
-

-
-

- j -

-
-

-
-

- j -

-
-
- j j j j
·Individually test each input applying VIH or VI L to input under test.
 f 'I MECL 10,000 series~
L -_ _.... QUAD OR/NOR GATE
\.---------'~
MC10l0l

The MC10l0l is a quad 2-input OR/NOR

gate with one input from each gate common to
pin 12. Input pulldown resistors eliminate the
POSITIVE LOGIC NEGATIVE LOGIC need to tie unused inputs to an external supply.

4----~.-~,.---- 4

-;-~~---3 --~~--~~~---3

t----'L__.... ~--- 6 r---~ __ ~------6

10--~~,-~~-----14 10 ..t:.I1~'d"~---14

~-"----11 r---~ __~------11

P D = 25 mW typ/gate (No Load)
13 1---~~~~-15 13-+-~1--~~----15
tpd = 2.0 ns tvp
12 ~,.<.-"'-----9 12 9 Output Rise and Fall Time:
= 3.5 ns typ (10% - 90%)
= 2.0 ns typ (20% - 80%)

vee1 = Pin 1
VCC2 = Pin 16
VEE=Pin8

SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS@ 2SoC

Vin Vee1 = VCC2 V aut V aut

""' t I±""'
To Channel "A" +2.0 Vdc NOR OR

To PROPAGATION DELAY
Channel
"B"
Input --- - --...,
I +1.11 V
50%
Pulse Generator
' -____-J_ -------+0.31 V

Input Pulse
t+ = t- = 2.0 ±. 0.2 ns V aut OR
(20'080%)
Unused outputs connected to ,+
SO-ohm termination to
ground located in each
a 50-ohm resistor to ground. ,-
scope channel input. L ___ ~_ _ ..J
V out NOR
All input and output cabl.s to the
scope are equal length, of 50-ohm
eoaxial eable. Wire length should
be < 1/4 inch from TPin to input
I-= 0.1 ,.,.F

Din and TP out to output pin.

VEE: -3.2 Vdc

See General Information section for packaging.

3-5
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,000 series has been de· ...o
(')
signed to meet the de specifications shown
...o

"Ji' - ...
in the test table, after thermal equilibrium
has been established. The circuit is in a
5
test socket or mounted on a printed circuit
7 3
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
~4 L SUFFIX 8
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
10

11
CERAMIC PACKAGE
CASE 620
...
::J

::J
only one gate. The other gates are tested iJ 15 c:
'2 9 It!
in the same manner. c..

TEST VOLTAGE VALUES

(Volts)
@Test
Temperature VIHmax Vilmin VIHA min VILA max VEE
-lOoe -0.890 -1.890 -1.205 . -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.415 -5.2
+85o C -0.700 -1.825 -1.035 -1.440 -5.2
MC10101l Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
_lODe +25 0 C +8S0C
Undo< IVeel
Characteristic I Svmbol Test Min Ma. Min Tv. Ma. Min Ma. Unit VIHmax VIL min VIHA min VILA max Vee Gnd
I
W
c»
I Power Supply Drain Current
Input Current
I
Ie
linH
8

"
12 - ..
-

-
20
-
-
26
265
535
-
-
- -
-
-
mAde
~Adc
~Adc
-

4
12
-
-
-
-
-
-

-
8
8
8
1,16
1,16
1.1S
linL 4 0.5 - - - - ~Adc - 4 8 1,16
12 - - 05 - - - - "Ado - 12 - - 8 1,16
Logic "1"
Output Voltage
I VOH 5
5
-1.060
-1.060
-1.060
-0.890
-0.890
-0.890
-0.960
-0.960
-0.960 -
-0.810 -0.890
-0.810 -0.890
-0.810 -0.890
-0.700
-0.700
-0.700
Vdo 12
4
-
-
- -
-
8 1.16

-1.060 -0.890 -0.960 -0.810 -0.890 -0.700 + - - - - + +

Logic "0"
Output Voltage I VOL
I 5
5
1-1.890
f1890
-1.675
-1.675 -1.850
-1.850 -
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdo -
-
-
- -
-
-
8 1,16

-1.890 -1.675 -1.850 -1,650 -1.825 -1.615 12 - -

-1.890 -1.675 -1.850 - -1.650 -1.825 -1.615
+ 4 - - - +8 +
Logic "1"
Threshold Voltage I VOHA
I 5
5
1-1 .080
-1.080
- -0.980
-0.980
-
-
-
-
--0.910
-0.910 -
Vdo -
- -
12
4 -
- 1,16

1-1.080 -0.980 - -0.910 - - - 12

-1.080 -0.980 -0.910 -
+ - - 4
+8 +
Logic "0"
Threshold Voltage I VOLA I 5
5
I -
1.655
-1.655
-1.655 -
-
-
-
-1.630
-1.630
-1.630
- -1.595
-1.595
-1.595
Vdo -
-
-
-
-
-

-
12
12
4
-
1,16

Switching Times
-1.655 - - -1.630 - -1.595
+ 4 - + +
(5()..ohm loadl
Propagation Delay I '4+2- 2 1.0 3.1 1.0 2.0 2.9 1.0 3.3 n, -
Pulse In
4
Pul. Out
2
-3.2V
8
+2.0V
1,16

~ + ~ +
t4_2+ 2 2
t4+5+ 5 - 5
5
+ + -

j j j j
t4_5_

j
- 5
Rise Time '2+ 2 1.1 3.6 1.1 3.3 1.1 3.7 - 2

~ ~
120 to IICJ%I '5+ 5 - 5
Fall Time
(20 to 80%1 I '2_
'5_
2
5 + + + +
-
-
-
,
2
 3:
0
...A

ELECTRICAL CHARACTERISTICS C
...A

-
Each MECL 10,000 series has been de- C
...A
signed to meet the de specifications shown P SUFFIX
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
.~.
7
5
3
PLASTIC PACKAGE
CASE 648
g-
....
::J

board and tranSverse air flow greater than

500 linear fpm is maintained. Outputs are
10 ':4 S'
c
11 CD
terminated through a 50-ohm resistor to 13 15
Co
-2.0 volts. Test procedures are shown for
" 9
onlv one gate. The other gates are tested TEST VOLTAGE VALUES
in the same manner. (VoIt.1
IiiTost
Temperature VIH max Vil min V'HAmi" VILAma" VEE
-3O"c -0.890 -1.890 -1.205 -1.500 -5.2
+25 o C -0.810 _1.850 -1.105 -1.475 -5.2
+85o C -0.700 -1.825 -1.035 -1.440 -5.2
MC10101P Test Limits
Pi" TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Unci .. -JO"C +25o C +SSoC
(Veel
Characteristic Symbol To.. Min Ma. Min TV. Ma. Min Ma. Unit VIH ma. Vilmin VIHA min VILA mall( VEE GncI
Power Supply Drain Current IE 20 26 mAde 8 1,16
Input Current linH 4 265 /JAde 8 1,16
12 535 /JAde 12 8 1,16
W 0.5 4 8 1,16
linL 4 /JAde
..:... 12 0.5 .Ad, 12 8 1.16
Logic "1" VOH 5 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vd, 12 8 1,16
Output Voltage 5 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700
2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700

Logic "0" VOL

2 -1.060
-1.890
-0.890
-1,675
-0.960
-1.850
-0.810
-1.650
-0.890
-1.825
-0.700
-1.615
+
Vdc
+8 +
1,16
Output Voltage -1.890 -1.675 -1.850 -1.650 -1.825 -1.615
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 12
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615
+ 4
+8 +
LogiC "'"
Threshold Voltage
VOHA 1-1.080
-1.080
-0.980
-0.980
-0.910
-0.910
Vdc 12
4
1.16

-1.080 -0.980 -0.910 12

Logic "0"
I I
-1.080
-1.655
-0.980
-1.630
-0.910
-1.595
+
Vdc
4
12
+
8
+
1.16
Threshold Voltage VOLA
I = -1.655
-1.655
-1.630
-1.630
-1.595
-1.595 12
4

Switching Times
-1.655 -1.630 -1.595
+ 4
+ +
(5().ohm load)
Propagation Delay I '4+2- 1.0 2.0 2.9
Pulse In
4
PuI.Out -3.2 V +2.0V
1,16

~
l4-2+
l4+5+
+
j j 1 j
t4-5-
AiseTime '2+ 1.1 3.3

1
(20 to 80%) '5+
Fall Time
(20'0_1
'2_
'5- ~ ~
L-._ _.....
f QUAD 2-INPUT NOR GATE
"\ MECL 10,000 series
~"'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'

MC10102

The MC10l02 is a quad 2-input NOR gate,

Input pulldown resistors eliminate the need to
tie unused inputs to an external supply,
POSITIVE LOGIC NEGATIVE LOGIC

:~2 :=::=:cr--- 2

:~3
,O~ '4 ,O~
:=::=:cr--- 3

'4
"~ "~ Po"" 25 mW typ!gate (No Load)
tpd :: 2.0 ns typ
12~15 '2~'5
Output Rise and Fall Time:
13~9 '3~9 = 3.5 nstvp (10% - 90%)
= 2.0 n$ typ (20% - 80%)

vee1 "" Pin 1

VCC2::: Pin 16
VEE=Pin8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC

Vin Vee1 = VCC2 V out V out

To Channel "A" +2.0 Vdc NOR OR

Input
1
'''',---± ---,
±""' To
Channel
"S"
PROPAGATION DELAY

Pulse Generator U>--+

Input Pulse
t+ ::: t- = 2.0 ±. 0.2 ns ~ V out OA

~
(20 to 80%)

I I
50·ohm termination to
9'0 und located in each V out NOR
L ___ ~_ _ -l
scope channel input,
Unused outputs connected to
All input and output cables to the a 50-ohm resistor to ground.

:~~~a~~a:~~81~~:t~~::h5~~~~:
be < 1/4 inch from TPin to input -
l 0.1 JlF
pin and TP out to output pin. VeE = -3.2 Vdc

See General I nformation section for packaging.

3-8
 ELECTRICAL CHARACTERISTICS s:
Each M·ECL 10.000 series has been de·
signed to meet the de specifications shown
....
(")

o
in the test table. after thermal equilibrium
has been established. The circuit is in a
....
o
test socket or mounted on a printed circuit N
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are :~2 8
terminated through a 50-ohm resistor to

-
-2.0 volts. Test procedures are shown for
onlv one gate. The other gates are tested
:~3 =.c:
::J

::J
in the same manner. 10~ 14 L SUFFIX
11
CERAMIC PACKAGE ~
t2~15
CASE 620
lJ~9

TEST VOLTAGE VALUES I

(Voltsl
@Test
T emperatur. VIH max VIL min VIHAmin \(ILAmax VEE
_30 D e -0.890 -1.890 -1.205 -1.500 -5.2
+250 C -0.810 -1.850 -1.105 -1.475 -5.2
+85 0 C -0.700 -1.825 -1.035 -1.440 -5.2
MC10102L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Undo<
lOoe +25 o C +SSoC (Vee l
w Characteristic Symbol Te.. Min Ma. Min Tvp Ma. Min Ma. Unit VIH max VILmin VIHA min VILA max VEE G"d
cO Power Supply Drain Current 'E 8 20 26 - mAdc - 8 1,16
I nput Current linH 12 - - 265 - ,&lAde 12 8 1,16
IlnL 12 0.5 - - ,&lAde 12 8 1,16
Logic "1" VOH 9 1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 12 8 1,16
Output Voltage 9 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 13 -
15 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 -

Logic "0" VOL

15
9
-1.060
-1.890
-0.890
-1.675
-0.960
-1.850
-0.810
-1.650
-0.890
-1.825
-0.700
-1.615
+
Vdc
-
-
-
-
+
8
+
1,16
Output Voltage 9 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 - -
15 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 12

Logic "1" VOHA

15
9
-1.890 -1.675
-1.080
-1.850
-0.980
-1.650 -1.825
-0.910
-1.615
+
Vdc
13
12
+8 +
1.16
Threshold Voltage 9 -1.080 -0.980 -0.910 13
15 -1.080 .. -0.980 -0.910 - 12

Logic "0" VOLA

15
9
-1.080
-1.655
- -0.980
-1.630
-0.910
- -1595
-
+
Vdc -
13
12
+
8
+
1.16
Threshold Voltage 9 - -1.655 -1.630 -1.595 13
15 - -1.655 -1.630 -1.595 12

SWltchmg Times
15 - -1.655 - -1.630 - -1.595
+ 13
+ +
(50-ohm load) Pulse In Pul. Out -3.2V +2.0 V
Propagation Delay t12+15- 15 1.0 3.1 1.0 2.0 2.9 1.0 3.3 - - 12 15 8 1.16
"'
~
112-15+ 15 - - 15
112+9+ 9 - - 9

+ + + -

•~
9

• j
9

j
-

j j j
t12-9-
R,seTime 115+ 15 1.1 3.6 1.1 3.3 1.1 3.7 - - 15

~ ~
120 to 80%1 '9+ 9 - - 9
Fall Time 115_ 15 - - 15
'9_ 9 + + - - 9

•
120 to 80%)
 s:(')
ELECTRICAL CHARACTERISTICS
...o
...
Each MECL 10,000 series has been de-
signed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a o
N
:~2

-
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are :~3
8
terminated through a 5<H»hm resistor to ....
::I

-2.0 volts. Test procedures are shown for ,O~

11
,. PSUFFIX
PLASTIC PACKAGE
5'
I:
only one gate. The other gates are tested
in the same manner. '2~'5
13~9
CASE 648
~

TEST VOLTAGE VALUES

(Voltsl
@Tost
T emperatur. VIH max VILmin VIHAmin VILAm •• VEE
_lODe -0.890 -1.890 -1.205 -1.500 -5.2
+25 o C -0.810 -1.850 -1.105 -1.475 -5.2
+8So C -0.700 -1.825 -1.035 -'.440 -5.2
MCl0102P Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
u ..... _lODe +2Soc +85o C (Veel
y Ch.ract.istic Symbol To" Min Mo. Min Ty. Ma. Min Ma. Unit VIHmax VILmin VIHA min VILA max VEe G...
~
I Power Supply Orain Current Ie 20 26 mAde 1,16
0 I Input Current linH 12 265 ,.,Adc 12 1,16
linL 12 0.5 ,.,Ade 12 1,16
Logic "1" VOH 9 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 12 8 1,16
Output Voltage 9 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 13
15 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700

Logic "0" VOL

15
9
-1.060
-1.890
-0.890
-1.675
-0.960
-1.850
-0.810
-1.650
-0.890
-1.825
-0.700
-1.615
+
Vdc
+8 +
1,16
Output Voltage
I I 9
15
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615 12
15 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615
+ 13
+8 +
Logic "'"
Threshold Voltage I VOHA I 9
9
-1.080
-1.080
-0.980 -0.910 Vdc 12 1.16

~
-0.980 -0.910 13
15 -1.080 -0.980 -0.910 12
15 -1.080 -0.980 -0.910
+ 13
+
Logic "0"
Threshold Voltage
I VOLA
I
9
9
-1.655
-1.655
-1.630
-1.630
-1.595
-1.595
Vdc 12
13
8 1.16

15 -1.655 -1.630 -1.595 12

Switching Times
15 -1.655 -1.630 -1.595
+ 13
+ +
ISO-ohm load)
Propagation Delay I '12+15- 15
15
1.0 2.0 2.9
Pulse In
12
PuI.Out
15
-3.2V
8
+2.0 V
1.'6

~
t12-15+ 15

I':::
t12+9+ 9 9
+
j j
9

j j j
9
AiseTime 15 1.1 3.3 15
9

~
C20 to 8O%J '9+ 9
Fall Time t15_ 15 15

•
(20 to acn.1 '9- 9 9
 MC10l03
Advance In~orD'l.atlon

The MC10l03 is a high-speed, low-power

quad 2-input OR gate_ One of the gates has
both OR and NOR outputs_ Input pulidown
resistors eliminate the need to tie down unused
inputs_
POSITIVE LOGIC NEGATIVE LOGIC

4
5 :[)--2 :=::[J--2
6
=L>--3 ~=.:[)--3 Po'" 25 mW typ/gate (No Load)
tpd:E 2.0 nt t:yp

:: -----':-...0:= 1:
12~15
13~9
10
11
:[)--14 11 10==:[)=-- . 14
veel "" Pin 1
VCC2 ~ Pin 16
VeE = Pin 8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @125°C

V out
NOR

PROPAGATION DELAY

Coax Coax

Input +1.11 V
50%
Pulse Generator ' - - - - - - ----+0.31 V
Input Pulse
t+ - t- = 2.0 ±. 0.2 ns
(20 to 80%1 t:L>+ I V out OR

SO-ohm termination to
~ Unused outputs connected to
ground located in each
~-f a 50·ohm resistor to ground.
scope channel input.
V out NOR'

"--n-:'"'
VEE = -3.2 Vdc

All input end output cabl•• to the ICOpti .r. equal lengths of 50-ohm coexlal C8bl •.
Wire length should be< 114 inch from TPln to input pin end TPout to output pin.

See G.n .... ' Information Metlon for packaging and maximum r8tingl.
Thill, advance Information and .peclflc.tionl ar. subject to change without notice.

3·11
 ELECTRICAL CHARACTERISTICS 3:
Each MECL 10,000 series circuit has been ...o
("')
designed to meet the de specifications
shown in the test t~le. after thermal equi-
librium has been established. The circuit is
...o
in a test socket or mounted on a printed w
circuit bo.d and tr.,werse air flow greater C')
than 500 linear tpm is maintained. Outputs o
are terminated through a 50-ohm resistor to
-2.0 volts. -Test procedures are shown for
:~2 =.
:::l

:::l

-
c:
;~3
only one input and one output. The other
CD
inputs and outputs are tested in the ~me
L SUFFIX
a.
manner.
12~'5 CERAMIC PACKAGE
13~9 CASE 620

10~'4
"~

TEST VOLTAGE VALUES

IVolts)
Ii! T",
Temp .... tur. VIHmex VILmin VIHAmin VILAm •• VEE

ctJ -30"<: -0.890 -1.890 -1.205 -1.500 -5.2

..... +2SoC -0.SI0 -1.S50 -1.105 -1.475 -5.2
~
+8SoC -0.700 -1.S25 -1.035 -1.440 -5.2
MC10103L Test Limits TEST VOLTAGE APPLIED TO
Pi"
Undof _30 oe +2SoC +85oC PINS LISTED BELOW: (Vee)
CharK.,iltic Symbol T. . Min M •• Min Typ M •• Min M .. Unit VIHmax VILmin VIHAmin VILAm.x VEE Gnd
Power SupplV Drain Current Ie S - - - 21 26 - - mAde - - - - 8 1,16
Input Current linH 4" - - - - 245 - - IolAde 4" - - - 8 1,16
'inL 4" - - 0.5 - - - - IolAde - 4" - - 8 1,16
Logic "'" Output Voltage VOH 2 -1.060 -0.890 -0.960 - -0.SI0 -0.S90 -0.700 Vdc 4,5 - - - 8 1,16
9 -1.060 -0.890 -0.960 - -O.SIO -0.890 -0.700 Vdc - - - - S 1,16
Logic "0" Output Voltage VOL 2
9
-1.S90
-1.S90
-1.675
-1.675
-1.850
-1.S50
-
-
-1.650
-1.650
-I.S25
-1.S25
-1.615
-1.615
Vdc
Vdc
-
12,13
-
-
-
-
-
-
S
8
1,16
1,16
L.ogic "'" Threshold Voltage VOHA 2 ·1.080 - -0.980 - - -0.910 - Vdc - - 4,5 - 8 1,16
9 ·1.080 - -0.9S0 - - -0.910 - Vdc - - - 12,13 8 1,16
Logic "0" Threshold Voltage VOLA 2
9
-
-
-1.655
-1.655
-
-
-
-
-1.630
-1.630
-
-
-1.595
-1.595
Vdc
Vdc
-
-
-
-
-
12,13 -
4,5 8
S
1,16
1,16
Switching Times Pul.ln Pul.Out -3.2 V +2.0 V
(5O-ahm load)
Propagation oalav t4+2+ 2 - - - 2.0 - - - n. - - 4 2 S 1.16
t'2+9· 9 - - - - - - - - 12 9
Rise Tin.
(20%'0 SO%)
FaU Ti,...
(20%'080%)
'2+

'2_
2

2
-
-
-

-
-

- j -

-
-

-
-

- j
-

-
-

-
4

4
2

2 j j
·Individu:ellv Iftt .ach input eppIving VIH or VtL to input undar talt.
L -_ _.... f QUAD 2-INPUT AND GATE
' MECL 10,000 series
"'-...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'

MC10l04

The MC10l04 provides a very useful low power, high

speed logic AND function. High Z input pulldown resistors
allow high dc and ac fanouts and eliminate the need to
tie unused inputs to an external supply. The open emitter
outputs allow maximum flexibility in the selection of ter-
Po = 35 mW typ/gate (No load) mination techniques and minimize the power requirements
lpd = 2.7 ns typ when driving transmission lines. Open emitter outputs
Output Rise and Fall Times: also allow wire-ORing capability, which is very useful in
~ 3.5 ns typ (10% - 90%) control, bussing, and communications in high speed central
= 2.0 ns tYP (20% - 80%) processors, high speed peripherals, digital communications
systems, minicomputers and instrumentation.

POSITIVE LOGIC NEGATIVE LOGIC

:~2
;~3
10~ 14 10~ ~14
11 11~
12'~9 12~9
13~15 13~15
veel = Pin 1
VC C2 == Pin 16
VEE == Pin 8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC

Vin veel = VCC2 Your Your

To Channel "A" +2.0 Vdc NAND AND

PROPAGATION DELAY
To
Channel
"8"
Input

Pulse Generator

Input Pulse
t+ = t- = 2.0 ±. 0.2 ns Your AND
(20 to 80%)

+1.11V~
L __ ~_..J
0.1"F J Unused outP~ts connected to
a 50-ohm resistor to ground.

~0.1"F
SO-ohm termination to
ground located in each
VEE = -3.2 Vdc
SCOpe channel input.
All input and output cabl., to the scope ar. equallengthl of 50~hm coaxial CIIbl•.
Wlr. length thould be< 1/4 inch from TP'n to input pin and TPout to output pin.

s~ G.".,..I Information Section for packaging and maximum ratings.

3-13
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,000 series has been de·
...o
(')
signed to meet the de spacifications shown
in the test table, after thermal equilibrium ...

-
~
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear 'pm is maintained. Outputs are :~2 L SUFFIX n-
O
CERAMIC PACKAGE
terminated through a 5O-ohm resistor to
....
::J
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
:~3 CASE 620
3"
c:
in the same manner. 10~""14 (I)

"~ Co
12~9
TEST VOLTAGE VALUES
13~15
Volts
ilTost
Temperatur. VIH m •• Vil min VIHAmin VILAm.. VEE
-30"<: -0.890 -1.890 -1.205 -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+8S o C -0.700 -1.825 -1.035 -1.440 -5.2
MC10104L Test Limits
TEST VOLTAGE APPLIEO TO PINS LISTED BLEOW,
-lOOC +25 0 C +850 C
(Vec'
Ch..acteristic Symbol I Tnt Min I Max Min Typ I Max Min I Mu Unit VIH max VILmin VIHAmin VILAl'ftllx VEE Gnd
Power SupplV Drain Current 'E 8 28 35 mAdc 8 1.16

-cp
Input Current linH· 12 265 /JAdc 12.13 8 1.16
13 220 /JAdc 13 8 1.16
.;:. linL 12 0.5 /JAde 12 8 1.16
Logic "1"
Output Voltage
VOH 15
9
-1.060
-1.060
I -0.890
-0.890
I -0.960
-0.960
-0.810 1-0.890 1-0.700
-0.810 -0.890 -0.700
I Vdc
Vdc
12.13 8 1.16
1,16
Logic "0" VOL 15 -1.890 1-1.675 -1.850 -1.650 1-1.825 -1.615 Vdc 1.16
Output Voltage 9 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 12,13 1,16
Logic "1" VOHA 9 -1.080 -0.980 -0.910 Vdc 12 8 1.16

~ ~ ~
Threshold VOltage 9 -1.0BO -0.980 -0.910 13

Lgolc "0"
15
15
-1.080
-1.080
-{I.980
-0.980
-0.910
-0910
12
13 I -
-

-
I 13
12 I -
-
-
I I I
VOLA 9 -1.655 -1.630 -1.595 Vdc 12 13 8 1.16
-
~
Threshold Voltage

~
9 -1.655 -1.630 -1.595 13 - 12
15 -1.655 -1.630 -1.595 12
15 -1.655 -1.630 -1.595 13
Switching Times· +1~ Pulse In Pul_Out -3.2 V +2.0V
(50-ohm load)
Propagation Delay t12+15+ 15 1.0 4.3 1.0 2.2 4.0 1.0 4.2 13 - 12 15 8 1.16

~
15

~
15

~
'12-15-
112+9- 9 - 9
t12-9+ 9 - 9
t13~15+ 15 2.7 12 - 13 15
t13+9- 9 2.7 12 - 13 9
Rise Time t15+ 15 1.5 37 1.5 3.5 1.5 3.6 - 15

~
(20 to 80%1 19+ 9 - 9
Fall Time
(20 '080%1
t15-
19_
15
9
j l T l t -
- t 15
9

·Inputs 4,7, 10, and 13 will behave similarly for ac and linH values.
InputI5.S. 11 • .,d 12wil~ beh ..... ir:n~~y for K and linH Ylllu~.
 ELECTRICAL CHARACTERISTICS
3:.
(')
E.... MECL 10.000 ......... been de· -"
ligned to ..-1 the de _ificalionl shown o
-"
in the test bbll, 8fter th_mll equilibrium
o.p.

•
. . been ntablilhed. The circuit is in I
test mcket or mounted on I printed circuit
boerd and ,,.nwe,.. lir flow gr••tar than
:~2 P SUFFIX 8:J
500 lin. . fpm is mlinhined. Outputs .r.
••min.ted through • 5O-ohm resistor to
PLASTIC PACKAGE ...s·
-2.0 volts. Test procedures ara shown for ~~3 CASE 648
c
only ona gate. The other gates ar. tested CD
,.~- a.
in the ume manner. 11~'4
12~9
13 15 TEST Val TAGE VALUES
Volts
@Test
Temperatur. VIH mall( VIL min VIHA min VILA max VEE
-30 oe -0.890 -1.890 -1.205 -1500 -5.2
+25 o C -0.810 -1.850 -1.105 -1.475 -52
+85"c -0.700 -1.825 -1.035 -1.440 -5.2
MC10104P Test Limits
TEST VOLTAGE APPLIED TO PINS LISTED BlEOW,
-lOoe +25"c +8SoC 1Veel
Ch..8Cteriscic Symbol Toot Min Mo. Min Ty. M•• Min M •• Unit VIH max Vil min VIHAmin VILA max VEE Gnd
Power Supply Drain Current IE 8 - - - 28 35 - - mAde - - - - 8 1.16

C:J Input Current linH- 12 - - - - 265 - - /lAde 12.13 - - - 8 1.16

..... 13 - - - - 220 - - J.lAdc 13 - - - 8 1.16
U1 linL 12 - - 0.5 - - - - jJAdc - 12 - - 8 1.16
Logic "1" VOH 15 -1.()60 -0.890 0.960 -0.810 0.890 -0.700 Vdc 12.13 8 1.16
Output Voltage 9 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc - - - 8 1,16

Logie "0" Val 15 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc - - - - 8 1.16
OutPUt Volt. 9 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 12.13 - - - 8 1,16
Logic "1" VOHA 9 -1.080 - -0.980 - - -0.910 - Vdc - - - 12 8 1,16
-
~ ~ ~
Threshold Voltage 9 -1.080 - -0.980 - - -0.910 - - 13
15 -1.080 - -0.980 - - -0.910 - 12 - 13 -
15 -1.080 - -0.980 - - -0.910 - 13 12 -
Lgoic "0" VOLA 9 - -1.655 - - -1.630 - -1.595 Vdc 12 - 13 - 8 1.16
-
~
- - - - -
~
Threshold Voltage 9 -1.655 -1.630 -1.595

~
13 12
15 - -1.655 - - -1.630 - -1.595 - - _. 12
15 - -1.655 - - -1.630 - -1.595 - - - 13
Switching Tim.- +1.11 V Pulse In Pulse Out -3.2 V +2.0V
(50-ohm 1... 1
Propegetion Delay t'2+15+ 15 - - 1.0 2.2 4.0 - - ns 13 - 12 15 8 1.16

~
15 - - 15

~ ~
- -
tI2-15-
-

I
'12+9- 9 - - - - 9
t12-9+· 9 - - - - - 9
t'3"'5+ 15 - - 2.7 - - 12 - 13 15
'13+9- 9 - - 2.7 - - 12 - 13 9
Rise Time t15+ 15 - - 1.5 2.0 3.5 - - - 15

! ! !
- - - -
,I
120 to 110%1 t9+ 9 - 9
FeU Time
120 t.80%1
tl5-
t9-
15
9
-
-
-
-
-
-
-
- t -
-
15
9

-lnputs4, 7.10. and 13 will behave simil.ly for ac and I inH valulS.
Input'S. 6, " , and 12 will behave similarly for a: and linH vatues.
 MECL 10,000 series
TRIPLE 2-3-2 INPUT
OR/NOR GATE

MC10l05

The MC10l05 isa triple 2-3-2 input OR/NOR

gate. Input pulldown resistors eliminate the need
to tie unused inputs to an external supply.
POSITIVE LOGIC NEGATIVE LOGIC

:~:
4~3
5~2

1:~~ 1:~~
11~ 11~
Po = 30 mW typ/gate (No Loa(H
13~14 13~14
tpd = 2.0 ns typ
12~15 12~15 Output Rise and Fall Time
=::: 3.5 ns typ (10%-90%)

"" 2.0 ns typ (20%-80%)

veel : : Pin 1
VCC2 = Pin 16
VEe =Pin8

SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS @ 25°C

VCC1 = VCC2 V out V out

+2.0 Vdc NOR OR
PROPAGATION DELAY

Coax Coax

~
Input Puis.
t+ = t- "" 2.0 ±. 0.2 ns
(20 to 80%1 V out OR

50-ohm termination to ~
ground located in each ~ Unused outputs connected to
scope channel input. L _ _ _ _ __ -I a 50-ohm resistor to ground.

All input and output cables to the

scope are equal lengths of 50-ohm
~ V out NOR
coaxial cable. Wire length should I 0.1 jJF
be < 1/4 inch from TP in to input _
pin and TP out to output pin. -

VeE = -3.2 Vdc

s .. Ganeral Information _c:tion for packa"ln".

3-16
 ELECTRICAL CHARACTERISTICS 3:
(')
Each MECL 10,000 series circuit has been ...,
designed to meet the de specifications o...,
shown in the test table, after thermat equi·
librium has been established. The circuit is
in a test socket or mounted on a printed
~
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs 8
are terminated through a 50-ohm resistor to ....
::J

-2.0 volts. Test procedures are shown for ::J

c:

-
only one input and one output. The other
inputs and outputs are tested in the same ~
manner. 4~3 L SUFFIX
'~2 CERAMIC PACKAGE
9 CASE 620
10~~'
11~
lJ~14
12~15

TEST VOLTAGE VALUES

(V ....,
@IT ...
C:-l
..... Temperllture VIH max VILmin VIHAmin VILA max VEE
'-I -lOoe -0.890 -1.890 -1.205 -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+8So C -0.700 -1.825 -1.035 -1.440 5.2
MCl0105L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Under -3IJOe +25 o C +8Soc (Vee)
Characteristic Symbol Te" Min Max Min TVp Ma. Min M.. Unit VIH max VILmin VIHA min VILA max VEE Gnd
Power Suppty Drain Current Ie 8 - 17 21 - mAdc - - - 8 1.16
tnput Current tinH 4 - 265 - - /JAdc 4 - - - 8 1,16
tinL 4 0.5 - - - /JAdc - 4 - - 8 1.16
LogiC "1" VOH 3 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vd, - - - 8 1,16
Output Voltage 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vd, 4 - - - 8 1.16
LogiC "0" VOL 3 1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vd, 4 - - - 8 1,16
Output Vottage 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vd, - - - - 8 1,16
LogiC "'" VOHA 3 -1.080 -0.980 -0.910 - Vd, - - - 4 8 1,16
Threshotd Voltage 2 -1.080 - -0.980 - -0.910 - Vd, - 4 - 8 1,16
LogiC "0" VOLA 3 -1.655 -1.630 -1.595 Vd, - 4 - 8 1,16
Threshotd Voltage 2 - -1.655 - - -1.630 -1.595 Vd, - - - 4 8 1.16
SWitching Times
(50-ohm toad) Pulse In Pul.Out -3.2 V +2.0V
Propagation Detay t4+3_ 3 1.0 3.1 1.0 2.0 2.9 1.0 3.3 - - 4 3 8 1,16
t4-3+ 3 "' - - 3

I I I
14+2+ 2 - - 2
+ 3.6+ +
j + + +
j
14_2_ 2 - - 2
Rise Time 3 1.1 1.1 3.3 1.1 3.7 - - 3
'3'

~ ~ ~ ~ ~ ~
(20 to 80%) '2' 2 - - 2
Fait Time '3_ 3 - - 3
(20 to 80%1 '2- 2 - - 2
 ELECTRICAL CHARACTERISTICS
3:
(')
Each MECl 10,000 series circuit has been
--o
designed to meet the de specifications
shown in the test table. after thennal equi-
librium has been established. The circuit is
in 8 test socket or mounted on a printed
--~
circuit bo_d and transverse air flow greater 8
th., 500 line.. fpm is maintained. Outputs
are terminated through a S(k)hm resistor to
...5'
:I

-2.0 volts. Test procedures are shown for c:

only one input and one output. The other ~

-
inputs and outputs are tested in the same
manner.
'~3 PSUFFIX
5~2
PLASTIC PACKAGE
.~. CASE 648 .
10~7
"1~~14
':Z~'5

TEST VOLTAGE VALUES

IVoIts)

'fl "Test

--
(XI
Temper8lure
_lODe
+25o C
VIH max
-0.890
-0.810
VIL min
-1.890
-1.850
VIHA min
-1.205
-1.105
VILA max
-1.500
-1.475
VeE
-5.2
-5.2
+8SoC -0.700 -1.825 -1.035 -1.440 5.2
MC10105P T_ limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Under -300e +2SoC +850 C (Vee l
Chllracteristic SVmbol Test Min Max Min TV. Ma. Min Ma. Uni1 VIH max VIL min VIHAmin VILAm8x VeE Gnd
Power Supply Drain Current 'E 8 - - - 17 21 - - mAde - - - 8 1,16
Input Current linH 4 - - - - 265 - - j.lAdc 4 - - - 8 1,16

Logic "1"
linL
VOH
•
3
- -
-1.0GO -0.890
0.5
-0.960
-
-
-
-0.810
-
-0.890
-
-0.700
-",Adc
Vdo
-

-
4 -

-
-
-
8
8
1,16
1.16
Output Voltage
Logic "0" VOL
2
3
-1.060 -0.890
-1.890 -1.675
-0.960
-1.850
- -0.810
-1.650
-0.890
-1.825
-0.700
-1.615
Vdo
Vdo
•
4
- -
-
- 8
8
1.16
1,16
Output Voltage 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdo - - - - 8 1,16
Logic "1"
Threshold Voltage
VOHA 3
2
-1.080
-1.080 -
-0.980
-0.980 -
- -0.910
-0.910 -
Vdo
Vdo - - 4
•
-
8
8
1,16
1,16
Logic "0" VOLA 3 -1.655 -1.630 -1.595 Vdc 4 8 1,16
Threshold Voltage 2 - -1.655 - - -1.630 - -1,595 Vdo - - - 4 8 1,16
Switching Times
(50-ohm load) Pulse In Pulse Out -3.2 V +2.0V
Propagation Delay '4+3- 3 - - 1.0 2.0 2.9 - - n, - - 4 3 8 1,16
3 - - - - - - 3

II
14-3+
14+2+ 2 - - - - - - 2

j •~ -
j j
- - - -

•~
14-2- 2 - 2
Rise Time '3+ 3 - - 1.1 3.3 - - - - 3
(2010~) '2+ 2 - - - - - - 2
Fell Time '3- 3 - - - - - - 3
(2010_1 '2_ 2 - - - - - - 2
 MECL 10,000 series
TRIPLE 4-3-3 INPUT
NOR GATE

MC10106

The MC10l06 is a triple 4-3-3 input NOR

gate_ Input pulldown resistors eliminate the need
to tie unused inputs to an external supply_
POSITIVE LOGIC NEGATIVE LOGIC

1:~--2 1:~2
11~ 11~ Po "" 30 mW tvp/gata (No Load)
tpd = 2.0 ns typ
12~ 12~
13
14
15 13~15
14
: 3_5 n.
Output Rise and Fall Time
typ (10% - 90%)
::z: 2.0 ns typ (20% - 80%)

veel = Pin 1
VCC2 "" Pin 16
Vee = Pin 8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C

Vee, ~ Vee2
+2.0 Vdc

''''i~''''
PROPAGATION DELAY

Coax Coax

Input r-- --, ,.-----+1.11 V

I
I
-----+0_31 V
I
I
Input Pulse
~! V

~
t+:::; t- = 2.0±. 0.2 ns out
120 to 80%)

5O~hm termination to ground lo-

cated in each scope channel input. ~nu"'d
'- --ti _..J
outputs connected to
• 50-ohm ,.sisto, to g,ound_
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
N < 1/4 inch from TP in to input
! ~O.II'F
pin and TP out to output pin.
Vee' -3.2 Vdc

&H Oen.,.llnformatlon section for packaging.

3-19
 ELECTRICAL CHARACTERISTICS
s:
Each MECL 10,000 series circuit has been
designed to meet the de specifications
n
.....
shown in the test table, after thermal equi- o
.....
librium has been established. The circuit is
in a test socket or mounted on a printed o0)
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
only one input and one output. The other
:~3
7
8::J
~,
::J
inputs and outputs are tested in the same C
9~2

-
(I)
manner. IO~ Co
11

12~'5 L SUFFIX
13~ CERAMIC PACKAGE
14 CASE 620

TEST VOLTAGE VALUES

(Volts)
ctJ @Test

'"0 Temperature
_lOGe
VIH max
-0.890
VILmin
-1.890
VIHA min
-1.205
VILAma.
-1.500
VEE
-5.2
+250 C -0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.100 -1.825 -1.035 -1.440 -5.2
MCl0106L Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Und.. -3O"c +2SoC +85o C 1VCCI
Characteristic 1 Symbol Te .. Min Max Min TV. Max Min Max Unit VIH max VILmin VIHAmin VilA max VEE Gnd
Power Supply Drain Current 'E 8 17 21 mAde 1,16
Input Current
l l,n H
ImL 4 0.5
265 .,Adc
~Adc
1.16
1.16
Logic "'" VOH 3 -1._ -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 1,16
Output Voltage 2 -1.060 -0.890 -{).960 -0.810 -0.890 -{).7oo Vdc 1,16
Logic "0" VOL 3 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 4 8 1,16
Output Voltage 2 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 9 8 1,16

Logic "'" VOHA -1.080 -0.980 -0.910 Vdc 8 1,16

Threshold Voltage -1.080 -{).980 -0.910 Vdc 8 1,16
Logic "0" VOLA -1.655 -1.630 -1.595 Vdc 8 1,16
Threshold Voltage -1.655 -1.630 -1.595 Vdc 8 1,16
Switching Times
(50-ohm load)
Pulse In Puis. Out -3.2 V +2.0 V

Propagation Delay 14+3- 1.0 3.1 1.0 2.0 2.9 1.0 3.3 4 3 1.16
t4-3+ 1.0 3.1 1.0 2.9 1.0 3.3
Rise Time '3+ 1.1 3.6 1.1 3.3 1.1 3.7
120'080%'
Fa.. Time
12111080%'
,~
1 1.1 3.6 1.1 1 3.3 1.1 3.7 1 1 1 1 1
 ELECTRICAL CHARACTERISTICS 3:
Each MECl 10,000 ..,ies circuit has been n
...a
designed to meet the dc specifications
shown in the test table, after thennal equi- C
...a
librium has been established. The cirC1lit is
C
in a test socket or mounted on 8 printed en
circuit bo ..d and tr.,sverse air flow greater
th... 500 linear fpm is maintained. Outputs
are terminated through a 50-0hm resistor to
g
-2.0 volts. Test procedures are shown for ....
:l
:;'
:~3
only one input and one output. The other t:
inputs and outputs are tested in the same CD
Co
manner.

-
7
9

'0~
11~2
P SUFFIX
PLASTIC PACKAGE
12 CASE 648
'3~
14~'5

TEST VOLTAGE VALUES

(Volts)
Co) @Test
~ Temperature VIH max Vilmin VIHA min VILA max VEE
_30 D e -0.890 -1.890 -1.205 -1.500 -52
+250 C -0.810 -1.850 -1.105 -1475 -52
+8SoC -0.700 -1.825 -1.035 -'440 -52
MC10106P Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Und. -3O"c +2SoC +8So c (Vee'
Chlnct.,istie I Symbol Test Min Mo. Min TVp Max Min Max Unit VIH max VIL min VIHAmin VILA max VEE Gnd

Power Sup~y Oram Current Ie 17 21 mAde 1.16

Input Current
l Im H
4 0.5
265 J..IAde
J..IAdc
1.16
1.16
ImL
LogiC "1" VOH 3 -1.060 -0.890 -0.960 -0.810 -0.890 -0 700 Vdc 1,16
Output Voltage 2 -1.060 -0.890 --0.960 -0.810 -0.890 -0700 Vdc 1.16
LogiC "0" VOL 3 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 4 8 1,16
Output VOltage 2 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 9 8 1,16

LogiC "1" VOHA 3 -1.080 -0.980 -0.910 Vdc 1,16

Threshold Voltage 2 -1.080 -0.980 -0.910 Vdc 1.16
Logic ..a" VOLA 3 -1.655 -1.630 -1.595 Vdc 1.16
Threshold VOltage 2 -1.655 -1.630 -1.595 vdc 1,16
Switchmg Times +-2.0 V
Pulse In PulseOul -3.2 V
ISO-ohm loacl)
Propagation Delay t4+3- 1.0 2.0 2.9 4 1.16
t4-3+ 1.0 2.9
Rise Time '3' 1.1 3.3
120'080%1
Fall Time
120'080%1
1~ 1 1.1 1 3.3 1 1 1 1 1
 TRIPLE 2-INPUT EXCLUSIVE MECL 10,000 series
"OR"/EXCLUSIVE "NOR"

MC10l07

This three gate array is designed to provide

the positive logic Exclusive OR and Exclusive
NOR functions in high speed applications.
POSITIVE LOGIC NEGATIVE LOGIC
Input pulldown resistors eliminate the need to
tie unused inputs to VEE·
:~:
4~2
5~3
9~11 9~11
7~IO 7~IO
'4~'2 14~12
15~13 15~13
Po = 40 mW typ/gat8 (No Load)
3 : (4 • 5) + (4 • 5) 3 :=; (4 .5) + (4 • 5)
tpd "" 2.5 ns typ
2 : (4 • 5) + (4 • 5) vee1 "" Pin 1 2: (4 • 5) + (4 • 5)
Output Ri .. and Fall Time.
VCC2::::S Pin 16 "" 2.5 n. typ (20% to 80%)
VeE"" Pin 8 "" 3.5 ns typ (10% to 90%)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C

V out V out
VCCI : vCC2 EXCLUSIVE- EXCLUSIVE-
+2.0 Vdc NOR OR
PROPAGATION DELAY

Coax Coax

-+1.11 V

Input Pulse
V out EXCLUSIVE-NOR
t + = t- "" 2.0 ± 0.2 ns
(20 to 80%)
t+
t-
50-ohm termination to ground lo-
cated in each scope channel input.
V out EXCLUSIVE-OR
All input and output cables to the
scope are eQual lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin. VIH VEE: -3.2 Vdc

Unused outputs connected to

8 50-ohm resistor to ground.

See General I nformation section for packaging.

3-22
 ELECTRICAL CHARACTERISTICS ~
n

-
Each MECL 10,000 _ies circuit has been ...a
designed to meet the de specifications
shown in the test table, after thermat equi-
4~'
LSUFFIX
o...a
5~3
librium has been established. The circuit is
in a test socket or mounted on a printed
9~11
7~'O
CERAMIC PACKAGE
CASE 620
...,o
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs 14~12
15~13
n-
O
are terminated through a 50-ohm resistor to ::J
-2.0 volts. Test procedures are shown for
....
only one gate. The other gates are tested
5'
c:
in the same manner.
a

TEST VOLTAGE VALUES

IVoitsl
• Test
T-.nperature VIHmax VIL min VIHA min VILAm.. I VEE
-3O"c -0.890 -1.890 -1.2(1) -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+SSoC -0.700 -1.825 -1.035 -1.440 I -5.2
MC10107L T . . Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Under _30°C +25"<: +asoc
tVee'
Characteristic Symbol TH' Min Mu Min Mox Min M.,. Unit VIH m.. I VIL min VIHAmin VILAmu VEE Gnd

W
r\.)
I Power Supply Dram Current
',p", Cu,,,",
'E
lin H 4,9,14
5,7,15
28
265
220
mAde
j.lAdc
j.lAdc
All Inputs 1,16
1,16
1.16
W lin L 0.5 .Ade 1,16
Logic "1" VoH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vd, 4,5 8 1,16
Output Volt&ge -1.060 -0.890 -0.960 -0.810 -0.890 -0.700
-1.060 -0.890 -0.960 -0.810 -0.890 -0.700
-1.060 -0.890 ...(}.960 -0.Bl0 -0.890 -0.700
+ + +
Logic "0"
Output Voltage
VOL -1.890
-1.890
-1.675
-'.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-'.615
-1.615
Vd,
•
5
8 1.16

-1.890 -1.675 -1.850 -, 650 -1825 -1.615 4,5

LogIC "1" I
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615
+ + +
I I
VOHA -1.080 ...(}.980 -0.910 Vdo 1.16
Threshold Voltage -1.080 -0.980 -0.910
-1.080 -0.980 -0.910

LogIC "0" VOLA

-1.080
-1.655
-0.980
-1.630
-0.910
-1.595
+
Vd, 8
+
1.16
Threshold Voltage -1.655 -1.630 -1.595
-1.655 -1.630 -1.595

SWitching Times 150 H Load)

-1.655
Mo" Ty.
-'.630
Mu
-1.595
+
Unit +1.1 V Pulsetn Pu . . Out
+
-3.2 V
+
+2.0 V
Propagation Oelay Inputs 1.1 3.8 11 2.0 3.7 1.' 40 5,7,15 Input Correspondino 8 1.16

~ ~
,+- 4, 90r 14 4,9,or Ex-OR/E.·NQR
H
,--
to either
Output
•• Outputs

Inputs
5,7, or 15
to either
Output
j j 2.8

~
j j 4,9,14

~
Input
5.7, or
15
Corresponding
e • .oR/h·NQR
Outputs

Rise Time 1.1 3.5 2.5 3.5 3,8 4,9,14 Any Input
Corresponding
120 to 80%1
b-OR/Ex NOR
Fall Time 1.1 3.5 2.5 J.5 3.8 4,9,14 Any Input Outputs
12Oto~)

"IndIVidually test each Input applymg VI H or VI L to Input under test

"Any Output
 ELECTRICAL CHARACTERISTICS s:
("')
Each MECL 10.000 series circuit has been ....

-
designed to meet the de specifications
shown in the test table, after thermal equi-
o....
librium has been established. The circuit is
4~2
o.....
in a test socket or mounted on a printed S~3 PSUFFIX
circuit bo..d and transverse air flow greater CERAMIC PACKAGE
than 500 linear fpm is maintained. Outputs
9~11
7~1()
CASE 648 8::J
are terminated through a 50-ohm resistor to ....
-2.0 volts. Test procedures are shown for
14~12
15~13
s·
only one gate. The other gates are tested c
CD
in the same manner. Co

TEST VOL TAGE VALUES

(Volts)
.Tut
Temper.ture VIHm.JII VIL min VIHAmin I VILA m." I Vee
-3O"c -0.890 -1.890 -1.205 -1.500 -5.2
+25 o C -0.810 -1.850 -1.105 -1.475 -5.2
+85o e -0.700 -1.825 -1.035 -1.440 -5.2
MCl0107P Tnt Limi"
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Undo, -3O"C +25"1: +85o C IVee·
Ch....:: ....... ic Symbol T .., Min M.. Min M •• Mi" M.. Unit VIHma. VIL min VIHAmin VILA ma. V •• Gnd

W
~
Power SupplV Drain Current
I,np ", Cu",", '.
lin H 4,9,14
5,7,15
28
26.
220
mAde
_Ade
j.lAdc
All Inputs 8

8
1,16
1,16
1,16
1,16
lin L O.S .uAdc
~
Logic "1"
Output Voltage
VOH -1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vd,
'.' 8 1,16

-1.060 -0.890 -0.960 -0.810 -0.890 -0.700

Logic "0" VOL

-1.060
-1.890
-0.890
-1.675
-0.960
-1.850
-0.810
-1.650
-0.890
-1.815
-0.700
-1.615
+
Vd,
+
8
+
1.16
Output Voltage -1.890 -1.675 -1.850 -1.650 -1825 -1615 S
-1.890 -1.675 -1.850 -1650 -1.825 -1.615 ',S

Logic "1" VOHA

-1.890
-1.080
-1.675 -1.850
-0.980
-1.650 -1.825
-0.910
-1.615
+
Vd,
+ +
1,16
Threshold Voltage -1.080 -0.980 -0.910
-1.080 -0.980 -0.910

LOllic "0" VOLA

-1.080
-1.655
-0.980
-1.630
-0910
-1.595
+
Vd,
+
8
+
1,16
Threshold Voltage
I I I -1.655
-1.655
-1.630
-1630
-1.595
-1.595

Switchinll Times (50 n Load) I -1.655

Min TVO
-1.630
Mu
-1.595
+
Unit +1.1 V Pulse In Put. Out
+
-3.2 V
+
+2.0 V
Propagation Oelav ,++ Inputs 2.0 3) 5,7,15 Input Corresponding 8 1,16
,+- " ,.
i
4,9 or 14 4,9,or Ex-ORfEx·NOA
,-+ to either Outputs
,-- Output
+

i j
,++ Inputs 2.8 4,9,14 Input Corresponding
,+- 5,7, or

i
5.7, or 15 Ex-OAfEx-NOR
to either 'S Outputs
Output
Rise Time
(201080%)
2.' 3. 4,9,14 Anv Input
I Corresponding
Ex-OR/Ex NOR
Fall Time 2.S 3.S 4,9,14 Anv Input Outputs
(20 to *"'1
·lndivkiu"ly t ..t each input~lvinll VIH or Vil to input under test.
··Any Output
 MECL 10,000 series
DUAL 4-5-INPUT
"OR/NOR" GATE

MC10109

The MC10l09 is a dual 4-5 input OR-NOR

gate which is pin compatible with the MECL III
MC1660L dual OR-NOR gate. All inputs are
POSITIVE LOGIC NEGATIVE LOGIC terminated by a 50 k ohm resistor to VEE
eliminating the need to tie unused inputs low.

:~3
6
7
2
:§=t=3
6
7
2

11:~
12
14
15
1:~
11

12
14
15 tpd = 2.0 ns typ
PO::: 30 mW tvp/gate (No Load)
13 13 Output Rise and Fall Times
(10%t090%13.5 ns
(20% to 80%) 2.0 ns
vee1 = 1
VCC2" 16
VEE" 8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC

Vin Veel = VCC2 V out V out

i
To Channel "A" +2.0 Vdc NOR OR

,,»
r---
£ ±""' ---,
To
Channel
··8"
PROPAGATION DELAY

+1.11 V
50%
'--_ _....L_ - - - +0.31 V

~
Input Pulse
t+ :r:: t- :.: 2.0 ±. 0.2 ns V out OR
(20 to 80%)
Unused outputs connected to
a 50-ohm resistor to ground. t+
50-ohm termination to t-
. ground located in each
scope channel input. V out NOR
. L ______ J

All input and output cables to the

scope are equal lengths of 50-ohm
~ 0 1 ~F
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
I
-=
'
pin and TP out to output pin.
Vee::: -3.2 Vdc

See-Generellnformation section for packaging.

3-25
 ELECTRICAL CHARACTERISTICS
3:
(')
Each MECL 10.000 series circuit has been .....
designed to meet the de specifications o.....
shown in the test table. after thermal equi-
librium has been established. The circuit is
in a test socket or mounted on a printed
~
circuit bo .. d and tranwerse air flow greater
than 500 linear fpm is maintained. Outputs
8"
::J
are terminated through a SG-ohm resistor to .+
-2.0 volts. Test procedures are shown for :i'
c:
only one input and one output. The other
inputs and outputs are tested in the same
:§=t' ~

-
manner. • 2
7

9~
10 L SUFFIX
11 14 CERAMIC PACKAGE
12 15 CASE 620
13

TEST VOLTAGE VALUES

(Voltsl
I;> Test
W Temper.tur. VIHmu VILmin VIHA min VILA max I VEE
~ _lOGe -0.890 -1.890 -1.206 -1.500 -5.2
CD
+25"<: -0.810 -1.850 -1.105 -1.475 I -5.2

~
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2
MC10109L TN Limits TEST VOLTAGE APPLIED TO PINS BELOW:
Pin
_JaDe +250 C +85D C {Veel
Under
Characteristic I Symbol Test Min Max Min TV. Max Min Max Unit VIH max Vilmin VIHA min VILA rna. VEE Gnd
Power Supplv Drain Current
'E 11 14 mAde 8 1.16
Input Current
l ItnH
0.5
265 JlAdc
,I.IAdc
1.16
1.16
linL
High Output Voltage VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 1.16
-H160 -0.890 -0.960 -0.810 -0.890 -0,700 Vdc 1.16
Low Output Voltage VOL -1.890 -1.675 -1.850 1.650 -1.825 -1.615 Vdc 1.16
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 1.16
High Threshold Voltage VOHA -1.080 -0.980 -0.910 Vdc 1.16
-1.080 -0.980 -0.910 Vdc 1.16
Low Threshold Voltage VOLA -1.655 -1.630 -1.595 Vdc 1.16
-1.655 -1.630 -1.595 Vdc 1.16
SWitching Times
(50-ohm load) Pulse In Pul .. Out -3.2 V +2.0 V
Propagation Delay 14+2+ 1.0 3.1 1.0 2.0 2.9 10 3.3 1,16

l ~ ~ ~ ~
14-2-
14+3-

Rise Time
14_3+
1.1 3.6
J
1.1 3.3 1.1 3.7
12+
420 to 80%)

l ~ l l l
13+
Fait Time
(20 to80%. '2-
'3_ l
 3:
ELECTRICAL CHARACTERISTICS n
Eoch MECL 10,000 _ie.
circuit ho. been
designed to meet the de specifications
.....
o.....
shown in the test table, after thermal equi- o
librium hes been established. The circuit is c.c
in I test socket or mounted on a printed
circuit bo.d and tranwerse air flow greater 8
th., 500 line... fpm is maintained. Outputs
are terminated through. SO-ohm resistor to
....
::l
3'
-2.0 volts. Test procedures are shown for
onlv one input and one output. The other
inputs and outputs are tested in the same :¥J c
~

--
• 2
manner.
7
PSUFFIX

9~
10 PLASTIC PACKAGE
11 14 CASE 648
12 15

13

TEST VOLTAGE VALUES

(Volts)
iiITost
w Temperatur. VIH max Vel min VIHAmin VILAmu VEE
N _lOGe -0.890 -1.890 -1.205 -1.500 -5.2

" +25oC
+85·C
-0.810
-0.700
-1.850
-1.825
-1.105
-1.035
-1.475
-1.440
-5.2
-5.2
MCl0109P Test Limits TEST VOLTAGE APPLIED TO PINS BELOW:
Pin
Under -:ID"c +25°C +85o C 1VCCI
CharK,.ristie Symbol T_ M;" M •• Min Typ M .. Min M.. Unit VIH max Vll min VIHAmin VILA mu: VEE Gnd
Power Supply Drain Current Ie 8 11 14 - mAde - 8 1.16
Input Current linH 4 - 265 ,.,.Ade 4 8 1.16
linL 4 - 0.5 - .uAdc 4 8 1.16
High Output Voltage VOH 2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 4 - - - 8 1.16
3 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc - - - - 8 1.16
Low Output Voltage VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc - - - - 8 1.16
3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 4 - - - 8 1.16
High Threshold Voltage VOHA 2 -1.080 - -0.980 - - -0.910 - Vdc - - 4 8 1.16
3 -1.080 - -0.980 - - -0.910 - Vdc - - - 4 8 1.16
Low Threshold Voltage VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc - - 4 8 1.16
3 - -1.655 - - -1.630 - -1.595 Vdc - - 4 - 8 1.16
Switching Times
(50-ohm load) Pulse In Pul.Out -3.2 V +2.0 V
Propagation Delay t4+2+ 2 - - 1.0 2.0 2.9 - - n, - - 4 2 8 1.16
2 - - - - - - 2

l
t4-2-
3 - - - - - - 3
1
I
t4+3_
3 - - - - - - 3

j
14!.3+
_.
Rise Time
120'.80%1
Fall Time
120'.80%1
'2+
'3+
'2_
'3_
2
3
2
3
-
-
-
-
-
-
-
-
1.1

l
3.3

l
-
-
-
-
-
-
-
-
j -
-
-
-
-
-
-
2
3
2
3
 MEel 10,000 series
DUAL 3-INPUT 3-0UTPUT
"OR"GATE

MClono

The Mel 011 0 is designed to drive up to three

transmission lines simultaneously. The multiple
outputs of this device also allow the wire·"OR"·
ing of several levels of gating for minimization
POSITIVE LOGIC NEGATIVE LOGIC of gate and package count.
The ability to control three parallel lines
from a single point makes the Me 10 11 0 particu'

~~2
7 3
larly useful in clock distribution applications
where minimum clock skew is desired. Three
4 Vee pins are provided and each one should
be used.
1~~12
11 13
1~~12
11 13

14 14 Po = 80 mW typ/gate (No Load)

tpd "" 2.4 ns typ (All Outputs Loaded)
Output Rise and Fall Time: (All Outputs Loaded)
veel = 1, 15 "" 2.2 ns typ (20% to 80%)
VCC2 = 16 = 4.0 ns typ (10% to 90%)

VEE = 8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

PROPAGATION DELAY
Coax

Input
r----- +1.11 V

- - - - - +0.31 V
Pulse Generator

Input Pulse
t+ = t- '"" 2.0 ±. 0.2 ns
(20 to 80%)

5O-ohm termination to ground 10'

cated in each scope channel input.

All input and output cabl •• to the

scope are equal lengths of 50·oh m
coaxial cabl.. Wire 'ength should VEe = -3.2 Vdc
be < 1/4 inch from TPin to input
pin and TP out to output pin.

See General 1nformation section for packaging.

3-28
 ELECTRICAL CHARACTERISTICS 3:
Each MECL 10,000 series circuit has been ....oo
designed to meet the de specifications
shown in the test table, after thermal equi- ........
librium has been established. The circuit is
in a test socket or mounted on a printed o
circuit board and transverse air flow greater o
o

-
than 500 linear fpm is maintained. Outputs ::J
are terminated through a 50-ohm resistor to !:!.
-2.0 volts. Test procedures are shown for
only one input and one output. The other
~~2
7 3
L SUFFIX
CERAMIC PACKAGE
::J
c:
CD
inputs and outpu ts are tested in the same
manner.
4
CASE 620 .e:
10
11
9~1213
14 TEST VOLTAGE VALUES
(Volts)
@Test
Temperature VIH max VILmin VIHAmin VI LA max I VEE
-JOoe -0.890 -1.890 -1.205 -1.500 -5.2
+2SOC -0.810 -1.850 -1.105 -1.475 I -5.2
+85 0 C -0.700 -1.825 -1.035 -1.440 I -5.2
MC10110L Test limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
_lODe +250 C +8SoC (Veel
Under
W I Characteristic I Symbol Te.. Min Max Min TV. Max Min Max Unit VIH max VILmin VIHAmin VILA me)! VEE Gnd
~ I Power Supply Drain Current I IE 30 38 mAdc 8 1.15.16
CO Input Current
L linH
linL
5,6,7
5,6,7 0.5
425 /JAdc
IJAdc
1,15,16
1.15.16
LogiC "1" VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 1.15.16
Ou tpu t Voltage -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 1,15,16
4 -1.060 -0.890 -0.960 -0.810 -0890 -0.700 Vdc 1,15,16
LogiC "0" VOL 2 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 1.15.16
Output Voltage 3 -1.890 -1.675 -1.850 -1.6S0 -1.825 -1.615 Vdc 1,15.16
4 -1890 -1.675 -1.8S0 -1.650 -1.825 -1.615 Vdc 1,15.16
Logic ·'1" VOHA -1.080 -0980 -0.910 Vdc 1.15.16
Threshold Voltage -1.080 -0.980 -0.910 Vdc 1,15,16
-1.080 -0.980 -0.910 Vdc 1,15,16
LogiC "0" VOLA -1.655 -1630 -1.595 Vdc 1.15.16
Threshold Voltage -1.655 -1.630 -1.595 Vdc 1.15.16
-1.655 -1.630 -1.595 Vdc 1,15.16
Switching Times
(50-ohm load) Pulse In Pul.Out -3,2 V +2_0 V
Propagation Delay t5+2+ 1.4 3.5 1 .• 2.4 3.5 1.5 3.8 8 1,15,16
t5_2_
t5+3+

1
t5_3_ 3
t5+4+
t5_4_
•
4 1 1 1
Rise Time '2+ 10 1.1 2.2 1.2
120 to 80%1 '3+
'4+

1 1 11 1
Fall Time '2_
1201080%1 '3_
'4_
-IndiVidually test each Input uSing the pm connections shown.
 3:
ELECTRICAL CHARACTERISTICS o
~
Each MECL 10,000 series circuit has been o
~
designed to meet the de specifications
~
shown in the test table, aher thennal equi-
librium has been established. The circuit is o
in a test socket or mounted on 8 printed
8

-
circuit bo_d and transverse air flow greater
then 500 line. fpm is maintained. Outputs ....
::J
3'
~~2
are terminated through. 51k>hm resistor to P SUFFIX
PLASTIC PACKAGE ~
-2.0 volts. Test procedures are shown for
only one input and one output. The other
7 3

4
CASE 648 a
inputs and outputs are tested in the same
manner.
10
11
9~12 13
TEST VOLTAGE VALUES
14
(Volts)
In...
Temperature VIH max VILmin VIHAmin VILA ma. I VEE
-lOoe ~.890 -1.890 -1.205 -1.500 I 5.2
+26OC -0.810 -1.850 -1.105 -1.475 I -5.2
+85oC ~.700 -1.825 -1.035 -1.440 I -5.2
Mel0110P Tnt Limits
Pin TEST VOLTAGE APPLlEO TO PINS LISTED BELOW,
u_, _lOGe +25"<: +85·C (Veel

'rl I CharKteristic I Symbol T ... Min Ma. Min Ty. Ma. Min M.. Unit VIH max VILmin VIHAmin VILA max VEE Gnd
(,J I Power Supplv Drain Current I IE 8 38 mAde 8 1.15,16
0 I I nput Current
~ linH 5,6.7 425 /lAde 1.15.16
linL 5,6,7 0.5 /lAde 1,15.16
VOH 2 -1.060 ~.890 -0.960 -0.810 -0.890 -0.700 Vdc 8 1.15,16
Logic "'"
Output Voltage 3 -1.060 -0.890 -0.960 -0.810 -0.890 ~.700 Vdc 8 1,15,16
4 -1.060 ~.890 ~.960 -0.810 -0.890 -0.700 Vdc 8 1,15,16
Logic "0" VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vde 1,15,16
Output Vol1age -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 1,15,16
4 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 1,15,16
logic "1" VOHA 2 -1.080 -0.980 ~.910 Vde 8 1,15,16
Threshold Voltage 3 -1.080 ~.980 -0.910 Vdc 8 1,15,16
4 -1.080 ~.980 -0.910 Vde 8 1,15,16
Logic "0" VOLA -1.655 -1.630 -1.595 Vdc 1,15,16
Threshold Voltage -1.655 -1.630 -1.595 Vdc 1,15,16
-1.655 -1.630 -1.595 Vdc 1,15,16
Switching Times
(50-ohm load) Put. In Put.Ou1 -3.2 V +2.0 V
Propagation Delay t5+2+ 1.4 2.4 3.5 2 8 1,15.16
t5_2_ 2
t5+3+ 3

1 1
15-3- 3
t5+4+
t5_4-
Rise Time '2+ 1.1 2.2
1201080%) '3+

!
'4+

1 1I
Fell Time '2_
(20 .. _1
....
'3_

·lndlViduetty tett eKh Inpu1 usn'll the PI" connlC1lon1lhown.

 MECL 10,000 series
DUAL 3-INPUT 3-0UTPUT
"NOR"GATE

MC10lll

The Me 10111 is designed to drive up to three

transmission lines simultaneously, The multiple
outputs of this device also allow the wire-"OR"-
ing of several levels of gating for minimization
POSITIVE LOGIC NEGATIVE LOGIC of gate and package count.
The ability to control three parallel lines
from a single point makes the Me 10 111 particu-
larly useful in clock distribution applications
where minimum clock skew is·desired. Three
Vee pins are provided and each one should be
used.
~
12

~
12

9 13 13
10 14 1~ . 14
11 11

Po == 80 mW typ/gate (No Load)

tpd = 2.4 ns typ (All Outputs Loaded)
VCCI = I, 15
Output Ris. and Fall Time: (All Outputs Loaded)
VCC2 = 16
==2.2 ns typ (20% to 80%)
VEE = 8 == 4.0 nl tvp (10% to 90%)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

VCC 1 = VCC2
+2.0 Vdc Vout
PROPAGAT)ON DELAY

,,,,t1t""
r--- ----,
~.
I ~-+-_----J
Input I
V out

Pulse Generator

Input Pulse
t+ ;. t- = 2.0 ± 0.2 ns
(20 to 80%)

50-ohm termination to ground lo-

cated in each sCOpe etlannel input.

All Input and output cables to the

scope are equal lengths of 50-ohm
coaxial cabl.. Wire length should VEE == -3.2 Vdc
be < 1/4 inch from TPin to input
pin and TP out to output pin.

s.. G,enera' Information section for packaging.

3-31
 ELECTRICAL CHARACTERISTICS 3:
(')
Each MECl 10,000 series circuit has been .....
~ ~:
designed to meet the de specifications Q
shown in the test table, after thermal equi-
lSUFFIX
.....
.....

'"
librium has been established. The circuit is
in I test socket or mounted on 8 printed 7~4 CERAMIC PACKAGE .....
CASE 620
circuit bo_d and tra"$Verse air flow greater
n-o
~
12
than 500 linear fpm is maintained. Outputs
are terminated through a 5o.ohm resistor to 9 13
....
::J
-2.0 volts. Test procedures are shown for
only one input and one output. The other
10
11 14 :5'
I:
inputs and outputs are tested in the same
manner.
a

TEST VOLTAGE VALUES

(Voltsl
• Test
Temperatar. VIH me. VIL min VIHA min VILA m.. VEE
-JOoC -0.890 -1.890 -1.205 -1.500 -5.2
+25o C -0.B10 -1.850 -1.105 -1.475 -5.2
+8So C -0.700 -1.825 -1.035 -1.440 -5.2
MCl0111l Test Limits
Pin TEST VOL rAGE APPLIED TO PINS LISTED BELOW:
-lOoe +25 o e +85o e
'fJ
W .
Charact.",tte Symbol
Under
T ... Min Max Min TV. M.. Mon M.. Unit VIH max VIL min VIHA min VILA max VEE
IVeel
GncI
'" Power Supply Dram Current 'E 8 38 mAdc 8 1,15,16
Inpu1 Current IlnH 5,6.7 425 ~Adc 1.15,16
IlnL 5.6,7 0.5 ~Adc 1,15,16
LogiC "1" VOH 2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdo 1,15,16
Output Voltage -1,060 -0.890 -0960 -0.810 -0.890 -0.700 Vdo 1,15,16
-1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdo 1,15,16
LogiC "0' VOL I -1890 -1.675 -1850 -1.650 -1.825 -1.615 Vdo 1,15,16
Output Voltage -1.890 -1.675 -1.850 -1650 -1.825 -1.615 Vdo 1,15,16
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdo 1,15,16
LogiC "1"
Threshold Voltage
VOHA I I -1080
-1.080
-0.980
-0980
-0.910
-0.910
Vdo
Vdo
1.15,16
1,15,16
-1.080 -0980 -0.910 Vdc 1.15,16
LogiC "0" VOLA I -1655
-1.655
-1630 -1.595 Vdo 1.15,16
Threshold Voltage -1630 -1.595 Vdo 1,15.16
-1.655 -1630 -1.595 Vdo 1,15,16
S....lItchmg Times
(50·ohm load) Pul.ln Pul_Out -3.2 V +Z.oV
Propagation Delay t5+2_ 14 3.5 14 2.4 3.5 1.5 3.8 8 1,15,16
15-2+
t5+3_

1 1 1 1
16-3+

Rise Time
15+4_
15_4+
'2' 10
1
1.1 2.2
1
3.5 1.2 3.8
~20 to amc.I '3'
'4'

1 1 1 1 1
Fall Time '2_
IZOtoaa..1 '3_
'4_
-Individuelly test eech input using the pin connections stlown.
1
 3:
ELECTRICAL CHARACTERISTICS n
Ea:h MECL 10,000 _ie.circuit has been
designed to moet the dc opecificetion.
.-
o
.-

-
shown in the test table, after thenn. equi- .-
~: .-
librium has been established_ The circuit i.
in I test mcket or mounted on I printed : 8
ciraJit bo.d and trlnwene lir flow greater
th.. 500 linear fpm is maintained. Outputs
7~4 ::J
~
ant t .. minlted through a 5O-ohm resistor to '2 3'
~
PSUFFIX
-2_0 volts. Test procedure. are shown for
9 13 PLASTIC PACKAGE
c
only one input and one output. The other
inputs and outputs are tasted in the same 10
11 14
CASE 648 !l
manner.

TEST VOL TAGE VALUES

IVolts)
@T8'51
T .mperature VIHm ... Vilmin VIHAmln VILA mu I VEE
_lODe -0.890 -1.890 -1.205 -1.500 -52
+25o C -0.810 -1.850 -1.105 -1.475 -5.2
+85 Q C -0.100 -1.825 -1.035 -1.440 I -52
MCl0111P 111ft Limit.
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW'
_lOGe +2SoC +850 C tVee'
u ...
~
W
CharKtaristic vmbol Toot Min I M.. Min I Tvp I MIX Mon
I Max Unit VIHmax Vil min VIHAmtn VILArn. . VEE Gnd
Power SupplV Drain CurrenT 'E 8 38 mAde: 8 1,15,16
W
Input Current IlnH 5,6,1 425 J.lAde: 1,15,16
Iml 5,6,7 OS J.lAde: 1,15,16
LogiC "'" VOH 2 -1.060 -0.890 -0960 -0810 -0.890 -0700 Vdo 1,15,16
OutPUt Voltage -1._ -0.890 -0960 -0810 -0.890 -0.700 Vdo 1,15,16
-1.060 -0.890 -0960 -0.810 -0.890 -0.700 Vdo 1,15,16
Logic "0" VOL -1.890 -1.675 -1850 -1650 -1.825 -1.615 Vdo 1,15.16
Output Voltage -1.890 -1.675 -1850 -1650 -1825 -1.615 Vdo 1,15,16
-1.890 -1675 -1.850 -1.650 -1.825 -1.615 Vdo 1,15,16
LogIC "1" VOHA -1.080 -0980 -0.910 Vdo 1,15,16
Threshold Volt. -1.080 -0980 -0.910 Vdo 1,15,16
-1.080 -0980 -0.910 Vdo 1,15,16
Logic "0" VOLA -1.655 -1630 -1.595 Vdo 1.15,16
Threshold Voltage -1.655 -1630 -1.595 Vdo 1,15,16
-1.655 -1630 -1.595 Vdo 1,15,16
SWitching Times
(5().ohm load' Pulse In Pul_Out -3.2 V +2.0 V
ProP8glltlon Delay 15+2_ 1.4 2.4 3.5 8 1,15,16
'5-2+
15+3_
15-3+

Rise Time
'5+4-
15-4+
'2.
1 1
1.1 2.2
12Ota_1 '3.
Fan Time
12Ota_1

-Individually test NCh input USing

'4.
'2_
'3_
'4-
the pin connections shown.
!1
 MECL 10,000 series
QUAD EXCLUSIVE
OR GATE

MC10113

Advance InforIDation
The MC10113 is a quad Exclusive OR gate,
POSITIVE LOGIC with an enable common to all four gates. All
four outputs may be wire·ORed together to
E 9 perform a 4·bit comparison function (A = BI.
The enable is active low. Input pulldown reo
2
sistors included in the circuit make it un·
necessary to tie down unused inputs. Open
emitter outputs permit direct connection of
6 TRUTH TABLE
3
A B E OUTPUT
outputs to busses.
L L L L
L H L H
10--"-~~ H L L H
14 H H L L
11 H
4> 4> L
<P = Don't Care

12
15 Po = 175 mW typ/pkg (No Load)
13
tpd = 2.5
ns typ
Output A iss and Fall Times
= 2.0 ns typ (20% to 80%)

vee1 = Pin 1
VCC2 = Pin 16
VEE=Pin8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C

VCC1~VCC2
+2.0 Vdc V out

Input
Coax

"">$"'">
r - - - -,
Coax

(~--~~--TI~~ I
I :>'"-Ir-+--------'
Pulse Generator

Input Pulse
t+ = t- = 1.5.±. 0.2 ns
(20 to 80%) V out

50-ohm termination to ground

located in each scope channel
input.
All input and output cables to the
VEE = -3.2 Vdc
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
Unused outputs connected to
a 50-ohm resistor to ground.
pin and TP out to output pin.

This is advance information and specifications are subject to change without notice.
See General I nformation section for packaging.

3-34
 ELECTRICAL CHARACTERISTICS 3:
Each MECL 10.000 series circuit has been
E
...
o
......w
designedta meet the de specifications shown 9
in the test table. after thermal equilibrium 4
LSUFFIX
CERAMIC PACKAGE
o

"'"
has been established. The circuit is in a CASE 620
test socket or mounted on a printed circuit
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
6
3 8
::J
-2.0 volts. Test procedures are shown ~.
only for selected inputs and outputs. Other
::J
10---'--'" c:
inputs and outputs are tested in a similar CD
14
manner. .eo
"~
TEST VOLTAGE VALUES
@Tost (Volts)
12 1"5 Tlmp ••tur. VIH IftIIx VILmin VIHAmin VILA mix VEE
13 _30G e -0.890 -1.890 -1.205 -1.500 -5.2
+25"C -0.810 -1.850 -1.t05 -1.475 -5.2
+85oC -0.700 -1.825 -t.035 -1.440 -5.2
MCl0113l Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Unci.
_lODe +25°C +85oC (VCC)
Characteristic Symbol Tort Min Ma. Min Ma. Min Ma. Unit VIH mIIX VILmin VIHAmln VILAma. VEE GncI
Power Supply Drain Current
Input Current
IE 8
lin H 4,7,10,13
-
-
-
-
-
-
42
265 -
- -
-
mAdc
,.Adc ..
- -
-
-
-
-
-
8
8
t,16
1,16
5,6,11,12 - - - 220 - - SlAdc - - - 8 1,16
w
W
UI
lin L
9
. -
-
-
-
-
-
545
0.5
-
-
-
-
SlAdc
,.Adc
9
- .
- -
-
-
-
8
8
1.16
1.16
Logic "1" VOH 2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 4 8 1,16

l
- -
! l
Output Voltage 3 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 7 -
14 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 11 - - -
15 -t.060 -0.890 -0.960 -0.810 -0.890 -0.700 13 - - -
Logic "0" VOL 2 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc - 4 - - 8 1.16
- -
~ l l
Output Voltage 3 -t.890 -1.675 -1.850 -1.650 -1.825 -1.615 - 7
14 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 - 11 - -
15 -.1.890 -1.675 -1.850 -1.650 -1.825 -t.615 - 13 - -
Logic "1" VOHA 2 -1.080 - -0.980 - -0.910 - Vdc - - 4 - 8 t,16

l l l
Threshold Voltage 3 -1.080 - -0.980 - -0.910 - - - 6 -
14 -1.080 - -0.980 - -0.910 - - - 10 -
15 -1:080 - -0.980 - -0.910 - - - 12 -
Logic "0" VOLA 2 - -1.655 - -1.630 - -1.595 Vdc - - - 5 8 l.t6
- - -
~ l l
Threshold Voltage 3 - -1.655 - -1.630 - -1.595 7
14 - -1.655 - -1.630 - -1.595 - - - 11
15 - -1.655 - -1.630 - -1.595 - - - 13
Switching Times (50 n Load) Min TVp Ma. Unit +1.11 V Pulse In Pul_Out -3.2 V +2.0 V
Propagation Delav t4+2+ 2 - - - 3.0 - - - ns - - 4 2 8 1.16
2 - - - - - - - - 4

I I II
14-2_ 3.0
t9+2- 2 - - - 3.4 - - - 4 - 9
t9-2+ 2 - - - 3.4 - - - 4 - 9
Rise Time 12+ 2 - - - 2.0 - - - - - 4
(20 to 80%)
Fall Time 12_ 2 - - - 2.0 - - - - - 4
(20 to 80%)
. - --
-Individuallv test each input applying VIH or V'L to input under test.
 MECL 10,000 series
TRIPLE LINE RECEIVER

MC10114

The MC10114 is a triple line receiver designed for

use in sensing differential signals ovef long lines. An
active current source and translated emitter follower
inputs provide the line receiver with a common mode
noise rejection limit of one volt in either the positive
or the negative direction. This allows a large amount
of common mode noise immunity for extra long lines.
Another feature of the MC10114 is that the OR
outputs (pins 3,7, 15) go to a logic low level whenever
the inputs are left floating. The outputs are each cap.
POSITIVE LOGIC NEGATIVE LOGIC
able of driving 50 ohm transmission lines.
Thisdevice is useful in high speed central processors,
minicomputers, peripheral controllers, digital commu-
nication systems, testing and instrumentation systems.
4~2 4~2 The MC10114 can also be used for MOS to MECL
5~3 5~3 interfacing and it is ideal as a sense amplifier for MOS
RAM's.
9~6 9~6 A VBB reference is provided which is useful in
'0~7 '0~7 making the MC10114 a Schmitt trigger, allowing single-
ended driving of the inputs, or other applications where
'2~'4 '2~'4 a stable reference voltage is necessary.
'3~'5 '3~'5
L-"
Vee L-"
Vee

vee1 ""Pin 1
VCC2 = Pin 16 tpd = 2.4 ns typ (Single Ended Input)
=
VEE Pin 8 tpd = 2.0 ns typ (Differential Input)
Po = 145 mW typ/pkg

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

VCC1 ::: VCC2

V out V out
+2.0 Vdc

PROPAGATION DELAY
Coax

Input

Pu lse Generator

Input pulse
""ill'' '
r-- ----,
I

V out

Unused outputs
t+ '" t - '" 2.0 ±. 0.2 ns
connected to a
(20 to eO%)
50-ohm resistor
to ground.
I
I
I
IlOne .Input from
50-ohm termination to ground 10'
.cated in each scope channel input.
L
-11-.-J each gate must
be tied to Vee (Pin 11) during testing .

All ;nput and output cables to the

scope ere equal lengths of 50-ohm
coaxial cable. Wire length should I O" "F ::to'IlF
be < 1/4 inch from TPin to input
pin and TP out to output pin. -32 Vdc

See General I nformation section for packaging.

3-36
 ~
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been de-
signed to meet the de specifications shown
......
o
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
...
~
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
n-
4~2 O
terminated through a 50-ohm resistor to :::J
-2.0 volts. Test procedures are shown for 5~3 ~.
:::J
only one gate. The other gates are tested 9~6 c:
in the same manner. 10~7 <»
a.

-
12~14
'3~'5 L SUFFIX
~"
VBB
CERAMIC PACKAGE
CASE 620

TEST VOLTAGE VALUES

(Voftsl
.. T",
Temperatur. VIH max Vil min VIHA min VILA rna. V •• VIHH-I VllH-1 VtHl·\ VILL -I VEE
-30ot: -O.B90 -1.890 -1.205 -1.500 F,~ +0.110 -0.890 -1.890 -2.890 -5.2
.25OC -0.B10 -1.850 -1.105 -1.475 Pm +0190 -0.850 -1810 -2850 -5.2
+8SOC -0.700 -1.825 -1.035 -1.440 11 +0.300 -0.825 -1.700 -2.825 -5.2

w
W
Iu_ Pon -30"<:
MC1D114l T . . Limits
+zsOC +85OC
TEST VOL TAGE APPLIED TO PINS BELOW:
{Vee l

...... C.....act.,istic Symbol Test Min M.. Min Typ' Me. I Min 1 Mall Unit I V'H rna. V,L min I V,HA min I V,LA mlJl. I VBB I V,HH·' VllH·' V,Hl· I VILl· I VEE Gnd
Power SupplV Drain Current 28 35 mAd< 4,9.12 I 15,10,131 1 - I - 1,16
"
Input Current 'inH
ICeD
4'
1.0
.AoX 9,12
9,12
I 15,10,13
5,10,13 8.4
1,16
1,16

=~ :~~ I=~::: I =~:~:

VOH -1.060 -0.890 -0.960 9.12 5,10,13 1,16
I logiC "1" Output Volt. -1.060 -0.890 -0960 5,10,13
4 1,16

=~::~~ I=~.:~~ I =~::~~

VOL -1.890 -1.675 -1.850 4 5,10,13 1,16
I logiC "0' Output Voltage
-1,890 -1.675 -1.850 9,12 5.10,13 1,16
IlogiC ·'1" Threshold Voltege VOHA -1.CIIO
-1.080
-0.980
-0.980
-0.910
-0.910
Vd,
VOX 9,12
9.12 5.10,13
5.10,13
1,16
1,16
LogiC ·'0" Threlhold Volt8lle VOLA -1.655 -1.630 - -1.595 Vd< 9,12 5.10,13 1,16
-1.655 -1.630 - -1.595 Vd, 9.12 5,10,13 1,16
Reference Voltage Vea I 11 -1.420 -1.280 -1350 -1.230 -1.295 -1.150 Vd, 5,10,13 1,16
Common Mode Rejection Tnt VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vd, 1.16
-1.060 -0.890 -0.960 -0.810 -0.890 -0.700 VOX 1,16
VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vd, 1,16
-1.890 -1.675 -1.8SG -1.650 -1.825 -1.615 VOX 1,16
Swnchi", Ti_ (SO-ohm lOMt) Min M.. Min Tvp M •• Min M.. Pul.'n Pul.Oul -3.~V 1+2.0V
Prop...-Ilon oelav·· 14+2+ , 0 44 '.0 2.4 40 0 .• 43 4 5,10,13
"

I 'J
t4-2_
14+3-

AI. Time (20% 1080%)

t4_3+
'2.
'3·
1.-+ •
38
+ +
I.' 21
•
3.' I.,+ • j
3.7
j j
FaU Time (20% 10 80%) '2_
'3_ ~ + + ~ + + +
·V,HH = Input logiC "1" level shifted poSitive one volt for common mode rejection tests.
V, LH '" I nput logiC ..a" level shifted positive one volt for common mode rejection tests.
Y,HL '" Input logiC "I" level shifted negative one volt for common mode rejection tests.
Y,LL a Input logiC "O"level shifted negative one volt for common mode rejection tests.
·-Delay IS 2.0 ns With differentlellnput.
 ELECTRICAL CHARACTERISTICS 3:
Each MECL 10.000 .ries has been de- n
....o
signed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
....
....
test socket or mounted on a printed circuit ~
board and tranlV8rse air flow greater than
.r. n-O
500 linear fpm is maintained. Outputs
t.min.ted· through 8 SD-ohm resistor to
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
4~2
5~3
9~6
..
:J
:j'
c
in the same manner. CD

-
10~7 Co

12~14
PSUFFIX
'3~'5 PLASTIC PACKAGE
L-"
VBe
CASE 648

TEST VOLTAGE VALUES

IV_
.T",
T . . . .atun VIH", .. Vllmin VIHAmin VILA max V•• VIHH-I VILH-J VIHL -I VILL -1 VeE

MCl0114P Test Limits

......""""
-30"1: -<>.890
-0.810
-0.700
-1.890
-1.850
-1.825
-1.205
-1.105
-1.035
-1.500
-1.475
-1.440
F,om
Pin
>1
+0.110
+0.190
... 0.300
-0.890
-0.850
-0.825
-1.890
-1.810
- t. 700
-2.890
-2.850
-2.825
-5.2
-5.2
-5.2

W 'No TEST VOLTAGE APPLIED TO PINS BELOW:

W C_ _ _ istic u_
T_
-3QOc
MinlMulMifllTyplMa
+25OC .IS""M,.
Min Unit VIH",... VIL min VIHAmin VILA max V. . V'HH- VILH- VIHL- VILL- VEE
lYeel
a ...
CO
Power Supply Orein Current
Input Current
8 28 I 36
45
mAdo
"A""
4,9.12
9.12
5.10,13
5,10,13
• 1.16
1.16
1.0 "Ado 9.12 5.10,13 .,' 1,16

Loaic "'" Output Vol• •

-1.060 ~.890
-1.060 -0.890
-0....
-0....
-0.810
-0.810
-0.890 -0.100
-0.890 -0.700
Vdo
Vde •
9,12
9,12
4
5,10,13
5:10.13
8
8
1.16
1,16
VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vde 9,12 4 5,10,13 1,16
Logic "0" Output Volt.
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vde 4 9,12 5,10.13 1.16
VOHA -1.080 -0.980 -0.910 Vde 9.12 5,10,13 1.16
Logic "'" ThreshOld Voigge
-1.080 - -0.980 -0.910 Vde 9,12 5,10,13 1,16
logic "0" Threshold Voluee VOLA I 2
3·
-1.655
-'.655
-'.630
-1.630
-1.595
-1.595
Vde
Vde
9,12
9.12
5,10.13
5,10.13
1.16
1,16
R.f8f"enCeVoltege V•• J. 11 -1.420 -1.280 -1.350 -1.230 -1.295 -1.150 Vde 5,10,13 1,16
Common Mode Rltjection Tes. VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vde 1.16
-1.060 -0.890 -0.... -0.810 -0.890 -0.700 Vde 1,16
VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vde 1,16
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vde 1.16
Swhchina T ..... (IO-oh... Loedl M,. M.. M..
~
Min Typ Min Pul.ln Pul_Out -3.2 V +2.0 V
P,opeption Oeley·· '4+2. 1.0 2.4 4.0 no 4 5,10,13 8 1.16

t
....2-
'4+3-
+
• j j j j j
....3.
Ri. Time (2mC, to 8010' '2. '.5 2.' 3.5

~
'3.
FilII Time (ZOK t. 11ft. '2_
'3-
+
·VIHH .. Input logic "l"level shifted po.iti.". one volt for common mod. rejechon tests.
+
VILH - Input logic "0" tlNel.hifted positiveonevolt tor common mode reiec1ion t ......
VIH.L '" Input logic "'''level.hitted ne.... iwone voh for common mode reiectfon tests.
'Vlll • Input lolic ..0'·. ...,.1 .r.iftad n ...trw OM 11011 for common mod. rejection test •.
--De&ay i. 2.0 n. with differ .... till input.
'--___ J QUAD LINE RECEIVER
"'\ MECL 10,000 series
'--...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......J

MC10115

The MC10115 is a quad differential amplifier

designed for use in sensing differential signals
over long lines. The base bias supply (Va a) is
made available at pin 9 to make the device useful
POSITIVE LOGIC NEGATIVE LOGIC as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the MC 10115
with excellent common mode noise rejection.
:~2 If any amplifier in a package is not used, one
input of that amplifier must be connected to
:~3 Vaa (pin 9) to prevent upsetting the current
source bias network.
10~ 14 10~
11 11~14

13~ 16 13~ 16
12 L-g 12 L-g
VBB VBB tpd ... 2.0 n. typ
Po - 110 mW typ/pkg (No Load)
VCC1 - Pin 1
VCC2-Pln 16
VEE'" PinS

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS.:zsOc

VCC, - VCC2
V out

,.,,± I±""
+2.0 Vdc

Coax
PROPAGATION DELAY
Input r----....,
I

l"putPul..
t+ - t- - 2.0±. 0.2 nl Vout
(20 to 80%)

5O-ohm terminetion to ground 10'

cet. . in .ach tcope channel input.

All Input and output cable. to the

scope ar. equal I.ngths of 50-ohm One Input from .ch gete must be t'-t to Vas
co.JCI.1 cabl.. WI,. length should (Pin 9) during tmlng.
be < 1/4 Inch from TPln to Input
pin and TP out to output pin. unu.-:l outputl connected to • 50-0hm ,.Iaor
to ground.

VEE - -3.2 Vde

s_ Oen._1 I "formation _etlan for .peckaglng.

3-39
 s:
o
~

o
~
~
(11
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been de-
n-
O
signed to rnfit the de specifications shown ::J
~,
in the test table, .fter thermal equilibrium ::J
has been established. The circuit is in a c:
(1)
test socket or mounted on a printed circuit a.
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are :~2
:~3
terminated through a 50-ohm resistor to

-
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
,O~
11
,. L SUFFIX
CERAMIC PACKAGE
13~'5 CASE 620
12 L-g
Vea

lilT.., TEST VOLTAGE VALUES

Temper.ture VIHmax VIL min VIHA min VILA me. VBB VEE
W
~ -lODe -0.890 -1.890 -1.205 -1.500 From -6.2
0 +25"c -{J.810 -1.850 -1.105 -1.475 Pin ~
+85o C -0.700 -1.825 -1.035 -1.440
9
~
MC10115L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Under -lODe +25"c +ISOC (Vee)
Ch.rec:'eri.Uc Svmbol T.., Min M .. M .. M •• Min M •• Unit VIHmo VILmin VIHA min V.LAmb VBB VEE Gnd
Power Supply Drain Current IE 8 26 mAde 4,7,10,13 5,6.11,12 8 1,16
I nput Current lin H 95 /JAde 7,10,13 5,6,11,12 1,16
IceD 1.0 /JAde 7,'0,13 5,6,",12 8,4 1,16
Logic "'" Output VOltage VOH -1.060 -0.890 -{J.960 -0.810 -0.890 -0.700 Vde 7,10,13 4 5,6.11,12 8 1,16
Logic "0" Output Voltage VOL -1.890 -1.675 -1.850 -1.650 -1.825 1.615 Vde 7,10,13 5,6,11,12 8 1,16
Logic "'" Threshold Valt&ge VOHA -1.080 -{J.!lB0 -0.910 Vde 7,10,13 5,6,11,12 8 1,16
Logic "0" Threshold VOltage VOLA -1.655 -1.630 -1.595 Vde 7,10,13 5,6,11,12 8 1,16
Reference Voltage V88 1.420 1.280 -1.350 -1.230 1.295 -1.150 Vde 5,6,11,12 1,16
Switching Times (50 n Load) Pul_ln Pul.Out -32 V +2.0 V
Propagation Delav t4_2+ 1.0 3.1 1.0 2.9 1.0 3.3 4 2 5,6,11.12 8 1,16

~
3.3

~ ~ ~
t4+2_ 1.0 3.1 2.9

~
1.0 1.0
Rise Time (20% to 80%)
Fall Time (20% to 80%)
'2+
'2_
1.1
1.1
3.6
3.6
1.1
1.1
3.3
3.3
1.1
1.1
3.7
3.7 !
 ~
o.....
o....
....
(J1
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been de· 8:J
signed to meet the de specifications shown
in the test table, after thermal equilibrium
...
::J
has been established. The circuit is in 8 c:
Cl)
test socket or mOU'lted on a printed circuit a.
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are 4=::::t>--2
5

7=::::t>--3

-
terminated through a 5(}'ohm resistor to
-2.0 volts. Test procedures are shown for 6
only one gate. The other gates are tested
in the same manner. 10 =::::t>--14
11
P SUFFIX
PLASTIC PACKAGE
CASE 648
13~15
12 L-9
v ••

~Test
TEST VOLTAGE VALUES
Temperature VIH max VILmin VIHA min VILA max Vaa VEE
W -lODe -1.890 -1.500
~
-0.890 -1.205 From
~ Pin
~
+25"c -0.810 -1.850 -1.105 -1.475
+85°C -0.700 -1.825 -1.035 -1.440 9 -5.2
MCl01 15P Tnt Limhs
Pin TEST VOLTAGE APPLIEO TO PINS LISTEO BELOW,
Und.r -lODe +25"c +8SOC (Vee)
Ch.rKteristic: Symbol Test Min Ma. Min M .. Min Ma. Unit V'Hmo VIL min VIHA min VILA max Vaa VEE Gnd
Power Supply Drain Current IE 8 26 mAde 4,7,10,13 5,6,11,12 1,16
I nput Current 'in H 4 95 IlAdc 7,10,13 5,6,11,12 1,16
IcaO 4 1.0 }JAde 7,10,13 5,6,11,12 8,4 1.16
Logic "1" Output Voltage VOH ·-1.060 -0.890 ~.960 -0.810 -0.890 -0.700 Vdc 7,10.13 4 5,6.11,12 8 1.16
Logic "0" Output VOltage VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vde 7,10.13 5,6,11,12 1,16
Logic "'" Threshold Voltage VOHA -1.080 ~.9B0 -0.910 Vde 7,10,13 5,6,11,12 1,16
Logic "0" Threshold Voltage VOLA 2 -1.655 -1.630 -1.595 Vde 7,10,13 4 5,6.'1.12 1,16
Reference VOltage V88 9 '.420 1.280 -1.350 -1.230 1.295 -1.150 Vde 5,6.11.12 1,16
Switching Times (50 1l Load) Pul.ln Pul.Out -3.2 V +2,0 V
Propagation Delav t4_2+ 1.0 2.9 4 2 5,6,11,12 1,16

~. ~ ~ ~ ~ ~
t4+2- 1.0 2.9
Rise Time (20% to 80%1 '2+ 1.1 3.3
Fall Tim. (20% to 80%1 '2_ 1.1 3.3
 MECL 10,000 series
TRIPLE LINE RECEIVER

MC10116

The MC10116 is a triple differenlial amplifier

designed for use in sensing differential signals over long
lines. The base bias supply (Vaa) is made ..ail_
at pin 11 to make the device u.ful as 8 Schmitt
trigger, or in other applications INhere a stable reference
voltage is necessery.
POSITIVE LOGIC NEGATIVE LOGIC
Active current sources provide the MC101 16 with
excellent common mode noi. rejection. If any ampti-
fier in 8 package is not used, one input of that amplifter
must be connected to Ves (pin 111 to prevent upsetting

:~: :=:tt=~ the current source bias network.

Complementary outputs are provided to allow driv·
9~6 9~6 ing twisted pair lines, to enable cascad ing of several
10~7 10~7 amplifiers in a chain, or simplv to provide complement
12~14 12~14 outputs of the input logic function.

13~16 13~16
L--ll L--ll
Vaa Vaa

VCCI - Pin 1 fpd - 2.0 ns typ

VCC2 - Pin 16 Po - 86 mW typ/pkg (No Load)
VEE - Pin 8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 25°C

VCCI - VCC2
V out V out PROPAGATION DELAY
+2.0 Vdc

25"F~0'I"F
r - -......' - - - - - + 1 . 1 1 V

Coax

r£l~~
+0.31 V

Input
V out

t+

Input pulse t-
t+,.. t-- 2.0t. 0.2 ns
(20 to 80%)

Unused outputl connected to

50~hm termination to ground 10'
c.ted in each lCOpe channel input. • 50-ohm res'ltor to ground.

All Input and output cab'.. to the One Input from each gete mult
IeOp. are equal langthl of 50-ohm be tied to Vee (Pin 11) during testing.
coaxial cabl._ WI,. length ahould
be < 1/4 Inch from TPln to Input
pin and TP out to output pin.

Sea Ganerallnformatlon ..etlon for packaglno.

3-42
 ELECTRICAL CHARACTERISTICS
3':
Each MECL 10,000 series has been de-
...
C")
signed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
......
I:)

0)
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are c;-
terminated through a 50-ohm resistor to O
:l
-2.0 volts. Test procedures are shown for :::!.
only one gate. The other gates are tested :l
in the same manner. c:
~

-
4~2
L SUFFIX
5~3 CERAMIC PACKAGE
9~6 CASE 620
'O~7
'2~14
13~'5
L-"
V
"" TEST VOLTAGE VALUES
(Volts)
filTost
Temperature VIHm •• VILmin VIHAmin VILA max Vaa VEE
w -3o"c
~
-0.890 -1.890 -1.205 -1.500 From
.;:. +25o C -0.810 -1.850 -1.105 -1.475 Pin -5.2
W
+8So C -0.700 -1.825 -1.035 -1.440 11 ~
MC1Q116L T_ Limits
Pi" TEST VOLTAGE APPLIED TO PINS BELOW:
u_, -3o"c +2SoC +8SoC
IVCCI
Characteristic Svmbol T_ Min M .. Min TV. Ma. Min M •• Unit VIH max VILmin VIHAmin VILA max Vas VEE God
Power Supply Drain Current 'E 8 - 17 21 mAde 4,9,12 5,10,13 8 1,16
Input Current linH 4 - 95 /JAde 4 9,12 5,10,13 8 1,16
'eao 4 - - 1.0 .- /JAde 9,12 5,10,13 8,4 1,16
High Output Vortage VOH 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 4 9,12 - .. 5.10,13 8 1,16
3 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 9,12 4 - - 5.10.13 8 1,16
low Output VOllage VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 9,12 4 - - 5,10,13 8 1,16
3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 4 9,12 - - 5,10,13 8 1.16
High Threshold Voltage VOHA 2 -LOBO - -0.980 - - -0.910 - Vdc - 9,12 4 - 5.10.13 8 1.16
3 -LOBO - -0.980 - - -0.910 - Vdc 9.12 - - 4 5.10.13 8 1.16
low Threshold Voltage VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc - 9,12 4 5,10.13 8 1,16
3 - -1.655 - - -1.630 - -1.595 Vdc 9.12 - 4 - 5.10.13 8 1.16
Reference V04tege Vas 11 -1.420 -1.280 -1.350 - -1.230 -1.295 -1.150 Vdc - - - - 5.10.13 8 1.16
Switching Times (50 n Load)
Min Mu Min Typ M •• Min M •• Pulse In Put. Out -3.2 V +2.0 V
Propagation Delay '4+2+ 2 1.0 3.1 1.0 2.0 2.9 1.1 3.3 n, - - 4 2 5.10.13 8 1.16
- -
~ ~ t ~
2 2

~
'4-2-
"'+3-
'4-3+
3
3 t -
-
-
-
-
-
3
3

j t ~ ~ j j
Rise Time 2 1.1 3.6 1.1 1.1 3.7 2

j j j
12+ 3.3
- -

~
3 3

~ ~
(20% to 80'" 13+
Fall Time 12_ 2 - - 2
(20%1080%' 13_ 3 - - 3
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,000 series has been de-
...
(')
signed to meet the de specifications shown
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
...o...
Q)
board and transverse air flow greater than
500 linear 'pm is maintained. Outputs are
terminated through a 50-ohm resistor to
8
:J
-2.0 volts. Test procedures are shown for ~,
only one gate. The other gates are tested :J
r:::
in the same manner.
~

•
4~2
5~3 P SUFFIX
9~6 PLASTIC PACKAGE

'O~7 CASE 648

'2~'4
'3~'5
L-"
V BB
TEST VOL TAGE VALUES
(Volts)
@Test

to.) Temperature VIH max VILmin VIHA min VILA rna. VBB VEE
~ -30 De -0.890 -1.890 -1.205 -1.500 From -52
~ +2SoC -0.810 -'.850 -1.105 -1.415 p,n -:sT
+8So C -0.700 -1.825 -1.035 -1.440 11 ~
MCl0116P Test limits
Pin TEST VOLTAGE APPLIED TO PINS BELOW'
Under -3o"e +2SoC +8SoC
(Vee l
Characteristic Symbol Tes' Min M .. Min Ty. M •• Min M •• Unit VIH mall: VILmin VIHA min VILA max VBB VEE Gnd
Power Supplv Oram Current 'E 8 17 21 mAde 4,9,12 5,W,13 8 1,16
Input Current ImH 4 95 )JAde • 9,12 5,10,13 8 1,16
'CBO • 1.0 )JAde 9,12 5,10,13 8,' 1.16
HIgh Output Voltage VOH 2
3
-1.060
-1.060
-0890
-0.890
-0.960
-0.960
-
-
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vd,
Vd,
•
9,12
9.12
•
-
-
-
-
5,10,13
5.10,13
8
8
1.16
1,16
Low Output Voltage VOL 2
3
- 1890
-1.890
-1.675'
-1.675
-1.850
-1.850
-
-
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vd,
Vdc
9,12
•- •
9,12
-
-
-
-
5,10.13
5.10,13
8
8
1.16
1.16

-•
High Threshold Voltage VOHA 2 -1.080 - -0.980 - - -0.910 - Vd, 9,12 - 5,10,13 8 1,16
3 -1.080 - -0980 - - -0.910 - Vd, 9.12 - • 5,10,13 8 1,16
Low Threshold Voltage VOLA 2
3 -
-1.655
-1655
-- -
-
-1.630
-1.630
-- -1.595
-1.595
Vd,
Vd,
-
9,12
9, '2
- 4
4
-
5.10,13
5.10,13
8
8
1.16
1.16
Reference Voltage V88
" -1.420 -1.280 -1.350 - -1.230 -1.295 -1.150 Vd, - - - - 5.10.13 8 1,16
SWitching Times 150 it load)
Min M •• Min Ty. M •• Min M •• Pulse In Pulse Out -3.2 V +2.0 V
Propagat Ion Delav t4+2+ 2 1.0 2.0 2.9 - - n, - - 4 2 5.10.13 8 1.16
2 - - - - - - 2

~
t4-2_

I I I II I
t4+3_ 3 -
- - - - -
-
-- 3
t4_3+ 3 -
+ - - 3
-
--
Rise Time '2+ 2 - 1.1 3.3 - - - 2
120% to 80%) 3 - - - - - 3

~ ~
'3+

-- --
Fall Time '2- 2 - - - - 2
'120% to 80%) '3_ 3 - - -
- - 3
 DUAL 2-WIDE 2-3-INPUT MECL 10,000 series
"OR-AND/OR-AND-INVERT"
GATE

MC10117

The MelOl17 is a general purpose logic ele-

Po = 100 mW typ/pkg (No Load) ment designed for use in data control, such as
tpd = 2.3 ns typ digital multiplexing or data distribution_ Pin 9
Output Rise and Fall Times: is common to both gates_
= 3.5 ns (10% to 90%)
= 2.2 ns (20% to 80%)
r------ POSITIVE LOGIC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ NEGATIVE LOGIC _ _ _ _---,

4 4
5 5
3
2
6

9 9

10 10
11 veel = Pin 1 ,,~_1~--

L-_r---~ ____ 14 VCC2 = Pin 16 ~_~--~~ ___ 14

15 VEe = Pin 8 ~-~__~---o15

12 12
13 13

2 = (4 + 5) • (6 + 7 + 9) 2 = (4.5) + (6.7.9)
3 = (4 + 5) • (6 + 7 +9) 3= (4e5) + (6-'-9)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@250C

V out
VCCI = VCC2 OR-AND- V out

''m
+2.0 Vdc I NVEAT OR-AND

Coax
PROPAGATION DELAY
""'c...
r - - - - - --.-------,
I I

~----+1.11 V

---~-+O.31 V

V out OR·AND

Input Pulse t+
t+ = t- = 2.0 ±. 0.2 ns t-
(20 to 80%)
V out OR·AND·INVERT

L _ _ _ _ _ _ _ _ _ _ ----l

5O..ohm termin.tton to Ground 10- ~ Unused outputs connected to

CIIted in •• ch scop. chenne' input. a 50-ohm resistor to ground
All input and output cables to the
scope are equal lengths of 50-ohm
I
_
0.1 ,.,F

coaKial cable. Wire length should -

:7n ~n~~~:~~ :~o:::Jt:~it"p~~.input VEE = -3.2 Vdc

s.. Ganaral I nformatlon section for packSging.

3-45
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,QCK) series circuit has been
n
....o
designed to meet the de specifications
shown in the test table, after thermal equi- ....
....
librium has been established. The circuit is 4

8""""
in a test socket or mounted on a printed 5
circuit board and transverse air flow greater
~3
than SOO linear fpm is maintained. Outputs ::J
are terminated through a 50-ohm resistor to ~.
6~ ::J
-2.0 volts. Test procedures are shown for C
~
only one gate. The other gates are tested

-
in the same manner.
L SUFFIX
CERAMIC PACKAGE
10 CASE 620
11
~14
15
12
13~
TEST VOLTAGE VALUES
(VoI..1 I
@IT.st
Temperature VIHma VILmin VIHAmin VILA INX VEE
_30 G e -0.890 -1.890 -1.205 -1.500 -5.2
t.)
+25o C -0.810 -1.850 -1.105 -1.475 -5.2
,i. +85"C -0.700 -1.825 -1.035 -1.440 -5.2
0>
MCl0111L Test limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
-lODe +25"C +850 C
Under IVeel
Characteristic Svm~ Test Min Ma. Min TV. Ma. Min Ma. Unit VIH max VIL min VIHAmin VILA max VEE Gnd
Power Supply Drain Current IE 8 20 26 - - mAde - - - 8 1,16
Input Current lin H 4 - - - - 265 - - ./JAde 4 - - - 8 1,16
9 - - - - 350 - - ./JAde 9 - - - 8 1.16
lin l 4 - - 0.5 - - - - ./JAde - 4 - - 8 1,16
9 - - 0.5 - - - - .lJ Ade - 9 - - 8 1.16
Logic "1" Output Voltage VOH 2 -1.050 -0.890 -0.960 - -0.810 -{).890 -0.700 Vd, 4,9 - - - 8 1,16
3 -1.050 -0.890 -0.960 - -0.810 -{I.890 -0.700 Vd, - - - - 8 1,16
Logic "0" Output Voltage VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vd, - - - - 8 1,16
3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vd, 4.9 - - - 8 1,16
Logic "1" Threshold Voltage VOHA 2 -1.080 - -0.980 - - -0.910 - Vd, 9 - 4 - 8 1.16
3 -1.080 - -0.980 - - -0.910 - Vd, - - - 4 8 1,16
Logic "0" Threshold Voltage VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc - - - 4 8 1,16
3 - -1.655 - - -1.630 - -1.595 Vd, 9 - 4 - 8 1.16
Switching Times (50 n Load) +1.11 V Pul.ln Pul_Out -3.2 V +2.0 V
Propagation Delay t4+2+ 2 1.4 3.9 '4 2.3 3.4 1.4 3.8 ns 9 - 4 2 8 1,16
-

~ ~
t4-2_ 2 2

I Ij
t4+3- 3 - 3

+ +
j j
-
Rise Time
t4-3+
'2+
3
2 0.9 4.1 1.1 2.2
+
4.0
+
1.1 +
4.6 -
3
2
- 3

~
(20'080%1 '3+ 3
Fall Time '2_ 2 - 2
(20 '0 110%1 '3_ 3
+ + + + + + - 3
 ELECTRICAL CHARACTERISTICS 3:
Each MECL 10,000 series circuit has been
....
(")
o
designed to meet the de specifications
shown in the test table, after thermal equi-
........
librium has been established. The circuit is ......
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
4
5~
8
::J
are terminated through 8 50-ohm resistor to ~3
:.
::J
-2.0 volts. Test procedures are shown for 2 c
only one gate. The other gates are tested 6~
~

-
in the same manner.

9 P SUFFIX
PLASTIC PACKAGE
CASE 648
10
11
~14
15
'---"
12~
13
TEST VOLTAGE VALUES
(Volts)
tiT ...
Temperatur. VIH max VIL min VIHA min VILA max VEE
-30"C -0.890 -1.890 -1.205 -1.500 -5.2
w +25o C -0.810 -1.850 -1.105 -1.475 -5.2 !
~
..... +85"C -0.700 -1.825 -1.035 -1.440 -5.2
Mel0117P Te. Limfts
Pin TEST VOLTAGE APPLIEO TO PINS LISTEO BelOW,
Undlr -30"e +25"C +85"e 1Veel
Ch.KC.ristic Symbol Tost Min Mu Min TVp Ma. Min M •• Unit VIH max VIL min VIHAmin VILA m.x VEE Gnd
Power Supply Drain Current IE 8 - - - 20 26 - - mAde - - - - 8 1.16
Input Current 'in H 4 265 ~Adc 4 8 1.16
9 - - .- - 350 - - .Adc 9 - - - 8 1.16
lin L 4 - - 0.5 - - - - .Adc - 4 - - 8 1.16
9 - - 0.5 - - - - .Adc - 9 - - 8 1.16
Logic "1" Output Voltage VOH 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 4.9 - - - 8 1.16
3 -1.060 -0.890 -0.960 - -0.810 ~890 -0.700 Vdc - - - - 8 1.16
Logic "0" Output Voltage VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc - - - - 8 1.16
3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 4.9 - - - 8 1.16
LogK: "'" Threshold Voltage VOHA 2 -1.080 - -0.980 - - -0.910 - Vdc 9 - 4 - 8 1.16
3 -1.080 - -0.980 - - -0.910 - Vdc - - - 4 8 1.16
Logic "0" Threshold Voltage VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc .- - - 4 8 1.16
3 - -1.655 - - -1.630 - -1.595 Vdc 9 - 4 - 8 1.16
Switching Times (50 n loadl +1.11 V Pul.ln Pul_Out -3.2 V +2.0 V
Propagation Delay ~+2+ 2 - - 1.4 2.3 3.4 - - ns 9 - 4 2 8 1.16
- - -
~
- -

~ ~
'4-2- 2 2

I
14+3- 3 - - - - - 3
'4-3+ 3 - - - - - 3
Rise Time
120'080%1
Fall Time
120'080%1
'2+
'3+
'2_
'3_
2
3
2
3
-
-
-
-
-
-
-
-
1.1

~
2.2

!
4.0

~
-
-
-
-
-
-
-
-
j -
-
-
-
j 2
3
2
3
j j
 DUAL 2-WIDE 3-INPUT MECL 10,000 series
"OR-AND" GATE

MC10llS

The MC10118 is a basic logic building block

Po = 100 mW tvp/pkg (No Load) providing the OR-AND function, useful in data
tpd = 2.3 ns tvp control and digital multiplexing applications.
Output Rise and Fall Times:
:::: 3.5 ns (10% to 90%)
= 2.5 ns (20% to 80%1

POSITIVE LOGIC NEGATIVE LOGIC

3
4
5
2 2
6 6

Vee1 :::: Pin 1

9 VCC2:::< Pin 16 9
10
Vee = Pin 8 10
11 11
15 15
12 12
13 13
14 ·Collector Dot 14

SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS@2SoC

VCCI = VCC2
+2.0 Vdc V out

CoaM.

PROPAGATION OELAY

Input

Pulse Generator

Input Pul ..
t+ .. t- ~ 2.0 ±. 0.2 ns
(20 to 80%1 V out

5O..,hm to'mlnotlon to ground 10.

c.ted in ••ch &COp. channel input.
L- - - ~-- - ---.J Unused outputs connected to
a 50-ohm resistor to ground

All input and output coblo. to tho I-= 0.1 ~F

scop. ar. equal lengths of 50-ohm
coe.iel cabl.. Wire length should
be < 1/4 inch from TPin to input VeE = -3.2 Vdc
pin end TP out to output pin.

See Genera' I nformation section for packaging.

3-48
 ELEC1RICAL CHARACTERISTICS s:(")
Each MECL 10,000 series haS been de,
signed to meet the de specifications shown
....
in the test table. after thermal equilibrium
has been established. The circuit is in a
....
C
....
test socket or mounted on a printed circuit 00
board and transverse air flQW greater than
500 linear fpm is maintained. Outputs are 8
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for
...5'
::J

onlv one gate. The other gates are tested 11 c:

in the same manner. 15 CD
12 a.

-
14

L SUFFIX
CERAMIC PACKAGE
eASE 620

,
TEST VOLTAGE VALUES
ct> (Volts)
~ @Test
Temperature VIHmax Vil min VtHA min VILA max VEE
_30 o e -0,890 -1.890 -1.205 -1.500 -5,2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+8So C -0,700 -1.825 -1,035 -1,440 -5.2
MC10118L Test Limits TEST VOLTAGE APPLlEO TO PINS LlSTEO BelOW:
Pin
Und .. -lOoe +25o C +8So C 1Veel
Characteristic Symbol Tes. Min Max Min Typ Max Min Max Unit VIH max VIL min VIHA min VILA max VEE Gnd
Power Supply Drain Current IE 8 - - - 20 26 - - mAde - - 8 1.16
- -
I nput Current 'In H 6
7
-
-
-
-
-
-
-
-
265
265 - -
~Ade 6
7 -
-

- -
8 1.16

9 - - - - 370 -

-
- + 9
-
-
6
- - +8
+
1.16
lin L 6 - - 0.5 - - - /JAde
7 - - - - - - - 7
9 - .- t - - - -
+ 9 - - + +
Logic "'" Output Voltage VOH 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0,700 Vdc 3,9 - - - 8 1.16
Logic "0" Output Voltage VOL 2 -2.000 -1.675 -1.990 - -1.650 -1.920 -1.615 Vdc - - 8 1.16
Logic "'" Threshold Voltage VOHA 2 1.080 -0.980 - -0.910 Vdc 9 3 8 1,16
Logic "0" Threshold Voltage VOLA 2 -1.655 -1.630 -1.595 Vdc 3 8 1,16
Switching Times (50 H Load) +1.11 V Pulse In Pulse Out -3.2V +2.0V
Propagation Delay t6+2+ 2 1.4 3.9 1.4 2.3 3.4 1.4 3.8 n, 3 -- 6 2 8 1.16
3.8 -

~ ~ ~
1.4

~ ~
'6_ 2- 1.4 3,9 1.4 2.3 3.4
Rise Time C20 to 80%) t+
~ 0.8 4.1 1.5 2.5 4.0 1.5 4.6
4.6
-

•
Fall Time C20 to 80%1 t- 0.8 4.1 1.5 2.5 4.0 1,5
 ELECTRICAL CHARACTERISTICS
3:
Each MECL 10.000 series has be.n de- 3 n
~
signed to meet the de specifications shown
in the test table. after thermal equilibrium
4
o
~
has been established. The circuit is in a 5
~
test socket or mounted on a printed circuit 6
board and transverse air flew greater than
CO
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to 9 8:::l
-2.0 volts. Test procedures are shown for 10 ....
only one gate. The other gates are tested 11 s·
in the same manner. 15
c:
(I)
12 Co

-
13
14
P SUFFIX
PLASTIC PACKAGE
CASE 648

Col TEST VOLTAGE VALUES

g, IVolh'
0 ilT ...
T emperatur. VIH max VILmin VIHA min VILA !NIX VEE
-lOoC -0_890 -1.890 -L205 -1.500 -5.2
+25°C -0.810 -L850 -1.105 -1.475 -5_2
+85o C -0.700 -1.825 -L035 -1.440 -5.2
MCl0118P Test Limit. TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Unci.. -lOOC +25D C +lI!i"c IVCC'
Characteristic JSYmbol I Test Min Ma. Min Typ Ma. Min Ma. Unit VIH max VILmin VIHAmin VILAIU. VEE GncI
Power Supply Drain Current I Ie 8 - - - 20 26 - - mAde - - - - 8 1.16
Input Current I 1m H
I 6
7
-
-
-
-
-
-
-
-
265
265
-
-
-
-
/JAde 6
7
-
-
-
-
-
-
8 1.16

9 - - - - 370 - - + 9 - - - + +
lin L I 6 - - 0.5 - - - - IJAdc - 6 - - 8 1.16
7 - - - - - - -- 7 - -

Logic "1" Output Voltage

9
2
- -
-1.060 -0.890
+ -
-
- - - + -
3.9
9
-
-
-
-
-
+
8
+
VOH -0.960 -0.810 -0.890 -0_700 Vdc 1.16
Logic "0" Output Voltage VOL 2 -2.000 -1.675 -1.990 - -1.650 -1.920 -L615 Vdc - - - 8 1.16
Logic "1" Threshold Voltage VOHA 2 -1.080 - -0_980 - - -0_910 - Vdc 9 - 3 - 8 1.16
Logic "0" Threshold Voltage VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc - - - 3 8 1.16
Switching Times (50 12 Loadl +1.11 V Pulse In Pul.Out -3.2V +2.0 V
Propagation Delay 16+2+ 2 - - 1.4 2.3 3_4 - - ns 3 - 6 2 8 1.16
ts- 2- - - 2_3 3.4 - - -

~ l l ~
L4
Rise Time f20 to IO%J
10%'
.+
.- - - 1.5 2.5 4.0 - -
l -
l
- -
•
fa!1 Time 120 10 1.5 2_5 4.0 - - -
 MECL 10,000 series
4-WIDE 4-3-3-3 INPUT
"OR-AND" GATE

MC10119

The MC10119 is a 4-Wide 4-3-3-3 Input OR-

AND gate with one input from two gates com-
POSITIVE LOGIC NEGATIVE LOGIC mon to pin 10_ Input pulldown resistors elimi-
3 3 nate the need to tie unused inputs to an external
4 4----"',r--' supply_
5 --~ ___ 5
6 6
7 7-~'L._

9 9

10 10 2

11 11 Po = 100 mW typ/pkg (No Load)

12 12---"'.r-- tpd - 2.3 nl typ
13 13--,,-_ Output Alse and Fell Time:
~ 3_5 n. typ (HI" - 90%)
14 14 - 2_5 n. typ (20% - 80%)
15-...... . - - 15-""<::.r--

vee1 "" Pin 1

VCC2 = Pin 16
·Colleetor Dot VEE=Pin8

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 1!l2SoC

+2.0 Vdc

nco.. 25I'FRO.'I'F

r--~l~-_-,
Coax

I~ I
Pulse Generator
I PROPAGATION DELAY
I
Input Pul .. I
t+ - t- ., 2.0 ± 0.2 nl
(20 to 80") I
I
I
I V out
I
I
I
~hm t_ml".tlon to ground 10-
I
~=:
CMed in . .ch .co.,. channel input.
L ___
AU Input end output cabl •• to the
ICOpe .re equal length I of 50-ohm
co._la' cable. Wlr. length should
be < 1/4 Inch from TPln to input
pin and TP out to output pin. VEE:-' -3.2 Vdc

See G.nera' Information seetion for p6ekaging_

3-51
 ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series has been de-
s:
C')
~
signed to meet the de specifications shown
in the test table, after thermal equilibrium o
~
has been established. The circuit is -in a ~
test socket or mounted on a printed circuit (C
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
8
-2.0 volts. Test procedures are shown for ....
:J

onlv one gate. The other gates are tested :J

C
in the same manner.
[
'0

-
"
'2 L SUFFIX

,.'3 CERAMIC PACKAGE

CASE 620
'5

Co) TEST VOLTAGE VALUES

&.
I\) @Test
(Voltsl

Tempetoature VIH max Vil min VIHA min VILA max VEE
_lOGe -0.890 -1.890 -1.205 -1.500 -5.2
+25°C -0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2
MC10119L Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Pin
Unci. -lOoe +25oC +8SoC (VCCI
Characteristic Symbol Test Min Max Min Typ Max Min Max Unit VIH max VILmin VIHA min VILA max VEE Gnd
Power Supply Drain Current IE B 20 26 mAde - - - 8 1,16
Input Current lin H 7 - - - - 265 - - /.lAde 7 - - - B 1,16
9 - - - - 265 - - 9 - - -
10
7
-
-
-
-
-
0.5
-
-
370
-
-
-
-
-
+
,uAde
10
-
-
7
-
-
-
-
+ +
1,16
lin L B
9 - - - - - - - 9 - -

logic "1" 0 utput Voltage

10
2
- -
-1.060 -0.890
+
-0.960
-
-
-
-0.810
-
-0.890 -0.700
- +
Vdc
-
3,10,15
10 -
-
-
-
+
B
+
VOH - 1.16
Logic "0" Output Voltage VOL 2 -2.000 -1.675 -1.990 -1.650 -1.920 -1.615 Vdc - - 8 1,16
Logic "1" Threshold Voltage VOHA 2 -1.080 -0.980 -0.910 Vdc 10,15 3 B 1,16
Logic "0" Threshold Voltage VOLA 2 -1.655 -1.630 -1.595 Vdc 3 B 1,16
Switching Times (50 n Load) +1.11 V Pulse In Pulse Out -3.2V +2.0 V
Propagation Delay t3+2+ 2 1.4 3.9 1.4 2.3 3.4 1.4 3.8 ns 10,13 - 3 2 8 1,16
-

~
1.4 3.9 3.4 1.4 3.8

~ ~
1.4 2.3

~ ~ ~ ~
'3-2-
Rise "Time 120 to 80%. ,+ 0.8 4.1 1.5 2.5 4.0 1.5 4.6 -
Fall Time (20 to 8O%J ,- 0.8 4.1 1.5 2.5 4.0 1.5 4.6 -
 ELECTRICAL CHARACTERISTICS
3:
Each MECL 10,000 series has been de-
signed to meet the de specifications shown
n
~

in the test table. after thermal equilibrium Q

~
has been established. The circuit is in a
~
test socket or mounted on a printed circuit cg
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are n-
O
terminated through a 50-ohm resistor to
...::s:;-

-
-2.0 volts. Test procedures are shown for
only one gate. The other gates are tested
in the same manner.
c:
CIl
Co
'0
"'2 ..... P SUFFIX

,.,.
'3 "tI~'tinl ~ ~ PLASTIC PACKAGE
CASE 648

w TEST VOLTAGE VALUES

~ lilTost
IVoltsl

T emperatur. VIHm.. VIL min VIHAmin VILA miX VEE

-3O"c -0.890 -1.890 -1.205 -1.500 -5.2
+25°C -0.810 -1.850 -1.105 -1.475 -5.2
+85°C -0.700 -1.825 -1.035 -1.440 -5.2
MC10119P Test Limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW,
Und. _30°C +25°C +85o C IVcel
Ch.... ct.'i.ic Sy_ Toot Min Mo. Min Typ Mo. Min M.. Unit VIH max YILmin VIHAmi" VILA.,... VEE Gnd
Power Supply Drain Current IE 8 - - - 20 26 - - mAde - - - - 8 1,16
Input Current lin H 7 - - - - 265 - - ",Adc 7 - - - 8 1,16
9 - - - - 265 - - 9 - - -

lin L
10
7
-
-
-
-
-
0.5
-
-
370
-
-
-
-
-
+
",Adc
10
-
-
7
-
-
-
-
+
8
+
1,16
9 - - - - - - - 9 - -

Logic "1" Output Voltage

10
2
- -
-1.060 -0.890
+
-0.960
-
-
- -
-0.810 -0.890 -0.700
- +
Vdc
-
3,10,15
10
-
-
-
-
-
+
8
+
1,16
VOH
Logic "0" Output Voltage VOL 2 -2.000 -1.675 -1.990 - -1.650 -1.920 -1.615 Vdc - - - - 8 1,16
Logic "1" Threshold Voltage VOHA 2 -LOBO - -0.980 - - -0.910 - Vdc 10,15 - 3 - 8 1,16
Logic "0" Threshold Voltage VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc - - - 3 8 1,16
Switching Times (50 n Load) +1.11 V Pulse'n Pul.Out -3,2 V +2,0 V
Propagation Delay t3+2+ 2 - - 1.4 2.3 3,4 - - ns 10,13 - 3 2 8 1,16
- - - - -

~ ~
3.4

~ ~ ~
1.4 2.3

~ l
'3-2-
Rise Time t20 to 80". .+ - - 1.5 2.5 4.0 - - -
Fall Time 120 to 80%)
.- - - 1.5 2.5 4.0 - - -
 4-WIDE MECL 10,000 series
"OR-AND/OR-AND-INVE RT"
GATE

MC10121

The MC10121 is a basic logic building block

Po = 100 mW typ/pkg (No Load) providing the simultaneous OR-AND/OR-AND-
tpd ::: 2.3 ns typ INVERT function, useful in data control and
Output Rise and Fall Times: digital multiplexing applications_
= 3.5 ns (10% to 90%)
= 2.5 ns (20% to 80%)

POSITIVE LOGIC NEGATIVE LOGIC

:--~--~-------. 4
5
&--'-----------, 6 --L---'----,

7--~--~--~__, 7
9 9

10 2 10 2
3 3

11 11
12--'---./----.,. 12 ---'_..r-~
veel ::: Pin 1
VCC2 0 Pin 16
VEE-Pln8
13-~--~~~--~ ~l-~-~--r--~
14
15--'--------- 15 ---"L---'---

2 ::: (4 ... ~ ... 6) • (7 ... 9 + 10) • (10 + 11 + 12) • (13 + 14 + 15) 2= (4_ se6) + (7 _9_ 10) + (10. 11.12) + (13.14.15)
3= (4+ 5+6) .(7+ 9'+ 10)e(10+ 11 + 12) .(13+ 14+ 15) 3 - (4.5.6) + (7.9.10) + (10.11.12) + (13.14.15)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC

veel =: VCC2
+2.0 Vdc
V out

~,tiJ'"
r----- - - - - - ---.,
Coal(
Coax

I
50
Input Pul ••
50 PROPAGATION DELAY
:z 2.0 ± 0.2 ns
t ... "" t-
(20 to 80%)

+1.11 V
I Vin

I
I
I
5O-ohm termln.tion to ground 10- I V out OR-AND
CIIted in ..ch lcope chennel input.

All input and output cables to the

scope are equal lengths of 50-ohm
----fl_ ::-,,~ - _.J
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.
VE E
1~
= -3.2 Vdc
V out OR AND INVERT

See General Information section for packaging.

3-54
 ELECTRICAL CHARACTERISTICS
E.:h MECL 10,000 _ie.
circuit 11M b8en
delignod to meet tho de spocificotions ...~
shown in the test table, after thermal equi-
...
o
librium has been established. The circuit is
in 8 test socket or mounted on 8 printed
circuit bo..d and transverse air flow greater
i~
...
N

th.. 500 linear fpm is maintained. Outputs

are terminated through a 5O-ohm resistor to 8
-2.0 volts. Test procedures are shown for ....
::J

onlv one gate_ The other gates are tested 7~

5-

-
in the same manner. 9 c:
It>
LSUFFIX c..
2 CERAMIC PACKAGE
1D 3
CASE 62D

11
12~

13~
14
15~ TEST VDL TAGE VALUES
(Volts)
@Test
Temperature VIH max VILmin VIHAmin VILA max VEE
-30D e -0.890 -1.890 -1.205 -1.500 -5.2
Co.) +2S o C -0.810 -1.850 -1.105 -1.475 -5.2

<it +8SD C -0.700 -1.825 -1.035 -1.440 -5.2

UI MCl0121l Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
-3QOe +25D C +8SoC
Under IVeel
Characteristtc Symbol Test Min Max Min TVp Max Min Max Unit VIH max VIL min VIHA min VILA max VEE Gn.
Power Supplv Drain Current IE 8 - - - 20 26 - - mAde - - - - 8 1.16
Input Current lin H 7 - - - - 265 - - #lAde 7 - - - 8 1,16
9 - - - - 265 - - 9 - - -
10 - - - - 370 - -
-
+ 10 - - - + +
lin L 7 - - 0.5 - - - ,u.Adc - 7 - - 8 1.16
9 - - - - - - - 9 - -

logic "," VOH

10
3
-
-1.060
-
-0.890
+
-0.960
-
-
-
-0.810
-
-{).890
-
-0.700
+
Vdc
-
-
10 -
-
-
-
+
8
+
1.16
Output Voltage 2 -1.060 -0.890 -0.960 - -0.810 -{I.890 -0.700 Vdo 4.10.13 - - - 8 1.16
Logie "0" VOL 3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdo 4,10,13 8 1,16
Output Voltage 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdo - - - - 8 1.16
Logic "1" VOHA 3 -1.0B0 - -0.980 - - -0.910 - Vdo - - - 4 8 1.16
Threshold Voltage 2 -1.0BO - -0.980 - - -0.910 - Vdo 10.13 - 4 - 8 1,16
Logic "0" VOLA 3 - -1.655 - -1.630 -1.595 Vdo 4 8 1.16
Threshold Voltage 2 - -1.655 - - -1.630 - -1.595 Vdo 10,13 - - 4 8 1.16
Switching Times
lson Loadl +1.11 V Pulse In Pulse Out -3.2 V +2.0V
Propagation Delay t4+3- 3 1.4 3.9 1.4 2.3 3,4 1.4 3.8 ns 10.13 - 4 3 8 1,16
t4-3+ 3 - 3
t4+2+ 2 - 2

+ + + + + + +
j j
t4-2- 2 - 2
Rise Time
(20 to 8O"XJ
Fall Time
120 to SO%I
'3+
'2+
'3_
'2_
3
2
3
2
0.9

~
4.1

~
1.1

~
2.5

~ ~
4.0 1.1

~
4.6

~
-
-
-
-
j 3
2
3
2
j j
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,000 series circuit has been ...
n
designed to meet the de specifications
shown in the test table. after thermal equi· ...
o
librium has been established. The circuit is
in a test socket or mounted on 8 printed
circuit bo ...d and transverse air flow greater
i~ ...
N

th., 500 line.. fpm is maintained. Outputs 8

are terminated through a S€k>hm resistor to
-2.0 volts. Test procedures are shown for
~~ ...:;i'
:l

only one gate. The other gates are tested c:

-
CD
in the same manner. 10 2 Co
3 P SUFFIX
PLASTIC PACKAGE
11 CASE 648
12~

13~
14
15
TEST VOLTAGE VALUES
(Vellsl
@Test
Temperature VIH max VILmin VIHA min 1 VILA max 1 VEE
_30 Ge -0.890 -1.890 -1.205 I -1.500 I -52
1
-~ 1
-0.810 -1.850 -1.105 -1."75 -52
W - -- ---
~ ~
.
C) MlO,n,,,p -~ I -U./UU - ".LO • "35 I -1.440 I -5.2

TEST VOL TAGE APPLIED TO PINS LISTED BELOW,

IVeel
Characteristic 1 Symbol VIH max VIL min VEE
Unit VIHA min VILA max Gnd
Power Supph,. Drain Current I IE mAd<: 8 1,16
Input Current lin H 7
.Ad<: 8 1,16
9

lin L
+ 10 + +
J..IAdc 8 1,16

Logic "1" I VOH

+
Vdc
10
+ +
1,16
Output Voltage
Vdc 4,10,13 1,16
logic "0" VOL Vdc 4,10,13 1,16
Output Voltage
Vdc 1,16
logic "1" I VOHA Vdc 1,16
Threshold Voltage
Vdc 10.13 1,16
Log" "0" I VOLA Vd<: 1,16
Threshold Voltage
Vdc 10,13 1,16
Switching Times
(SO n load)
Propeg8tion Delav

Rise Time
(20'080%)
FO\lT ....
,~ ... ~ it.-,"

iif'E9.j.111~~ r. CHVI4V<a.ftiI2J.iC2
 MECL 10,000 series
TRIPLE 4-3-3 INPUT
BUS DRIVER

MCl0123

The MC10123 consists of three NOR gates

designed for bus driving applications on card or
between cards. Output low logic levels are
POSITIVE LOGIC NEGATIVE LOGIC
specified with VOL"; -2.0 Vdc so that the bus
may be terminated to -2.0 Vdc. The gate out·
put, when low, appears as a high impedance to
the bus, because the output emitter-followers
of the MC10123 are "turned·off". This elim-
imates discontinuities in the characteristic im-
':~-2
11~
':~2
11~-
pedance of the bus.
The VOH level is specified when driving 8
25·ohm load terminated to -2.0 Vdc, the equ·
12~ 12~_ ivalent of 8 50-ohm bus terminated at both
13, 15 '3~'6
14
ends. Although 25 ohms is the lowest char-
14
acteristic impedance that can be driven by the
Vcc, • Pin 1 Po' 310 mW typ/pI<g (No Load) MC10123, higher impedance values may be
VCC2' Pin 16
tpd - 3.0 nl tvp
used with this part. A typical 50-ohm bus is
Vee - Pin 8
shown in Figure 1.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 26°C

V out
PROPAGAT)ON DELAY

Coax Coax

Input
r----+1.11 V

Puis. Ganerator
- - - - - +0.31 V
I
50

~=
Input Pulse
t+ ~ t-,., 2.0i. 0.2 ns V out
(20 to 80%)

50-ohm termination to ground lo-

~!
~unU"d
cated in each IeOp. channel input.

All input and output cab I•• to the

L - - f:i. outputs connected to •
_.J 25-ohm reslltor to ground.

lCope .r. aque' lengthl of 50-ohm

coaxial cabl•. Wire 'aneth should
be <1/. Inch from TPin to input
pin .,d TPout to output pin.
l*·O"I'F
VEE"" -3.2 Vdc

FIGURE 1 - 5O-0HM BUS DRIVER

-2.0 Vdc -2.0 Vdc

RECEIVERS (MECL Gat.,)

See Ganeral Infornwtion -.:tio" for pack8ll'n8..

3·57
 S
ELECTRICAL CHARACTERISTICS ...
n
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table. after thermal equi- :~3 ...
o
N
7 tAl
librium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow weater
9
'0~ 8
than 500linearfpm is maintained. Outputs 11~2 ....
::J

-
are terminated through a 25-ohm resistor to 12 ::J
'3~~ C
-2.1 volts. Test procedures are shown for
only one input and one output. The other
inputs and outputs are tested in the same
14~15 L SUFFIX
CERAMIC PACKAGE
a
CASE 620
fT'8nner.

TEST VOLTAGE VALUES

(Voh.1
@lest
Temperature VIH max Vilmin VIHA min V,LA m •• VEE
_lODe -0.890 -1.890 -1.205 -1.500 -5.2
W +25°C -0.810 -1.850 -1.105 -1.475 -5.2
m
CJ)
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2
MC10123 Test limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Und.. -3O"C +2SoC +SSoC IVeel
CharKt.istic I Symbol Test Min M.. Min Ty. Max Min Max Unit VIH max VILmin VIHAmin VILA max VEE Gnd
Power Supply DraIn Current I 'E 17 21 mAde 4,5,6.7,9,10 I I I I I 1.16
11,12,13,14
I
Input Current
I lin H 265 ,.Ade 1.16
linL 0.5 ,.Ade 1,16
LogIC "1" VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vde 8 1,16
Output Voltage
Logic "0" VOL -2.100 -2.030 -2.100 -2.030 -2.100 -2.030 Vde 4,5,6,7,9,12 8 1,16
Output Voltage

Logic "1" VOHA -1.080 -0.980 -0.910 Vde 4,5,6,7 1.16

Threshold Voltage
Logic "0" VOLA -2.010 -2.010 -2.010 Vde 9,12 4,5,6,7 8 1.16
Thresl'told Voltage

, , ,
Switchi ng Times Pulse In Pulse Out -J.2V +2.0 V
(50-0hm loadl
Propeglltion Delay 14+3- 1.2 4.6 1.2 3.0 4.4 1.2 4.8 4 3 1.16

RIse Time
t4-3+
'3+
+ +
1.0 3.7 1.0
3.0
2.5 3.5
+
1.0 3.9
(20 to8~)
Fall Time
(20 to 80%)
t~
+ + + 2.5
+ + + 1 1 1 1 1
 QUAD MTTL TO MECL MECL 10,000 series
TRANSLATOR

MC10124

The MC10124 is a quad translator for interfacing

data and control signals between a saturated logic
section and the MECL section of d~ital systems. The
MC10124 has MTTL compatible inputs, and MECL
complementary open-eminer outputs that allow use as
an inverting/non-inverting translator or as a differen-
POSITIVE LOGIC NEGATIVE LOGIC tial line driver. When the common strobe input is at
the low logic level, it forces all true outputs to a
MECL low logic state and all inverting outputs to a
MECL high logic state.
4 4 Power supply requirements are ground, +5.0 Volts,
6 6 2 and ·5.2 Volts. Propagation delay of the MC10124 is
3
typically 3.5 ns. The dc levels are standard or
Schottky TTL in, MECL 10,000 out.
An advantage of this device is that MTTL level
10 12 10 12 information can be transmitted differentially. via
15
balanced twisted pair lines, to the MECL equipment,
15
where the signal can be received by the MC10115 or
11 13 11 13 MC10116 differential line receivers. The MC10124 is
14 14 useful in computers, instrumentation, peripheral
controllers, test equipment, and digital
communications systems.

Gnd=Pin16 Po'" 380 mW typ/pkg (No Load)

Vee (+5.0 Vdc) :0 Pin 9
tJXt "" 3.5 n. typ (+1.5 Vdc in to 50% out)
VEE (-5.2 Vdc) '" Pin 8
Output Rise, Fall Times;
2.5 ns typ (20% to 80%)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25"C

V out V out
+6.0 Vdc VCC NAND AND

Coex

""'J ~,,± f"F"

r-------,
Coax Coax

Input

Pul.e Generator
PROPAGATION DELAY
Unused outputs
Input Pulse connected to a
=
t+ "" t- 5.5 ±O.S ns 50·ohm resistor
(to to 90%) to ground.

0.1 "F
V out AND
50-ohm termination to ground 10-
e.ted in each scope channel input.

All input and output ca~les to the

1C0pe are equal lengths of SO-oh m V out NAND
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.

See Oeneral Information Metlon for ~.ckeglng.

3-59
 ELECTRICAL CHARACTERISTICS s:
(")
Each MECL 10.000 .ries circuit has been
designed to meet the de specifications
...a

-
shown in the test table. after thermal equi·
0
...a
librium has been _Iished. The circuit N
is in a test socket or mounted on a printed 4 ~
circuit board and transv.... air flovv greater 6 2
than 500 lin... fpm is maintained. Out·
puts are terminated through 8 SlH>hm re-
3 8::J
L SUFFIX ~.
sistor to -2.0 volts. Test procedures are
10 CERAMIC PACKAGE ::J
shown for only one translator. The other 12 c::
CASE 620 ct>
tl'1lnslatorlar& tested in the same manner. 15 C.
11 13
14

TEST VOLTAGE/CURRENT VALUES

Volt.
n ...
T.mper ..tur~ V,H Vll "'l1li VIHA' VILA' v, I v. I Vee I VEE I " I'i.
3O'C "0 ><I'D '200 +1.10 ><1.40 ,240 '.00 .S> 10 +1.0
+2SoC "0 ><140 +1.80 +1.10 ><140 +2.40 +5.00 ·5.2 ·10 " 0
+8SoC +4.0 ><1'0 +1.80 +0.90 00.40 +2.40 '.00 ".2 ·10 " 0
MCl0124l T •• llr'1ltl
~
C)
r Ch.,..::t.,,,hc Sv_
......
Pi"

T... M,.
·lOoe
Moo, Mi.
+25°C
Tvo Moo, Min
+8SoC
Moo, Unit V,H VllllWlx
TEST VOLTAGE/CURRENT APPLIED TO PINS LISTED BELOW;

VIHA" VILA' V, V. Vee VEE 'in GM

C NegatIVe Power Supply 'E -66 mAde 16
OrarnCurrenl
pOSllI\le Power SupplV 'CCH 16 5,6.7.10,11 16
Drain Current
ICCL 25 mAde .. 5,6.1,10,11.16
AeverseCurrent 'R 200 Jl.Ade 5,7.10,11 16
SO Jl.Ade 6 16
forward Current I, -12.8 mAde 5},IO,11 16
-3.2 mAde 6 16
I nput Breakdown Voltage eV ln
••
55
Vd,
Vd,
5},10,11,16
6,16
Clamp Input Voltage V, ·IS Vd, 16
IS Vd, 16
High Output Voltage VOH -1060 -0.890 -0.960 -0810 -0890 -0700 Vd, 6.7 16
-1.060 -0890 -0960 -0.810 -0890 -0.700 Vd, 6.7 16
LOW Output Voltage VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vd, 6.7 .. 16
-1.890 -1.675 -1.850 -1.650 -1825 -1615 Vd, 6.7 16
Hogh Threshold Voltage VOHA -1.080 -0980 -0.910 Vd, .. 16
-1.080 -0.980 -0910 Vd, I.
LOW Threshold Vollage VOLA -1655 -1.630 -1595 Vd, 16
-1655 -1630 -1.595 Vd, 16
$Wild,,", TirM t50-H lo.-n +6.0 Vdc Puis-Out +7.0 Vdc
PuIM In ·3.2 Vdc ~dc
PrOPdOJiI'lon Delav
,>3!) Vde 10 50%J(j)
16+1+
'6-1-
IS
10
6 .•
6.0
IS 3.' 6.0 10 6.0
••
7
7
6
6
• I.
t7+1+ 6 .• " 7

... 1 1 1
IS 10 60 6
11_1_
+ 10 •.0 1.'
••
11+3_ 3 1.' 1.0
..•
..0 3

j j
17-3+ 3

*
1.0 •.0 15 3

• ~T'_I20"'0_1
fall TIrM'18O%to2O%1
I I" 1.0 '.2 2.' 3.' '.3 j j j
'1· 1.0 '.2 2.5 3.' 1.1 '.3

(j) see 8'¥ilchi,. time .... CI,cull. P.-o~i9n .;t,li!v••O! this Circ:1I11 is 1PK,il.ild frDtQ;t 1.5 Vdc 11\ to the 50.. pomt on tM..outpul wBVelorm. T'- .3.6 Vdc • " - n ....... IMoItu• •~-Iettc ... ..,.ty·I......... tlttflelil il VOic.positi¥e.)
 EL~ctRICAL CHARACTERISTICS 3:
Each MECL 10,000 lO,in circuit hIS been ...o
o
designed to meet the de specifications
...

-
shOVlIn in the test table, after thermal equi-
librium has been established. The circuit N
is in a test socket or mounted on a printed 4 ~
circuit board and transverse air flOI/II greater
than 500 linear fpm is maintained. Out-
6
3
8
:l
puts are terminated through a 5~ohm re- ~.
sistor to -2.0 volts. Test procedures are P SUFFIX :l
shown for only one translator. The oth.r 10~ 12 PLASTIC PACKAGE C
Cl)
translators are tested in the same manner. CASE 648 Co
~15
11~~ 13
~14

....
' ......_ure
. lOoe
VIM
+4.0
I VIL,....
"'.40
I VIMA'
'200
TEST VOL TAGE/CURRENT VALUES

I VILA'
+1.10
Volt,

I VF
"'.40
I VR
+2.40
I Vee
+5.00
I VEE
-5.2
II
·'0
mA

I lin
+1.0
+2SoC +4.0 00.40 +1.80 +1.10 "'.40 +2.40 +5.00 -5.2 ·'0 +1.0
I I
.......
+8S0 C +4.0 +0.40 1 +1.80 1 +0.90 1 +040 1+2.401 +500 1 ~.2 ·10 +10

..- ..
tAl MC1D124P T . . Limkl

m .... ·...c
.... ....c ...·c TEST VOLTAGE,lCUARENT APPLIED TO PINS LtSTED BELOW:
V,
a-8CtInaec
N9tlW Power Supply 'E
T_ TyO M..
....
M;n I Max I Unit
mAde
V'H Vll"". I VIHA' I VII.A' VA Vee VEE I~
,.
[)fa," Current

POIItM PIMer Supply

o,.ainCurrent
ICCH ,. mAde 5.6.1.10,11 ,.
25 mAde
,.I.
5.6.1.10.11.16

1 1
'CeL

I.,.
ReoverseCurrent
'A 5,1.~0.11
1
200 "Ade

Forw.,d Current
50
_12,8
",Ade
mAd' 5,7,10.11
1 - - -
" -3.2 mAd'
•
I.I.
Input Bq~ Yolt. 8Vin SS Vd, 5.1.10,11.16
5.5 Vd' 6.16

I.I.
Ca.mp Input V~t. V, -1.5 Vd,

.... -t.5 Vd,

I
I.
.1.(8)
~:~
H .... Output Yolt. VOH ~ -<I.9tiO -0.810 -<1890 -0.100 •.7

.... - I
I.I.I.
·1.0S) .(I. . . . -<I.9tiO -0.810 -0.890 -0700 •. 7
Low Output Volt. . VOL -,-, .... -1,675
-1.675
-1.850
-1.850
-1.650
-1.650
-1825
-1.825
-1615
-1615
Vd,
Vd,
I -
.,7
I ..7

Hogh Tt'lreshokl Volt. YOHA -1.080 -0.980 -0.910 Vd,

-1.'" -
I.
-0.980 -0.910 Vd,
Low Threshold Volt. VOLA -1.656 -1.630 -1595 Vd' 16
-1.655 -1.630 -1.595 Vd'
.......... T ..... lI01I . . .1 -ttI.OVdc Pul.ln

•• ,
Pu. . Out +,.09Vdc 1·3.2_V* +2.DV*
PrClplphon Delay
1+3.5 Ydc to SO'Mo)(j)' ....,-
teH+ 1.0 3.5 6.0 7
7
'6

t7+1+ • 7
t'_I_
+
t7+3-
1 1 1 J

j j
1'_3+ J

R_Tlrne'~toam..1
'I. 2.5 3."

F"'T"ne ,am..tolO'lliol I,. ,., 7.5 3.9

<D See_lid... ", lime IHI cirCUli. Pr~lIondea.v for Ih"ewcuII tslPKihed from +1.5 Vde in 10 Ihe50% point on Iheoutput waveform. The +3.5 Yde IS shown tM!,ebec.ause ilIl1loglc ilInd supply levels are shifted 2 voltspo$,t,ve)
 QUAD MECL TO MTTL MECL 10,000 series
TRANSLATOR

MC10125

The MC10125 is a quad translator for interfacing

data and control signals between the MECL section
and saturated logic sections of digital systems. The
MC10125 incorporates differential inputs and Schottky
MTTL "totem pole" outputs. Differential inputs al-
low for use as an inverting/non-inverting translator or
as a differential line receiver. The Va8 reference volt·
POSITIVE LOGIC NEGATIVE LOGIC age is available on pin 1 for use in single-ended input
biasing. The outputs of the MC10125 go to a low logic
level whenever the inputs are left floating.

~~4 Power supply requirements are ground, +5.0 Volts

and -5.2 Volts. Propagation delay of the MC10125

~~5
is typically 4.5 ns. The MC10125 has fanout of 10
MTTL loads. The dc levels are MECL 10,000 in and
Schottky TTL, or MTTL out. This device has an
,o~ '2 ,o~ '2 input common mode noise rejection of ±1.0 Volt.

" "
An advantage of this device is that MECL levBI
information can be received, via balanced twisted pair
'4~ '3 '4~ '3 lines, in the MTTL equipment. This isolates the MECL
'5 '5 logic from the noisy MTTL environment. This device
L--, L--, is useful in computers, instrumentation. peripheral con·
VeB VBB trollers, test equipment and digital communications
systems.

Gnd '" Pin 16

Vee (+5.0 Vdc) = Pin 9
VEE (-5.2 Vdc) = Pin 8 Po"" 380 mW typ/pkg (No Load)
tpd "" 4.5 ns typ (50% to +1.5 Vdc out)
Output Rise, Fall Times;
2.5 ns typ (20% to 80%)
VCCmax:=: +7.00 Vdc

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S oC

Vcc V aut Vec

G"~
+5.0 Vdc

Coax
rO. 1 I'F
280

450
Input r-- --,
I
Pulse Ganerator
All Diodes

J
Input Puis.
CL MMD7000
t+ .. t- = 2.0 ±O.2 ns or Equiv.
120 to 80%)

-'.69 Vdc o--+-__-I-....oq-,

I
50-ohm termination to ground lo-
I
cated in each scope channal input. '-----t--t V8B I PROPAGATION DELAY

All input and output cables to the

scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
L;;,--nJJ
,~ 8

Oo'IlF
V out
CL "" 26 pF, Including ten fixture
-5.2 Vdc
One input from each gate must be tied to VBe VEe
(Pin 1) during testing.

Se. General Information section for peck aging.

3-62
 ElECTRICAL CHARACTERISTICS
3:
Each MECL 10,000 series circuit has been
~~4 ....00

-
designed to meet the de specifications
shown in the test table, after thermal equi- ....
librium has been established.
is in a test socket or mounted on a printed
The circuit
;~5 N
CJ1
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Test 10~ 12 n0
11
procedures are shown for only one trans-
lator. The other translators are tested in
L SUFFIX ....
::J

the same manner. 14~ 13 CERAMIC PACKAGE

CASE 620
::J
£::
15
L-1
'"
~
VBB

TEST VOL TAGE VALUES

(Volts)
@I Test
Temper,.tur.
-lOoe
VIH rna"
-0.890
VILmin
-1.890
VIHAmin VI LA milx VIHH VllH VIHL VrLL
-1205 -1500 +0.110 -0.890 -1.890 -2Jl9O
V.. l Vee
+5.0
1 VEE
-S.2
From
+25o C -0.810 -1.850 -1.105 -1475 +0.190 -0.850 -1.810 -2,ffiO Pin .50 -52
+8SOC -0.700 -1.825 -1.035 -1.440 'OJJO -0.825 -1.700 -2825 I '50 I -52
MCl0125L rm limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
I
II Undo< -lOoe '25"<: +8SOC Output
Co)
Ch .. .ct.rdtic Gnd CONhtion
cD
Co) Negiltlve Power Supplv
Svmbol Tos' Min Mo. Min Ty. Mo.
40
Min Mo. Unit
mAde
VIHmu VILmin VIHAmin VILA max VIHH VllH VIHl Vlll V ••
3,7.11.15
Vee
9
VEE
B I.
'E
Drain Current
POSitive Power SupplV ICCH 52 mAde 2,6,10,14 3,7,11.15 I.
Dram Current 16
'eel 39 mAde 2,6,10,14 3,7,11,15
Input Cuuent lin H (J) 115 ",Adc 2,6,10,14 3,7,11,15 16
Input leakage Current 'CBO 1.0 ""Adc 3,7,11,15 2.6,8,10,14 16
High Output Voltage VOH 2.5 2.5 25 Vdo 2,6,10,14 3,7,11,15 B IS ·20mA
low Output Voltage Val 0.5 0.5 05 Vdo 2,6,10,14 3,7,11.15 IS lOrnA
High Threshold Voltage VOHA 2.5 2.5 2.5 Vdo 6,10,14 3,7.11.15 16 -2.0mA
low Threshold VOltage VOLA 0.5 05 0.5 Vdo 6.10,14 3.7.11,15 16 20mA
Indetennin . . Input VOlS' 0.5 0.5 05 Vdo 2,3,6.7,8, 16 20mA
Protection Tests 10,11,14,15
VOLS2 0.5 05 05 Vd< 8 IS 20mA
Short,ClrCUIt Current T lOS 40 100 mA 2,6,10,14 3.7.11.15 4,16
Reference Voltage VB. -1.420 -1.28 -1.350 -1.230 -1295 -1150 Vdo 2.6,10,14 3.7.11.15
Common Mode
Rejection T8$ts
l VOH
2.5
2.5
25
2.5
2.5
2.5
Vdo
_.
16
16
-2.0mA
-2.0mA

Val 0.5 0.5 0.5 Vd< 16 120mA

0.5 0.5 0.5 16 20mA
Switchi . . Til'l'lft
Propaplion Delay
I '6'S-
1.0 6.0 1.0 4.5 6.0 1.0 6.0
Pulse In
6
Pul.OUt CL Ipfl
25 3.7.11.15 8 16

~ ~ ~
150% 10 +1.5 Vdc) 6

~
I
'&-5'
t2+4- 2

R;,. T;me "1.0 Vdc '0 2.0 Vdd

Fall Time (+1.0 Vdc t02.0 Vdc)
I t2_4+
'4'
'4_ ! + +
3.3
3.3
3.3
3.3
+
3.3
3.3 1 ! ! 1 1 1 1
<J) Individuilily test -=h input. ~Iy VIH max to pin under test.
 ELECTRICAL CHARACTERISTICS
Each MECL 10,000 se,ies ci,cuit has been
designed to meet the de specifications
shown in the test table, after thermal equi-
librium has been established. The circuit
is in • test socket or mounted on a printed
circuit board and transverse air flow greater
th., 500 Ii.... fpm i. maintained. Test
procedures •• shown for only one trans-
10
11
~ =:::t>---
~ =:::t>---
=:::t>---
4

12
,. ....s:
n
o
N
C1I
C')
o
::J
'ator. The other translators are tested in
the urn. manner. 14
15
=:::t>--- 13
PSUFFIX
PLASTIC PACKAGE
CASE 648
~.
::J
c:
a
L-l
VSS

TEST VOL TAGE VALUES

. ''''
Temperature VIHml. Vilmin
(Volu!

V.. Am,n VI LA ml" V,HH VILH VIHL VILl I I v.. I Vee I VEE
-lOoe -0.890 -1.890 -1205 -1500 +0110 -0.890 -1.890 -2890 •• 0 ·52
From
+25°C -0.810 -'850 -1 105 -1475 +0.190 -0.850 -1.810 -2.850 Pm +5.0 -5.2
+8SOC -0700 -1825 -1035 -1440 'O:JJO -0.825 -17001. 282• I ".0 I ·.2
MC10125P T_ Limit.
Pin

,_
U..... -3O"e +>sOC +8SOC
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
I
m II
Output
W C.....ect.ristic Condition
Symbol Min Mo. Min TV. Mo. Min Mo. Unit VIH max VIL min VIHAmin VILAmu V:"iH VILH VIHL VILL V•• Vee VEE God
N~r"e Power Supply IE 40 mAdc 3,1,11.15 8 16
~
Dram Current
POSItIve Power Supply leO-l .2 mAdc 2,6,10,14 3,1,11,15 16
Drain Current 3,1,11,15 16
leCl 39 mAdc 2,6,10,14
Input Current linH <I> II. s.cAdc 2,6,10,14 3,1,11,15 16
Input Leekage Current ICBO 1.0 J,lAdc 3,1,11,15 2,6,8,10,14 16
HI~ Output Voltage VOH 2.' 2.' 2.' Vd, 2,6,10,14 .~

3,7,11.15 8 16 -20mA
LOw Output VOltage VOL 0.' a.• 0.' Vd, 2,6,10,14 3,7,11,15 16 20mA
High Threshold VOltage VOHA 2 .• 2.' 2.' Vd, 6,10,14 3,7,11,15 16 -2.0 rnA
Low Threshold VOltage VOLA 0.' 0.' 0.' Vd, 6,10,14 3,7,11,15 16 20mA
Indelermin... Input VOlSl 0.' 0.' 0.5 Vd, 2,3,6,7,8, 16 20mA
Protecttan Tests 10,11,14,15
VOlS2 0.' 0.' 0.5 Vd, 8 16 20mA
Short·Circuit Current lOS 40 100 mA 2,6,10,14 3,7,11,15 4,16
Ret.,ence Volt.
Common Mode
ReJection Tests
VB.
VOH
-1,420
2.'
-1,28 -1,350
2.'
-1,230 -1295
2'
-1.150 Vd,
Vd,
2,6,10,14 3,7,11,15 16
16 T -2 OmA
-2,0 rnA
VOL
2.'
0.'
2.5
0.'
2.'
A. Vd, ,.
16

16
120mA
20mA
0.' 0.' 0.'
SWi.intTi ....
Prop-o-llon Oelav
(~to +1.5 Vd(1
I~+~ 1.0 4.5 6.0
Pulse In
6
Pulse Out Cl (pF)
2. 3,7,11,15 16

~ ~
'6-5+ 6

I
12+4- 2
+
~ ~ ~
12-4+
RilO Timo 1+1.0Vdc 10 2.0 Vdcl
Fett Timtt+l,OVdc to 2,0 Vdd

(J-·',,"~idu.lly
'4+
.....

....... Inpu'r,.-v VIH INK to pin t,lnd., teat.

3.3
3.3 1 1 1 1 1 1
 BUS DRIVER
" MECL 10,000 series
'------------'
MC10128

Ad vance InforIllation
The MC10128 is designed to provide outputs which are
compatible with IBM·type bus levels; or, if desired, it will
drive TTL type loads andlor provide TTL three·state out·
puts. The inputs accept MECL 10,000 levels. The MC·
10128 output levels can be accepted by the MC10129
Bus Receiver.
The operating mode I BM or TTL is selected by tying
the external control pins to ground or leaving them open.
Leaving a control pin open selects the TTL mode, and
tying a control pin to ground selects the I BM mode.
The TTL mode will drive a 25-ohm load, terminated to
+1.5 Vdc or a 50·ohm load, terminated to ground. The
device has totem· pole type outputs, but it also has a dis·
able input for three· state logic operation when the circuit
is used in the TTL mode. When in the high state the disable
input causes the output to exhibit a high impedance state
when it would normally be a positive logic "1" state. When
the strobe is in the high state it inhibits the output data
to the low state.
Latches are provided on each data input for temporary
storage. When the clock input is in the low logic state,
information present at the data inputs Dl and D2 will be
fed directly to the latch output. When the clock goes high,
the input data is latched. The outputs are gated to allow
full bus driving and strobing capability.
The MC10128 is useful in interfacing and bus applica·
tions in central processors, mini·computers, and peripheral
equipment.

CONTROL'
'3

0"0'-----'-10

'0
CLOCK:6--~-~

RESETo7___+-~_~

DISABLE ,'2
6--~--l----+..J
5
01 SAB L E 2:0----+-1----+...,

6
020----+-1......,

_ _ _3
STROBEo------------~

4
CONTROL2

Vee = Pin 14
Gnd 1 = Pin 16
Po = 700 mW pkg/typ (No Load)
Gnd 2 =: Pin 1
tpd = 12 ns typ
Gnd 3 =: Pin 9
VEE = PinS

Thfll, advance information and specifications are subject to change without notice.
S •• General I nformat-ion section for packaging, and maximum ratings.

3-65
 ELECTRICAL CHARACTERISTICS
-MTTLMODE ~
"fl~~:ynl' l
L SUFFIX
CERAMIC PACKAGE
CASE 620 ..s:..
(")

o
Each MECL 10,000 series circuit has been N
designed to meet the de specifications
00
TEST VOL TAGE/CURRENT VALUES
shown in the test table, after thermal TEST VOL TAGE VALUES n
equilibrium has been established. The Volts
mAde I /JAde mAde
o
:l
circuit is in a test socket or mounted on a @Test ~.
printed circuit board and transverse air Temperature I
VIHmall.1 Vilmin VIHAmin VllAmallJ: I VEE Vee ~IOHI1 'OH2 ~ 'Ol
:l
flovv greater than 500 linear fpm is _lODe -0890 -1.890 -1.2051 ., 500 ·52 +5.00 -50
c::
'00..1 +56 CD
maintained. +25°C -0.810 -1.850 -1.105 -1475 ·52 +5.00..1 -50 1
Q.
- '00...l +56
+85 0 C -0.700 I ·1825 I -10351 -'440 -5.2 +5.00 I
-50 -'00 I 1 +56
Pin MCl0128L Tnt Limits
TEST VOL TAGE APPLIfEO TO PINS LISTED BELOW:
Und.r -JO"e +25 oe +8So C
Char.t.risttc: Symbol I Te>st Min I Mn I Min I Max I Min I Max I Unit I VtHmaxl VILmin IVIHAmin I VllAm.lI{ I VEE I Vee IIOHl I IOH2 IOl Gnd
Negat.v. Power Supply 'E 97 I - I - I mAde I 6,11 I I 8 I 14
Drain Current '. 9.16
Positive Powe, Supply ICC '4 73 mAde 6,11
'4 1 9.16
Drain Current
Input Leakage Current linH 620 /JAde 8 '4 1. 9.16
350

l.nL
"
'0

'2
All
-0.-5~-
265
265
500 1
.£.lAde
10

"
'2 !! '4
!
1, ,9.16
Logic "1" Vd<
to)
en Output \loltage
VOH '5
'5
2.5
~ Vd< "" '4
,4 2~'5 1 2,'5
1, ,9,16
1. ,9,16
en logIC "0" VOL '5 0.5 Vd< 3

1
'4 - 2.15
Output Voltage '. ,9.16
2 0.5 Vd< 3 - 2,15 I, .9.16
'4
logic "1" ~ Vd< ®
Threshold Voltage
Logic "0"
VOHA '5
2 2._5_ Vd< "
6
10
1O@ '4
'4
2,15
2,15
1. ,9,16
1..9,16
0.5 Vd< 7,10
Threshold Voltage
VOLA '5
0.5 " '4 2,15 1. ,9 .16

Output S~on Circuit Current IsC -1.- 2

260
260
Vd<
mAde
mAde "
6

6
7.10
'4
'4
2.15 ',.9,16
1.2 .. 9.15,16
'4 1,2 .. 9.15,16
SwitehingTimes t
Propagation Delay
Data Input ,5 3.5
,. -0.890 V -1.690V Pulse In Pulse OUt

-
""
·'1+15+ '0 '5 I 8 I '4 I 1.9.16
111-15- '5 '8 '0
Clock Input 110-15+ 15 $ 20 10,11

Reset Input
'10-15-
17+15-
17+2-
'5
15 ~
2 2
2

1 !,. "6
10,11
7,10
7,10
1
STROBE Input 2.5
13+15- '5
" '0 3 '5

Setup Time
13-15+
13+1-
13-1+
tsetupH
'5

'5
! ~ !
10.11
'5
2
2
'5
tsetupl '5
Hold Time tholdH '5
lholdl '5 1
Rise Time 120% to 80%1
Fall Time (20% to 80%)
115+ '5 '.0
1.0
I •. 0
8.0
'0
10 "
"5- '5

(J)
"
Apply VILmin individu.lly to pin under test.
<D OutPU11etct.::t to logic Low SUte priOf' to tftt.
A pulse i5 applied to pin 10.
V," "LFVI"
(%) OutPUt tett:h«I to logic High ,tate prior to test,
ts.. .......fM V1LA--i ~100n.. cmin
MC10128 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@250C - MTTL MODE

V@C~5TOV:C, ~F
+5.0 Vdc

CONTROL'
-=- '3
1------.2..4 ----- -,

11 I I
o-+---~D I 280
I

Input '0
All Diodes
MMD7000
Pulse Generator or Equiv.

Input Pulse
t+ = t - = 2.0 + 0.2 n5
12
15V
(20 to 80%)
PRF::: 1.0 MHz
V,H = -0.890 6 CL =- 20 pF, including test fixture
VIL = -1.690

I
I
I
3 I
I

L---')Cr---rt,"~~
L'fdC
VEE

~---~ ------0.890
50-ohm termination to ground lo-
50%
' -_ _ _ _ -1.690 cated in each scope channel input.
o
All input and output cables to the
~-------0.890 scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin
c:-----~,------- -1.690 and TP out to output pin.

3·67
 - ::
ELECTRICAL CHARACTERISTICS L SUFFIX
CERAMIC PACKAGE
-IBMMODE ,I I CASE 620 (')
~
Each MECL 10,000 series circuit has been 0
designed to meet the de specifications Rm T,i-- ~

shown in the test table, after thermal ~::::~:

equilibrium has been established. The
> TEST VOLTAGE/CURRENT VALUES
TEST VOLTAGE VALUES mAd. /JAde
N
CO

D ~'.'-
Volts
circuit is in a test socket or mounted on a
printed circuit board and transverse air
",l.-
n0
Temperature VIHmax VILmin VIHAmin VILAm•• VEE Vee IOHl IOH2 IOL
flow greater than 500 linear fpm is ::l
-30°C -0.890 -1.890 -1.205 -1.500 -5.2 +6.00 -59.3 -30 -240 ~.
maintained. ::l
STlroil J CO"lR~' 1 +25OC -0.810 -1.850 -1.1OS -1.475 -5.2 +6.00 -59.3 -30 -240
c:
+85 o c -0.700 -1.825 -1.035 -1.440 -5.2 +6.00 -59.3 -30 -240 C!)

Pin MCl0128L T. limits 9;

TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
Under -3o"e +25 o C +8S oC
Cb8ractermic Symbol T... Min M •• Min M •• Min M .. Unit VIHmax VILmin VIHAlnin VILAmax VEe Vee IOH1 IOH2 IOL Gnd
Negative Power Supply 'E 97 mAde 6,11 8 1,4,9,13,16
I'
Drain Current
Positive Power Supply 'ee I. 73 mAde 6,11 1,4,9,13,16
I'
Drain Current
Input Leak. Currant linH 620 /lAde 8 l,4.9,P,16

10
350
265
7
10
"
11
12
265
500 1 11
12 1 1 1
,.,."
linL All 0.5 j.LAdc 1,4,9,13,16
logic "'" VOH 15 3.11 Vd, 11 8 2,15 1,4,9,13,16
Output Voltage 15 5.85 Vd,
W
cD
I Logic "0"
Output Voltage
VOL 15
2
-0.5
-0.5
0.15
0.15
Vd,
Vd,
11
3
3
8
8
,."
2,15
2,15
2,15
1,4,9,13,16
1,4.9,13,16
1,4.9,13,16
Q)
logic "1" VOHA 15 2.9 Vd, 11 10 @ 2,15 1,4,9,13,'6
Threshold Voltage 2 2.9 Vd, 6 7 1O@ " 2,15 1,4,9,13,16
logic "0" VOLA 15 -0.5 0.25 Vd, 11 7,10 "
1. 2,15 1,4,9,13,16
Threshold Voltage -0.5
Output Short Circuit Current 'se
2
15
2
0.25
320
320
Vd,
mAde
mAd,
6
11
6
7,10
,.,.
1. 2,15 1,4,9,13,16
1,2,4,9,13,15,16
1,2,4,9,13,15,16
Switching Times t -0.890 V -1.690 V Pulse In Pulse Out
Propagation Delay
Data Input 111+15+ 15 3.5 23 10 11 15 I 8 I " I - I 1,4,9,13,16
111-15- 15 10 11
Clock Input 110-15+
110-15-
15
15
ffi 10,11

1
10,11
J
~~
Reset Input t7+15_ 11 7,10
17+2_ 6 7,10
STROBE Input 13+15- 15 2.5 11 10 3 15
15

!
13-15+ 15

Setup Time
t3+2_
t3-2+
tsetupH
2
2
15
!
10.11
2
2
15
15

!
1setupL

I
HOld Time lholdH 15
lholdl 15
Aise Time (20% to 80%) t15+ 15 1.0 8.0 10 11
Fall Time (20% to 80%) t15_ 15 1.0 8.0 10 11

ApplV VILmin individually to pin under test.

<D OutPUt latched to logic Low Itate prior to test.
~ A put. is applied to pin 10.
V,H L.r-- V,H

a> Output latched to logic High st ... prior 10 tnt.

~l00n.ec-min
ts..w.veforns VILA--..j
MC10128 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @250C -IBM MODE

VfiC~6TOV:C, ~F
Vin
CONTROL 1
-=- 13

r - - - - - -'4 ----

11 I 450
o--+--~D

10
56 !!
Pulse Generator
Input Pulse
12
t+ '" t- '" 2.0+ 0.2 ns
(20 to 80%) 5 CL - 50pF, Including test fixture

PRF = 1.0 MHz

V,H = -0.890 6
VIL = -1.690

~---""' - - - - - - - 0 . 8 9 0
50%
\..-_ _ _ -1.690
50-ohm termination to ground lo-

r------- -0.890 cated in each $Cope channel input.

c : - - - - - - J - - - - - - - - -1.690
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable, Wire 'ength should be
< 1/4 inch from TPin to input pin
and TP out to output pin.

3-69
MC10128 (continued)

VOLTAGE WAVEFORMS

DATA INPUT

Start Cycle
'11-15 -
,----_.+--+-------------- -0.890
Oata
4-------------1.690

Ou'

STROBE INPUT

-0.890

~
-1.690
Ou'

t3+15-
t3-15+
13+2- t3_2+

CLOCK INPUT

-0.890
200 nl
Data
-1.690
Clock

140 nt

Output

'10_15_

RESET INPUT

Clock
-0.890
~60n.-I
1.690
35 nl 0.890
II 50% \
Resat 60 ns \ -1.690

-
Output +1.5 Volts

j.:==- '7+2_

TTL - MODE IBM - MODE

Vo L '" 0.5 Volts Max Vo L = 0.25 Volts Max
VOH - 2.5 Volts Min Vo H - 5.85 Volts Min

3-70
 '\ MECL 10,000 series
QUAD BUS RECEIVER ~...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----l

MC10129

The MC10129 bus receiver works in conjunction with
the MC10128 to allow interfacing of MECL 10,000 to
other forms of logic and logic buses. The data inputs are
compatible With, and accept MTTL logic levels as well as
levels compatible with IBM-type buses. The clock, strobe,
and reset inputs accept MECL 10,000 logic levels.
The data inputs accept the bus levels, and storage ele-
ments are provided to yield temporary latch storage of
the information after receiving it from the bus. The out-
. puts can be strobed to allow accurate synchronization of
signals and/or connection to MECL 10,000 level buses.
When the clock is low, the outputs will follow the D in-
.puts, and the reset input is disabled. The latches will
store the data on the rising edge of the clock. The outputs
are enabled when the strobe input is high. Unused D
inputs must be tied to VCC or Gnd. The clock, strobe,
and reset inputs each have 50 k ohm pulldown resistors to
VEE. They may be left floating, if not used.
The MC10129 will operate in either of two modes.
The first mode is obtained by tying the hysteresis control
input to VEE. In this mode, the input threshold points
of the 0 inputs are fixed. The second mode is obtained
by tying the hysteresis control input to ground. In this
mode, input hysteresis is achieved as shown in the test
table. This hysteresis is desirable where extra noise mar-
gin is required on the 0 inputs. The other input pins are
unaffected by the mode of operation used .
The MC10129 is especially useful in interface applica-
tions for central processors, mini-computers, and periph-
eral equipment.

POSITIVE LOGIC

DO 7 TRUTH TABLE
1400

0 C STROBE RESET °n+1

<P <P L <P L
<P H <P H L
L L H <P L
<P H H L On
H L H <P H
0113
1501 4J = Don't Care

Po = 750 mW typ/pkg (No Load)

tpd = 10 ns typ
02 6
3 02

Vcc=Pn9
Gnd E: P ns 1 and 16
VEE""PnB
2 03

Hysteresis
Control 50--------'
Clock 11 0--------'
Reset 1 0 0 - - - - - - - - - 4 - - . . . . . J
Strobe 12 o-___________---J

8M General Information .ectlon for packaging and maximum ratln9llnformatlon.

3·71
 00 7 ELECTRICAL CHARACTERISTICS 3:
14 ao
Each MECL 10,000 series circuit has been n
.....
designed to meet the de specifications
o

-
0113
shown in the test table, after thermal
equilibrium has been established. The L SUFFIX .....
15Q1
CERAMIC PACKAGE N
circuit is in a test socket or mounted on a
printed circuit board and transverse air CASE 620
co
02.
3 02
flow greater than 500 linear fpm is main·
lained. Outputs are terminated through a
8
:::J
50-0hm resistor to -2.0 volts. Test pro· ~.
cedures are shown for only one input/out· :::J
put combination. Other combinations are
c::
(!)

.8;
034
2 03
tested in the same manner. • r .., 'I'M..... V'l,",,, V,I-tAm ... V,U_ V... 'IlL V,H'" 'IlL'" V... 'IlL V'H'" V'L'" V ...,,'" VILA"
.
v",

.•'" ..'" .
.... yst••"'., ·0890 ·1890 -'2~ 1500 looo 0400 2000 0800 0.150 2~ 2.Oii
.~Oc 0810 -'850 ,"06 _IU5 l.l1
Control
Cloek 11 -0700 ·1 US ·1Q3S ,'UD lO(lO 0400
'
S:= ~~:::===::::::=~ ........... ,cw...
."", ."",
u.... 1 V'H,"I.I 'I,l ...... Iv,H.I....... lv~,J V... ! V'L ! VIH'" ! 'I'L'" I VIH! V'L I V'H'" I VILA' I V'H"" I V'L"'" I V,.. " ..,! VIU.": I Vcc<J Vn

~lwO,.'''O''''.n'l 'E
."'" "" 5'..1 'i~i~"
'01'''.. ' _ ' '
Supply Dr.,nc"".n,
I ICC

.,,
..'"j,
1.1.

I'Bl
"
"" '"
·'t"
T "" i II 1.1'

w•

.....
"-l
I
Il~~:·~o". VOH
~~
17

"
05
,

i -'i 'OjO -Oi or 'OJ 'iJT r

T "
"
1011
iiI ,..
':
UI
us

L~p~~~o"... ~ -'r "r

5 O
'r "r ,~

"
!
'l' .·
':
1.Ii,UI
',&.1'
1.11
us

'~~~ovo...
VOL

l; TTT
.Ii
! I
", .·j j 1.1.1.
1,•• 1.
1,18

I \'
Vo .. , ; 10.11

L~"O"
ThFftholdVol,_
lVOL"~'
~(JII
IOi'1
"
•
·j 1.6,18
IiI'

liT · :.5.:I
10.12

~2$
l1t1l

\' I
...... ..,V
-,..,.",- I -
p.op _ _

DI'.I~'
Oo~

'1" .. , ' 4 66 210 10,11

+Z.40V ' .... ' .... .1.IV ..uv +J.oy

'1_14_ 14 31 ,!to " 1.1-

"""
10,11

II
'11.14. 14 21 110
""
....
'1'_'''_ '4 27 110
'12"" 10,11
"2-14.
14
14
16
'6
10
10 lb,ll ""
....
A_,I....." 11'0<14_ 14 80

""4' 14
"" 1,1,'1

I""
'1_14. 14 10,1' 1,1,11
'.!UP
'~OICI
14 25
0 "" " '.'
"
" '0,11
'0," I I
'VW"-"'''''''IICIl_.,!he<MTTlor'8Mlnp,oll_.
--.w ....

j
<D 0..-"'0<> _ hm't. _ _ ... Vee' '60 V

<V '_"_ondl.. '_t ..........m.04VuplQ""" ... , _ ....

'tj.¥
~ V'HA" V'HA'"
CD ,_,I_Ion'''",,,,,,,, ""'" "....,.40 V _ .. ,0~oI' ... I_' "'.... t 1 Hysteresis Mode
@o..... r..-"',.. ........ t
....-...
pr ... " " _
V,M"'. 'I'L"'.' " ........ ,.... '"''" _ ' . . .a· IIITTL "' ..... oId " " ' ' -
V out Logic"1" Threshold Voltage
V'M"", V'lo"'", ViM ...•·• _
~
V'L .....· . . ,""" "I'" _Iotic '"0'" ",..... oId yoU_,n .... ""......... ..,_
Logic "0" t
I I" .
... -. 'V'LA"': V,LA'"
MC10129 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@l2SoC

+5.0 Vdc Vee

~~tLt~~_--,I
Coax
Coax

1 __
Input I
{0+--.._ _ _ _ _--o007 I 0 114
Pulse Generator
I ooo-------~

Input Pulse
I
t+= t- == 5.5 ± 0.5 ns I R
(10 to 90%)
I
I
13
01

Unused outputs
con nected to a
50-ohm termination to ground lo-
50-ohm resistor
cated in each scope channel input.
to ground.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin
and TP out to output pin.
03
I
Hysteresis
Control 5 ~L- _ _ _ _..J II
Clock 11 ~L- _ _ _ _ _~ I
Reset 10

L
Strobe 1 2 o - L - - -
1 16
f[-_------'
o-!L-------~_

________ ___'

~J
8
I

25/lFJ r0 1/lF
32 Vdc
+2.0 Vdc

3-73
MC10129 (continued)

FIGURE 1 - DATA to OUTPUT FIGURE 2 - STROBE to OUTPUT

(Clock and Reset are low, Strobe i. high) (Data is high. Clock and Reset are low)

~---+5.0V
~--,,------ +1.11 V

Osta _ _ _ _ _J Strobe
' - - - - - ' , - - - - - +2.4 V ' - - - - - +0.31 V

+ ________ +1.11 V
+--- +1.11V

' -_ _ _ _ _ _ _ _ +0.31 V Q
Q------I' +0.31 V

t12+14+ '12-14-

FIGURE 4 - CLOCK to OUTPUT

(Reset i.low, Strobe i. high)

Data +5.0 V
FIGURE 3 - RESET to OUTPUT
(Data and Strobe are high) +2.4 V

CloCk------,. ~---+1.11V

, - - _ , - - - - - - +1.11 V
'-_J ______ +0.31 V

Reset _ _ _ _ _ _ _J 0----1">1- 1-=:::------ +1.11 V

' - - - - - +0.31 V

- - - - - +0.31 V

Clock +1.1' V

t11-14- tl1-14+

+0.31 V

FIGURE 5 - TSET UP AND THOLo WAVEFORMS

+1.11 V
r----_, - - - - - - +5.00 V
50% /50% 150%
o _ _ _-¥ 20% D~L- ----+2.400 V

'~'up
+0.31 V

F-'-h-O-'d---
-

50%
+1.11V

C +0.31 V

tl1-14+

t10+14-

3-74
 '\ MECL 10,000 series
DUAL LATCH
"-------------'
MC10130

The MC10130 is a clocked dual D type latch.

POSITIVE LOGIC NEGATIVE LOGIC
Each latch may be clocked separately by holding
the common clock in the low state, and using
515------, Al 5 - - - - - - ,
the clock enable inputs for the clocking function.
If the common clock is to be used to clock the
latch, the clock enable (CE) inputs must be in
the low state. In this mode, the enable inputs
perform the function of controlling the common
clock (e).
Any change at the D input will be reflected
C 9
5213-+-----, at the output while the clock is low. The out-
puts are latched on the positive transition of the
clock. While the clock is in the high state, a
~e2 11 eE2 11 - - , - - - - "
change in the information present at the data
0210 15 inputs will not affect the output information.
Input pulldown resistors eliminate the need
A212------
to tie unused inputs to VEE.
Output rise and fall times have been opti-
TRUTH TABLE mized to provide relaxation of system layout
vee1 : : :
Pin 1
CE On+1
VCC2 "" Pin 16
and design criteria.
L
VeE"" Pin 8 The set and reset inputs do not override the
Co clock and D inputs. They are effective only
Co
Co Po = 155 mW typ/pkg (No Load)
when either C or CE or both are high.
f/! - Don', Ca,. tpd = 2.5 ns typ

CIRCUIT SCHEMATIC

s .. Gen • • llnformatlon section for packaging.

3·75
 ELECTRICAL CHARACTERISTICS
3:
Each MECL 10,000 series circuit has been
...
n
designed to meet the de specifications
shown in the test table, after thermal equi·
librium has been established. The circuit is
in a test socket or mounted on a printed
Sl 5----------------
...
o
Col
circuit board and transverse air flow greater
01 7 ..
o
than 500 linear fpm is maintained. Outputs CE 1 6
are terminated through a 50-ohm resistor to 8::J
3
-2.0 volts. Test procedures are shown for ~.

-
only one latch. The other latch is tested ::J
c:
in the same manner.
Rl 4~ ~
L SUFFIX

R~ 1:---r-1------------ CERAMIC PACKAGE

eASE 620

14

CE211~
0210 :~~15 @Test
TEST VOLTAGE VALUES
(Volts)

Temperature VIHmax VILmm VIHAmin VILAmax VEE

S212 ~ _lODe
+2SoC
·0.890 -1.890 -1.205 -1.500 -5.2
-0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2
to) MC10130L Test Limits
TEST VOL TAGE APPlIEO TO PINS lISTEO BELOW,
~ Pin
_lODe +2Soc +8So C
0) Und.. (Vee'
Characteristic Symbol Test Min Max Min Typ Max Min Ma. Unit VIHmax VILmin VIHAmin VILAmax VEE Gnd

PO\l\ler Supply Drain Current IE 8 - - - 30 35 - - mAde - - - - 8 1,16

Input Current linH 6,11 - - - - 220 - - /JAde 6,11 - -- - 8 1,16
9 - - - - 265 - - 9 - - -
4,5,9 - - - - 285 - 4,5,9 - - -
+
-

7,10,12,13 - -
-
- -

-
285
-
-
-
-

-
7,10,12,13
-
9 - -
-
+ +
I inL 4- - 0.50 J.lAdc 4 .- 8 1,16
Logic "1" VOH 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 5 .- - - 8 1,16
Output Voltage
Logic "0" VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 4 - - - 8 1,16
Output Voltage
Logic ''1'' VOHA 2 -1.080 - -0.980 - - -0910 Vdc - 9 7 - 8 1,16
Threshold Voltage
Logic "0" VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc - 9 - - 8 1,16
Threshold Voltage
Switching Times (50 n Load) +1.11 V Pulse In Pulse Out -3.2 V +2.0 V
(See Figure 1)
Propagation Delay 17+2+ 2 1.0 3.6 1.0 2.5 3.5 1.0 3.8 n, - - 7 2 8 1,16
3.6 2.7 1.1 3.9 6 5

• I I II
15+2+

II
14+2- 3.6 2.7 1.1 3.9 6 - 4

Rise Time (20% to 80%1

16-2+
'2+
4.3
3.6
+
1.1
-
2.7
4.0
3.5
1.0
1.1
4.1
3.B
-
-
- 6
7
Fall Time (20% to 80%1 '2- 3.6 1.1 2.7 3.5 1.1 3.8 - - 7
Setup Time 1.tup 2 - - 25 - - - - n, <D - 6.7 2 8 1,16
ns ~~6,7_ 8 1,16
Hold Time thold.....::...:... 2 1.5
<D 2

-All other inputsar. tested in the same manner

 ELK.T~~!'; C:HARAC:.1'E_"'S!~CS
e..h '3:
MECL 10,000 _iet circui.t hIS been
designed to meet the de specifications SI 5 - - - - - - - - - - - - - ,
o....
shown in the test table, after thermal equi-
librium has been established. The circuit is
in 8 test socket or mounted on a prtnted 01 7 -;
....ow
circuit bo ..d and tranwerse air flow greater
eEl 6
o
than 500 linear fpm is maintained. Outputs
are terminated through a 5(}'ohm resistor to 8"

•
3 ::J
-2.0 volts. Test procedures are shown for
~.
only one latch. The other latch is tested ::J
in the same manner. c:
(1)
A143 Q.
P SUFFIX
A; 1:--+---------. PLASTIC PACKAGE
CASE 648

14

eE2"~
0210
Q2~15 TEST VOLTAGE VALUES
eVolts)
Test
@I

~
Temperatur. VIHm. . VILmin VIHAmin VILAmix VEE
S212 _lODe -0.890 -1.890 -1.205 -1.500 -5.2
+25o c -0,810 -1.850 -1.105 -1.475 -5,2
+85o C -0.700 -1.825 -1.035 -1.440 -5.2
w MC1013QP Test Limits
~ Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
'-I Und.
_lODe +25 o c +85 oC IVee l
Chllr.ct.istic Sv_' T_ Min Mo. Min TV. Mo. Min M •• Unit V,Hm.. I V,Lm;n I V,HAm;n I V,LAm.. I VEE Gnd
Powver Supply Drain Current
Input Current
'E
linH
8
6.11
9
4.5.9
30 35
220
265
mAde
/.lAde
6.11
9
4.5.9
J 8
1.16
1.16

•
285

lin
'7,10,12,1
4· 0.50
285
p.Adc
7.10.12.13
4
+ +
8 1,16
logic "1" VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 1.16
Output Voltage
logic "0" VOL 2 1-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 4 8 1.16
Output Voltage
logic '.,.' VOHA -1.080 -0.980 -0.910 Vdc 9 1.16
Threshold Voltage
logic "0" VOLA 2 -1.655 -1.630 -1.595 Vdc 1.16
Threshold Voltage
Switching Times (50 n load) Pul. Out I - 3.2 V I +2.0 V

~V
Pul.ln
(See Figure 11
Propagation Oetay 2 - - 1.0 2.5 3.5 - - n, 7 1,16
t7+2+
- - 2.7 - - I 5
t
I j I II
t5+2+
t4+2- - - 2.7 - - 4
t~2+ - -
+ - 4.0 - - 6
Rise Time (20% to 80%) '2+ - - 1.1 2.7 3.5 -
Fall Time (20% to 80%) '2_ 1.1 2.7 3.5
Setup Time
~
2 2.5 n'l <D 6.7 1.16
Hold Time thold 2 1.5 n, I <D 6.7 1.16

·AII other inputs are tested in the same manner

MC10130 (continued)

FIGURE 1 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @25° C

VCCI = VCC2=
+2.0 Vdc V out

Input Pulse
t+= t-= 2.0ns± 0.2n5
(20 to 80%)

Clock Input
":m~'"'
r-

o-t-----iO
s
-,
I

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cabl.s to the

scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
L

ti - ~O.'I'F
j
I
I
TP out

+1.11 Vdc -3.2 Vdc

VIH VEE

+1.11 V

CIOCkl~------------------------- +0.31 V r - : - - - - y - - - - • 1 .11 V

C 50%
------'I '----+0.31 V

-----+1.11 V --------+1.11 V

Rlnpu,~
o
·'---------.0.31 V
'-----+0.31 V t setup

r-+1.11 V Q

S Input 50% ...____~~---------JI'

. +0.31 V
NOTE,
.,
'2+ t setup is the minimum time before the positive .J
transition of the clock pulse (e) that information must
a Output be present at the data input (0).
thold is the minimum time after the positive tran- ~
sition of the clock pulse (e) that information must
remain unchanged at the data input (01.

3-78
 MECL 10,000 series
DUAL TYPE D MASTER-SLAVE
FLIP-FLOP

MC10131

The MC10131 is a dual master-slave type D

flip-flop. Asynchronous Set (S) and Reset (R)
override Clock (CC) and Clock Enable (CE)
inputs. Each flip-flop may be clocked separately
R.s TRUTH TABLE by holding the common clock in the low state
R S °n+l and using the enable inputs for the clocking
L L an function. If the common clock is to be used to
L H H clock the flip-flop, the Clock Enable inputs
H L L must be in the low state. In this case, the en-
H H N.D.
able inputs perform the function of controlling
N.D.:::: Not Defined the common clock.
The output states of the flip-flop change on
the positive transition of the clock. A change
in the information present at the data (D) input
CLOCKED TRUTH TABLE will not affect the output information at any
C D °n+1 other time due to master slave construction.
L <1> an Input pulldown resistors eliminate the need
H L L to tie unused inputs to VEE. Output rise and fall
H H H times have been optimized to provide relaxation
<p "" Don't Care of system design and layout criteria.
e = Ce + ee·
A clock H is a clock transition
from a low to a high state.

Po = 235 mW typ!pkg (No Load)

f Tog = 160 MHz typ

POSITIVE LOGIC NEGATIVE LOGIC

S1 5------------~ R1 "5-------------,

01 7 --------~ 01 7 ---------""I
eEl 6 CE 1 6

3 3

A1 4--+---------~ 51 4 __~----------~
Cc 9 CC 9
A2 13--1-----------, S2 13--~----------~

14 14

CE 2 11 ------.._~ C E 2 11 -----...__--'
02 1 0 --------~ 15 02 10---------""1 15

S212--------------~ R2 12--------------~

vee1 == Pin 1
VCC2 = Pin 16
Vee '= Pin 8

See Gen.,..llnformation section for packaging.

3·79
 ELECTRICAL CHARACTERISTICS 51
s:

-
Eac~ MECL 10,000 series circuit has been
designed to meet the de spacifications shown
01
eEl
7
6 L SUFFIX
n
....
in the test table, after thermal equilibriu m
hilS been established. The circuit is in a
3 CERAMIC PACKAGE o
....
CASE 620
test socket or mounted on a printed circu it R1 4-4+------' w
....
board and transverse air flow greater than cc 9 -i

""'~
500 linear fpm is maintained. Outputs are TEST VOLTAGE VALUES 0-
terminated through a 50-ohm resistor to
152 14 (Valts)
o
-2.0 volts. Test procedures are shown for @Test ....
::J
only one input, or for one set of input con-
ditions. Other inputs tested in the same
CE2 11
0210 02 15
Temperature VIH max Vilmin VIHA min VILA mal( VEe :i"
c
-looe -0.890 -1.890 -1205 -1.500 -5.2
CD
manner. 5212 +25 o C -0.810 -1.850 -1.105 -1.475 -5.2 Co
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2
MC10131 L Ted limits
Pin VOL TAGE APPLIED TO PINS LISTED BELOW:
Under
-lOoC +250 C +850 C (Vee l
Characteristic Symbol Test Min Max Min TV. Max Min M.. Unit VIH max VILmin VIHA min VILA max VEE Gnd
Power Supply Drain Current IE 8 - - - 45 56 - - mAde - - 8 1,16
I nput Current linH 4 330 .uAdc 4 8 1,16
5 - - - - 330 - - 5 - - -

I nput Leakage Current linL

6
7
9
4,5,·
-
-

-
-
-
-
-
-
-
-
-
0.5
-
-

-
-
220
245
265
-
-
--
-
-
-
-
-
!
JJ.Adc
6
7
9
-
-
-
-
-
-
-
-
-
-
-
! !
8 1,16
6.7,9· - - 0.5 - - - - JJ.Adc - - - 8 1,16
Logic "1" VOH 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 5 8 1,16
Output Voltage 21 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 7 - - - 8 1,16
w Logic "0" VOL 3 -1.890 -1.675 -1.850 - -1.650 -1.825 1.615 Vdc 5 8 1. 16
~ Output Voltage
Logic "1" VOHA
31
2
-1.890
-1.080
-1.675 -1.850
- -0.980
-
-
-1.650
-
-1.825
-0.910
-1.615 Vdc
Vdc
7
--
-
5
- 8
8
1,16
1,16
Threshold VOltage 21 -1.080 - -0.980 - - -0.910 - Vdc - - 7 9 8 1,16
logic "0" VOLA 3 - -1.655 - -1.630 - -1.595 Vdc 5 8 1,16
Threshold Voltage 31 - -1.655 - - -1.630 - -1.595 Vdc - - 7 9 8 1,16
Pulse Pulse
SWitching Times +1.11 Vdc In Out -3.2 Vdc +2.0 Vdc
Clock Input
Propagation Delay 19+2- 2 1.4 4.6 1.5 3.0 4.5 1.5 5.0 ns - - 9 2 8 1,16
-

~ ~
9 2

I
2 7

~ ~
I
t9+2+
t6+2+ 2 7 - 6 2
t6+2- 2 + - - 6 2
Rise Time {20 to 80%1
Fall Time (20 to 80%1
Set Input
t2+
t2_
2
2
1.0
1.0
1.1
1.1
2.5
2.5 1 1.1
1.1
4.9
4.9 1 7
-
-
-
9
9
2
2 1
Propagation Delay t5+2+ 2 1.1 4.4 1.2 2.8 4.3 1.2 4.8 ns - - 5 2 8 1,16

~ ~ ~ ~
112+15+ 15 6 12 15
t5+3- 3 - - 5 3

Reset Input
t12+14- I.
+ + + + 9 - 12
I' + +
Propagation Delay t4+2- 2 1.1 '.4 1.2 2.8 '.3 1.2 '.8 ns - 4 2 8 1,16
-
~
113+15_ 15 6 13 15
t4+3- 3 - - 4 3
I.
+ + + + + + -
+ +
•
113+14+ 9 13 I.
Setup Time !setup 7 - - 2.5 - - - - ns - - 6.7 2 8 1.16
Hold Time thold 7 - - 1.5 - - - - os 6,7 2 8 1,16
Toggle Frequency (Maxi 'Tog 2 125 - 125 160 125 MH, 6 2 8 1,16
Individl,laUy tnt each ingut: IPPY VIL min to pin under test.

t.OIollPUJ ,....to be m....[Jd .•ft" .• cloc;k .PU.Iahai bMn IRPlitd to. th:t CE ingyt (gin W J L VI.H .m.x
VILmin
",,""n't~ECTRiCACeHWCT£RlsTICS,""_ADVANCE INFORMA.TION-
S1 5 - .- 3:
...
-
Each MECL 10,000 series circuit has been (")
designed to meet thede specifications shown 01 7

...
2 P SUFFIX
in the test table. after thermal equilibrium CE1 6 PLASTIC PACKAGE 0
has been established. The circuit is in a
test socket or mounted on a printed circuit
3 CASE 648
...
W

A14~
board and transverse air flow greater than
ee 9
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
A213 TEST VOL TAGE VALUES
(Volts)
8
::J
-2.0 volts. Test procedures are shown for 52 14 ~.
@Test
only one input, or for one set of input con- Temperatur. VIH malll VILmin VIHAmin VILA max VEE ::J
CE2 '1 C
ditions. Other inputs tested in the same 0210 Q2 15 -30oe -0.890 -1.890 -1.205 -1.500 -5.2 CD
manner. Co
+25o C -0.810 -1.850 -1.105 -1.475 -5.2
5212
+8S o C -0.700 -1.825 -1.035 -1.440 -5.2
MC10131P Test Limits
Pin VOL TAGE APPLIED TO PINS LISTED BELOW:
_30 o e +2SOC 1 +8SO C (Vee)
Charac:teristic I Symbol I ~,:!~r MinI M8Il Min I Typ I Max 1 Min ~ Max Unit VIH max VILmin VIHA min VILA max VEE Gnd
Power Supply Drain Current I 'E I 8 - I - - I 45 I 56 mAdc 1,16
Input Current I linH I 4 - I - - I - I 330 j.lAdc '1':16
330

Input Leakage Current ImL 4,5,- 0.5

220
245
265 !
j.lAde
7
9 ! ! 1,16
6,7,9" 0.5 j.lAde 1,16
Logic "1" VOH 2 -1.060 -0.890 -0.960 -0.810 -0.8~T-O.7oo Vd, 8 1:16
Output VOltage 21 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vd, 8 1,16
to)
00 I Logic "0"
Output Voltage
VOL 3
31
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650 -1.8251-1.615
-1.650 -1.825 -1.615
Vd,
Vd,
8
8
1,16
1.16
Logic "1" VOHA -1.080 -0.980 -0.910 Vd, 1,16
Threshold Voltage 21 -1.080 -0.980 -0.910 Vd, 1.16
Logic "0" VOLA 3 -1.655 -1.630 1-1.595 Vd, 1,16
Threshold Voltage 31 -1.655 -1.630 -1.595 Vd, 9 1,16
Pulse Pulse
Switching Times +1.11 Vdc: In Out -3.2 Vdc +2.0 Vdc:
Clock Input
Propagation Delay I t9+2- 2 - - 1.5 3.0 4.5 9 8 1,16
2 - - 9

~ ~
I I II
t9+2+
- -

I
t6+2+ 2 6
2 - - 6
Rise Time (20 to 80%1 '6,::- 2 - - 1.1 2.5

yr.
Fall Time (20 to 80%1 '2_ 2 - - 1.1 2.5
Set Input
Propagation Delay I t5+2+ 2 -
-
-
-
1.2 2.8 4.3 8 1,16

~
t12+15+ 15 12 15
t5+3- 3 - -
- -
t12+14- 14
+ + 12 14 + +
Reset Input
Propagation Delay I t4+2- 2
15
-
-
-
-
1.2 2.8 4.3 4
13 15
8 1,16

~
t13+15-
t4+3_ 3 - - 4 3

Setup Time I
113+14+
!se,up
14
7
-
-
-
- 2.5
+ + + 13
6,7
14
+ +
1,16
Hold Time I 'hold 7 - - 1.5 6,7 1;16
Toggle Frequency (Max) I fTog 2 - 125 T 160 MH, 6 ;-:-;s
-IndiVidually test each Input,apply VI L mm to pin under test.
-.
t Output level to be measured after a clock pulse has been applied to the CE Input (pm 6)
. !..IT VIH max
VILmin
-This IS advance information and specifications are subject to change without notice.
MC10131 (continued)

FIGURE 1 - TOGGLE FREOUENCY TEST CI RCUIT

VCC1 = VCC2 - +2.0 Vdc V out

Coax Coax

2
Clock Input (O~_.-jo-_ _ _ _..:6'-1 Qr-------'
9

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm 50
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.

VEE - -3.2 Vdc

FIGURE 2 -SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS @2SoC

VCC1 = VCC2 =
+2.0 Vdc V out

I "put Pulse
ncaa.
t+ = t- = 2.0 ± 0.2 ns
(20 to 80%)
JTPout
Clock Input (O~----;~-o

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the

1:: 0.1 I'F
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input Vee = -3.2 Vdc
pin and TP out to output pin.

, ' - - -__- - - - - + 1 . 1 1 V
C 50%
R Input '-----+0.31 V

o
---J]
S Input _ _ _-'I

Q __ -..J/
Q Output _ _ _ -+J NOTE,
tsetup is the minimum time before the positi ....
a Output ----,1 transition of the clock pulse (el that information mUlt
be present at the data input (0).
thold is the minimum time after the positive tran-
sition of the clock pulse (el that information must
remain unchanged at the data input (0).

3-82
 MECL 10,000 series
DUAL MULTIPLEXER WITH
LATCH AND COMMON RESET

MC10132

The MC10132 is a dual multiplexer with clocked D
type latches. It incorporates common data select and
reset inputs. Each latch may be clocked separately by
holding the common clock in the low state, and using the
clock enable inputs for a clocking function. If the common
clock is to be used to clock the latch, the clock enable
(CE) inputs must be in the low state. In this mode, the
enable inputs perform the function of controlling the com·
mon clock (CC).
The data select (A) input determines which data input
is enabled. A high (H) level enables data inputs D 12 and
D22 and a low (L) level enables data inputs D11 and D21.
Any change on the data input will be reflected at the
outputs while the clock is low. The outputs are latched
on the positive transition of the clock. While the clock is
in the high state, a change in the information present at
the data inputs will not affect the output information.
The reset input is enabled when the clock is in the high
state, and disabled when the clock is low.

POSITIVE LOGIC NEGATIVE LOGIC

All All

011 4 011 4
2 01 2 01

012 5 012 5
CEO 10 CE010
3 01 3 01
Cc 7 Cc 7
A 6 A 6
15 02 15 02
eEl 9 CEl 9
021 13 021 13

140.2 140.2
02212 02212

TRUTH TABLE

R 0 Cc CE °n+1 vee1 = Pin 1

If! L L L L 0= IA. 011) + IA. 012) VCC2 = Pin 16
L L L H VeE = Pin 8
an
L L H L an
L L H H an
If! H L L H
L H L H an Po = 225 mW tvp/pkg (No Load)
L H H L an tpd :::% 3.0 ns typ
L H H H On
H If! <1> H L
(/) E Don't Car.

SH General Information section for packaging.

3·83
 ELECTRICAL CHARACTERISTICS s:
n
Each MECL 10.000 series circuit has been
~
designed to meet the de specifications
shown in the test table. after thermal equ j- Al1
o
~
librium has been established. The circuit is to)
in a test socket or mounted on a printed 011 4 11""---' 2 Q, N
circuit board and transverse air flow greater
than 500 linear 'pm is maintained. Outputs
n-
O
are terminated through a SO-ohm resistor to
-2.0 volts. Test procedures are shown for
0 ' 2,.
CEO 5 ~ ::J
~.
3 01 ::J
only one Iltch. The other latches are tested Cc' ---'~H;- C
in the ~e manner. R6 T ,-, CD
Q.
15 02 . LSUFFIX
_
=:: ,: • III ~ CERAMIC PACKAGE
CASE 620

02212 hL/.=:::r-- 140.2

TEST VOL TAGE VALUES

(Volts)
~T"t
Tempere'ure VIH INX VIL min VIHA min VILA max VEE
_lODe -0.890 -1.890 -1.205 -1.500 -5.2
+2S oc -0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.700 -'.825 -1.035 -1.440 -5.2

Co)

l I I Und",
PI" _lOGe
MCl0132L Test Limits
+25 0 C +8S0C
TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
1Vee'

t Ch"Kteriltic
Power Supply Current
Symbol
IE
Test
a
Min M •• Min Typ
44
M ..
55
Min M •• Unit
mAde
VIH max Vll min VIHA min VILA INX VEE
a
Gn.
1,16
Input Current
I 'in H
I 4 290 .uAdc ---s- r--;-:-;s
5 290
6 390

'in L
7
10
11
4" 0.50
290
265
265 1
J.lAdc
7
10
11 I
-
-
-
4
-
-
--
-
-
-
-
-
11
8 1.16
logic "1" VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vd, 7,9,10 - 8 1.16
Output Voltagl -1.060 -0.890 -0.960 -0.810 -{I.890 -0,700 Vd, 5,11 7,9,10 - - 8 1,16
Logic "0" VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1,615 Vd, 4 7,9,10 - - 8 1,16
Output Voltage -1.890 -1.675 -1.850 -1.650 -1.825 -'.615 Vd, 5,11 7,9,10 - - 8· 1,16

Logic "'" VOHA -'.080 -0.980 -0.910 Vd, 7,9,10 4 8 1,16

Threshold Voltage -1.080 -0.980 -0.910 Vd, 11 7,9,10 5 - a 1,16
Logic "0" VOLA -1.655 -1,630 -1.595 Vd, - 7,9,10 4 - 8 1.16
Threshold Voltage -1,655 -1.630 -1.595 Vd, 11 7,9,10 5 - 8 1,16
SWitching Times (5().ohm load) l.11V +0.31 V Pulse In Pulse Out -3.2 V +2.0V

ProP8lJ8ltion Delay Data t4+2+ 2 1.0 - 3.3 7,9,10 4 2 8 1,16

~ ~
Aeset t6+2- 1.0 3.8
Clock t7-2+ 1.0
I I 5.7
I
• • •
Select t11+2-+ 1.0 4.6 7 11
Setup Time Data tsetup 2.5 11 4,10 2 8 1,16
Select lsetup 3.5 7 10,11 2 8 1,16
Hold Time Data lt10ld 1.5 11 4,10 2 8 1,16
Sliect lt10ld 1.0 7 10,11 2 8 1.16
Ri. Time (20% to 80%) '2+ 1.5 3.5 7,9,10 4 2 8 1,16
hit Ti.,. (2~ to 80%) '2_ 1.' 3.5 7,9,10 4 2 8 1,16

-All other inputs tIIted·in·th. ~ m"1I~.r.

 ElECTRICAL CHARACTERISTICS
r--=--" '" 3:
! Each MECL 10,000 senes circuit has been
designed to meet the de specifications ...
(")
shown in the test table, after thermal equi-
librium has been established. The Circuit is
In a test socket or mounted on a printed
All

011 4 11.,---... 2 Q,
...
o
W
circuit board and transverse air flow greater N
than 500 linear fpm IS maintained. Outputs c:;-
~
are terminated through a 5()..ohm reSIstor to O
0125
CEO '0
::J
-2.0 volts. Test procedures are shown for 3 01 ~.

-
only one latch. The other latches are tested Cc 7 r-----l ::J
in the same manner. A 6 T c:
(I)
15 Q2 Co
PSUFFIX
~:,',: III~ PLASTIC PACKAGE
CASE 648

02212 ~-===r--
TEST VOLTAGE VALUES
(Voltsl
(ilT"t
Tempereture VIH m. . J VIL min I VIHA min VILA .... VEE
_30o e -0.890 -1.890 -1.205 -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2

Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW;

Under ~-:!!;~--+----r2!;!...!:,-~-+--:-::...:..::r-=::­ (Vee l
w Characteristic Symbol T... Unit VIH m •• I Vll min I VIHA min I VILA INX I VEE Gnd
00 Po~r Supply Current 'E 44 I 55 mAde 1,16
U1 Input Current 290 4 8 1.16
lin H

lin L
7

..
10
11
050
290
390
290
265
265
"f
~Adc
5
6
7
10
l' 1 1 1,16
Logie "I" VOH 2 -1060 -0.890 -0.960 -0.810 -0.700 Vd, 7,9,10 1,16
Output Voltage 2 -1.060 -0.890 -0960 -0.810 -0.700 Vd, 5,11 7,9,10 1,16
Logic "0" VOL -1.890 -1.675 -1.850 -1.650 -1.615 Vd, 4 7,9,10 8 1,18
Output Voltage -1.890 -1.675 -1.850 -1.650 -1.615 Vd, 5,11 7,9,10 8 1,16
Logic "'" VOHA -1080 -0.980 Vd, 1,9,10 8 1,16
Tlue5l'l0ld Voltage -1.080 -0.980 Vd, 11 1.9.10 8 1,16
Logic "0" VOLA -1.655 -1630 -1.595 Vd, 7,9,10 8 1,16
Threshold Voltage -1.655 -1630 -1.595 Vd< 11 7,9.10 8 1,16
SWitching Times (Sl).ohm load) +1.11 V +0.31 V Pul .. ln PuI.Ou1 -3.2 V +2.0V

Propagation Delav Data t4+2+ 2 1.0 3.3 7,9,10 I 2 8 1,16

~
Reset ts+2- 1.0 3.8
Clock t7_2+ 1.0 5.7

• • •
Select 1.0 4.6 7 tt

•
tl1+2+
Setup Time Data tsetup 2.5 1i 4,10 2 8 1,16
Select tsBtup 3.5 7 10,11 2 8 1,16
HOld Time Data thold 1.5 11 4,10 2 8 1,16
Select thold 1.0 7 10,11 2 8 1,16
R lie Time (20% to 80%) '2' 1.5 3.5 7,9,10 1,16
Fall Time 120% to 80%) '2- 1.5 3.5 7,9,10 1,16

• All other Inputs tested In the same manner.

MC10132 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

vee1 '" VCC2 =

+2.0 Vdc

Input Pulse
25~F$f$01~F V out

t+ = t- = 2.0 ± 0.2 nl r-----------,

(20 to 80%) I Coa)(
I
I

\ TP out
50 ol"lm termonation to ground 10
cated In each scope channel ,nput

All Input and outj.Jut cables to the

scope are equal lengths of 50 ohm
caallial cable Wife length sho,Jld
be < 1/4 Inch from TP. n to Input
pm and TP out to output pm

Unused outputs connected to a

50-ohm resistor to ground.

C Input _ _ _ _ -JI ______ n - _ - ___ :~~::

~---------- +1.11 V
o Input
--_'+. ___________ +0.31 V D "----+031 V

~-----+'.'1 V
a Output

C - - - - -I ------------+031 V

~---'------ +1.11 V
A Input
_ _ _ _ _ _J ________________ +0.31 V

NOTE:
t setup is the minimum time before the positive tran-
sition of the clock pulse (e) that information mun be
pr.,ent at the data input (0).
thold is the minimum time .fter the positive tran·
litian of the clock pulse (e) that information must
remain uncnanged at the data input (D).

3-86
MC10132 (continued)

APPLICATION INFORMATION

A typical application of the MC10132 is temporary
,storage in a minicomputer. The arithmetic section of a
minicomputer might have a configuration similar to that
illustrated in Figure 1. Data may be entered into the "B"
register from either the register file or the input bus, re-
quiring a multiplexed input to the register.
Figure 2 shows the MC10132 as the elements in the
"B" register. Eight packages of the dual latch is necessary
to construct a 16-bit register. Note that reset is available
on the MC10132 if this capability is required.

FIGURE 1

Register File
16 x 16 Bit

Input Bus Output Bus

FIGURE 2

Data lines from Register File

(_-----------------------------A-----------------------------~

Data
Lin ..
from
Input
BUI
Receiver

I II
I~ ~~ ~II~ ~~ -II~ 2- ~H~ 2~ 2~J I~ 2~ 2~II~ 2~ ~II~ 2~
_I\J..~1I2 2~ ~I
N -N'"
Mgl0l~2
N _N.....
'1lCl0~2
N
Mffl0~2
-N'"
101 2
N
2
Me=101e
_,..,
2
... N
MS=101e
_N'"
Mi3 il
N"'t..)... N
MpCl0le
N _N
Mfole
...

I I I I I I I I I I I I I I I I
\----------------------------~y-----------------------------~)
Data Lines to Arithmetic Logic

3-87
 '\ MECL 10,000 series
QUAD LATCH
'--
_ _ _ _ _ _- - - - - 1

MC10133

The MC10133 is a high speed, low 'power,

MECL quad latch consisting of four bistable
latch circuits with D type inputs and gated a
TRUTH TABLE outputs. Open emitters allow a large number of
G c 0 On+1 outputs to be wire ORed together. Latch out-
H rt> rt> L puts are gated, allowing direct wiring to a bus.
L L rt> an Po = 310 mW typ/pkg (No Load) When the clock is high, outputs will follow 0
L H L L tpd = 4.0 ns typ inputs. Information is latched on negative going
L H H H transition of the clock. '
tj)- Oont Care
C "" Cc + CE

DO 3
2 00

GO 5
6 01
01 7

CE 4

Cc 13

CE 12

02 9
1102
(3110

15 03
0314

veel = Pin 1
VCC2 = Pin 16
VEE=Pin8

See General Information section for packaging.

3·88
 "I:i~'\rjM' ~::;, ~'~:. ~Q: f'5J'!;rf::1I'~ ,l.r.,,~··-,rl<-: ',p" ';f.".'

ElECTRICAr'cHARAC"rERISftCS . OO·.3~ 2 00
3:
EaCh MECL 10,000 seri •• has been de·
......
n

-
signed to meet the de specifications shown ~o. .~
in the test table. after thermal equilibrium 01 7 I "'I
6 al
o
has been established. The circuit is in a L SUFFIX
EE 4 Co)
test socket or mounted on a printed circuit CERAMIC PACKAGE
Co)
board and transverse air flow greater than Cc 13
CASE 620
500 linear fpm is maintained. Output :0 GIl::
8
::':~"O'
'r to TEST VOLTAGE VALUES :J
dor (Voltsl !:'.
~sted :J
Gl10 @Test c:
Temperature VIH max VIL min VIHA min VILA max VEE CO
15 Q3 _30°C -0.890 -1.890 -1.205 -1.500 -5.2 .e:
0314 0.3 +25 0 C -0.810 -1.850 -1.105 -1.475 -5.2
+85 0 C -0.700 -1.825 -1.035 -1.440 -5.2
MC10133L Test Limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELDW,
_30D C +2SoC +8SoC
Under tVccl
Characteristic Symbol Test Min Max Min TVp Max Min Max Unit VIH max VIL min VIHAmin VILA max VEE Gnd
Power SUpply Drain Current IF 8 - - - 60 75 - .. mAdc - 13 - - 8 1,16
Input Current linH 3 - - - - 245 - - JiAdc 3 - - - 8 1,16
4 - - - - 265 - - 4 - - -
5 - - - - 350 - - 5 - - -

+ +
13 - - - 350 - - 13 - - -
•
-

lin 3 - - 0.5 - - - - JiAdc - 3 - - 8 1,16

,
LogiC "1" VOH 2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 3.4 - - - 8 1,16
w

,
OutPut Voltage 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 3,13 - - - 8 1,16
eX!
(D LogIC "0" VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 13 3 - - 8 1.16
Output Voltage

Logic "1"
Threshold Voltage
VOHA
2
2
2
2
• • •
-1.080 -
-
-0.980
-

..
-
•
-
-
+
-0910
+
-

-
Vdc
3,5,13
4
3.4
4
-
3
-
-
-
-
-
3
-
-
5
-
•
8 1,16

2 - - - 3.4 - - -
2t -

j j 3 - - -
-
_.
2tt
2tt
2
2
j -
-
-
-
j -
-
-
-
-
-
-
-

-
-
-
3
3
-
-
-
.-
-
4
13
-
4
-
- 1 j
Logic "0" VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc 3.4 - 5 - 8 1,16
Threshold Voltage 2 - - - - 4 - - 3
2 - - - - 4 - - -
2t - - - - - - - -

Switching Times
2tt
2tt
-
- 1 -
-
-
- 1 -

- 1 1 3
3
-
-
-
-
-
13 1 1
150 l! Loadl +1.11 V Pulse In Pulse Out -J,2V +2.0V
Propagation Delay t3+2+ 2 1.0 5.6 1.0 - 5.4 1.1 5.9 ns 4 - 3 2 8 1,16
t4+2+ 2 1.0 ,,4 - 5.4 1.2 6.0 3 • - 4 2
+

I
t5_2+ 2 1.0 3.2 - 3.1 3.4 - 5 2

j j
-
1.0
tSetup 3 - - 2.5 - - - - 3 2
tHold 3 - - 1.5 - - - - - 3 2
Rise Time (20% to 80%) '2+ 2 1.0 3.6 1.1 - 3.5 1.1 3.8 • - 3 2
Fall Time (20% to 80%) '2- 2 1.0 3.6 1.1
. - ~~- ~~ ----
3.8
'--- -
• ' - -. - --
3 2
tOutput level to be measured after iii clock pulse has been applied to the clock input (Pm 41. ILV1Hma)( • Latch set to zero state before test.
VIL min
ttData input at proper high/low level while clock pulse is high so that device latches at proper
highltow level. for test. Levels are measured after device has latched.
 E lECTR ICAl CHARACTER 1ST ICS
2 00
s:

--
Each MECL 10,000 series has been de·
signed to meet the de specifications shown
P SUFFIX ....
(')

~~ I~
in the test table. after thermal equfiibrium
has been established. The circuit is in a
6 01
PLASTIC PACKAGE o
....w
test socket or mounted on a printed circuit CASE 648
CE 4
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are Cc 13
w

a,,~
(")
terminated through a 50-ohm resistor to o
TEST VOL TAGE VALUES
-2.0 volts. Test procedures are shown for
IVolts) ,...
::J

~,.~
only one gate. The other gates are tested
in the same manner. Gl10 "0' @Test
Temperature VIHmax VIL min VIHA min VILA max VEE
::J
c:
(1)
_JODe -0.890 -1.890 -1.205 -1.500 -5.2 Q.
1503
0314 03 +250 C -0.810 -1.850 -1.105 -1.475 -5.2
+8So C -0.700 -1.825 -1.035 -1.440 -5.2
MC10133P Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BElOW,
_JODe +25 O C +8SoC
Under (Vee l
Characteristic Symbol Test Min Ma. Min TVp Ma. Min Ma. Unit VIH maK VIL min VIHA min VILA max VEE Gnd
Power Supply Drain Current 'E 8 - - - 60 75 - - mAde - 13 - - 8 1,16
Input Current ImH 3 - - - - 245 - - ~Adc 3 - - 8 1,16
4 - - - - 265 - - 4 - - -
5 - - - - 350 - - 5 - ..
13
3
-
-
-
-
-
0.5
-

-
350
-
-
-
-
-
+
.u.Adc
13
-
-
3
- -
-
+
8
+
1,16
'inL
-

,,, ,,,,
Logic "1" 2 -1.0E0 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 3.4 8 1.16

,
VOH
to) Output Voltage 2 -1.0E0 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 3,13 - - 8 1,16

~ Logic ·"0"
Output Voltage
VOL 2
2
-1.890 -1.675 -1.850 -
-
-1.650 -1.825 -1.615 Vdc 13
3,5,13
3 ..
-
-
-
8 1.16

t
-

2 - 4 3 .. ..
Logic "1" VOHA 2 -1.080 - -0.980 - - -0.910 - Vdc 3,4 - 5 8 1,16
Threshold Voltage 2 - - - - 4 - 3 ..
2 - - - - 3,4 .. -

j j j j j
21 - - 3 - -

211
211
2
2
j -
-
-
-
-

-
-
-
-
-
-
-
-
3
3
-
-
..
-
4
-

13
-
4
-
-
Logic "0" VOLA 2 -1.655 - - -1.630 .. -1.595 Vdc 3.4 - 5 - 8 1,16
Threshold Voltage 2 - - - 4 - 3
2 - - - 4 - - -

Switching Times
21
211
211
-
-
- l -
-
-
-
1
-
1 1
-
3
3
-
-
-
-
-
-
-
-
13 1 l
(50 H Loadl +1.11 V Pulse In Pulse Out -3.2V +2.0V
Propagation Delay 13+2+ 2 - - 1.0 - 5.4 - - ns 4 -
..
3 2 8 1,16
'4+2+ 2 - 5.4 - - 3 • 4 2
2 - -
+ - - - - - 5 2

j j
'5-2+ 3.1
3 - 2.5 - - - -

j - - 3 2
-
'Setup
'Hold 3 - - 1.5 - - - - - - 3 2
Rise Time 420% to 80%) '2+ 2 - - 1.1 - 3.5 - - 4 - 3 2
Fall Time 120% to 80%) '2_ 2 - - 1.1 - 3.5 - - 4
":- 3 2
tOutput level to be measured after a clock pulse has been applied to the clock input"(Pin 41. .Jl:VIHmax • Latch set to zero state before test.
YlL min.
ttO ata input at proper· high/low I41verwhile ctOek pulse is high so that devicalatches.jll Pfoper
high/low level for test. Level, ara measured aftar device has latched. -
 MC10133(continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 250 C

VCCl : VCC2
Vin +2.0 Vdc V out

~"'t tt"" ~.
r----- -- --...,
PROPAGATION DELAY

I
+1.11 V
50%

Input Pulse
t+ c t- = 2.0 ± 0.2 ns
(20 to 80%)
Vout from 0 input

50-ohm termination to ground 10- I

,ceted in each scope channal input._.;-1------"'1 Vout from G input
L ____ -t-=-,----...J I

Unused outputs connected to

a 50-ohm resistor to ground.
1 ~ 0.1 ~F
C
VEE: -3.2 Vdc

o
All input and output cables to the
scope are equal lengths of 50-ohm

1
coaxial cabl.. Wire length should
be < 1/4 Inch from TPin to input a
pin and TP out to output pin. _--.-J

tSetup is minimum time before the negative transition of the clock

pulse (e) that information must be present at the data input (D),
tHold is the minimum time after the negative transition of the clock
pulse ee) that information must remain unchanged at the data input (0).

APPLICATION INFORMATION
The MC10133 device consists of four bistable latch
circuits with 0 type inputs and gated Q outputs. When
the clock is high the outputs will follow the 0 inputs.
The latch will store the data on the falling edge of the
clock. The outputs are gated when the output enable is
low. All four latches may be clocked at one time with the
common clock, or each half may be clocked separately
with its clock. This device is useful as a temporary storage
element in high speed central processors, accumulators,
register files, digital communication systems, instrumenta·
tion and test equipment.

3-91
 MECL 10,000 series
DUAL MULTIPLEXER
WITH LATCH

MC10134

The MC1D134 is a dual multiplexer with clocked D
type latches. Each latch may be clocked separately by
holding the common clock in the low state, and using the
clock enable inputs for the clocking function. If the com',
mon clock is to be used to clock the latch, the clock enable
(CE) inputs must be in the low state. In this mode, the
enable inputs perform the function of controlling the com,
mon clock (CC).
The data select inputs determine which data input is
enabled. A high (H) level on the AD input enables data input
D12 and a low (L) level on the AD input enables data input
D11. A high (H) level on the A1 input enables data input,
D22 and a low (L) level on the A 1 input enables data,
input D21.
Any change on the data input will be reflected at the
outputs while the clock is low. The outputs are latched.
on the positive transition of the clock. While the clock is
in the high state, a change in the information present at'
the data inputs will not affect the output information.
, Output rise and fall times have been optimized to pro,.
vide relaxation of system layout and design criteria.

POSITIVE LOGIC NEGATIVE LOGIC

AO 6 AO 6

Al 11 AlII

011 4 ----+++I~I....., 011 4

2 01

012 5 ----++--w:......./ 012 5

GE010 CE010
3 01
Cc 7 Gc 7

15 02
GEl 9 CEI 9
021 13 -----~~~--, 02113

14 02
02212 02212

TRUTH TABLE

C AO 011 012
veel = Pin 1
On+l VCC2 = Pin 16
L L L 4> L Vee = Pin 8
L L H 4> H
L H 4> L L
L H 4> H H
H 4> an Po = 225 mW tvp/pkg (No Load)
4> 4>
tpd'" 3.0 ns typo
cP - Don t Care
C = CE + Cc

See General Information section for packaging.

3-92
 ,
~""""""~~_.:.r.~:~.'~:::'~~.10 ......:;;:;'. ~'.< .
ELecTRICAL CHARACTERISTICS
E";h MEet 10,000 ~r,sclri:ui'thas been
designed to· \ meet·· the dc specifications
shown in the test table, after thermal equi-
librium has been established. The circuit is
.00.

AI 11
..o..
3:
o
in a test socket or mounted on a printed
circuit board and transverse air flow greater
0114 IIII~ ~
2 Q,

g
~
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor to

~~'~,~ .11 ~ ....

::J
-2.0 volts. Test procedures are shown for
only one latch. The other latches are tested
in the same manner,
3 a,
nv;~:l~; if I: I L SUFFIX
5'
c(1)
CERAMIC PACKAGe
.e:
CE1
D2113
9 II ==::::: 15 a~ CASE 620

D2212~r---14C2

TEST VOL TAGE VALUES

(Voltsl
@Test
Temperature VIH max VIL min VIHA min VILA milk VEE
-lOoe -0.890 -1.890 -1.205 -1.500 5.2
+25 o C -0.810 -1.850 -1.105 -1.475 -5.2
+8So C -0.700 -1.625 -1.035 -1.440 -5.2

Pin
w Under
TEST VOL TAGE APPLIED TO PINS LISTED BELOW
W Characteristic SYmbol T..t ..... 1Veel
w Power Supply Drain Current
Min M •• Min Unit VIH max VIL min I VIHA min I VILA max I VEE Gnd
Ie 55 mAdc 1.16
Input Current lin H

"f
290 4
290 5

logic "1"
lin L
7
10
4' 0.50
265
290
265
~Adc
6
7.
10 11 T 1.16 '
VOH 2 -1.060 -0.890 -0.960 -0814[)
Output Voltage -0.890 -0.700 Vdc 4 6,7.10. 1,16
2 -1.060 -0.890 -0.9S0 -0.81~ -0890 -0.700 Vdc 5.6 7.10 1,16
Logic "a" VOL -1.890 -1.675 -1.850 -1.651t) -1.825 -1615 Vdc 4.6.7,10. 1,16
Output Voltage -1.890 -1.675 -1.850 -1.65eo -1.825 -1.615 Vdc 5,7.10 1,16
logic "1" VOHA -1.080 -0.980
Threshold VOltage -0.910 Vdc 6.7,10 8 1,16
-1.080 -0.980 -0.910 Vdc 7,10 8 1,16
Logic "0" -1.655
VOLA -1.6Jt:) -1.595 Vdc 6,7,10 1,16
Threshold Voltage -1.655 -163(;) -1.595 Vdc ~.10 1,16
SWItchmg Times 150-ohm load)
~
~
M.. .0.31 V PuI_ln. Pul.Out -l.2V +2.0V
Propagation Delay Data 2 1.0
t.4+2+ 3.3 n• ., 6.7.10 4 2 8 1,16
Clock tl0-2+ 1.0 5.7
Setup Time
Select
Data
'6+2+
tsetup • 1.0
2.5
4.6 t 7
·"'7.10
6.7
10
6
4,10
t t m
t
Salect t setup 3.5 7,11 6.10 1.16
Hold Time Data lt10ld 1.5 6.7 4.10 ill
Seloct thold 1.0 7.11 6.10 1.16
Rise Time (20% to 80%)
Fall Time (20% to 80%)
'2+ 1.5 3.5 6.7.TIi m
'2_ 1.5 3.5 6,7.10 1.16
• All other inputs tested in the same manner.
 ELECTRICAL CHARACTERISTICS
Each MEeL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equi-
librium has been established. The circuit is
AO 6
....s:
o
o
~
A,111
in a test socket or mounted on a printed
circuit board and transverse air flow greater 1111.,-...
than 500 linear fpm is maintained. Outputs
Dl1 4
n-
O
are terminated through a 50-ohm resistor to ::J

-
-2.0 volts. Test procedures Ire shown for ::t,
only one latch. The other latches are tested
in the same manner.
;:;,:
Cc 7 •
II ~ J 0'
P SUFFIX
::J
C
It>
Cl.
PLASTIC PACKAGE
1502

~~:1: II ~
CASE 648

02212~~14Q2 TEST VOLTAGE VALUES

(Volts)
til Test
Temperature VIH mu. I Vil min I VIHA min VILA nux VEE
-lOGe -0.890 -1.890 -1.205 -1.500 -5.2
+25 o c -0.810 -1.850 -1.105 -1.475 -5.2
+850 C -0.700 I -1.625 I -1.035 -1.440 -5.2

Pin
MC10134P Test Limits TEST VOL TAGE APPLIED TO PINS LISTED BELOW
c.l

~ CharKteristic
Power Supply Drain Current
Symbol
'E
Under
T...
-30"<:
Min I .... I Min
+2S0C
I ....
55
Min
+8S0C
M..
mAdc
Unit VIH m.. I VIL min I VIHA min I VILA max I VEe
(Vee l
Gnd
1.16

"f
Input Current i";;"H 290
290

~
7
10
4' 0.50
265
290
265
/JAdc
10 11 T 1,16
LogiC ''1'' VOH -1060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 4 6.7,10. 1.16
Output Voltage -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 5,6 7.10 1,16
LogiC "0" VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 4.6.7.10, 1,16
Output Voltage -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 5,7,10 1,16
Logic "I" VOHA -1.080 -0.980 -0.910 Vdc 6,7,10 1,16
Thresl"lold Voltage -1.080 -0980 -0.910 Vdc 7,10 1,16
LogiC "0" VOLA -1.655 -1.630 -1.595 Vdc 6,7,10 1,16
Threshold Voltage -1.655 -1.630 -1.595 Vdc 7,10 1,16
Switcl"llng Times 150-ohm loadl Min M.. +1.11 V +0,31 V Pulse In I Pulse Out I -3.2 V I +2.0 V

Propagation Delay Data l4+2+ 2 1.0 3.3 6,7,10 2 8 1,16

Setup Time
Clock
Select
Data
tlO_2+
ts+2+
tsetup
t 1.0
1.0
2.5
5.7
4.6 l 7,10
6.7
10
6
4,10
t
2
t
8
t
1,16
Select tsetup 3.5 7,11 6,10 2 8 1,16
Hold Time Data "'old 1:5 6,7 4,10 2 8 1,16
Select ltlold 1.0 7,11 6,10 2 8 1,16
'2.
~
Rise Time (20% to 80%1 6,7,10 4 2 8 1,16
Fall Time '(20% to 80%) '2- 1.5 3.5 6,7,10 1,16

• All other inputs tested in the serne manner.

MC10134 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

V out
Input Pulse
t+ = t- = 2 a ns ±
(20 to 80%)
a 2 n5
Coax n
Dalal~
TPin/

50-ohm termination to ground 10'

cated in each scope channel input

All input and output cables to the

scope are equal lengths of S.O-ohm
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.

Unused outputs are terminated

50-ohm resistor to ground.
I I
~-----10~:-_1
VEE LY2 Vdc

C Input _ _ _ _ _ J/n ______ _____ :~:::: ~ _ _......,,_ _ _ _ _ +1. II V

~----------- +1. II V
o Input
___,,-+____________ +0.31 V
o '-----+0.31 V
+---~-~thold
~ _ _ _ _ _ +1.11 V

a Output
C - - - - - - ' - - - - - - - - +0.31 V

NOTE'
tsetup is the minimum time before the positive tran-
a~
sition of the clock pulse (C) that information must be
pre.ent 8t the data input (0),
thold is the minimum time after the positive tran-
sition of the clock pulse (e) that information mult
remain unchanged at the date input (0),

3-95
MC10134 (continued)

APPLICATION INFORMATION

A typical application of the MC10134 is temporary quiring a multiplexed input to the register.
storage in a minicomputer. The arithmetic section of a Figure 2 shows the MC10134 as the elements in the
minicomputer might have a configuration similar to that "B" register. Eight dual latch packages are necessary to
illustrated in Figure 1. Data may be entered into the "B" construct a 16·bit register.
register from either the register file or the input bus, reo

FIGURE 1

Aegister File
16 Ii( 16 Bit

Input Bus Output Bus

FIGURE 2

Data Linas from Register Fil.

( r - - - - - - - - - - - -_________________ A~_____________________________,

Oeta
Lina,
from
Input
Bu.
Receiver

I I 1
[2 2~ ':[[2 2~ ~II~ 2~ ~1I2 2~ ~H2 2~ ~H2 2~ ~J 12 2~ ~112 2~ ~I
1'1.)

MB10le 4
_p,J ... "'

M§101§4
... IIJ .... N
M8101~4
.... N ... '"
MfOl~4
..oN'" II.)

MfOl§4
_I\J'" IIJ ... IIJ
M8101~4
... N
M8101~4
.... I\J ... N _I\J
Me 101e 4
...

I I I I I I I I I I I I I I I I
\------------------------------~y~----------------------------~)
Data Lines to Arithmetic Logic

3-96
 DUAL J-K MASTER-SLAVE MECL 10,000 series
FLIP-FLOP

MC10135

The Me 10135 is a dual master-slave dc coup-

POSITIVE LOGtc NEGATIVE LOGIC led J-K flip-flop" Asynchronous set (S) and reset
(R) are provided. The set and reset inputs over-
5' • ~, 5---~ ride the clock.
A common clock is provided with separate

.
"
,•
, J1 ,
J-K inputs. When the clock is static. the J-i<
inputs do not effect the output .
The output states of the flip-flop change on
the positive transition of the clock .
"' ••
C
• , 4_1-_--1
l! •
Input pulldown "resistors eliminate the need
5212 1212-1--~ to tie unused inputs to VEE. Output rise and
fall times have been optimized to provide relaxa-
J210 J210 15 tion of system design and layout criteria.
il211 '4
"213 "213;----
vee1 '" Pin 1
VCC2 = Pin 16
R-8 TRUTH TABLE CLOCK J.K TRUTH TABLE·
Vee == Pin 8
Q n+1 a n +1
Qn an
L
H Po ~ 280 mW typ/pk. (No Load)
fTog -= 140 MHz tvp

N.D. - Not O.fined ·Output l1.t.. ch,ne- on pOlio

,ive ,.,n,I,lon of clock fa.]·
i( input condition p ....nt.

CIRCUIT SCHEMATIC
1/20F CIRCUIT SHOWN Vee 2
MASTER LAVE
Vee'

h
Y
124 124 ) '68 '6. I ~~
I ,J" ~~~
rYl~ 51""'" ~ ~t'->=
,0>-
\- 30' 30'

rr ~
" y

)
)-
1.34311 1.3"3k

'0'( 1.914 k 1.91" k

t·,
Kt-<
~
R ,
..
13

'"17

>----
'"
~
43
I--
,.,
~
1.11Sk 647 1.0910;

!iii -': " L -_ _ _ _ _ _ _ _-'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.-J

8M G . . . .I Information section for packaging.

3-97
 51 5

ELECTRICAL CHARACTERISTICS
j 1 7 -------"'
.--l Ql~2
Each MECL 10,000 series circuit has been 3:

- ...
---'"
designed to meet thedc specifications shown
Ql~J
n
...
in the test table. after thermal equilibrium K 1 6 - ---'"
has been established in an ambient temper- L SUFFIX
0
ature of 2SoC, while the circuit is in a test Al 4 ~ ! I .
CERAMIC PACKAGE
CASE 620 Co)
socku or mounted on a printed circuit c ._
board and transverse air flow greater than U1
500 linear fpm is maintained. Outputs are
5212
r n0
terminated through a 50-ohm resistor to TEST VOLTAGE VALUES ::J
-2.0 volts. Test procedures are shown for ' ] 2 1 0 - -"'" Q2111o.......-'5 .-+
Vdc.t.'"
only one input, or for one set of input con- w.. @T... 5'
ditions. Other inputs tested in the same Temperature VIH max VILmin VIKAmin VILA INK VEE c:
j(:2 1 1 -------AI 62~14 CD
manner. _JODe -0.890 -1.890 -1.205 -1.500 -5.2 a.
A2 13 J +25 oC
+SSoC
-0.810
-0.700
1.850
1.825
-1.105
-1.035
-1.475
-1.440
-5.2
-5.2
MC10135L Test Limits
Pin VOLTAGE APPLIED TO PINS LISTED BELOW,
Under -lOoe +2S oC +8S oC 1Vc:cl
ChllrKt_istic Symbol Test Min Max Min TV. Ma. Min Ma. Unit VIH IMX VILmin VIHAmin VILA mIIX VEE GNI
Power Supply Drain Current IE 54 68 mAde 8 1.16
Input Current lin H 6.7.9.10.11 265 ~Ade <D 1.16
4,5,12,13 390 ~Adc <D 8 1.16

~
Input Leakage Current lin L 4,5,6,7,9, 0.5 ~Adc 8 1.16
10,11,12,13 0.5 ~Ade 8 1.16
Logic "'" VOH 2 -1.050 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 5 8 1.16
Output Voltage 2@ -1.050 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 6 8 1.16
Logic "0" VOL 3 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 5 8 1.16
W I Output Voltage 3@ -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 6 8 1.16
cO
CO
I Logic "1"
Threshold Voltage
VOHA 2
2@
-1.080
-1.080
-0.980
-0.980
-0.910
-0.910
Vdc
Vdc
1.16
1.16
Logic "0" VOLA 3 -1.655 -1.630 -1.595 Vdc 1.16
Threshold Voltage 3@ -1.655 -1.630 -1.595 Vdc 6 1.16

,
Switching Times Pulse In Pulse Out -3.2 Vdc +2.0 Vdc
Clock Input
Propagation Delay t9+2+
, ,
1.0 5.0 1.0 3.0
3.0
4.5 1.0
t
4.6 9
9
8 1,16

l l l
19+2-

l •
1.0
Rise Time (20 to 80%) 2.0 9 2.3

• •
t2+,t3+ 2.3 1.1 4.8 1.1 1.1 4.7
Fall Tune (20 to 80%1
Set Input
t2_.t3_ 2.3 1.1 2.0 + 9 2.3

Propagation Delay t5+2+ 1.2 5.6 1.0 3.0 5.0 1.0 5.2 5 2 8 1.16

~ ~ ~ ~
15 12 15

l
t12+15+
t5+3- 3 5 3
+
• • •
12 14

•
112+14- 14
Reset Input
Propagation Delay I t4+2-
14+3+
1.0 3.0 5.0 4
4
2
3
1,16

113+15- 15 13 15
+ + +
•
14

•
t13+14+ 14 13
Setup Time
Hold Time
Toggle Frequency
T tsetup
I
I
'hold
fTog
2.5
1.5
125 140 MHz
6.9
6.9 ®
9
® 2
• 1,16
1.16
1.16

NOTES,
<D Individually test each input; apply VIH max to pin under test.
~ Individually test each input; apply VIL min to pin under test. ..Il: VIH max
(J) Output level to ~ measured after a clock pulse has been applied to the C input (pin 9) VIL min
@ Output '...,.1 to be measured after a clock pulse has been applied to the C input (pin 91 J"1.: VIHA min
(5) See Figure 2 for timing lt11t diagram. VI LA mIIlC
 j, 7
3:
ELECTRICAL CHARACTERISTICS
...
0

-- ...
Each MECL 10.000 series circuit has been i(1 6
designed to meet thedc specifications shown 0
in the test table. after thermal equilibrium PSUFFIX
has been established in an ambient temper-
Al •
PLASTIC PACKAGE
W
ature of 2SoC, while the circuit is in a test
C 9 U1
CASE 648
socket or mounted on a printed circuit
5212
n0
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are J210- ...... Q21"--15
TEST VOLTAGE VALUES
....
::J

terminated through a 50-ohm resistor to ...... @T..,

Vdc± ,,,
::J
-2.0 volts. Test procedures are shown for
only one input. or for one se~ of input con-
.2 ,,------ Q2~"
Temperature
-30o e
VIHma.
-{).890
VILmin
-1.890
VIHAmili
-1.205
VILA.-.
-1.500
VEE
-5.2
C
~
ditions. Other inputs tested in the same
manner. R213 "---r +2soe
+8soe
-{).81 0
-0.700
-1.850
-1.825
-1.105
-1.035
-1.475
-1.440
-5.2
-5.2
MC10135P Test limits
Pin VOLTAGE APPLIED TO PINS LISTED BELOW,
Under _30°C +2SoC +8SoC
CVCCI
ChIIrKt..istic Symbol T.., Min M.. Min Ty. Max Min Max Unit VIHma. VILmin VIHAmin VILA.-. VEE Gnd
Power Supply Orain Current 'E 54 68 mAdc 8 1,16
Input Current lin H 6,7,9,10," 265 j.lAdc CD 1,16
4,5,12,13 390 j.lAdc CD 8 1,16
Input Leakage Curr."t 4,5,6,7,9, 0.5 j.lAdc 8 1,16
lin L
10,11,12,13 0.5 j.lAdc $ 8 1,16
Log;c "1" VOH 2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 8 1,16
Output Voltage 2@ -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 8 1,16
Logic "0" -1.675 -1.850 -1.650 1,16
W I Output Voltage
VOL
3@
3 -1.890
-1.890 -1.675 -1.850 -1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Vdc
8
8 1,16
cO
CO I Logic "1"
Threshold Voltage
VOHA 2
2@
-1.080
-1.080
-0.980
-0.980
-0.910
-0.910
Vdc
Vdc
5 8
8
1,16
1,16
logic "0" VOLA 3 -1.655 -1.630 -1.595 Vdc 5 8 1,16
Threshold Voltage 3@ -1.655 -1.630 -1.595 Vdc 6 8 1.16
Switching Times ...... In ...... ou, -3.2 Vdc +2.0 Vdc
Clock Input
Pr0P9tion 0eI-V t9+2+ 1.0 3.0 4.5 9 8 1,16
3.0 9

~ ~ ! !
t9+2- 1.0
Ri. Time (20 to 80%) t2+·t3+ 2.3 1.1 2.0 9 2,3
Fall Time (20 to 80%) t2_·t3_ 2.3 1.1 2.0 9 2,3
Set Input
Prop8gltion Oetay t5+2+ 2 1.0 3.0 5.0 5 2 8 1,16

~
t12+15+ 15 12 15
15+3- 3 5 3

+
• •
14

• •
t12+14_ 14 12
R_tlnput
Propagltion Oelay I '4+2- 1.0 3.0 5.0 4 2 8 1.16

~ ~
4 3

~
14+3+
t13+15- 15 13 15
+
•
t13+14+ 14 13 14
Se,upTime
Hold Time
Toggle Frequency
I
"'IUD
thold
ITog
2.5
1.5
125 140 MHz
6.9 (lj)
6.9 (lj)
9 9
• 1.16
1,16
1.16
NOTES,
<D Individually test each input; apply VIH max to pin under test.
@ Individually teste.::h input; apply VIL min to pin under test. ...fl: VIH max
@ Ou1PUt 'wel to be measured after a clock pulse has been applied to the C input ~pin 9) VI L min
@) Output level to be measured after a clock pulse has been applied to the C input ~pin 9) Jl: VIHA min
(5) See Figure 2 for timing test diagram. VI LA max
MC10135 (continued)

FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT

VCC, " VCC2"

+2.0 Vdc Vout

Coax

~~,"J'o"
Clock Input (O+----<>--------<>-...=...j
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin.
Input Pulse
t+ = t- = 1.0 ns Unused outputs connected to a
Duty Cycle'" 50% 50-ohm resistor to ground.

50-ohm termination to ground to

:::r:: 0.' I'F
cated in each scope channel input.

VEE" -3.2 Vdc

FIGURE 2 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 2So C

veel = VCC2 '"

J
+2.0 Vdc Vout

::rO., I'F coa.

iT'P out
All input and output cables to the
scope are aqua,! lengths of 50-ohm
Clock Input coaxial cable. Wire length should
be < 1/4' inch from TPin to input
Input Pulse pin and TP out to output pin.
t+ " t- " 2.0 ns ± 0.2 ns Unused outputs connected to a
(20 to 80%1 SO-ohm resistor to ground.
50-ohm termination to ground 10· XO.'I'F
cated in each scope channel input.

VEE = -3:2 Vdc

+1.11 V
C 50%
+0.31 V
R Input
thold
+0.31 V
+1.11 V K
S 'nput - - - - ' I
Q
/
Q Output - - - - , , . . . , NOTE,
ts8'tup is the minimum time before the positive
a Output - - - -...... 1
transition of the clock pulse (C) that .information must
be present at the inputs} or K.
thold is the minimum time after the positive tran-
sition of the clock pulse (C) that information must
remain unchanged at the inputs J or K.

3-100
 MECL 10,000 series
UNIVERSAL HEXADECIMAL
COUNTER

MC10136

--
The MC10136 is a high speed synchronous counter
that can count up, count down, preset, or stop count at
frequencies exceeding 100 MHz. This binary counter
is useful in high speed central processors and peripheral
controllers, minicomputen, high speed digital commu-
nications equipment and instrumentation. The flexi-
SEQUENTIAL TRUTH TABLE' bility of this device allows the designer to use one
INPUTS OUTPUTS basic counter for most applications, and the synchron-
ous count feature makes the MC10136 suitable for
Carry Clock Carry either computers or instrumentatio_n._ _
SI S2 DO 01 02 03 iii" ao Ql 02 03 Out ThreecontroilinoslSl,S2, and Carry In) determine
L L L L H H <I> H L L H H L the operation mode of the counter. lines 51 and 52
L H <I> <I> <I> <I> L H H L H H H determine one of four operations; pr:eset (program).
L H <I> <I> <I> <I> L H L H H H H
rp increment (count up), decrement (count down), or
L H <I> <I> <I> L H H H H H L
hold 1stPI' count). Note that in the prosat mode a
L H <I> <I> <I> <I> H L H H H H H clock pulse is necessary to load the counter. and the
L H <I> <I> rp <I> H H H H H H H information present on the data inputs (DO, 01, 02.
H H <I> <I> rp rp <I> H H H H H H and D3) will be entered into the counter. Carry Out
L L H H L L <I> H H H L L L
goes low on the terminal count. or when the counter
H L rp rp <I> rp L H L H L L H is being preset.
H L <I> rp rp <I> L H H L L L H This device i. not designed for u ... with gated
H L <I> <I> rp <I> L H L L L L L clocks. Control i, via 51 and 52.
H L <I> <I> <I> <I> L H H H H H H
A proseal,r can b, constructed using the MC10136
in conjunction with the MC10231 which will operate
tP ... Don't cara . at over 200 MHz inputfroquency. A 500 MHz proseal,r
• Truth table shows logic states assuming inputs vary in sequence
shown from top to bottom. is possible using an MC1690 500 MHz 0 Flip-Flop, an
•• A cloek H is defined as a clock input transition from a low to a MC1670300MHz D Flip-Flop,and the MC10136 .
high logic level.

1 0 - Cin 00 r- 14
13- C FUNCTION SELECT TABLE
1 2 - DO
01 f----- 15 SI S2 Operating Mode
1 1 - 01 L L Preset (Program)

6- 02
02 r- 2 L H Incramant (Count Up)
H L Decrement (Count Down)
5 - 03 03 r- 3 H H Hold (Stop Count)
9 - SI
7 - S2 C out r- 4

Po; 625 mW typ/pkg (No Load)

vee1 :z Pin 1 f eount = 150 MHz typ
VCC2= Pin 16
Vee = Pin 8

1 ..
i;-
!~
i<L-______________________________________________________________________________ ~

j'.' :

. . . Gen.ral I nformation section for packaging.

 ELECTRICAL CHARACTERISTICS
10 Cin 00 14
..s:..
(")

-
Each MECL 10,000 series circuit has been 0
designed to meet the de specifications 13 C LSUFFIX
shown in the test table, after thermal equi- 12 00
01 15 CERAMIC PACKAGE W
CASE 620 0)
librium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
11
6 - 02
01
02 2 n0
TEST VOLTAGE VALUES :l
than 500 linear fpm is maintained. Test 5 - 03 03 - 3 IVolb) ....
procedures are shown for only one output.
9 - 51 .or.. 5'
The other outputs are tested in the same Temper.'ure VIHmu VILmin VIHAmin VILA.".. VEE e:
rTanner. 7 - 52 C;;; - 4 _30°C
+25 o C
-0.890
-0.810
-11190
-1.850
-1.205
-1.105
-1.500
-1.475
-S 2
-5.2
a
+8SoC -().700 -1.825 -1.035 -1.440 -5.2
MCl013&L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW

a...,..,iltic I Simbal I u;: ..n

_30°C
Ma. "n
+2Soc
TyO .... ..n
<OS"!:
.... Unit VIHmax VILmin VtHAmin VILA.".. VEE
tVee l
Gnd
Power Supply Drain Current
"
120 ISO mAde
• 1,16
Input Current
I 1m H I 5.6.11.12 220 ~Adc 5.6.11.12
• 1.16

I
7

l
26S

I
7
9,10 24S 9.10
13 290 13
1m L All 0.5 /J.Adc <D 1,16
VOH 14(2) -1.060 -0_890 -0.960 -0.810 -0890 -0_700 Vd, 12 7,_ 1.16
Logic "'"
Output Voltage

'fJ
.....
I~~~~'~:'vohage VOL 14 J2) -1.890 -1675 -1.850 -1.650 -1.825 -1_615 Vd, 7,_ 1,16

0
I\,)
Ilogic "'"
Threshold Voltage
VOHA 14 J2) -1.080 -0.980 -0.910 Vdc 7,_ 12 1.16

Logic "0" VOLA 14~ -1.655 -1.630 -1.595 Vd, 7,_ 12 1,16
Threshold Voltage
Switching Times -+1.11 V +0.31 V Pulse In Pulse Out -3.2 V -+2.0 V
ISO-ohm Load I
Propagation Delav
Clock Input I t13-+'4-+ 14 0 .• 4.8 1.0 3.3 '.S 1.4 S.O 12 13 14 1,16
tI3-+14-
tI3-+4-+
t'3+4-
14 0 .•
2.0
2.0
4.8
10.9
10.9
1.0
2.S
2.S
3.3
7.0
7.0
'.S
10.5
10.5
1.4
2.'
1._
2.'
S.O
11.5
11.5 I I •14

Carry In To Carrv Out tl0--4_ 4<:!l 1.6 7.4 1.6 S.O 6._ 7.S 13 10

Set Up Time
110-+4-+
• 1.6 7,' 1.6 S.O 6._ 1._ 7.0 13 10

7, _
Data Inputs t12-+13-+ I. 3.0 12,13 14
tI2-13-t 14 3.S 7,_ 12,13
Select Inputs 19+13-+ 7.0 9.13
[7+13-+ "
14 7.S 7.13
CarrV In Input tl0_13-+ 3.7 10,13 14
113+10+ "
I. -1.0 10.13 I.
Hold THne
Data Inputs tI3+12-t
,. -1.0
-1.0
7,_
7, _ 12,13
12,13
I.
tI3+12_
Select Inputs 113-+9-+
"
14 -2.5 9.13
tI3+7-+ -2.5 7.13
CarrV In Input 113-tl0_
"
14 -1.6 10,13
tl0-t13-+ 3.1 10.13
Counting Frequency 'countup
" 12S 12S ISO 12S MH, 13
'COuntdown "I. 12S 120 150 12S MH,
Rise Time '4' 0._ 3.3 1.1 2.0 3.3 1.1 3.5

~ ~
l2V" to ID"I

!
t14-t I• 2.0 '4
..... ,.
Fell Timll
f2MC.to . , , ' t14-
4
I.
2.0
2.0 1 4

CD IndiY....Uy 8JIPIy VIL min to pin undtt tnt. (b Meaure output attar clock pulse VIL fVIH appean at clock input (pin 13) (3) Before tnt ..t all a outpuu to a logic hi...
MC10136 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25"c

Vee, '" VCC2" +2.0 Vdc Vout

NOTE;
t . .tup is the minimum time before the pOliti.....
transition oi tn. eloe"" pulse \C) tne' in1ormation mu\t
be pr••• nt at the input 0 or S.
thold il the minimum time atter tn. positive tran-
sition of the clock pul,. (e) that Information
remain unchanged at the Input 0 or S.
Input Pulse
t+ .. t-; 2.0±. 0.2 ns Cloek Input @----+---o
(20 to 80%)
\ \ TP out
ClOck

a Output

VEE = -3.2 Vdc

r-----__- - +1,11 V
c
+0.31 V

50-ohm t .... min.tion to 'IIround 10-

ceted in •• ch teOp. chenrMIl input.
OarS All Input and output CIIbl •• to the
IeOp' .re equal lengths of 60-ohm
coulela' ctlble. Wire length should
be < 1/4 inch from TPln to input
pin end TP out to output pin.
Unu.-d outputl ere connected to
• 50-ohm rMiltor to ground.

SET UP AND HOLD TIMES

'a' il the minimum tim. to w.it .ft.r the

count.r n., beIIn .n.bled to clock it.
Ib) I, the minimum tim. b.-for. tl'1,
count.r h •• b"" diMble<l th.t it ~v
b. clock.d. Clock
Ie) i, tM minimum tim. bllfor. tne
counter I, en,bled th.t • clock pul.
mev be .ppJied with no eff.ct on tn,
stet. of the counhlr.
Id) I, the minimum time to weit . f t .
the counhlr i, dlMbled thllt • clock
p~IM mev be .ppl~d with no .ff.ct in
the stete of the count.....
(b) .nd Ie) m.v be n.g.t' .... numbflrl.

3-103
MC10136 (continued)

COUNT FREQUENCY TEST CIRCUIT

vee1'" VCC2" +2.0 Vdc Vout

COax

ClOck Input @--....----<>---I

Input Pul ••
t+ .. t- .. 1.0ns

Duty Cycl. " 50% ~

All input and output cabl •• to the
scope are equal 'ength, of 50-ohm
O.lJ.&FJ; coaxial cabl •. Wire length should
be < 1/4 inch from TP,n to input
50-ohm t ... ml~tlon to ground 10-
pin and TP out to output pin.
CIIt.::t in .ach tcOp. channa' Input.
UnuMd outputs .r. connected to
III 50-ohm r81iltor to ground.
+1.11 V VEE'" -3.2 Vdc

UNIVERSAL BINARY UP/DOWN COUNTER

51 9

100-1-+----,

1200 14QO 1101 15Q1 602 202 503 303

3-104
 MC10136 (continued)

APPLICATIONS INFORMATION
To provide more than four bits of counting capability several
MCl0136 count.... may be cascadad. Th. C.rry In input ov.rrides
the clock when the counter is either in the increment mode or the
decrement mode of operation. This input allows several devices to
!be CIIICeded in a fully synchronous multistage counter as illustrated
'in Figura 1. Th. carry is advancad b.tween stages as shown with
:noexternal gating. The Carry In of thafirst device may be left open.
;The aystem clock is armmon to all devices.
The various operational modes of the counter make it useful
for • wide variety of applications. If used with MECL III devices,
prelCalers with input toggle frequencies in excess of 300 MHz are
;possibl•. Figure 2 shows such a prasealer using the MC10136 and
MC1670. Usa of the MC10231 in place of the MC1670 permits
200 MHz op.ration.
Th. MC10136 mav also be used as a programmable counter.
The configuration of Figure 3 requires no additional gates, although
maximum frequency is limited to about 50 MHz. The divider
modulus is equal to the program input plus one 1M = N + 11. there
fore, the counter will divide by a modulus varying from 1 to 16.
A second programmable configuration is also illustrated in
Figure 4. A pulse swallowing technique is used to speed the counter
operation up to 110 MHz typically. The divider modulus for this
figuro is equal to the program input 1M = N). The minimum
modylus is 2 because of the pulse swallowing technique, and the
modulus may vary from 2 to 15. This programmable configuration
requires an additional gato. such asllMC10l09 and a flip-flop such
as IIMC10131.

FIGURE 1 - 12 BIT SYNCHRONOUS COUNTER

LSB MSB

~r;::m----~~---------- ______________ ________________________--1

~

Note: S1 and S2 are set either for increment or decrement operation.

FIGURE 2 - 300 MHz PRESCALER

Logic High

MC10136
SI
S2
ar--r-------i~C ________ ~--~
I "put F requencv
32
a
MC1670

3-105
MC10136(continued)

FIGURE 3 - 50 MHz PROGRAMMABLE COUNTER

Program Input

I I I I
DO 01 02 03
fin C

t= Cln
52
Cout f out

i 51

fin
1 f out ""
Program I "put +1
2 f max ~ 50 MHz Typ.

3 Divide Ratio is from 1 to 16.

FIGURE 4 - 100 MHz PROGRAMMABLE COUNTER

Program I "put

I I I I
DO 01 02 03
C

- 52 MC10136

r-- 51
00 02 03

L
~

r-----"
%MC10l09
0 Q J f out

YaMC10131

°l
C

fin
f out - ::---"-"--
Program I "put
2 1m.x ~ 110 MHz Typ.

3 Divide Ratio I, from 2 to 16.

3·106
 ELECTRICAL CHARACTERISTICS

....s:
10 Cin 001--14
Each MECL 10,000 series circuit has been 13· C
designed to meet the de specifications
12 DO
011--15 L SUFFIX n
shown in the test table, after thermal equi. CERAMIC PACKAGE
o

""
librium has been established. The circuit 11 01 CASE 620
021--2
is in a test socket or mounted On a printed
circuit board and transverse air flow greater
6
5
02
03
~
than 500 linear fpm is maintained. Test 031-- 3 TE$TVOLTAGE VALUES
Procedures are shown only for selected 9 S1
.T.. IVolt" 8::J
inputs and outputs. Other inputs and out- S2 Cout~4 T_.....tu,. VEE ~,
puts are tested in a similar manner.
-:JOllie -5.2 ::J
c::
(!)
+25 I11 C -5.2
+85 I11 C -5.2 Co

Po~r
a...ect.i1lic ....... "n
Undo<
T.t Min
_30°C
M. . Min
MCl0137l Tett Limits
+25 0 C
TyO .... Min
..."" r.t.. Unit
TEST VOLTAQE APPLIED TO PINS LISTED aELOW

VIH mu I Vil min I VIHA min I VILA mu I VEE ....

!Veel

SupplV Dr •• n Current 'E 120 ISO mAde 1,1.

Input Current 1m H 5,6,11,12 220 J.lAdc 5,6,11,12 1,16

~ ~
7 265 7
9,10 2'5 9,10
13 290 13
1m l All 0.5 .I.lAdc <D 1,16
logiC ''1'' VOH I. (2) -1060 -0.890 -0.960 -0.810 -0.890 -0700 Vde 12 7,9 1,16
Output Voltege
LogiC "0" VOL 140 -1.890 -1675 -1.SSC -1.650 -1.825 +1615 Vde 7.9 1,16
Output Voltage
LogiC "I" -0.910 Vde 7,9 12 1.16
VOHA "0 -1.080 -0.980
foP
..... Threshold Volt~

LogiC "0" 7,9 12 1,16

oCX) Threshold Volt;tge
VOLA "<21 -1.655 -1.630 -1.595 Vde

Swltchmg Times +1.11 V +0,31 V Put .. In PuI.. Out -3.2 V +2.0 V

lSO·ohm Load'
ProPlQatlon Delay
ClOCk Input 113+14+ 14 0.8 4.8 1.0 3.3 '.5 1.1 5.0 12 13 1,16
"14
~
113+14_ 14 0.8 4.8 10 3.3 '.5 11 5.0
113+4+
tI3+4_
4
4
20
2.0
10.9
10.9
2.5
2.5
7.0
7.0
10.5
10.5
2.5
2.5
11.5
11.5
•
Carry In To Carry QUI tI0-4_ 4Cl) I.' 74 1.6 5.0 6.9 1.5 7.5 13 lQ
1'0+4+ 4 I.' 7.' 1.6 5.0 6.9 15 7.5 13 10
Set Up Time
Dala InpulS t12+13+ 14 3.5 7,9 12,13 I'
t12-13+ 14 3.5 7.9 12,13
Select Inputs 19+13+ 14 7.5 9.13
17+13+ 14 75 7,13
Carry In Input tl0_13+ 14 3.7 10,13
113+10+ 14 -1.0 10,13 "
"
Hold Trme
Data Inputs 113+12+
,.
14
-1.0
-1.0
7,9
7,9
12,13
12,13
I.
t'3+'2_
Select Inpuls 1'3+9+ I. -2.5 9,13
t13+7+ I. -2.5 7,13
Carrv In Input 113+10_ I. -1.6 10,13
tl0+13+ 31 10,13
Counlmg Frequency 'count up
" 125 125 ISO 125 MH, 13
'countdown "
I. 12S 125 ISO 125 MH,
Rile TIme
120"'0"'" ". •
I.
0.9 3.3 1.1 2.0 3.3 1.1 35

~ ! ~
t'4+ 2.0

• "•
Fall TlmtI
(20"10"'"
'4-
114-
"
2.0
2.0 1 "
(i) IndivtdUIIlly a-ppl, Vil min 10 ptn .... ndII, test .~~. OUI,PUt ah.r clock pUlM VI L . . r VIH. IPPIIn • t cloc~ t!\put (pin 13) Q) Elef9re .te$tl!!!t.Ql and 02 output.~. ~~ ~IO'pic tow.
MC10137 (continued)

COUNT FREQUENCY TEST CIRCUIT

"CCl = Vee2 ~ +2.0 Vde; V out

COl"

Clock Input @--+------o---i 50-ohm ""min.tion to ground 10-

c.ted in eech IeOp. chennel input.

Input Pulse
t ... '" t- ..
Duly Cy".' 50%
1.0"'
fi All input end output cab'" to the
IeOp. ,r.
equ.1 le"gth. of 50-Ohm
cou; ••• c8bI.. Wire le"gth thould

1
be 1/4 inch from TPin to input
pin end TP out to output pin,
0.1"'1 Unu_d output, .re connected to
• SO-ohm , . . ,tor to ground.

+1.11 V VEE" -3.2 lick

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@l2S0C

Carry In
1,1 1$ the m,nlmum t,mll0 ...... ,1 'her thl
count •• I'll. b . ." I"abled 10 clack '1
Ib) II the m,"'mum Ilml b,fo •• thl
co",,,I,. tin be." d ... bled thll II mlV

(e) .. the m,n,mum l,me b.tO" !I"

counler " I"ebl-.;l 11'111 • clock pul.
mlv bl ,pplled WIth no ,lfect on U,.
It.tl of tI,. COunter
Idl Ii thl m.",mum tome to ""'I't .It ..
1M count., IS di.. bl.d th.t • clock
pulle m.y be appll.d With no .tt.ct In

(b) aond (c) m • .,. ber>eg.t ..... numb'"

VCCl VCC2 '20 Vdc You!

NOTE
t setup IS thE' minimum tim. before the pOsitive
tranSllton of the clock pulse (el that Information must
be present at the Input 0 or S.
thold .s the minImum tIme after The pOSItive tran·
Sitlon of the clock pu lse (el that information must
remain unchanged at the input 0 or S.

~
.'IIIV

Clock 50% Clock I.,~"t (Ol--+----o

+031 V \
tc.a. . tc.a- 1+- 1-- 2.0n. t 0,2n.
(20 10 eow,)

a Output

'0·

,-----~--.1 11 V
VEE - -32Vdc
'0.31 V

50-ohm ~rmination to ground 10'

cat«:l in each scope channel input
o or S
All input and outPut cabl . . to the
scope ar. equal length, of 50·ol'lm
coaxial cable. Wire lengtl'l thould
be 1/4 inch from TP,n to input
pin and TP out to outp ... t pin.
Unuied outpull .r. connected 10
a 50-ohm '"Itor to FO ... nd.

3·109
MC10137 (continued)

UNIVERSAL DECADE UP/DOWN COUNTER

519

527

10'0---+-+-

12 DO 1400 1101 1501 602 2 Q2 503 3 03 4 Carry Out

STATE DIAGRAMS

COUNT UP

3·110
 BI-QUINARY ~~__________________M
__E_C_L_l_0_,O_o_o__~_r_ie_s~
COUNTER

MC10138

Advance In:forDl.ation
The MC10138 is a four bit counter ca-
pable of divide by two, five, or ten functions.
COUNTER TRUTH TABLES It is composed of four set-reset master-slave
flip-flops. Clock inputs trigger on the posi-
tive going edge of the clock pulse.
BI-QUINARY
(Clock connected to C2 Set or reset input override the clock,
and Q3 connected to CII allowing asynchronous Hset" or "clear". In·
dividual set and common reset inputs are
COUNT 01 02 03 00 provided, as well as complementary outputs
0 L L L L for the first and fourth bits. True outputs
1 H L L L
2 L H L L are available at all bits.
3 H H L L
4 L L H L
5 L L L H
6 H L L H
7 L H L H
8 H H L H Po '" 370 mW typ/pkg (No Load)
9 L L H H 1tog '" 150 MH:; typ

vee1 :c Pin 1
BCD VCC2 :: Pin 16
(Clock connected to Cl Vee"" Pin 8
and 00 connected to C21
COUNT 00 01 02 03
12 - - C1 00 - - 1 5
0 L L L L
1 H L L L 9- R 01 - - 1 3
2 L H L L 7 - - C2 02 - - 4
3 H H L L
4 L L H L 1 1 - - 50 Q3 --2
5 H L H L 10 - - 51 00 - 1 4
6 L H H L
7 H H H L 6 - - 52 03 --3
8 L L L H 5 - 53
9 H L L H

BLOCK DIAGRAM

50 00 51 01 52 02 53 03
11 15 10 13 6 4 5 2

5 5 5 5
L51 0- LB1 of- L51 Or-
Q~
51

0',---- ~
52 o'r-- - C1 0'- r - - 52 o'r--
12
Clock 0-- C1 0'- - C2 or---- - C2 o - C2 of-
R R R R

I
I
9
Reset 1 1
14 7 3
00 C2 03

This i. advance information and specifications are subject to change without notice.
s.. Genaral I nformation section for packaging and maximum ratings.

3-111
MC10138 (continued)

ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal eqUI-
librium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater 12 C1 ao 15
than 500 linear 'pm is maintained. Outputs 9 R a1 13
are terminated through a 5~ohm resistor to C2 L SUFFIX
a2 4
-2.0 volts. Test procedures are shown for CERAMIC PACKAGE
11 50 OJ
onlv one input and qne output The other CASE 620
inputs and outputs are tested In the !iame 10 51 00 14
manner 6 52 3
03
53

TEST VOLTAGE VALUES

(VollI)

Temp ....tur. VIHmII. VILmin VIHAmini VILAm.. VEE

_30 oe -0.890 -1.890 -1.205 -1.500 -5.2
+250 C ~.810 -1.850 -1.105 -1.475 -5.2
+85 0 C -0.700 -1.825 -, .035 -1.440 -5.2

MCl0138L Tea limit. TEST VOLTAGE APPLIED

.... ....
Pin TO PINS LISTED BELOW

.
-JUoe "'250 e ...a50e
Und.
eh.racteriltu: Symbol T... Min M .. TyO M" Min Unit V," V I..min VJHAmj, VlLAnw< VH- ~
Power Supply Dram Current 'E 70 mAde "6
Input Current 12

!
1m H 220 12

lin L
5,6,10,11

All ..
0.5
2'5
290
"0
I'Adc
5,6,10,11

!! "6
LogIc "'" VOH 3.1~~ -1.060 -0.890 "".960 -0.810 -0.890 -0.700 Vdo 1,18
Output Voltage 2.4d),'5 -1.060 -0.890 "".960 -0.810 -0.890 -0.700 Vdo 5,6,10,11 1,18

Logic "0" VOL 3,14 <D

-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdo 5,6,10,11 1,18
Output Vollage 2,4@"S -1.890 -1.675 -1,850 -1.650 -1.825 -1.615 Vdo 9 1,18

LogIc "1" VOHA 2,4,13,15 -1.080 -0.980 -0.910 Vdo 5,6,10,1 6 1,16
Threshold Vollage (j)
3,14(1)

LogIc "0"
13,15(1)
VOLA 2,4,13,15
+ -1.655
+ -1.630
+ -1.595
+
Vdo
7,12
5,6,'0,"
+ +
6 1,16
Threshold Voltage @
3
1j,',;<& + + + + 7.12
+ +
Swilching Times PuIMln PuI.Out -3.2 V +2.DV.
(5()..ohm Loadl
Propagetion Delay
Clock Delays '12""5'" 15 3.5 12 I. 1.16
50 U Loads 112""4'"
17""3'"
••
13
•2
7
I•
13

~
17"'4'"
'7"'2+
IH3'"
15 12
1f2+15-
112+14- I. 12 "
I.
17""3_ 13 7 13

~
17"'4_
17"'2_
17"'3_
Set Delay 11'''''5''' 15 5.2 11 15

,.
~
111""4- I. 11 I.
Aeset Delay 9

,."
'9""4'"
tg""5- 15 9 15
Rise Time "4'" 2.' 11 I.

~ ~
(20% 1080%1 1'5'" 15 11 I.
FallT,ma
120% 1080%)
114_ I.
• ""
Counting Frequency
'15-
fcount
"2 150 MH, 2
150 MH, 12 I.
-Ind,v,dually apply VILmin 10 pm under telt.
"
<D Set all four flip·slops by applying pul ..
IL~II~:: to pins 5,6,10,11 prior 10 applyIng tnt volt... indicated.

<l> Resel ell four flip-flops by ~plying pul .. n VIH",.JO;

VILmin
lEI pin 9 prior to IIPPlying test volt. indicated.

3-112
MC10138 (continued)

COUNT FREQUENCY TEST CIRCUIT

"eCl· VCC2· +2.0 Vde:

CIOc:k Input ~_...J.---'Cl 00

R 01
Input Pul •• C2 Q2
t+ - t- '" 1.0 nl
Duty Cycle" SO%
50 Cl3
51 00
52 Ci3
53 5C).ohm .. ,min.tion to ,round lo-
All Input MId output cebl.. to the cated In leeh Kope channel Inp",t.
KOp • • r.
-.ual lengths 0' 50-ohm
cOI.i,1 c.... Wire I'nlth ....ould
be 1/4 inch from TPin to Input

r.
pin MId TP out to output pin:
Unu.d output•• connected to
• 5O-ohm , . . .tor to .ound.
VEe" .3.2 Vde:

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 25°C

V,n "CC1" VCC2" +2 0 Vde "OUI

+1.11V

Cl or C2 +O.31V

Cl QO

R 01 aOor 03
C2 Q2 Output
50 Cl3
Clock Input
51 00 00 or 0.3
52 Ci3 Output
50-ohm grmination to ,round 10- 53
CIted In ..,h KOpe enannl' input.

All input end output cabl .. to thl

.cope .r. lIqual langtl,. of 50·ot"lm
coaxi,1 cabl.. Wire length should
be 1/4 Inch from TP in to input
pin and TP out to output pin.
Un ... 1M! outputs .... oonnect~ to veE" -32 Vdc
• 5O-ohm , • •tor to .ound.

COUNTER STATE DIAGRAM - POSITIVE LOGIC

Clock connected to C2 00 c:onnocted to C2

3·113
 FOUR-BIT UNIVERSAL
MECL 10,000 series
SHIFT REGISTER

MC10141

The Me 10141 is a four-bit universal shift

register which performs shift le~t, or shift right,
13
serial/parallel in, and serial/parallel out opera-
OL tions with no external gating. Inputs SI and 52
4 C 00 14
control the four possible operations of the
12 DO
register without external gating of the clock.
11 01 01 15 The flip-flops shift information on the positive
9 02 edge of the clock. The four operations are stop
03 02
veel = Pin 1
6 2 VCC2:: Pin 16 shift, shift left, shift right, and parallel entry of
10 51 VEE = Pin 8 data. The other six inputs are all data type in-
52 03 3 puts; four for parallel entry data, and one for
DR shifting in from the left (OL) and one for shift-
5---...J ing in from the right (DR). All four outputs
are car1ble of driving 50 ohm lines. .
TRUTH TABLE
When the register is used for serial output
SELECT OUTPUTS only, the unused emitter follower outputs can
rs-;-'S2 OPERATING MODE 00n+1 Q1n+1 Q2n+1 Q3n +1 be left open.
P.r.II •• Entry D.
Shift Right· 0'" 02" 0'"
Shift Left· 00" 0'"
Stop Shift 00" 0'" 0." Po = 425 mW tvp/pkg (No Load)
·Outputs .. eXI't .tt., putM-.pCle.".' "e" input With rroput condition.
fShift = 200 MHz typ
. . .hown. (Put .. - Poaltiv. tran.ition of clock Input).

LOGIC DIAGRAM

0'

5'

52

OR~----~+----L~

OJ 02 Q1 00

See General Information section for packaging.

3-114
 ...."...., .... " ....,. ---'-"-~- ............,.
~-

13

-
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 _i .. circuit lin been OL 3:
designed 'to meet the de specifications
shown in the tost tobie, after thermal
4 C 00 14
....
(")

equilibrium has been established. The cir-

cuit is in a test socket or mounted on a
12
11
DO
01 01 15 ....C
printed circuit board and transverse air flow
greater than 500 linear fpm is maintained.
9 D2
D3
L SUFFIX
CERAMIC PACKAGE
....
~

02 n
Outputs are tenn inated through a 5O-ohm CASE 620 0
10 SI
resistor to -2.0 volts. Test procedures are
....
::J
shown for only selected inputs and outputs.
Other inputs and outputs tested in the
7 - 52
DR
03 f - - 3
TEST VOL TAGE VALUES :i"
c:
(Volts)
same manner.
J @Test
Temperature VIH mu: VILmin VIHAmi VILAmax VEE
_lODe -0.890 -1.890 -1.205 -1.500 -5.2
I I I I I ~
+25 De -0.810 -1.850 -1.105 -1.475 -5.2
+ssoe -0.700 -1.825 -1.035 -1.440 -5.2
MC10141L Test Limits TEST VOLTAGE APPLIED TO PINS
Pin
_lODC +25 De +BSDe LISTED BELOW:
IVee)
Characteristic 1SymbDlj U~:: Min I Max Min Typ I Max Min Max Unit VIHmu VILmin VIHAmi VILAmax Vee PI P2 P3 Gnd
Power-Supply DraIn Current Ie 8 82 I 102 mAdc 8 1.16
Input Current I I,n H I 5 -
I - -
I -
I 220 - - .!JAdc 5 - - 8 - - - 1,16

~ ~
220 - - 6 - - - - - -

lIn L 12 - - 0.5 -
245
265
-
-
-
-
-

-
- .!JAdc
7
4
4.5.6.7.9.
-
-
12
-
-
-
-
-
-
t
8
-
-
-
-
-
-
-

-
1,16
10.11,13
~
.... I Logic "1"
Output Voltage
VOH 3 -1,060 -0.890 -0.960 - -0,810 -0,890 -0,700 Vdc 6 - - - 8 4 - - 1.16

C11 I Logic "0" VOL 3 -1.890 -1.675 -1.850 - -1,650 -1.825 -1.615 Vdc - - - - 8 4 - - 1.16
Output Voltage
Logic "'" V8)A
3 -1.080 - -0.980 - - -0.910 - Vdc - - 6 - 8 4 - - 1.16
•
~
- - - - @ - - -

t t ~
Threshold Voltage 6 7

t -
-
-
-
-
-
-

- t 6
-
@
-
-
-
-
- t -

-
••
4
-
-
•-
Logic "0"
I I 3 -1.655 - - -1.630 - -1.595 Vdc - - - 6 8 - 1,16

~ ~-
- -

t t
V(bA - - - -

t
Threshold Voltage

t
7

t t
- -

-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
• -•
-

~
Sw;tch;ng T;mes 150 n Loadll
Propagation Delay t4+3+ 3 0,9 3,9 1.0 2.9 3.8 1.2 4.2 ns 0 - - - ~ - - - 1.16
Setup Time (tsetupl t'2+4+ I. - - 2.5
t,2-4+ - - 2.5
t10+4+ - - 5,0

Hold Time (thold)

t10-4+
I t4+12+
t4+12-
t4+10+

I
j -
-
-
-
-
-
-
-
-
-
5.0
1.5
1.5
1,0

:~
t4+10-
R;se T;me 120% to 80%) t3+ 3 1,0 3.4 36

LI ~
I .."'.-,"-_._"
Fall TIme (20% to 80%1 t3- 3 1.0 3,' 1.1 ! U 33 ! 11 ! 36
u!
ShIft Frequency fShift - 150 - 150 200 150 - !

Pl VIH P2 VIHA P3 VILA

'".~.,
~VIL ~VIL
2 See switching tIme test cIrcuIt for test procedures.
3 See shift frequency test circu~t for test procedures.
JLVIL
4 Reset to zero before performing test
5 Reset to one before performing test.
 ELECTR ICAl CHARACTER ISTICS
13
Each MECL 10,000 series circuit has been
OL

-
designed to meet the de specifications
shown in the test table, after thermal 4 C 00 14 3:
equilibrium has been established. The cir- 12 DO
P SUFFIX
PLASTIC PACKAGE
n
...&
cuit is in a test socket or mounted on a 11 01 01 15 CASE 648 0
printed circuit board and transverse air flow ...&
9 02
greater than 500 linear fpm is maintained. ,JiIo
Outputs are tenn inated through a 5O-ohm 6 03 02 2 ...&
resistor to -2.0 volts. Test procedures are 1 0 - SI TEST VOL TAGE VALUES n0
shown for only selected inputs and outputs.
Other inputs and outputs tested in the 7 - S2 03 r-- 3 @I Test
IVolts)
....
:::J
same manner.
DR Temperature IVIH max Vll min VIHAminVllAmax VeE
:i'
-.J _lODe -0890
+2S o C -0.810
-1.890 -1.205
-1850~ -1.105
-1500
-1.475
-52 c:
ctI
-5.2 a.
+8Soc -0.700 1-18251 -1.035 I -1440 1 -52
MCl0141P Tost Limits TEST VOLTAGE APPLIED TO PINS
Pin
_lODe +2Soc +8So C LISTED BELOW:
Und. 1Vee l
Ch.r.ct_istie I Symbol Tnt Min ~ Max M;n I Ty. Max Min Max Unit VIHmax VILmin VIHAmu VILAmax Vee PI P2 P3 Gnd
Power Supply Drain Current Ie 8 82 102 mAdc 8 1.16
Input Current I lIn H 5 -
I -
- I - I 220 - - JJAdc 5 - 8 - 1,16
-

~
- - -

t
220 - 6 -

lin L 12 - - 0.5 -
245
265
-
-
-
-
-
- jJ.Adc
7
4
4.5.6,7,9,
-
-
12
-
-
.-
-
-

- 8
-
-
-
-
-
-
-
- t
1,16
10,11,13
Logic "1" VOH 3 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vde 6 - 8 4 1.16

I
Output Voltage
W
.:... Logic "0"
Output Voltage
VOL 3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vde - .- - - 8 4 - - 1,16

en logic "1" VOHA 3 1.080 -0.980 - -0.910 Vde 6 8 4 1,16

~
Threshold Voltage (!) - - - - 6 @) - 7 4 - -

t -

-
-
-
-

- t -
- t 6
-
@)
-
-
-
-
-
- 4
-
-
4
+
Logic "0"
Threshold Voltage I VThA I •t
3 -
-
-
t •
-1.655 -
-
-
-
-

-
-1.630

~
-
-
-
-1.595

t t
Vde
-
-
-

~-
-

-
-
6
7
-
8

t
4
4
-

-
4
-
-
1,16

- - - - 6 - -, - - 4
+
Sw;'eh;ng T;mes (50 n Loadll ,3.2V
~
Propagation Delay t4+3+ 3 - - 1.0 2.9 3.8 - - ~s CD - - - 8 - ., 1,16
Setup Time Itsetup) 112+4+ 14 - - 2.5
t12-4+ - - 2.5
t10+4+ - - 5.0
t10-4+ - - 5.0
Hold Time Ithold) I t4+12+ - - 1.5
t.t+12- - - 1.5
t4+10+
t4+10- 1 -
-
-
-
1.0

I
R;s. T;me 120% to 80%1
Fall Time 120% to 80%)
ShIft Frequency
1 t3+
t3-
fShift
3
3
-
-
-
-
-
-
-
1.0
1.1
1.1
150
17
1.7
200
I 33
-
I
= I
-
-
- I LI m............_." _.,...
~,. ,,-"
P~VIH P2~VIHA P3JLVILA
2 See sw'teh;ng t,me test e;'eu,t fo, test pmeedu,",.
3 See shih frequency test .cirCUit for test procedures.
VIL VIL VIL
4 Reset to zero befort.perfQrmina.test. !
5 Reset to one before ·per1ori'lN~~:--:. ':~ "
MC10141 (continued)
~

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C

VCC1 • VCC2
+2.0 Vdc V out

Input Pulse
t+ "" t- = 2.0 ±O.2 ns
251' F l lO.1I'F Coax

(20 to 80%)

All input and output cables to the Input

scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input Pulse Generator
pin end TP out to output pin.
f'
50-ohm termination to ground lo-
cated in each scope channel input.

Clock

I o. 1 I-l F

Q Output VEE· -3.2 Vdc

MC10102

SHIFT FREQUENCY TEST CIRCUIT

VCC1 ~ VCC2
+2.0 Vdc V out

All input and output cables to the

scope are equal lengths of 50-ohm
lO.1I'F Coax coaxial cable. Wire length should
be < 114 inch from TP in to input
pin and TP out to output pin.

Input

Pulse Generator

Test Procedures:

50..ohm termination to ground lo- 1. Set 01,02,03 = +0.31 Vdc (Logic L)

cated in each scope channel input. DO:: +1.11 Vdc (Logic H)

2. Apply Clock pulse n:~:~ to set ao high.

3. Maintain Clock Low.

Set Sl = +0.31 Vdc (Logic U
52 = +1.11 Vdc (Loyic H)
4. Test Shift Frequency

I O. 1 I'F

Vee = -32 Vdc

3·117
 '\ M Eel 10,000 series
QUAD LATCH

MC10153
'--------------'
Advance InforIllation
The MC10153 is a high speed, low power,
MECL quad latch consisting of four bistable
latch circuits with D type inputs and gated a.
outputs. Open emitters allow a large number of
TRUTH TABLE
outputs to be wire-ORed together. Latch out·
G c 0 °n+1
puts are gated, allowing direct wiring to a bus ..
H <P <P L
L H <P
When the clock is low, outputs will follow 0'
On Po = 310 mW tvp/pkg (No Load)
L L L L tpd'" 4.0 ns typ
inputs. Information is latched on positive going
L L H H transition of the clock. The MC1 0153 provides.
4J - Don t Care the same logic function as the MC10133, except'
C= CC+CE for inversion of the clock.

DO 3
2 DO

GO 5
6 01
01 7

CE 4

Cc 13

CE 12

02 9
1102
(;110

1503
0314

vee1 '" Pin 1

VCC2 '" Pin 16
VEE'" PinS

This is advance information and specifications are subject to change without notice.
See General I nformation section for packaging.

3-118
 ELECTRICAL CHARACTERISTICS
. Each MEeL 10,000 series has been de· 3:
2 00
o....

-
signed to meet the de specifications shown
in the test table, after thermal equilibrium
o
....
has been established. The circuit is in a
test socket or mounted on a printed circuit ~~~ I~ 6 01

L SUFFIX U1
board and transverse air flow greater than CE 4
CERAMIC PACKAGE w
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
Cc 13 CASE 620 0-
o
-2.0 volts. Test procedures are shown for CE 12~ ~~ :J
only selected inputs and outputs. Other - I J~ TEST VOLTAGE VALUES ~.
:J
inputs and outputs are tested in a5im;lar 02 9_ ~ 1102 (Volts' c:
manner. Go110 @Test (1)
Temperature VIH max VIL min VIHA min VILA max Vee c.
15 03 -JOoe -0.890 -1.890 -1.205 -1.500 -5.2
0314 QJ +25oC -0.810 -1.850 -1.105 -1.475 -5.2
+8Soe -0.700 -1.825 -1035 -1.440 -5.2 I

Pin MC10153L Test Limits TEST·VOl TAGE APPLIED TO PINS LISTED BELOW: I

Under _loDe +25 0C +85 0C (VCC)

Characteristic Symbol Test Min Max Min Typ Max Min Max Unit VIH max Vll min VIHA min VilA max VEE Gnd
Power Supply Drain Current IE 8 - - - 75 - _. mAdc - 13 - - 8 1,16

InputCunent l;nH ~ ~ = = = ~~ = = "At ~ = ~ = i 1'1

6

13 - - - - 350 - - , 13 - - - , •
I inL 3 - - 0.5 -- - /JAde - 3 - 8 1.16

....4l LogiC "1"

Output Voltage
VOH 2
2
-1060
-1.060
-0.890
-0.890
-0.960
-0.960 -
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Vdc
3
3
4
13
-
;-
-
-
8
8
1,16
1,16

<C
Log;c"O" VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc - 3,1J - 8 1,16

~'" d,!
Output Voltage

L09~~;~:'~Old Vollage VOHA L _1.]080 = _0.]980 =

" "

_ _09 10 v1dc
3.:5

~ ~
=
~
=
~
,
8
,
16
1'1

1 1
2tt - - - - -
2 - 3 - - 4

L09~~;~0~Old Voltage VOLA i2

~
-

_1.

1
655 ~ ~ _1 630

1 1 1
_1.5 95 v dc
3

~
-

~
-

~
13

~ 8

l
1'l16
2tt - 3 - - -
2t! - - - - 3 - - 13
Switching Times

I
(50 H Load) +1.11 V Pulse In Pulse Out -3.2 V +2.0 V
Propagation Oelav t:1+2+ 2 - 3.0 - - ns - - 3 2 8 1,16

R;se T;me (20% to 80%1

tt~;'~: ~
tHold
t2' I
3
2
~ =
-
=
-
-
H
0.7
2.0
=
-
-
- I j 3= •

-
~
-
i 3
3
~
2
2
j
Fall Time (20% to 80%) t2_ 2 - 2.0 - I I - 3 ~ -'---'_ __
tOutput level to be measured after a clock pulse has been applied to the clock input (Pin 41. LSVIH m~x • Latch set to zero state before test.
VIL min
ttData input at proper highllow level while clock pulse is low so that device latches at proper
highllow level for test. Levels are measured after device has latched.
MC10153 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

veel ' vCC2

+2.0 Vdc V out

Pulse Generator

Input Pulse
t+ = t- = 2.0 ± 0.2 ns
(20 to 80%)

All input and output cables to the

scope are equal lengths of 50· ohm
50-ohm termination to ground 10· coaxial cable. Wire length should
cated in each scope channel Input. be < 1/4 inch from TPin to .nput
--'----~ pin and TP out to output pin

Unused outputs connected to

a 50· ohm resistor to ground.
L-----l1~~"~J
VEE = -3.2 Vdc

PROPAGATION DELAY

j)

tsetup is minimum time before the positive transition of the clock

pulse (el that information must be present at the data input (0).

thold is the minimum time after the positive transition of the clock
pulse (el that information must remain unchanged at the data input (0).

3-120
 MEeL 10,000 series
12-BIT PARITY
GENERATOR-CHECKER

MC10160

The MC10160 consists of nine EXCLUSIVE-

OR gates in a single package, internally con-
nected to provide odd parity checking or gen-
eration. Output goes high when an odd number
3 .....-.,r-.....
of inputs are high. Unconnected inputs are
pulled to low logic levels allowing parity de-
4
tection and generation for less than 12 bits.
5
6 --.,<- ~-"

9-~L..-"
2 INPUT OUTPUT
10-,-r---.
Sum of
11-~1~ Pin 2
High Level
12 -'~.--..... Input,
13 - ......'---" Even Low
14 Odd High
15~""L-./ vee1 "" Pin 1
VCC2 = Pin 16 Po '"' 320 mW typ/pkg (NO Load)
Vee;;: Pin 8 tpd = 5.0 nl typ

APPLICATIONS INFORMATION FIGURE 1 - 48-BIT PARITY CHECKER

The MC10160 is useful in any system

requiring high speed detection or generation
of parity. The MC10160 can genarate parity
for twalva bits in 4 ns. A large number of
functions on one chip reduces package count
and saves system power. As shown in Figura
1, bV using four MC10160's and one MC10107
parity can be checked or generated on 48.
bits in 9.5 ns, or 7.5 ns if the MC10107 is
replaced by a MECL III MC1672 or MC1674.
If parity detection or generation is re-
quired for less than twelve bits, the unneces-
sary inputs can be left open. Input pulldown
resistors will insure that the unused inputs
are pulled to the low logic level.

~ $.neral Information section for packaging and maximum ratings.

i
~

3-121
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,000 series circuit has been
designed to meet the de specifications
...
n
o
shown in the test table. after thermal equi- ....
~
librium has been established. The circuit m
is in a test socket or mounted on a printed o
"~riyn!ll
circuit board and transverse air flow greater L SUFFIX
than 500 linear fpm is maintained. Outputs CERAMIC PACKAGE
CASE 620
8
::J
are terminated through a 50-ohm resistor
to -2.0 volts. Test procedures are shown
....
'0
:i"
for one set of conditions. Complete test- t:
ing according to truth table.
"'2 (!)
a.
,.,.13~ @Test
TEST VOLTAGE VALUES
(Volts)
Temperature VIHmax VILmin VIHAmin VILAm •• VEE
-30D e -0.890 -1.890 -1.205 -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2
MC10160L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Under _30 D e +25 o C +8SoC IVee l
Characteristic Symbol Test Min Max Min TVp Max Min Max Unit VIHmax VILmin VIHAmin VILAmax VEE Gnd
Power Supply Drain IE 8 - - - 62 78 - - mAdc 4.5.9.10.13.14 - - - 8 1.16
Current
ctJ I nput Current linH 3 - - - - 265 - - ~Adc 3 - - - 8 1.16
-'
I'-)
4 - - - - 220 - - JJAdc 4 - - - 8 1.16
I'-) linL 3 - - 0.5 - - - - JJAdc - 3 - - 8 1.16
Logic "1" VOH
Output Voltage 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 3 4.5.6.7.9.10. - - 8 1.16
11.12.13.14.15
Logic "0" VOL
Output Voltage 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc - 3.4.5.6.7.9.10. - - 8 1.16
11.12.13.14.15
Logic "'" VOHA
Threshold Voltage 2 -1.080 - -0.980 - - -0.910 - Vdc - 4.5.6.7.9.10.11. 3 - 8 1.16
12.13.14.15
Logic "0" VOLA
Threshold Voltage 2 - -1.655 - - -1.630 - -1.595 Vdc - 3.5.6.7.9.10.11 - 4 8 1.16
12.13.14.15
Switching Times
150 n Loadl
Propagation Delay +1.11 V Pulse In Pulse Out -3.2 V +2.0 V
t3+2+ 2 1.8 8.1 2.0 5.0 7.5 2.0 8.0 ns - - 3 2 8 1.16
t3+2- 4 -
t3-2- - -
t3-2+
t4+2+
t4+2-
t4-2-
t4-2+
j j j j j j j 4
-
3
-
3
-
-
-
-
-
+
4

+
Rise Time
(20% to 80%1 '2+ 1.1 3.5 1.1 2.0 3.3 1.0 3.5 - - 3
Fall Time
1211% to 811%1 '2- 1.1 3.5 1.1 2.0 3.3 1.0 3.5 - - 3
 ELECTfttCAL CHARACTERISTICS
Each MECL 10,000 .riel circuit hoi been
dni.,.ed to ....t the de specification I ....
~
o
o

-
shown in tt. test table, after thermal equi-
libri um has been established. The circu it PSUFFIX 0)
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
PLASTIC PACKAGE
CASE 648
o
than sao linear fpm is maintained. Outputs n
are terminated through 8 ~ohm resistor
o
:J
to -2.0 volts. Test procedures are shown ~.
10 :J
for one set of conditions. Complete test-
ing according to truth table. 11 c:
ct>
12.
13
.e:
14
TEST VOLTAGE VALUES
15
OT... (Vol..)
T emp....tur. VIHma" VILmin VIHAmin VI LAm. . T VeE
-30Ge -0.890 -1.890 -1.205 -1.500 -5.2
+250 C -0.810 -1.850 -1.105 -1.475 1 -5.2
+850 C -0.700 -1.825 -1.035 -1.440 -5.2
MC10160P T•• Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Und.r -3O"c +25oC +85·C (Vee)
Characteristic Symbol T ... Min Mo. Min Typ Ma. Min Ma. Unit VIHmelt VILmin VIHAmin VI LAm. . VEE GNI
Power Supply Drain IE 8 62 78 mAde 4.5,9,10,13,14 8 1,16
Current
W
.:.. II npu. Curren' linH 3
4
265
220
/JAde
/JAde
8
8
1,16
1.16
I\J
W linL 0.5 IJAdc 1,16
Logic "1" VOH
Output Voltage -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 4,5.6,7,9,10, 1,16
11,12,13,14,15
logic "0" VOL
Output Voltage -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 3.4,5,6,7,9,10,1 8 1.16
11,12,13,14.15
Logic "'" VOHA
Threshold Voltage -1.080 -0.980 -0.910 Vdc 4,5,6,7,9,10,11,1 3 8 1,16
12,13,14,15
Logic "0" VOLA
Threshold Voltage -1.655 -1.630 -1.595 Vdc 3,5,6,7,9,10,111 8 1,16
12,13,14,15
SWitching Times
(SO 0 Load)
Propagation Oelay +1.11 V Pul.ln +2.0 V
t3+2+ 2.0 5.0 7.5 3 1,16
t3+2- 4
'3-2-

j j j
t3-2+
t4+2+
4
+
4
'4+2-
'4-2-

Rise Time
'4-2+
+
(20% '080%) '2+ 1.1 2.0 3.3
Fall Time
(20% '080%) '2_ 1.1 2.0 3.3
, 3
Me1 0160 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SOC

:1.
Vin VCC1 ; VCC2 V out
+2.0 Vdc

25~F~ltO.1~F Coax

Input Pulse r---- - - --.,

Generator
I
o---<l
+0.31 V I
I
Input Pul .. I
t+ '" t- "" 2.0 ±. 0.2 ".
120 to 80%)
I
I
I
I
I
C ____ Fi.'-:- ~
I

Vee = -3.2 Vdc

5O~hm termination to ground 10- PROPAGATION DELAY

CIIted in ..ch scope channel input.

All input and output cable. to the

scope .re equal length. of 50-ohm
coaxial cabl.. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
V out

V out

3-124
 MECL 10,000 series
BINARY TO 1-8 DECODER
(LOWI

MC10l61

The MC10161 is designed to decode a three

bit input word to a one of eight line output_
The selected output will be low wh Be all other
outputs will be high. The enable inputs, when
either or both are high, force all outputs high.
This device has high Z input pulldown resistors
POSITIVE LOGIC
and open emitter outputs.

EO 2
1:'1 15
6 aD

5 a1

4 a2

A 7

3 a3

13 Q4

.9
12 05

11 06
Po ::: 315 mW typ/pkg (No Load)
tpd = 4.0 ns tvp
C '4 10 Q7

Veel "" Pin 1

VCC2 = Pin 16
VEE = Pin 8

TRUTH TABLE
ENABLE
INPUTS INPUTS OUTPUTS
~1 EO C B A 00 01 02 03 04 05 06 07
L L L L L L H H H H H H H
L L L L H H L H H H H H H
L L L H L H H L H H H H H
L L L H H H H H L H H H H
L L H L L H H H H L H H H
L L H L H H H H H H L H H
L L H H L H H H H H H L H
L L H H H H H H H H H H L
H <P <P <P <P H H H H H H H H
<P H <P <P <P H H H H H H H H
tj) = Don't Care

Gen ... _ Information section for packaging.

3-125
MC10161 (continued)

ELECTRICAL CHARACTERISTICS
Each MECL 10,000 serles elrcu,1 has been
desIgned to meet the de speCIfIcatIons
shown In the lest lable, aher thermal eqUI
Iobr'um has been establIshed. The Clfcu,t IS
,n a test socket or mounted on a printed
e.rcult board anotransverse a,r flow greater
Ihan 500 Imear fpm 15 millnlalnl.'d Outputs
are terminated through a 50-ohm resIstor 10
¥ 2 0 volts Test procedures afe shown for
only one onpul/outputcombin.tion. Other
combmatlons afe tested according to the
truth table
- CO"""
CERAMIC PACKAGE
CASE 620

TEST VOLTAGE VALUES

(Vol.

VILmin VIHAmin VILAm.. VEE

-1.890 -1.205 -1.500 -5.2
-1.850 -1.105 -',475 -5.2
-1.825 -1.035 -1.440 -5.2
MCl0181L T_ Limit.
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:

CharllC.,lstie S, .....
u....
T. . M'. ....
-JO"c
Min
.,
'25"C
T,• ....7. Mm
.85"C
Mu Unit VIHm_ VIL min VIHArnin VILAm.. VEE
1Vccl
0 ...

,.,. ,.
Po_ Supply Dr.in Currern 'E S mAd< 2,1,9,14,15 1,18
Input Current linH
lin 0.'
220 ,Ad<
,Ad< ,. 1,16

I_ogic "1"
OutputVolmge
VOH 13
13
-1.<160
-1.060
-4.890
-4.890
-0.960
-0.960
-0.810
-0.810
-0.890
-4.890
-0.100
-0.100
Vd<
Vd< ,.,.
2 l,1e
1,16
Logic "0" Output Voltage
Logic"l"
Threshold Voluge
VOL
VOHA
13
13
'3
-1.890
-1.080
-1.080
-1.675 -1.850
-4.980
-0.980
-1.650 -1.825
-0.910
-0.910
-1.615 Vdo
Vd<
Vd< ,.,.
2
l,1e
l,t6
1,18

,.
Logic "0" Thnllhold Voltage VOLA '3 -1.655 -1.630 -1.595 Vd< 1,18
SwitchintTi"",
150n LCMdI
Propagetio" Del.y tl4+1~ '3 6.2
6.2 ,1...• '.0 6.0 1.. 6.' ,.
Pul.ln Pul. Out
'3
-12V
S
+2.0 V
',18

~
1.. 6.0 1.. 6.'

~ ~
t14_13+ '3 '.0
Ri_Time 120% to 80%) 113+ '3 1.0 3.3 1.1 2.0 3.3 1.1 3.'
F.II TIme 120% to 80%) ":>- 13 1.0 3.3 1.1 2.0 3.3 1.1 3.'

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2S0C

V out

Coax Coax
PROPAGA TlON DE LAY

Input

Pulse
Generator

Input Pulse
t+ = t- = 2.0 ±. 0.2 ns
(20 to 80%1 V out

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the Unused outputs connected to

scope are equal lengths of 50·ohm a 50-ohm resistor to ground.
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin VEE 0:: -3.2 Vdc

3-126
MC10161 (continued)

ELECTRICAL CHARACTERISTICS
Elen MECL 10,000 series clfe .... ' has been
cfntgned to meet the de specificatIons
-.own in the test table, after thermal eqUI-
t;briurn hh been established. The CirCUit '5
in • test socket or mounted on a pnnted
circuit bo.d and tranwerse air flow greater
~... 500 line.. fpm IS maintained. Outputs
in tlll'minlled through a 50-ohm resistor to
·2.0 volt •. Tnt proc:edures are shown for
anly one input/outpUt combination. Other
QClmbiMitions If.
te.ted according to the
avrh Ilbl •.

- P SUFFIX
PLASTIC PACKAGE
CASE 648

TEST VOLTAGE VALUES

(Voltsl
n ...
Temperatu,. V'Hm .. VILmin VIHAmin VILA",.. "EE
-30"<: -0.890 -1.890 -1.206 -'.500 -5.2
.,.,,<: -0.8'0 -1.850 -1.105 -1.475 -5.2

u_P'.
..."<: ·0,700 -1825 -1.035 -1.440 -5.2

--
...... Supply Dr. Current
l ....tCunwnt

LAllie"'"
Sy_

"
'inH
linL
"OH
T. .

I.
8

"
13
Min
-30"<:

-1.060
M.

-".890
Min

•..
-".560
MC'O'6'P THI Limits

.,
'25"<:
TyO M.
7.
220

-0.810
Min
• .."<:

-0.890
M.

-0.700
Unn
mAd<
,Ad<
,Ad<
"d<
TEST VOLTAGE APPLIED TO PINS LISTED BELOW;

V'H",.
2,7.9,14,15
14

2
Val min

"
VIHA min VILA max VEE
(Veel
Gnd
1,16
1.16
1,16
1,16
I.

_T_
Ou1pUtVoitaIgt 13 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 "d< 1,16
laIk "a' OutpUt Vo'''' VOL 13 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 "d< 1,16
LeIII:"," VOHA 13 -1.080 -".560 -0.910 "d< " 2 1,16
"T"tNWIoIdVol.... 13 -1.080 -0.980 -0.910 "d< 1,16
"'''0''' Th ..... otd Vol . . . VOLA 13 -1.655 -1.630 -1.595 "d<
" 1,16
"
(IDOL_'
~ionDel.., 114+13- 13
13
I.,
I.'
..• ..0
Pul. In
14
Pul. Oul
13
-3.2 V
8
+2.0 V
1.16

~ ~
1'4-13-t '.0 •.0
R_ Time (~to 80%) '13+ 13 1.1 2.0 3.3
F.'TlrM(~toamc., '13- 13 1.1 2.0 3.3

A complete mux/demux operation on 16 bits for data

I APPLICATION INFORMATION distribution is illustrated in Figure 1. This system, using

the MC10136 control counters, has the capability of in-
crementing, decrementing or holding data channels. When
The Mel01Bl is a true parallel decoder. No series both SO and Sf are low, the index counters reset, thus
gating is used internally, eliminating unequal delay times initializing both the mux and demux units. Thefour binary
found in other decoders. This design provides the identical outputs of the counter are buffered by the MC10101s to
4 ns delay from any address or enable input to any send twisted-pair select data to the multiplexer/demulti-
output. plexer units.

3-127
 FIGURE 1 - HIGH SPEED 16-BIT MULTIPLEXER/DEMULTIPLEXER
s:
....
(")

o....
Control Selection

MC10101 MC10115
....
0)

8::J
....
::J
SO 15141312111098 7· 6 5 4 3 2 1 0 c:
Cl>
SI MC10136 Q.

CR
A B C 0

El El
C C
MC10164 MC10164
B B
A A
DO DO

C;ol
....
I\J
CD so

SO
SI
SI MC10136

CR
A B C 0
CR
EO EO
El El
C C
MC10161 MC10161
B B
A A

1514131211109 B 765 4 3210

 MECL 10,000 series
BINARY TO 1-8 DECODER
(HIGHI

MC10162

The MC10162 is designed to convert three

lines of input data to a one-of-eight output_ The
selected output will be high while all other out-
puts are low. The enable inputs, when either
or both are high, force all outputs low.

POSITIVE LOGIC

A 7

• 9

Po:::: 315 nl typ/pkg (No Load)

tpd '" 4.0 nl typ
C 14

vee1 = Pin 1
VCC2=Pln16
Vee E: PinS

TRUTH TABLE
INPUTS OUTPUTS
Eo E1 C B A 00 01 Q2 03 04 os 06 07
L L L L L H L L L L L L L
L L L L H L H L L L L L L
L L L H L L L H L L L L L
L L L H H L L L H L L L L
L L H L L L L L L H L L L
L L H L H L L L L L H L L
L L H H L L L L L L L H L
L L H H H L L L L L L L H
H 'i> 'i> 'i> 'i> L L L L L L L L
'i> H 'i> 'i> 'i> L L L L L L L L

'" - Don t Car•

. . . .Gen..1 Information section for peck-Uing.

3-129
MC10162(continued)

ELECTRICAL CHARACTERISTICS
Each MEeL 10,000 series circuit hal been
designed to I'TIHt the de specifications
shown in lne test table, after tMrmai equi-
librium has been established. The eita.!!t is
in a test socket or mounted on a printed
Circuit bo.d and tran .. erse ai, flow greater
than 500 linear fpm is meinlained. Outputs
are terminated through 8 SG-ohm resistor to
- 2.0 volU. Test procedures .reshown for
_liv input/O\ltput combination. Other L SUFFIX
combination, .... t-st~ Kcordinll to the CERAMIC PACKAGE
truth t8ble.
CASE 620

~"Q' TEST VOl.TAGE VALUES

~"Q'
IVahsl
@lIS!
Temperltur. VIHm..: VILmln VIHAmin VILA milt VEE
-lOoe -0.890 -1.890 -1205 -1500 -5.2
+25 o C -0810 -1.850 -1105 -1475 -5.2
+8SoC -0700 -1825 -1035 -1440 -5.2
MC10162L Tm Limilt
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:

.... ....
P'" -lOoe +2SoC +SSoC
U.... 1Veel
C .... '.ct.... ItIC Symbol T... M,n M," T,p M,n M•• UnIt VIHm. . VILmm VIHAmin VILAm •• VEE Gnd
Power Supply Or,lIo Current 'E 61 76 mAd.: 8 1.16
Input Current ImH 220 "Ade 1.16
l,nL O. "Ade 1,16
log.c·" VO" 13 ·1060 -<7890 -0960 -0810 -0890 -0700 Vd, 14 1,16
Output Voltage
Logie "0" VOL 13 ., 890 -1675 -1850 ., 650 1825 -1615 Vdc 2 1,16
Output VOltage 13 -1890 -1675 ·1850 -1650 -1815 -1615 15 1,16
Log'c"," VOHA 13 -1080 -0980 ·0910 14 1,16
Threshold VOltage
LogIC "0" VOLA 13 .1655 -1630 -1595 V", 2 1.16
Threshold Voltage 13 .1.655 ., 630 -1595 15 1,16
SWItChIng T ,mes
/SO-ohm loadl Pulse I" PulMOut -J.2V +2DV
Propagllt.on Delav ft4")+ 13 I.. 62 I.' 40 6.0 1.5 64 n, 14 13 1,16
'14-13- 13 15 62 I.' 4.0 6.0 15 6.4

l 1 l l l
Rise TIme 13 1.0 33 1.1 2.0 3.3 11 3.'
(20,*, 10 80%1
Fall TIme 13 1.0 33 1.1 2.0 3.3 1.1 3.'
(20~ to 80'1101

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C

VCC1 • VCC2

!t,,",
+2.0 Vdc Vout

Coax ~,,± ,... PROPAGATION DELAY

Input
r---------..,I
I
I
Pulse

~
+1.11V
Generator 50%
- ----+0.31 V
Input Put . .
t+:c: t- = 2.0
(20 to 80%)
±. 0.2 ns I t--
---......" 80%
t++

V out

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the Unused outputs connected to

scope are equal lengths of 50-ohm a 50·ohm resistor to ground.
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin. VEE"" -3.2 Vdc

3·130
MC10162 (continued)

I!t.ECTRICAL CHARACTERISTICS
Eah MECL 10,000 serlu ClfCUlt has been
dftitned to meet the de specifications

-
~n in the test table, after thermal eQui·
librh.lm hn been established. The circuit is
in • test KlCket or mounted on II prmted
circuit bo.d and tr .... "'erw alf flow greater
thlnftOOline.fpmismaintained. Outputs
. . terminated through II 50-ohm resistor to

--.
-2.0 vo'tI. Tnt proceduresllr. shown for
only input/output combination. Other P SUFFIX
combiMtions ere t"tecl according to the PLASTIC PACKAGE
CASE 648

TEST VOLTAGE VALUES

(Volu)

VILmm VIHAmin VILA me_ V,,

, .. -----r=r= -1890
-1850
-'205
-1105
-1500
-1.475
-5.2
-5.2
-1.825 -, 035 -1440 -52
MCl0162P Tillt limitt

et.ad.iR,C
Power SuPJlly Or.in Current
.Input Current
Symbol

"
linH
.- Pin
u ....

8
14
M~ Typ
61
M..
76
220
Min Mall Uml
mAde
J'Ade
TEST VOLTAGE APf'lIED TO PINS LISTED BELOW:
I---,----,---,-----,------j
VIH mell \IlL "lin VIHA min VILA mell VEE
B
(Vee l
Gnd
1,16
1,16
'inL 0.' J'Adc 1,16
LOIIIIC "'" VOH 13 -1.060 -<l890 -0960 -0810 -0890 -0100 1,16
Output Voltage
l.ogie''O'' Val 13 -l.B90 -1.675 -1850 ·1650 1.82S -HitS Vdc 2 1,16
DutputVOltlgf 13 -1.890 -1675 -1850 -1650 -1825 -1615 Vjc 15 1,16
:LGelC"'" vOHA 13 -1.080 -0980 -0910 1,16
Threshold Volt. .
logIC ''0'' VOLA 13 -1655 -1630 -t 595 Vdo 2 1,16
Threshold Voltage 13 -1655 -1630 -1.595 Vdo 15 1,16
SWl1c:tung TnT.,
CSO-ohmlo8d1 PulMtn Put" Out -3.2 V +2.0 V
PrOP9lion Delay '14+13+ I) I.' 40 6.0 14 13 8 l,t6
t,4·13_ 13 I.' 4.0 6.0
AiteTime 13 1.1 2.0 3.3
l2O'Ato8O'r.J
F.UTime
120% to eo%)
13 1.1 2.0 3.3 1 1 l 1 1
FIGURE 1 - DEMULTIPLEXER (1 OF·B LOCATIONS)

I APPLICATION INFORMATION

The MC10162 is a true parallel decoder. No series Oata Select

gilting is used internally, eliminating unequal delay times 00 01 02
found in other decoders.
This device is ideally suited for demultiplexer applica-
tions as shown in Figure 1. One of the two enable inputs
is used as the data input, while the other is used as a data Data In EO
enable input. Enable
A complete mux/demux operation on 16 bits for data
distribution is illustrated in Figure 2. This system, using
theMC10136 control counters, has the capability of incre-
menting, decrementing or holding data channels. When Oata Output
bOth SO and S1 are low, the index counters reset, thus
i~itializing both the mux and demux units. Control infor-
mation via twisted pair lines is sent through MC10101 gates
to the MC10115 line receivers to provide select data to the
f'l!ultiplexer/demultiplexer units.

3·131
 FIGURE 2 - HIGH SPEED 16-BIT MUl TlPlEXER/DEMUl TlPlEXER
~
...
(")

o...
Control Selection
C')
MC10101 MC10115 N

~ 8
:I
50
~­
1514131211109 8 76643210 :I
~151 MC10136
c:
CI>
I~CR c.
A B C o

t:::1
rrar
) x=;( I

MC10164

DO iBr MC10164

DO

ctJ
....
t.l MC10101 MC10115

~: 'II ~'--------'::
~

51
MC10136
CR
A B C o

rrar
CR~ I I
EO EO

Start/Stop
MC10162

iBr MC10162

1514131211 10 9 8 76543210
 ERROR DETECTION-
MECL 10,000 series
CORRECTION CIRCUIT

MC10163 • MC10193

Advance In~orDl.ation

The MC10163 and the MC10193 are error detection
and correction circuits. They are building blocks designed
for use with memory systems. They offer economy in the
design of error detection/correction subsystems for main-
frame and add-on memory systems. For example, using
eight MC10163's together with eight 12-bit parity check-
ers (MC10160), single-bit error detection/correction and
double-bit error detection can be done on a word of
64-bit length. Only eight check bits (80-87) need be
added to the word. A useful feature of this building block
is that the MC10193 option generates the parity of all
inputs to the block. Thus, if the MCl 0193 is applied in a
byte sequence, individual byte parity is automatically
available.

MCl0163 LOGIC DIAGRAM MC10193 LOGIC DIAGRAM

81 7 81 7
82 II 82 6
16POA 15 P4

8412 8412
8711 8711
3 P3 3 P3
86 4 85 4
86 6 86 5
2 P5
2 P08
80 II 80 9
8310 8310

}-----14PI r----14 PI

}-----'-13P2 }-----13P2

IBM CODE MOTOROLA CODE

PO A = 81. 82. 84. 87 PI - 81. 83. 85. 87
P08 - 80. 83. 85. 86 P2 = 82. 83. 86. 87
PI = 81. 83. 85. 87 P3 - 84. 85. 86. 87
P2 = 82. 83. 86. 87 P4- 81. 82. 84. 87
P3 = 84. 85. 86. 87 P5 = 8yt. (80.1.2.3.4.5.6.7)

VCCI = Pin 1
VCCI - Pin 1
VCC2 = Pin 16 VCC2 - Pin 16
VEE = Pin 8 VEE - Pin 8
Po = 520 mW typ/pkg (No Load) Po = 520 mW typ/pklj (No Load)
'Pd = 5.0 ns typ tpd E: 7.5 n. typ (pin 7 to pin 2)

Thill. advance information and specifications are subject to change without notice.
S- General Information section for packaging and maximum rating•.

3-133.
 ELECTRICAL CHARACTERISTICS 817 ~
s:("')
Each MECL 10,000 .ries circuit has been
....

-
15 PO",
designed to meet the de specifications
shown in the test table, after thermal o
....
equilibrium has been established. The cir-
cuit is in a test mcket or mounted on a
en
to)
printed circuit board and transverse air

s:•
flow greater than 500 linear fpm is main- 2 POe

tained. Outputs are terminated through

:~,~ I II I Ie L SUFFIX
....
a 50-0hm r.sistor to -2.0 volts. Test pro- I ("')
CERAMIC PACKAGE
cedures are shown only for selected inputs CASE 620
and outputs. Other inputs and outputs are o
....
tested in a similar manner.
CO
to)
n
~...
TEST VOLTAGE VALUES o
(Volts) ....
::J

@T.st ::J
13P2
Temperatur. VIHmax VILmin VIHAmin VILAmax VEE C
R>
_30 G e -0.890 -1.890 -1.205 -1.500 -5.2
20
+25 oC -0.810 -1.850 -1.105 -1.475 -5.2
+8So C -0.700 -1.825 -1.035 -1.440 -5.2
MC10163L Test Limits TEST VOLTAGE APPLIED TO
Pin
_lOGe +2SoC +ssoc PINS LISTED BELOW, IVcc l
Under
CharleteristK: Symbol T ... Min Mo. Min Typ Ma. Min Mo. Unit VIHmex VILmin VIHAmin VILAmax VEE Gnd
'rl Power Supply Drain Current 8 - 125 - - mAde - - - - 8 1.16
~
'E
w Input Current linH 4.6.10 220 jJAde 4,6,10 8 1.16
~
5.7.9.11.12 - - - - 265 - - jJAdc 5,7,9,11,12 - - - 8 1.16
linL 0.5 - - - - jJAde - - - 8 1,16
Logic "'" Output Voltage VOH 2 1.060 -0.890 0.960 0.810 -0.890 -0.700 Vdc 4 8 1.16
- - - -
~
3 4
13 - 11 - - -

Logic "0" Output Voltage

14
~ -1.890
+ +
-1.675 -1.850
-
-
+
-1.650
+
-1.825
+
-1.615
+
Vdc
11
-
-
4
-
-
-
-
+
8
+
1,16
VOL
- - -
~
-
~ ~
3 11
13 - - 11 - -

Logic "'" Threshold Voltage VOHA

14
2 -1.080
+ - -0.980
-
-
+
-
+
-0.910
+
- Vdc
-
-
11
-
-
5
-
-
+
8
+
1.16

~
- - - - - - -
~
3 11
13 - - - - - - 5 -

Logic "0" Threshold Voltage

14
2
+
-
-
-1.655
+
-
-
-
-
-1.630 -
-
-1.595
+
Vdc
-
-
-
-
4
-
-
5
+
8 1.16
VOLA
3 - - - - - - - 11
13 - - - - - - - 5

Switching Times
14 -
+ - -
+ -
+ + -
+1.11 V
- - 4
Pulse In Pul.Out
+
-3.2 V
+
+2.0 V
150 n Loadl
Propagation Delay t7+15+ 15 - - - 5.0 - - - n. - - 7 15 8 1,'6

~
-

~
- - - - - - - 14

~
t4+14+ 14 5.0 4
Rise Time (20% to 80%) t15+ 15 - - - 2.0 - - - - - 7 15
Fall Time (20% to 80%) t15- 15 - - - 2.0 - - - - - 7 15

-Individually telt each input, apply VILmin to pin under test.

 ELECTRICAL CHARACTERISTICS :;; r r:C 3:

-
Each MECL to,ooo .rias circuit has been (')
designed to ineet the de specifications ~

shown in the test table. after thermal o

~
equilibrium has been established. The cir·
cuit is in a test socket or mounted on a .. ~ I,I I! )C en
printed circuit board and transverse air
w
flow greater than 500 linear fpm is main-
tained. Outputs are terminated through
. a 5O-ohm resistor to -2.0 volts. Test pro-
L SUFFIX
CERAMIC PACKAGE
•
s:
CASE 620 (')
cedures are shown only for selected inputs ~
and outputs. Other inputs and outputs are o
tested in a similar manner. ~

<C
W

l
'---IL/
TEST VOL TAGE VALUES
14 PI n
(Volts) o
::J
@Test ~,
13P2 Temperature VIHmllx VILmin VIHAmin VILAmax VEE ::J
_30 G e -0.890 -1.890 -1.205 -1.500 -5.2 C
,~
C\l
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2 Cl..
+85 oC -0.700 -1.825 -1.035 -1.440 -5.2
MC10193L Test Limits TEST VOLT AG E APPLI EO TO
Pin
Und_ _30°C +250 C +850 C PINS LlSTEO BELOW: (Veci
ChI,acteristic Symbol Test Mm M •• Min Typ M •• Min M •• Unit VIHmax VILmin VIHAmin VILAmax VEE Gnd

~
Power Supply Drain Current Ie 8 - - - - 125 - - mAde - - - - 8 1.16
..... Input Current linH 4,6,10 - - - - 220 - - #lAde 4,6,10 - - - 8 1.16
-
w
(J1
linl
.
5,7,9,11,12
-
-
-
-
0.5
-
-
265
-
-
-
-
-
,uAde
/olAde
5,7.9.11.12
-
- -
-
-
-
8
8
1,16
1,16
logic "1" Output Voltage VOH 2 -1.060 -0.B90 -0.960 -0.810 -0.890 -0.700 Vdc 4 - - - 8 1,16

+ ~ ~
3 - 4 - - -
13 - 11 - - -

logic "0" Output Voltage VOL

14
2 -1.890
+ +
-1.675
+
-1.850
-
- -1.650 -1.825 -1.615 Vdc
+ 11
-
-
4
-
-
-
-
+
8
+
1,16
3 - - 11 - -
13 - - 11 - -

logic "'" Threshold Voltage VOHA

14
2 -1.080
+ +
-
+
-0.980
-
-
+
-
+
-0.910
+
- Vdc
+ -
-
11
-
-
5
-
-
+
8
+
1,16
3 - - - - - - 11 -
13 - - - - - - 5 -

logic "0" Threshold Voltage VOLA

14
2
+
-
-
-1.655
+
-
-
-
-
-1.630
+
-
-
-1.595 Vdc
+ -
-
-
-
4
-
-
5
+
8
+
1,16
3 -
-
-
-
-
-
- - - - 11
13 - - - - 5

Switching Times
14 -
+ - -
+ -
+ + -
+1.11 V
- -
Pul.ln Pul.Out
4
+
-3.2 V
+
+2.0 V
(50n Load)
Propagation Delay t7+15+ 15 - - - 5.0 - - - n, - - 7 15 8 1,16 -
t4+14+ 14 - - - 5.0 - - - - - 4 14
t7+2+ 2 - - - 7.5 - - - - - 7 2
- - - - -
1
t4+2+ 2 7.5 - - - 4 2
- - - - - -
Rise Time (20% to 80%)
Fall Time (20% to 80%)
t15+
tl&-
15
15 - - -
2.5
2.5 - - - J -
-
-
-
7
7
15
15 J
-Individually test each input, apply Vllmin to pin under test.
MC10163 • MC10193 (continued) .,."

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SOC (MC10163)

Input(9)~}
Output (4) 85 Biased lit VIH
Coax (2) (MC1 Even Parity on inputs
Output (See logic diagram)

(2) (MC1019'i)"\
P~ ~
r
Byte

Input(9~}
Output Odd Parity on Input.
(5•• logic diagram)
(2) (MC10163)
POB r---\
_._-.

-.J '-
I Output
(2) (MC10193)

I P5
Byte

I
I
I 50-ohm termination to ground located
in each scope channel input.

I,--=~
Unused outputl connected to II 50-ohm

l
re.iltor to ground.

,~.".,.
t+ - t- -
L_-
2.0 ± 0.2 ns
Il,:"o~~~ r.
All input and output cables to the
ICOp• • equal lengths of 50-ohm
coaxi.1 cabl •. Wire length should
be < 1/4 inch from TPln to input
(20 to 80%)
pin and TP out to output pin.

VEE - -3.2 Vdc

MC10163 APPLICATIONS INFORMATION

The MC10163 is a building block for generating the
modified H"amming single·error-correction. double·error·
detection (SEC·DED) code used in the IBM 370/145
memory. While the MCl 0163 can also be used for gener·
ating other patterns. it is optimized for generating the
pattern shown in the H matrix of Figure 1.
When writing into a memory, the MC10163 is used to
generate the eight check bits (CG-C32. CT) which are
stored with the 65 data bits (B()'B63). These check bits
are generated by taking the parity of all data bits marked
with an X in the appropriate row of the H matrix.
(CO, Cl. C32. CT. are even parity; C2. C4. CB. C17. are
odd parity.) To generate these check bits with the building
blocks. eight MC10163's and eight MC10160 parity
checkers ere used. One MC10163 is connected to each
byte of d~ta and the outputs of these building blocks are
connected to the eight MC10160 parity checkers. one for
each check bit. Figure 2 shows which connections are
required (i.e., CO is the even parity of output POA of the
MC10163 on the "zero" byte of data, output POB of the
"zero" byte. POA of the "one" byte, ...• POB of the
"three" byte and data bit 32.)
During the memory read operation. the fetched check
bits previously generated (as described) are exclusive·ORed
with newly generated C()'C32 to generate syndrome bits
SO·S32. Syndrome ST is a special case where ST is the
even parity of all eight fetched check bits and all 64·
fetched data bits. For determining the type and location
of an error:
1. If all syndromes (s()'S32 and ST) are false. there is
no error. .
2. If ST is true and s()'S32 are false, the CT is in error.
3. If ST is false and one or more of s()'S32 is true;an.
uncorrectable error has occurred.
4. If ST is true and one or more of SO·S32 is true, ~
simply add the Sl-S32 bits to get the binary location.'
of the error (Sl has weight 1. S2 weight 2. S4.;
weight 4. etc.)
Data bits BO and B32 are special cases of this location
technique: BO is in error if ST. SO. and S32 are true;'-
B32 is in error if ST. SO. Sl. and S32 are true. .

3-136
 FIGURE 1 -1701141 PAn:.aN .. ~
...o
o
...
a')
W

BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4' BYTE 5 BYTE 8 BYTE 7

•
s:
~~~~~~~~
0123468 8 910111213141518171819202122232426282728283031323334353837383940414243444648474849605152831i415118571181iB8081828381T
o...
XXX •••••• X ••••• IC ••• " ........ ICII....
... • Cl
m
...
o

. ..
•• x )I )( " • )I; C2
<C
• x •• Co)
III )I; )I; • C4
x x )(

.... o
)I; • III ,. .. • )I; )I; .. )I; x )I; •• C8
o
...
• • • • )( • • • C18
)( )( • • • • • • • C32 :::J
!:!.
• )I x CT :::J
c:
C1>
c.

ctJ
.....
W
.....,

FIGURE 2 - 370/146 PATTERN GENERATION

co = POAO P080 POAI P081 POA2 P082 POA3 P083 8(32)

Cl = Pl0 P11 P12 P13 P14 PIS P16 P17 8(32)
C2= P20 P21 P22 P23 P24 P25 P26 P27
C4 = P30 P31 P32 P33 P34 P35 P36 P37
C8 = POAI P081 POA3 P083 POA5 P085 POA7 P087
C16 = POA2 POA2 POA3 P0s3 POA6 P086 POA7 P087
C32= POA4 P0s4 POA5 P085 . POA6 P086 POA7 P087 8(0)
CT= POAO P081 P082 POA3 POA4 P085 P086 POA7 8(0)

Where for PNM: N = MC10163 OUtpUl

M = 8yt. Number
MC10163 • MC10193 (continued)

MC10193 APPLICATIONS INFORMATION

The MCl 0193 is a building block for generating modi-

;n&;~~~I~m fied Hamming SEC-OED codes. It can be used for any
length data word and for a variety of codes. The MC10193
0
is optimized for codes organized on a byte repetitive
ill basis and has the advantage of automatically supplying
18
., whole byte parity (P5 output). While it is possible to use
is a number of criteria for choosing a pattern, the pattern of
ill
<I
.,
~

:;;
· .· .· ·· . Figure 3 was chosen on the basis of speed and ease of
error location decode. As can be seen in the H matrix of
Figure 3, the pattern is repetitive by byte with the various
., rows generated by only five combinations of bit parities
Ii within the bytes. For the 64 bit data word in the example
ill
18 of Figure 3, the eight check bits (B64 to B71) are gener-
in ated by the odd parity of all data bits indicated by an X

· . ·· · .
:8 in the appropriate row. The syndromes Sl to 58 Bre
~

·
~

;!; generated by including the fetched check bits in the same

~
~ generator that originally generated the check bits.
:;; The pattern of Figure 3 is easily generated by using

··
~
eight MC10193 devices, one for each data byte and eight
Ii:
~ MC10160 parity checkers, one for each syndrome/check
w
.......::E
«
.
:
~

II
· bit. The connections of building blocks and parity checkers
are shown in tabular form in Figure 4 and in schematic
)(
~
form in Figure 6.
w ; Once the syndrome bits (Sl to S8) have been formed
Z
II: ~ from fetched data (BO to B63) and fetched check bit$..
w ~
l-
I- ;; (B64 to B71), the determination of type and location of.
...« ~ error is simply done:
«
....
i!l 1. If all syndromes are false, there is no error.
II! 2. If one syndrome is true, the corresponding check
0
II: ~

0 ill bit is in error.

I- ~

0 ~ 3. If more than one syndrome is true, and the parity

;!;

.
::E

W
II:
I
~
~
N
~

;:;
of all syndromes is even, a multiple (uncorrectable)
error has occurred.
4. If more than one syndrome is true, and the parity
g of all syndromes is odd, a single error has occurred,
·
:::l
Cl III
ii: ~
and is easily located by the circuit of Figure 5.
::; Figure 5 gives the error location circuit for the example
Ie pattern. The outputs EBO to EB7 are a one-of-eight-high
l!l code giving the byte in error. Outputs ECO to EC3 give
~
~
N
the binary location of the bit in error within the located
N
N byte. Since this location process can occur simultaneously
N
with the determination of error type described, the entire
.
g

!!
error correction sequence (using a toggling fetched data
latch) takes less than 20 ns. This is because an error
:: occurrance detector is a simple ORing of Sl to S8. The
!!
!!?
:!
:?
JC )( )( 10:

·· error locator has simultaneously located the error which

is then corrected as though the error was a single (and
therefore correctable) error. The parity of syndromes then
~
determines if the error was indeed single, and interrupts
::
~ the CPU if the error was an uncorrectable (multiple)
error. Since uncorrectable data is unusable without special
~
·. · . · · · handling, the CPU would be interrupted anyway; there-
fore this automatic correction of any error as if it were
single does not create any problems. This fast error cor-
rection technique allows single error correction on a non-
interrupt basis with only a 20 ns memory system access
ti me pena Ity .
These techniques can, of course, be extended to large
or smaller data words·

3-138
MC10163 • MC10193 (continued)

FIGURE 4 - M2 PATTERN BUILDING BLOCK

51 = Pl0 Pll P12 P13 P54 P55 P56 B(64)

52= P20 P21 P22 P23 P54 P55 P57 B(65)
53 = P30 P31 P32 P33 P54 P56 P57 8(66)
S4z P40 P41 P42 P43 P55 P56 P57 8(67)
55= P14 P15 P16 P17 P50 P51 P52 8(68)
56= P24 P25 P26 P27 P50 P51 P53 B(69)
57 = P34 P35 P36 P37 P50 P52 P53 B(70)
58= P44 P45 P46 P47 P51 P52 P53 8(71)

Where for PNM: N = MC10193 Output

M = Byte Number

FIGURE 5 - M2 PATTERN CORRECTION MATRIX

S5 56 _
S7 58 [ > - - - E 8 D

[>---E81

56 S6 -
S7§ij ~
~. EB2 SI- D} EC
52 - - - EC1 Byte. 0·3
55 56 _ ~ E83 53---EC2
.57§ij ~

$1-
52 53 [ > - - - EB4
55 ---ECD I
54 56 - - - EC1 (Byte. 4.7
57---EC2,
$1-
52 S3 - [ > - - - EB5
54

$1 52 53
- - [ > - - - EB6
54
51- ~
S2 5354 ~E87

3·139
MC10163 • MC10193 (continued)

FIGURE 6 - SYNDROME AND CHECK BIT GENERATOR. M2 PATTERN

Bit p

'IJ
"1" for Check Bits
1 10 "0" for Syndromes

...o{ 2
3
:
6
7 MC10193
20
30
40
50
10
12
54
56
11
13
55

MC10160
SI

664

{IJ"15 MC10193::
21
31

665
20
22
54
57
21
23
55

MC10160
S2

,{ "IJ
12
22 30 31
32 32 33 S3
42 54 56
52 57
23 MC10193 MC10160
866

{~IJ
13
23 40 41
33 42 43 S4
43 55 56
53 57
MC10160
667

·LIJ
14
24 14 15
34 16 17 55
44 50 51
54 52
MC10160
968

rIJ
15
25 24 25
5 35 26 27 56
50 51
53
47 MC10193:: MC10160
869

,{ ~IJ 16
26
36
46
56
34
36
50
53
35
37
52
57

55 MC1Q193 MC10160
870

'LIJ
17
27
44 45 '
37
46 47 58
47
51 52
57
53
MC10160
871

3-140
 '\ MECL 10,000 series
8-LlNE MULTIPLEXER
\.--------------'
MC10164

The MC10164 is a high speed, low power

eight-channel data selector which routes data
present at one-ot-eight inputs to the output_
The data is routed eccording to the three bit
TRUTH TABLE code present on the address inputs_ An enable
input is provided tor easy bit expansion_
---
ENABLE C
ADDRESS INPUTS
B A Z
L L L L xo
L L L H XI
i. L H L X2
L .L H H X3
L H L L X4
L H L H X5
L H H L X6 Po - 310 mW typ/pkg (No Load)
L H H H X7 tpd - 3.0 nl typ (Oete to output)
H q, q, q, L
t/J "" Don't Care

.--
A 7 )
.----
B 9
2
C 10
~
)
Jr-
~
15 Z

xo 6

~T
Xl 5

X2 4
R T
X3 3
R r
X4'1
y
~:;
X512

X613
>-- R
T
--===4 Y
X714

vee1 = Pin 1
VCC2 = Pin 16
't.
r..~ _____________________________________________________________________________________
Vee = PinS
--J

s .. Gen.r.1 Information section for packaging.

3-141
 ElECTR ICAl CHARACTER ISTICS
s:(')
Each MECL 10,000 series circuit has been
designed to meet thedcspecifications shown ...o
in the test table, after thermal equilibrium
has been established in an ambient temper-
A 1

...
~
ature of 2SoC, while the circuit is in a test • 9

socket or mounted on a printed circu it

board and transverse air flow greater than C 10 o
500 linear fpm is maintained. Outputs are
o
E"n.bi02 111111 ~ ....
::J

-
terminated through a 50-ohm resistor to 15 Z
-2.0 volts. Test procedures are shown for ::J
only one input. or for one set of input con- L SUFFIX c::
<»
ditions. Other inputs tested in the same CERAMIC PACKAGE a.
manner. CASE 620

)(4 11 t fTTT=L-.-

t]§
TEST VOLTAGE VALUES
)(5 12
(Volts)
tilT ...
)(6 13 T emper.ture VIH max VILmin VIHA min VILA milK VEE
-30"c ~.890 -1.890 -1.205 -1.500 -5.2
cp )(7 14 +:ZSOC ~.810 -1.850 -1.105 -1.475 -5.2
~

~ +85oC ~.700 -1.825 -1.035 -1.440 -5.2

I\)
MC10164L Tnt Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Under -30"c +25oC +l5oC
IVcCI
Charut .. istic Symbol T... Min Mo. Min Typ Mo. Min Mo. Unit VIH ~ax VILmin V'HAmin VILA max VEE Gnd
Power SupplV Drain Current IE 8 60 75 mAde 8 1,16
I nput Current lin H 2 - - - - 265 - - ,.Ade 2 - - - 8 1,16
lin L 4 0.5 ,.Ade 4 8 1,16
Logic "1" VOH 15 -1.060 ~.890 ~.960 - ~.810 ~.890 ~.700 Vde 4,9 - - 8 1,16
Output Voltage
Logic "0" VOL 15 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vde 9 - - - 8 1,16
Output Voltage
Logic "1" VOHA 15 -1.080 - ~.980 - - ~.910 - Vde 4,9 - - 2 8 1,16
Thres,",old Voltage
Logic "0" VOLA 15 - -1.655 - - -1.630 - -1.595 Vde 9 - - 2 8 1,16
Threshold Va Itage
Switching Times +1.11 V Pul .. ln Pulse Out -3.2 V +2.0 V
150 n Loadl
Propagation Delav t4+15+ 15 1.5 4.7 1.5 3.0 4.5 1.6 4.8 ns 9 - 4 15 8 1,16
'4-1&- 15 1.5 4.7 1.5 3.0 4.5 1.6 4.8 9 - 4
t7+15+ 15 1.9 6.3 2.0 4.0 6.0 2.2 6.5 5 - 7
'7-15- 15 1.9 6.3 2.0 4.0 6.0 2.2 6.5 5 - 7

j j j j
t2+15+ 15 0.9 3.3 1.0 2.0 2.9 1.0 3.1 7,5 - 2
15 0.9 3.3 1.0 2.9 1.0 3.1 7,5 - 2

~
t2-15+
Rise Time t+ 15 0.9 3.3 1.1 3.3 1.2 3.6 9 - 4
120%'080%1
Fall Time ,- 15 0.9 3.3 1.1 3.3 1.2 3.6 9 - 4
(2011 to 80%1
 ELECTRICAL:Cti'ARACTERisTICS
3:
Each MECL 10,000 series circuit has been
designed to meet thedcspecifications shown ...
o
in the test table. after thermal equilibrium
has been established in an ambient temper-
A 7

...
o
~
B 9
ature of 2SoC, while the circuit is in a test
socket or mounted on a printed circuit
board and transverse air flow greater than C '0
8

-
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
,n.bl. 2 I I I I I I ...,-----.., '5 Z
:::l
~.
-2.0 volts. Test procedures are shown for P SUFFIX :::l
only one input. or for one set of input con- X06 II~ PLASTIC PACKAGE
c:
(1)
ditions. Other inputs tested in the same CASE 648 a.
manner. X'.5 IIIIII G
X2 4 II I ffil--.-
X3 3 ' II ffil--.-
X411 tmn ____
L+R 'J TEST VOLTAGE VALUES I
)(5 12 IVoltsl

)(6 13
R 'J
~
@Test
T empM'.tur. VIH INX VILmin VIHAmin VILA max VEE

~
.....
)(7 14
-===\ r -ao"e
+;zsoe
+850 C
~.890
~.810

~.700
-1.890
-1.860
-1.825
-1.205
-1.105
-1.035
-1.500
-1.475
-1.440
-5.2
-5.2
-5.2
~
W MC10164P Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW
U'-
-30"e +2SoC +85o C
IVeel
Charact_istic Symbol T_ Min M.. Min Typ Mox Min Mox Unit VIHm..: VIL min VIHAmin VILA IN. VEE GNI
Power Supply Drain Current 'E 8 60 75 mAde 8 1,16
, I nput Current lin H 2 - - - - 265 - - ,.Ade 2 - - - 8 1,16
lin L 4 0.5 ,.Ade - 4 8 1,16
Logic "1" VOH 15 -1.060 ~.890 ~.960 - ~.810 ~.890 ~.700 Vde 4,9 - - 8 1,16
Output Voltage
Logic "0" VOL 15 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vde 9 - - - 8 1,16
Output Voltage
Logic "1" VOHA 15 -1.080 - ~.980 - - ~.910 - Vde 4,9 - - 2 8 1,16
Threshold Voltage
Logic "0" VOLA 15 - -1.655 - - -1.630 - -1.595 Vde 9 - - 2 8 1,16
Threshold Voltage
Switching Times +1.11 V Pul.ln PuI.Out -32 V +2.DV
150 n Loadl
Propagatton Delay t4+15+ 15 - - 1.5 3.0 4.5 - - n. 9 - 4 15 8 1,16
15 - - 1.5 3.0 4.5 - - 9 - 4

I
'4-15-
t7+15+ 15 - - 2.0 4.0 6.0 - - 5 - 7
'7-15- 15 - - 2.0 4.0 6.0 - - 5 - 7

j j j
t2+15+ 15 - - 1.0 2.0 2.9 - - 7,5 - 2
15 - - 1.0 2.9 - - 7,5 - 2

~
'2-15+
Rise Time ,+ 15 - - 1.1 3.3 - - 9 - 4
(20%'080%1
Fill Time t- 15 - - 1,1 3.3 - - 9 - 4
120%'080%1
--- - - - - - - '----~
Me1 0164 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C

VCC1 ~ VCC2
+2.0 Vdc V out

Coax

r---------
I
...---..
)
~"'rtJ'"'
,.
-- - - - ---,
1
~ Coax

Input
I I
I I
Pul. Generetor
2- I

~
I

Input Pul ..
t+-t-""2.0±O.2ns
(20 to 80%)
I
I
)
---
1,/
I
I
I
I ~y
I

I
I
===\
I
'5
I
I
~
;-
50..ohm termination to ground lo-
cated in each scope channal input.
I
I
I
r
I
I
'5
All Input and output cable. to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
I ~
B'5
~'5
be < 1/4 inch from Tpiin to input I
t
pin and TP out to output pin.

VEE - -3.2 Vdc

PROPAGATION DELAY

V out

3·144
 r'C10164 (continued)
i
'II-

_c
Itl{;-
Ii ei:'

!t::I!'~i ".

eight data inputs and an enable, A high level on the enable

APPLICATION INFORMATION
forces the output low. The MC10164 can be connected
directly to a data bus, due to its open emitter output and
output enable.
f1<ln
Figure one illustrates how a 1·of-64 line multiplexer can
~:"~jhe MC10164 can be used wherever data multiplexing be built with eight MC10164's wire ORed at their outputs
'4"__ IIel to serial conversion is desirable. Full parallel and one MC10161 to drive the enables on each multi-
_ .... permits equal delays through any data path. The plexer, without speed degradation over a single MC10164
•_ -_'~'''1)f the MC10164 incorporates a buffer gate with being experienced.
"1& 'i ,",

FIGURE 1 - l-OF-64 LINE MULTIPLEXER

ABC

MSB 07
14 A B C
06
05
C out
I 04
.
,,
r'~'
9 MC10161 03
I 02
f A B C
01
. t; LSB 00

ABC

°out

The Bit chosen i, dependent on six-bit

ABC
code present on Inputs 7. 9, 14 of the
Met01S1 and the A, B. C inputs of the
MC10164. D out

ABC

C out

3-145
 8-1 NPUT MECL 10,000 series
PRIORITY ENCODER

MC10165

Advance In:forIIl.ation.
The MC10165 is a device designed to encode eight
TRUTH TABLE inputs to a binary coded output. The output code is
that of the highest order input. Any input of 10_
DATA INPUTS OUTPUTS priority is ignored. Each output incorporates. l8tch
DO 01 02 03 04 05 06 07 03 02 01 00 allowing synchronous operation. When the clock i.\Qw
the outputs follow the inputs and latch when the clOCk
H H L L L goes high. This device is very useful for a variety of
L '" ''"" '" ''"" '" ''""
H '"
''""
H L L H applications in checking system status in control pro-
L
L
L
L
H
''"" '" ''"" '"
L H
H
H
L
L
H
H
L
H
cessors, peripheral controllers, and testing systems..
The input is active when high, (e.g. the three binary
L
L
L
L
L
L
'" ''"" ''""
L
L
H
L H
''"" H
H
H
H
L
L
L
H
outputs are low when input DO is high). The 03 output

L
L
L
L
L
L
L
L
'" L
L
L
L
H
L ''""
H
H
H
H
H
H
H
L
H
is high when eny input is high. This allows direct ex-
tension into another priority encoder when more tt:aan
eight inputs are necessary. The MC10165 can IllQrbe
L L L L L L L L L L L L
used to develop binary codes from random logic; i.~tI,
'" = Don't Care for addressing ROMs, RAMs, or for multiplexing deta.

Po = 545 mW typ/pkg (No Load)

tpd '" 7.0 ns typ (Data to Output)

C 4
VCC1 "" Pin
VCC2 = Pin 16
00 5 ) VEE = PinS

01 7 ~----~--------~L)­
.2.

0213
__
L
L-~--------~r+------to

03 10 --r',
~~~'______~~+-~ ____~

"This I, advance Info,.".tlon and tpeelflcatlonl ar. lubject to cheng. without notlc •.
S_ G.ner.1 Information Hetlon for peckaglng.

3·146
 •.,__ ,..... _ _ .___ "~... \-_~~ .... _ _ >.~~..,...;-.:.--.:-. .. ~.....:,....:.~ •.:._:<.,.,. ... ;:...;..:...;.~O.:.- ............,.;... ~~,.~-. ..... ~ ..... ,~~ .• '·1·'· "'",'"...'""
t', ..t:1 f· ...'..... ·~· "-"1
i -

;-5L.ecT"ICALCHAR~RfST-tCS
3
"-.----- 3:

-
Each MECl 10,000 _ios circuit has been
designed to meet thedcspecifications shown
• PSUFFIX
PLAS-TIC PACKAGE
l.SUFFIX--
CERAMIC PACKAGE ...o
("')
in the test table. after thermal equilibrium
has been established in an ambient temper-
ature of 250 C. while the circuit is in a test
100-- 03
2 CASE 648 CASE 620
...
CI')
socket or mounted on a printed circuit
TEST VOL TAGE VALUES U1
board and transverse air flow greater than 110-- 04 02 --015 C')
(Volts)
500 linear fpm is maintained. Outputs are 120-- 05
Test
o
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for 9 0 - - 06
@II
Temperature VIH max VILmin VIHAmin VILA max VEE ....
::J
5'
only one input, or for one set of input con- 6 0 - - 07 03
r---0 '4 _30°C -0.890 -1.890 -1.205 -1.500 -5.2 c
ditions. Other inputs tested in the same
manner.
+25OC -0.810 -1.850 -1.105 -1.475 -5.2 ~
+85 0 C -0.700 -1.825 -1.035 -1.440 -5.2
MC10165 Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Under -300C +25OC +8SOC (VCC)
Characteristic Symbol Test Min Max Min Typ Max Min Max Unit VIH max VIL min VIHA min VILA max VEE Gnd
Power Supply Drain Current IE 8 - - - 105 131 - - mAdc - - - - 8 1,16
I nput Current lin H 4 - - - - 245 - - "Adc 4 - - - 8 1,16
5 - - - - 220 - - "Adc 5(j) - - - 8 1,16
lin L 4 0.5 - "Adc - 4 - 8 1,16
5 - - 0.5 - - - - "Adc - 5(j) - - 8 1.16
Logic "1" VOH 2 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 6 4 - - 8 1.16
Output Voltage 3 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 - -
14 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 - -

...'fl Logic "0" VOL

15
2
-1.060
-1.890
-0.890
-1.675
-0.960
-1.850
-
-
-0.810
-1.650
-0.890
-1.825
-0.700
-1.615
+
Vdc
+
-
+
4
-
-
-
-
+
8
+
1.16
.j:O
..... Output Voltage 3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 - -- -
14 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 - -
Logic "1" VOHA
·15
2
-1.890
-1.060
-1.675
-
-1.850
-0.980
-
-
-1.650
-
-1.825
-0.910
-1.615
-
+
Vdc
-
-
+
4
-
6
-
-
+
8
+
1,16
Threshold Voltage 3 -1.080 - -0.980 - - -0.910 ~
- -
14 -1.080 - -0.980 - - -0.910 - - -
15 -1.080 - -0.980 - - -0.910 -
+ -
+ + -
+ +
Logic "0" VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc - 4 - 6 8 1.16
Threshold Voltage 3 - -1.655 - - -1.630 - -1.595 - -
14 - -1.655 - - -1.630 - -1.595 - -
15 - -1.655 - - -1.630 - -1.595 + - + - + + +
Switching Times (50-ohm Load) Unit +1.11 V +0.31 V Pulse In Pulse Out -3.2 V +2.0 V
Propagation Delay
Data Input t7+14+ 14 - - - 4.4 - - - ns - 4 7 14 8 1,16
15 - - - 6.5 - - - - 11 15

!
t11+15+
t7+3+ 3 - - - 11.0 - - - - 7 3
'13-2- 2 - - - 7.0 - - - - 13 2
t13+2+ 2 - - - 7.0 - - - - 13 2
Clock Input t4+2+ 2@ - - - 3.5 - - - 7 - 4 3
Setup Time tsetup H 3 - - - 3.4 - - - - - 4.7 3
tsetup L - - - 3.0 - - - - -

---~
HOld Time

Rise Time (20% to 80%~

Fall Time (20% '0 80%)
'hold H
thold L
'3+
'3_
j -
-
-
-
-
-
-
-
-
-
-
-
-
-2.3
-2.7
2.0
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-
-
-
-
4
4
---
+
7
7
--
j
(j) The same limit applies for all D type input pins. To test input currents for other D inputs, * To preserve reliable performance, the MC10165P (plastic-packaged device only)
individually apply proper voltage to pin under test. is to be operated in ambient temperatures above 7SoC only when 500 Ifpm blown
(2) Output latched to low state prior to test. air or equivalent heat sinking is provided.
MC10165 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

VCC1 KVCC2-
+2.0 Vdc V out

25"F~
C08J1i

Input Pul ..
t+ ". t- "" 2.0 ns ± 0.2 n.
(20 to 80%)

Data Input [()o~---""-o

TPin J '--TP out

Unu..c:l outputs connected to •

50-ohm termination to ground lo-
50-ohm rasistor to ground.
cated in each lcope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm
coaxial cabl.. Wire length should
be < 1/4 inch from TPin to input -3.2 Vdc
pin and TP out to output pin. VEE

~--"""',-------+1.11 V
o Input
NOTE:
'------+0.31 V
tsetup is the minimum time before the positive tra~
sitlon of the clock pulse (C) that information must be
pra.ent at the data Input (0).
thold is the minimum time after the positive tran-
sition of the clock pulse· (C) that information must
remain unchanged .at the data input (0).

~---+1.11V

.....--....,.,-+---- +0.31 V

C
+0.31 V

\"----

3-148
MC10165 (continued)
i
I

nected to this encoder such that, when a given condition

exists, the respective input will be at a logic high level. This
APPLICATION INFORMATION
scheme will select the one of 64 different system condi·
tions, as represented at the encoder inputs, which has
priority in determining the next system operation to be
~typical application of the MC10165 is the decoding of performed. The binary code showing the address of the
/It8qI $tatus on a priority basis. A 64 line priority encoder highest priority input present will appear at the encoder
tboW" in the figure below. System status lines are con· outputs to control other system logic functions.

64-LINE PRIORITY ENCODER

,---------------------------------------------OLse

112 MC10l0l
I MC10164
Iz
XO .... X7ABC
I MC10164
XO . . . X7ABC
Il ~z
MC10164
XO ...... X7ABCJ
I Six bit output
word yielding

Im=tta'~Il=mm=tt:E11~1=~
number of

i~r~!:'"~~ l~l~
hlghett priority

J
channel pr.sent
at input

Highest 0: DO ~ Q1 f+-+++l+lf+--------J
~'Io'ity ol-i
"Input ~03 ~
07 l1 02 ~:$!$~~===:$!$~~===~~~~===1rc--- DO 00 I-<>
r;:::::::= a 1 I- I-<> ,
C ., 00r- r;::= 02 I--H> MSB

i
DO ..
o 011---++1+If+-------~
r-
r- 07 ~
u 02~--~HH~--------~HH~------~ '-----
J. 07 l1 03~--++1+I~--------++1+If+---------++1+I~

~O ~ 001--
o
i 01~---+1+If+-------~
u 02~--~HH~--------~HHH_---------J
J. 07 l1 03~--~HH~--------~HHH_--------~HH~

~O ~ OOt--
i o 01~----1+If+---------~
u 02~----HHH-----------HHH_--------~
J 07 l1 03~----I+If+-----------I+IH-----------HHH_~

C ., 001----
DO ~ 01~-----HH-----------
i u 021------H~-----------Hf+---------~
J 07 l1 03~-----H~-----------HH-----------_HH_~

C 10 aO'L....----~
DO ~ 01~----_4+_----------~
U 02~----~+_----------~+_----------~
07 l1 03~----~+_----------~+_----------_;;_---"

;-
C
DO .
.,
0
00
01
U 02
.J. 07 l1 03
I C
.
.,
00
" DO
k'Ow"t i
iprlority
001
U 02
:tnput
i..:.
J- 07 l1 03

3-149
 5-BIT MAGNITUDE MECL 10,000 series
COMPARATOR

MC10166

Advance InforIllation
The MC10166 is a high speed expandable
5-bit comparator for comparing the magni-
TRUTH TABLE tude of two binary words. Two outputs 8Ff
Inputs Outputs provided: A < B and A > B. A = B can be
E A I 8 A <8 A>8 obtained by NORing the two outputs with ail·
H X I X L L additional gate. A high level on the enabl1t<
L Word A = Word B L L function forces both outputs low. Multlplr
L Word A > Word B L H
MC10166s may be used for larger word com-
parisons.
L Word A < Word B H L

Po = 440 mW tvp/pkg (No Load)

tpd = Data to output 6.0 ns typ
E to output 2.5 "I typ

LOGIC DIAGRAM

veel = Pin 1
VCC2'" Pin 16
Vee = Pin 8
A4 9
84 10----.-~ ./

A3 12
83 11 - - - _...._ /
2A>8

L
1
t
I
A2 13 1
B2 14 ---~--n._/

t;
3A<B
!I

Al
81
6

II
!i
I
AO 5--~~~~>-_ _ _ _~
!
!
BO 4

E 15

\
I

This is advance information and specifications are subject to change without notice.
S•• Genera' Information ..ction for packaging. ,.J

3-150
 ...o...3:
ELECTRICAL CHARACTERIST'ICS
Each ME C L 10.000 series has been de· (")
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a 0')
test socket or mounted on a printed circuit 0')
board and transverse air flow greater than
n-

-
500 linear fpm is maintained. Outputs are O
terminated through a 50-ohm resistor to ::J
-2.0 volts. Test procedures are shown for ::to
::J
only selected inputs and outputs. Other L SUFFIX
inputs and outputs are tested in a similar CERAMIC PACKAGE ffi
manner. CASE 620 c.

TEST VOL TAGE VALUES

Volts
@Tost
Temperatur. VIHmax VILmin VIHAmin VILAmax VEE
::!~ -lO"c -0.890 -1.890 -1.205 -1.500 -5.2
+25"c -0.810 -1.850 -1.105 -1.475 -5.2

......
If' +850 C -0.700 -1.825 -1.035 -1.440 -5.2

I
MC10166L Test Limits
U'I Pin VOLTAGE APPLIED TO PINS LISTED BELOW,
Unci... -lOoe +2SoC +8SoC (VCC I
Characteristic Symbol Test Min M•• Min Typ Ma. Min Max Unit V.Hmax VILmin VIHAmin VILAmex VEE GncI

Power Supply Drain Current 'E 85 106 mAde 4,7,10,11,14 1,16

Input Current linH 220 IlAdc 8 1,16
linL 5 0.5 .uAdc 8 1,16
Logic "'" Output Voltage VOH 2 -1.060 -0.890 -0,960 -0.810 -0.890 -0.700 Vdc 5 8 1,16
3 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 4 8 1,16
Logic "0" Output Voltage VOL 2 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 5,15 8 1,16
3 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 4,15 8 1,16
Logic "'" Threshold Voltage VOHA 2 -1.080 -0.980 -0.910 Vdc 5 15 8 1,16
3 -1,080 -0.980 -0.910 Vdc 4 15 8 1,16
Logic "0" Threshold Voltage VOLA -1.655 -1.630 -1.595 Vdc 5 15 8 1,16
-1.655 -1.630 -1.595 Vdc 4 15 8 1,16
Switching Time,
(50 n Loadl
Propagation Delay
- +1.11 V Pul.ln Pul.Out -3,2 V +2.0 V

Data to Output t9+2+ 2 6.0 9 8 1,16

2 9

I
'9_2_
t1'-2+ 2 12 11
t,'+2_ 2 12 11
17+3+ 3 6
'7-3- 3 6
Enable to Output 115-3+ 3 2.5 10 15
t'5+3- 3 2.5 10 15
Rise Time (20% to 80%) '2+ 2 2.0 9
Fall Time (20% 10 80%) '2_ 2.0 9
MC10166 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 25°C

VCCI ~ VCC2:
+2.0 Vdc V out

251'F ~ ,x.0.11<'F
Coax Coax

A >B
A2
Oate Input or----:6--o B2

TPinJ
AI
Bl A<B
\'TP out

AO
BO
E
50-ohm tarmlnation to ground 10·
cated In each scop. channel Input.
All input and output cables to the ~O.II'F
lCope .r. equal lengths of 50-ohm
coaxial cable. Wire lanoth Ihould
be < 1/4 inch from TPln to Input -3.2 Vdc
pin and TP out to output pin. VEE
UnuMd outputs tied through •
50-ohm rali_tor to .. ound.

....

.J

3-152
fMC10166 (continued)

APPLICATION INFORMATION

FIGURE 1 - 9·BIT MAGNITUDE COMPARATOR

AOBOA1B1A2B2A3B3A4B4 A6B6A6B6A7B7ABBB

B24 B4
A24 A4
B23 B3
A23 A3A<B MC10166 MC10166
B22 B2
A22 A2 A>B A<B
B21 Bl A>B
A21 Al
B20 BO
';'20 AO

B19 B4
A19 A4
BIB B3
AlB A3 A<B A>8 A<8 A' 8
B17 B2
A17 FOT 9-81t Word
A2
B16 Bl A>B
A16 Al
B15 BO
A15 AO

B14 B4 B4
A14 A4 A4 A-8
B13 B3 B3
A13 A3 A<B I-++---,A < 8
~==::jA2
B12 B2 FIGURE 2 - 25·BIT MAGNITUDE COMPARATOR
A12 A2
Bll Bl A>B . - - - - - i B l A>BI-....- - - A > 8
All Al A1
Bl0 80 80
Al0 AO AO

B9 84
A9 A4
BB B3
AS A3 A<B The MC10166 compares the magnitude of two 5·bit
B7 B2
A7 A2 words. Two outputs are provided which give a high level
B6 81 A>B for A> B and A < B. The A = B function can be obtai ned
AS AI by wire·ORing these outputs (a low level indicates A = B)
B5 BO
A5 AO or by NORing the outputs (a high level indicates A = B).
For longer word lengths, the MC10166 can be serially
B4 B4 expanded or cascaded. Figure 1 shows two devices in a
A4 A4
B3 B3
serial expansion for a 9-bit word length. The A> Band
A3 A3A<B A < B outputs are fed to the AO and BO inputs respectively
B2 B2 of the next device. The connection for an A = B output is
A2 A2 also shown. The worst case delay time of serial expansion
Bl Bl A>B
Al AI is equal to the number of comparators times the data· to·
BO BO output delay.
AO AO
For shorter delay times than possible with serial ex·
pansion, devices can be cascaded. Figure 2 shows a 25-bit
cascaded comparator whose worst case delay is two data·
to·output delays. The cascaded scheme can be extended
to longer word lengths.

3·153
 '\ MECL 10,000 series
QUAD LATCH

MC10168
"'---------'
Advance Infor:rnation
The MC10168 is a Quad Latch with common
clocking to all four latches. Separate output
enabling gates are provided for each latch,
allowing direct wiring to a bus. When the clock
is high. outputs will follow the 0 inputs. In·
formation is latched on the negative·going tran-
Po = 310 mW typ/pkg INo Load)
tpd: G to a,. 2 n. typ
sition of the clock.
o to a - 3 nl typ
C to a .. 4 n. typ

DO 3------------~~

00
GO 5----~~~~~----------~--/
Gl 4------+-----------------~
;c------- 6 01

01

Cc 13

02 9----~~------~

II 02
G2 12------+-----------------~~__/

G3 I 0 ----~----=----------~
;c------- 15 03

14 ____________ ~~

TRUTH TABLE
03
G C 0 a,,+1
H 0 0 L
L L 0 0
L H L L
VCC1 "" Pin 1
L H H H
VCC2 = Pin 16
VEE = Pin 8
-
0-dontcare

This is advance information end speciflcationsllr. subject to change without notice.

s . . General Information .action for peckaglng.

3·154
 ELECTRICAL CHARACTERISTICS
3:
Each MECL 10,000 series has been de· C')
signed to meet the de specifications shown ...&
in the test table. after thermal equilibrium o...&
has been established. The circuit is in a
0)
test socket or mounted on a printed circuit
board and transverse air flow greater than
00
500 linear fpm is maintained. Outputs are 0-
o

-
terminated through a 50-ohm resistor to :l
-2.0 volts. Test procedures are shown for ~.
only selected inputs and outputs. The :l
L SUFFIX c:
other inputs and outputs are tested in the ct>
same manner. CERAMIC PACKAGE c.
CASE 620

I-~L../

TEST VOLTAGE VALUES

(Volts)
@Test
Temperature VIHmax VILmin VIHAmin VILAmax VEE
-30oe -1.890 -1.890 -1.205 -1.S00 -5.2
<rl
.... +2SoC -1.810 -1.850 -1.105 -1.475 -5.2
(71
+8SoC -0.700 -1.825 -1.035 -1.440 ·5.2
(71 MC10168L Test Limits TEST VOLTAGE APPLIED TO PINS
Pin
_30°C +2SoC +8SoC LISTED BELOW: IVeel
Unci.,

,
Characteristic ISymbol Test Min M •• Min Typ Ma. Min , Max Unit I VIHmax IVILmin IVIHAminlVILAmax VEE Gnd

Power Supply Drain Current I IE 8 60 75 mAdc 8 1,16

I nput Current I 3,7,9,14 245 ~Adc

+ l'f
linH
4,5,IQ12 265
13 290 13
linl 0.5 j.l.Adc 8 1.16
logic "'" Output Voltage VOH 2 1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 3.13 8 1,16
6 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 7,13 8 1.16
Logic "0" Output Voltage VOL 2 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 3.5 8 1.16
6 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 4.7 8 1,16
Logic .. , .. Threshold Voltage VOHA 2 -1.080 -0.980 -0.910 Vdc 13 8 1.16
6 -1.080 -0.980 -0.910 Vdc 13 8 1.16
Logic "0" Threshold Voltage VOLA 2 -1.655 -1.630 -1.595 Vdc 13 8 1,16
6 -1.655 -1.630 -1.595 Vdc 13 8 1,16
SWitching Times
ISO n Loadl
Propagation Delay I '3+2+ 3.0 ns
+1.11 V
I~'; '" ,~,.O. -3.2 V I +2.0 V

8 1,16

~ ~
2.0

!
t5-2+
t13+2+ 4.0 13
Rise Time (20% to 80%) '2+ 2.0 3
Fall Time (20% to 80%) '2_ 2.0

-Individuallv test each input applying VIH or VIL to input under test.
MC10168 (continued)

SWITCHING TIME TEST CIRC.UIT AND WAVEFORMS. 2SoC

VCCI = VCC2
+2.0 "de V out

c~~JLt~~ Coax

Input Pulse
t+ .. t- == 2.0 ± 0.2 ns
(20 to 80%)

50-ohm termination to ground 10-

c.ted in each lCOp. channel input.
PROPAGATION DELAY

Unused outputs connected to

a 50-ohm resistor to ground.

Vee'" -3.2 Vdc r-----' '---;---- +1.11 V

+0.31 V

All input and output cables to the

lCope are equal lengths of 50-ohm t- -
coaxial eable. Wire length should
be < 114 inch from TPin to input
pin and TP out to output pin.

r------""---- + 1 11 V

+0.31 V

Q t+- t-+

',etup i. the minimum time before the positive

transition of the clock pul •• (C) that information
mUlt be pr.ent 8t the data input (Ol.
thold i. the minimum time .tt.r the positive tran-
sition of the clock pul .. (e) that information must
remain unchanged at the data input {Ol. Note that
thold may be 8 negative number.

3·156
 DUAL MECL 10,000 series
BINARY TO l-4-DECODER
(LOW)

MC10171

The Mel0171 is a binary coded 2 line to

dual 4 line decoder with selected outputs low.
With either ~O !lr ~ 1 high, the corresponding
POSITIVE lOGIC selected 4 outputs are high. The common enable
E, when high, forces all outputs high.
All propagation delay ti mes are equal due to
the internal emitter dotting techniques used.
E014
10 ao 3 High impedance 50 k ohm resistors on all inputs
eliminate the need to tie unused inputs to VEE.

11 ao 2

12 ao 1

A 9
13 ao 0

Po - 325 mW typ/pkg (No Load)

3 al 3
tpd = 4.0 nl typ
B 7
4 al 2

E 15 5 al 1

6 al 0
El 2

vee1:::: Pin 1
VCC2 - Pin 16
VEE" Pln8

TRUTH TABLE

ENABLE INPUTS INPUTS OUTPUTS

E EO El A B alO all a12 a13 000 001 002 a03
L. L I. L L L H H H I. H H H
I. I. L L H H L H H H L H H
I. L I. H I. H H L H H H L H
; - ,
L
I.
L.
L
I.
H
H
I.
H
L
H
H
H
H
H
H H
L H
I.
H
H
H
H
L
H
L H L I. L L H H H H H H H
H ~ ~ ~ ~ H H H H H H H H

til - Don't Cere

See Gene,.1 Information section for packaging end rna.Jl(imum [atlngs.

3·157
 ELECTRICAL CHARACTERISTICS
s:o
Each MECL 10.000 series circuit has been
...
designed to meet the de specifications EO
shown in the test table, after thermal equi- ,0 003
...
o
librium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater " 002
...""'"
n-
than 500 linear fpm is maintained. Outputs
are terminated through a 5~ohm resistor to
O
:l
-2.0 volts. Test Procedure, are shown only ~.
'2 00, :l
for selected inputs and outputs. Other
inputs and outputs are tested in a limilar
c:
<D
manner. a.
'3 000
_ . LSUFFIX
. CERAMIC PACKAGE
. . CASE 620

3 013

%
B 7
4 012

, .. ~ I 5 Q 11@ Test ''''"O''~H''"''

(Voltsl

'r'
.....
Temperature
_lOoe VIHma. VILmin VIHAmin VILAm.. VEE
(J'I El 2 6 0'0 +25oe -0.890 -1.890 -1.205 -1.500 -5.2
(XI
+85Ge -0.810 -1.850 -1.105 -1.475 -5.2
-0.700 -1.825 -1.035 -1.440 -5.2

Pin MC10171 L Test Limits TEST VOLTAGE APPLlEO TO PINS LISTED BELOW'
u..- -lOGe +25 oC +85 0 e 1Veel
Charecteristic Symbol Test Min Max Min Typ Max Min Max. Unit V,Hmax VILmin VIHAmin VllAma. VEE Gnd
Power Supply OrainCurrant Ie B - - - 65 77 - - mAde 2.7.9.14.15 - - - 8 1.16
Input Current linH 14 - - - - 220 - - j.lAdc 14 - - - 8 1.16
linl 14 - - 0.5 - - - - jJAdc - 14 - - 8 1,16
Logie "I" VOH 6 -1.1160 0.890 -0.960 -0.810 -0.890 -0.700 Vde 15 - - 8 1,16
Output Voltage 13 -1.060 -0,890 -0.960 - -0.810 -0.890 -0.700 Vde 15 - - - 8 1,16
Logie "0" Output Volt. VOL 13 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vde - 2,7,9,14.15 - - B 1,16
Logie "1" VOHA 6 -1.080 -0.980 - -0.910' Vde - - 15 B 1.16
Threshold Voltage 13 -1.080 - -0.980 - - -0.910 - Vdc - - 15 - 8 1,16
Logie "0" VOLA 6 1.655 -1.630 -1.595 Vde - 2,9.14,15 7 8 1.16
Th,asholdVoltoge 13 - -1.655 - - -1.630 - -1.595 Vde - 2,7.14,15 - 9 8 1.16
Switching Times
(50 n lo.en +0.31 V Pulse In Pulse Out -3.2 V +2.0 V

P,opagotion Dolay t::~~

t7_'3_
,~
13
r r r
, ,
6t t 6t
+ t
, t
4 10

•
1 ns =
-,
2,9, 'j"5 ]7 7~
13
B "1'6

Ri .. Timtl2O% toBO%1 t:+ ~ 'iO Y 'i' 2t Y 'i' i 34 = = ~3

. ,.f.U.ril1ll.(~t080111 ',3. 1)..t t t t , "t . t ., - - 13 .
 EL£CTRtCAL E:HARACTERfSTtcS
3:
Each MEeL 10.000 series circuit has been
.designed to meet the de specifications EO 14
shown in the test table, after thermal equi- 10 003
o...
o...
librium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
11 002
~
...
0-
are terminated through a 50-ohm resistor to o
::J
- 2.0 volts. Test procedures are shown for 12 001 ~,
only selected inputs and outputs. Other ::J

-
inputs and outputs are tested in a similar c:
II>
manner. Q.
13 000
PSUFFIX
PLASTIC PACKAGE
CASE 648

3 013

B 7

Qg:
4 012

• "~ I 5 all ,.. Toot ""~'~""'B IVaI.. I

...
<;ol
U1 E1 2
Temp.rnure

6 0 10
_30Ge
+2S<>C
VIHma.
-0.890
VILmin
-1.890
V'HAmi"
-1.205
VILAma.
1.500
VEE
-5.2
co +15<>C -0.810 -1.850 -1.105 -1.475 -5.2 '
-0.700 -1.825 -1.035 -1.440 -5.2 I

Pin MCt017tP T . . Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW,

Undo< -30<>C +2S oC +IS<>C IVCCI
CharKt_iltic Symbol Test Min Max Min TVp M.. Min Ma. Unit VIHm8. VILmin VIHAmin VILA..... VEE Gnd
Power Supply Drain Current Ie 8 - - - 65 77 - - mAde: 2,7,9,14,15 - - - 8 1,16
Input Current linH 14 - - - - 220 - - #lAde 14 - - - 8 1,16
linL 14 - - 0.5 - - - - #lAde - 14 - - 8 1,16
Logic "1" VOH 6 -1.060 -0.890 -0.960 -0.110 -0.890 -0.700 Vdc 15 8 1,16
Ouq,..,Voltage 13 -1.060 -0.890 -0.960 - -0.810 -0.190 -0.700 Vdc 15 - - - 8 1,16
Logic "0" Output Valtage VOL 13 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc - 2,7,9,14,15 - - 8 1,16
Logic "I" VOHA 6 -1.080 - -0.980 - - -0.910 - Vdc - - 15 - 8 1,16
Threshold Voltage 13 -1.060 - -0.980 - - -0.910 - Vdc - - 15 - 8 1,16
Logic "0" . VOLA 6 - -1.655 - - -1.630 - -1.595 Vdc - 2,9,14,15 - 7 8 1,16
Threshald Voltage 13 - -1.655 - - -1.630 - -1.595 Vdc - 2,7,14,15 - 9 1 1,16
Switching Times
(SO n Load) +0.31 V Pulse In Pulse Out -3.2 V +2.0 V

:~~~: 1~'5 2'9'1~4'15

Propagation Delay
t7+13+
t7-13-
13
13
::

-
-
::

-
-
4!.0
t
6 .0 ::
-
-
::
-
-
"5 ::

-
]7 :
13
13
8] 1,16

Rise Time (20% to 80%1

Fall Time 120'1(, to 10%1

1&+
t13+
Ifl-
t13-
6
13
6
13
-
-
-
-
-
-
-
-
t
1.1 2,0
J ! - -
3.3 -

-
-
-

-
-
-
-

-
-
-
-

-
-
6
13
6
13
MC10171 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25"c

Vec, - VCC2 V out V out

+2.0 Vdc

Pul .. PROPAGATION DELAY

Gener.tor

Input Pul ••
t+ = t-:::: 2.0± 0.2 ns
(20 to 80%)

L-------T f;.-,:-----' I
Unused outputs connected to
a 50-ohm resistor to ground.

Vee z -3.2 Vdc

All input end outpu t eabl •• to th_

scop ..... equal length. of 5G-ohm
coaxial cabl.. Wlr. length thculd
be < 1/4 inch from TPin to input
pin end TP out to output pin.

3-160
 MECL 10,000 series
DUAL
BINARY TO 1-4-DECODER
(HIGH)

MC10172

The MC10172 is a binary-coded 2 line to

dual 4 line decoder with selected outputs high.
POSITIVE LOGIC With either ~O or El low, the corresponding
selected 4 outputs are low. The common en-
able ~, when high, forces all outputs low.
All propagation delay times are equal. High
10003 impedance 50 k ohm resistors on all inputs
eliminate the need to tie unused inputs to Vee.

11 002

12001

A 9
13 '00.0

301 3 Po - 326 mW typ/pkg (No Load)

B 7
tpd'" 4.0n.typ

401 2

E 16 601 1

6 01 0
E1 2

vee1 - Pin 1
VCC2 '!'" Pin 16
VEE-PinS

TRUTH TABLE
E El EO A B 010 011 012 013 000 001 002 003
L H H L L H L L L H L L L
L H H L H L H L L L H L L
L H H H L L L H L L L H L
L" H H H H L L L H L L L H
L L H L L L L L L H L L L
L H "L L L H L L L L L L L
H 4> 4> .4> 4> L L L L L L L L
-
tP .. 00 nit Care

... G......,lnformetlon Mctlon for ~ck.liiJl"g and" ",..Imum ratlngl.

3-161
 ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
s:
designed to meet the de specifications ....
(')
shown in the test table, after thermal equi-
librium has been established. The circuit is
EOt.
10 ao 3 ....'-I
0
in a test socket or mounted on a printed
N

-
circuit board and transverse air flow greater
than 500 linaar fpm il maintained. Outputs
11 00 2
n-
O
are terminated through a 5O-ohm resistor ::J
to -2.0 volts. Test procadures are shown 12 ao 1
~.
only for selected inputs and outputs. A 9 ::J
Other inputs and outputl are tested in a ao
c:
13 0 <»
similar manner. L SUFFIX c..
CERAMIC PACKAGE
3 01 3
CASE 620

• 7
4 01 2

E 15 5 01 1

o;2~6al0 TEST VOLTAGE VALUES

IVolts'
lilT...
Temperature VIHmax VILmin VIHAmin VILA,...x VEE

-
_lO°e -0.890 -1.890 -1.205 -1.500 -5.2
~ +25"c -0.810 -1.850 -1.105 -1.475 -5.2
( I) +S5"c -0.700 -1.825 -1.035 1.440 -5.2
I\J

-
MC10172L T . . Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
U_ -30"c +25"c +B5"c IVee'
CMrllCteriltic SV- T.. Min Min TVp M... Min Mo. Unit VIHm.x VILmin VIHAmin VILAmex VEE Gnd
POwtr Supply Drain Current IE 8 62 77 - - mAde - - 8 1,16
Input Currant linH 14 - - - 220 - - .Ade 14 - - - 8 1.16
linL 14 - - 0.5 - - - - ",Adc - 14 - - 8 1.16
Logic "1" VOH 6 -1.060 -0.890 -0.960 0.810 -0.890 -0.700 Vdc 2 8 1,16
Outpu,Vol_ 13 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 14 - - - 8 1.16
Logic "0" Outpu, VoI_ VOL 13 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 15 2,7,9,14 - - 8 1,16
Logic "1" VOHA 6 -1.060 -0.980 - - -0.910 - Vde - - 2 - 8 1,16
Th ..... oIdVoI_ 13 -1.060 - -0.980 - - -0.910 - Vde - - 14 - 8 1,16
Logic "0"' VOLA 6 -1.655 -1.630 -1.595 Vdc 2.9,14 7 8 1,16
Th ..... oId Voltogo 13 - -1.655 - - -1.630 - -1.595 Vde - 2,7.14 - 9 8 1,16
Switching Times
ISO 0 Lood. +1.11 V +0.31 V Pulse In Pulse Out -3.2 V +2.0 V
Prop8ption DellIY '7+6- 6 1.5 6.2 1.5 4.0 6.0 1.5 6.4 ns 2 9,14 7 6 8 1,15

,,! ~ ~ ~
,,
t7-6+ 9,14

~
6 2

~
6
t7+13- 13 14 2,9 13
+
j
13 14 2,9
'7-13+
'6+ 6 1.0 + 3.3 1.1 2.0 3.3 1.1 3.4 2 9,14
13
6

~
RiM Time (20% to 8ea) 14 2,9

~
t13+ 13 13
'6- 6 2 9.14 6
Foil Time 120% 10_1 '13- 13 14 2,9 13
 , EUemfOAL CHARACTERISTICS
:;:
Each MECL 10,000 serias circuit has been
d.igned to meet the de specifications
n.....
shown in the test table, after thermal equi- E014
ao
o.....
librium has been established. The circuit is 10 3
in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear 'pm is maintained. Outputs
11 aD 2
"
N
c;-

-
O
are terminated through a 50-ohm resistor
to -2.0 volts. Test procedures are shown
only for selected inputs and outputs.
12 ao 1 ...5'
::J

A 9
Other inputs and outputs are tested in a c:
13 ao 0 (!)
similar manner. a.

J Q1 3
P SUFFIX
• 7 PLASTIC PACKAGE
CASE 648

E 15 5 Q1 1

601 0
e; :z
TEST VOLTAGE VALUES
(Volts)
@T...
4'
.... Temperature VIHmax I VILmin I VIHAmin VILAma • VEE
0) _lOGe -0.890 -1.890 -1.205 -1.500 -5.2
W
+25"<: -0.810 I -1.850 I -1105 -1.475 -5.2
+85"<: -0.700 I -1.825 I -1.035 -1.440 -5.2

TEST VOLTAGE API'LIED TO PINS LISTED BELOW,

IVee l
CNract_iltic VII·'ma. VEE Gnd
Power Supply Drain Current IE 8 I I 62 77 mAde 8 1,16
Input Current linH 14 220 .Ade 14 8 1.16
linL 14 - - 0.5 .Ado 14 8 1,16
Logic "1" VOH 6 -1.060 0.890 -0.960 -0.810 -0.700 Vdc 2 8 1.16
OulpU.Vol_ 13 -1.060 -0.890 -0.960 -0.810 -0.700 Vdo 14 8 1,16
Logic: "0" OuIPu, VoI_ I VOL 13 -1.890 -1.675 -1.850 -1.650 -1.615 Vdc 15 2.7,9,14 8 1,16
Logic: "1" I VOH!. 6 -1.080 - -0.980 Vde 2 8 1.16
Threshold Vohage 13 -1.080 - -0.980 Vdo 14 8 1,16
LOQic "0" I VOLA 6 - -1.655 -1.595 Vde 2,9,14 8 1,16
Throohold Vol.age 13 - -1.655 -1.595 Vde 2,7,14 8 1.16
Switching Times
150 n Loadl +1.11 V +0.31 V Pulse In Pul.Out -3.2 V +2.0 V
Propegetion OeIay '7<i1- 6 1.5 4.0 6.0 9,14 6 8 1,16

~ ~
t7~+

!
6 9,14 6
t7+13- 13 14 2,9 13
'7-13+ 13 14 2,9 13
ts+ 6 1.1 2.0 3.3 2 9,14 6

~ ~
t13+

~
Rise Time (20% to 80%) 13 14 2,9 13
ts- 6 2 9,14 6
Fall TIme C20% to 80%) '13- 13 14 2,9 13
MC10172 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 26"c

vee1 - VCC2
+2.0Vdc V out

""fl·,,,
r---!l!~-_-,
Input

Pul.
Generator PROPAGATION DELAY

~
+'."V
Vin 60%
+0.31 V
t--
t++

Input Pul ..
t+· t- - 2.0±. 0.2 nl
(20 to 80%1

O.'I'F
I
_
-
L _ _ _ _ _ _ _ _ _ -'I

+1.11 Vdc
or +0.31 Vdc,per
tnt table

VEE - -3 2 Vdc
n J 0.1
I'
F

UnuMd outputs connected to

• 50-ohm r..lltor to ground.

All Input and Qutpu t cable. to the

ICOp. a,. equal langth. of 50-ohm
coax la' cabl.. Wlr. 'ength thould
be < 1/4 Inch from TPin to Input
pin and TP out to output pin.

3-164
 QUAO 2·INPUT MEeL 10,000 series
MUL TIPLEXER/LATCH

MC10173

Advance Information
The MC10173 is a Quad two channel multiplexer with
latch. It incorporates common clock and common data
select inputs. The select input determines which data input
is enabled. A high (H) level enables data inputs 000,
Pl0, 020, and 030 and a low IL) level enables data inputs
DOt, 011, 021, 031. Any change on the data input will
be reflected at the outputs while the clock is low. The
outputs are latched on the positive transition of the clock.
While the clock is in the high state, a change in the infor·
mation present at the data inputs will not affect the out·
put information.

TRUTH TABLE

SELECT CLOCK aOn +l

Po ~ 275 mW tvp/pkg (No Lood)
H L 000
tpd - 2.5 nl tvp
L L 001
tI> H OOn

tP., Don't Cere

POSITIVE LOGIC NEGATIVE LOGIC

I 00 1 00
000 6 000 60

001 5 DOl 50

201 201
0104 0104

011 3 011 3

15 Q2 15 02
020 13 020 13

021 12 021 12

1403 1403
030 11 030 II
,
.(

031 10 031 10

Clock 7 - - - - - - '

Vcc - Pin 16
Vee z Pin 8

8M General Information section for packaging.

3-165
 ELECTRICAL CHARACTERISTICS

-
3:
Each MECL 10,000 series circuit has been
designed to meet the de specifications ...o
o
shown in the test table, after thermal
equilibrium has been established. The
circuit is in a test socket or mounted on a L SUFFIX
........
printed circuit board and transverse air W
CERAMIC PACKAG E
flow greater than 500 linear fpm is CASE 620
c;-
maintained. Outputs are terminated O
through a 5().ohm resistor to -2.0 volts. ....
::J

::J
c:
ro
~l
tEJ,,·
TEST VOLTAGE VALUES Co
(Vohl)
• Toot
Temper.tuN VIH max VIL min VIHAmin VILArnu VEE
-30"1: -0.890 1.890 -1.205 1.500 -5.2
+25"c -0.810 -1.850 -1.105 -1.475 -5.2
CIOC" 1 _ _ _DC -0.700 -1.825 -1.035 -1.440 -5.2

-
Pin MC10173L T_ Limit. VOL TAGE APPLIED TO PINS LISTED BELOW:
-30"1:
Ch • .ctl'risttc
j Symbol
lUnd ..
Test Min I Max Min I
+25"c
Typ M.. Min
+85"c
M.. Unit VIHma I VIL min I VIHA min I VILA mal VEE
(VCCI

Power Supply Drltin Current I 'E I 8 - I - - I 56 I 66 mAde 16

I"put Current
I linH I 5
I I I 295
295
~Adc 16

....ctJOl II Input leakage Cur"'"t linL All 0.5

250
250 l
~Adc
l
i6
Ol logic "'" VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 6.9 16
OutPUt Voltage -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 5 16
logic "0" -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 16
Output Voltage

Logic "'"
VOL

VOHA
-1.890
-1.(110
-1.675 -1.850
-0.980
-1.650 -1.825
-0.910
-1.615 Vdc
Vdc
I 8
8 I 16
16
Thr8lhold Voltega -1.080 -0.980 -0.910 Vdc 16
Logic "0" VOLA -1.655 -1.630 -1.595 Vdc 16
Threshold VoltagIJ -1.655 -1.630 -1.595 Vdc 16
Switching Tun.. 1.11 Vdc +0.31 Vdc Pul.ln Pul_Out -3.2 Vdc +2.0Vck
Propagation Delay
Data Input 16+1+ 0.8 3.7 1.0 3.5 1.1 5.3
I I 6 1 8 16

l l l
6

l l l I I I
'&-1-
t5+1+ 5
'5-1- 5
Clock Input t7-1+ 1.6 1.2 1.6 ~.8 1.4 6.8 5.7
t7_1_ 1.6 1.2 1.6 6.8 1.4 6.8 5.1
Select Input t9+1+ 1.1 6.2 1.3 5.1 1.2 6.1 9

l t l
t9+1-

Setup Time
t9-1+
'9-1- t t t I I I 1
Data Input lsetup 2.0 5.1
Select Input lsetup 3.0 1,9
Hold Time
Data Input thold 2.5 5,1
Select Input thold 1.5 1,9
RiNTime t+ 1.2 4.0 1.5 3.5 1.4 4.0
(20 to 80%1
Fell Time t- 1.2 4.0 1.5 3.5 1.4 4.0
(:!OlO_1".
·VILmin _led touch input pin, one at a time.
 EtEC'TRtCAt: CtlARACTE1llSTteS .

•
Each MECL 10,000 _ieo circuit hao been ~
designed to meet the de opacifications n
..&
_ n in the test table, eft.. thermal
. .uilbrium has been established. The
o
..&
circuit is in a test lOCket or mounted on a
P SUFFIX
.....
Co)
printed circuit board and transverse air
flow greet.. than 500 linear fpm is
maintained. Outputs are terminated
PLASTIC PACKAGE
CASE 648
n-O
::J
through a 51k>hm resistor to ·2.0 volts. ....
:5.
I:

~-.,
(I)
TEST VOLTAGE VALUES C.
(Volte)
o Toot
T.........eture VIH max VILmin VIHAmin ViLA ..... VEE
-3O"c -0.890 -1.890 -1.206 -1.500 ~.2
+25"<: -0.810 -1.850 -1.105 -1.475 ~.2
CIOC.'-- +8&"<: -0.100 -1.825 -1.035 -1.440 ~.2

Ch ....:teriltic
Power SupplV Drain Current
Input Currant
Symbol

'E
linH
Pin
Und.r
Toot Min
-30"<:
Max Min
MCt0173P TIM Limits
+25"<:
Ty. MIX
66
295
295
250
+85"<:
Min Max

.-l
Unit
mAde
VIHmu
VOLTAGE APPLIED TO PINS LISTED BELOW:

-
IVeel

16
16

1
--Cf'en III nput leek. Current linL All 0.5
250
",Adc 16
-...J
Logic "'" VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.100 Vdc 6.9 16
Output Voltage
Logi.c "0"
Output Voltage
VOL
-1.060
-1.890
-1.890
-0.890
-1.675
-1.675
-0.960
-1.850
-.1.850
-0.810
-1.650
-1.650
-0.890
-1.825
-1.825
-0.700
-1.615
-1.615
Vdc
Vdc
Vdc
9
5
I I I 16
16
16
lotte "'" VOHA -1.080 -0.980 -0.910 Vdc
T'h,lIhoid Voltage -1.080 -0.980 -0.910 Vdc
Logic "0" VOLA -1.655 -1.630 -1.595 Vdc
Threshold Voltage -1.655 -1.630 -1.595 Vdc
Switchl", TI ..... +1.11 Vdc
Pro~tion Oetev
Oat. Input 16+1+ 2.5 16

!
'6'1-
15+1+
15-1_
Clock Input 17_1+ 4.5 5.1
t7_1_ 4.5 5.1
Select Input 19+1+ 3.5 9
'9+1-
'9-1+

SetUP Tim.
Date Input
'9-1-

ltetup
1
1.5
1
5.1
Select Input lsetup 2.5 1.9
Hold Time
D.t.lnput thold 0.0 5,1
S.lect Input thold -0.5 1.9
Ri.Time t+ 2.0
120 to 80%1
F.II Time t- 2.0
(20 to 80%1
·Vllmin .pplied 10 each input pin, one III II time.
MC10173 (continued)

SWITCHING TIMES TEST CIRCUIT

V out

oeta
Input
s.1~tg

TP out
1 00

t+ .. t- '"' 2.0 nl
000' .;----+-I-ooJ
(20% to 80%)
f tOg a•• hown on wav",orml. 001 5 +----+_+<~

201
010" +---++.j...o.J
011 3 -'-----1-+...j...~

02013 .!....--++.+ooJ
021 12 +-----1-+.j...o~

030 11 +---++-,O,J

03110 -'---+--'01

3.2 Vdc
t·

50·ohm termination· -to ground fa·

cated in each ICOpe channel input.
All input and output cabl •• to the
scope ar. equal lengthl of SG-ohm
coaxl., cabl•. Wire length should be
< 1/4 inch from TPin to input pin
and TP out to output pin.

Unu_d outputl ar. connected to

50-ohm r.,lltor to ground.

3·168
MC10173 (continued)
,I
L

WAVEFORMS.26"C

DATA TO OUTPUT WITH CLOCK AT VIL

CLOCK TO OUTPUT

OATA

f tog - 1.0 MHz

J

OUTPUT

o ."~)-t:'~O~I-d----------~~~~: ~
, 50%
c-------I-------- +0.31 V

NOTE:
t . . up I, the minimum time !Mfor. the pollttv.
tranlltlon of the clock put.. le) ttaM Info,,.,...tion mu.
be pr_nt at the Input (D) or (~).
. thold I, the mlnl~um time aft. the posltlv. tran-
IItJon of the clock put. (e) thet Inform8tion mu.
ramain unchllnged at the det.lnput (D) or (S),

i-
t

3-169
 MECL 10,000 series
DUAL 4 TO 1 MULTIPLEXER

MC10174

The MC10174 is a high speed dual channe~

multiplexer with output enable capability. The:
select inputs determine one of four active data
inputs for each multiplexer. An output enable
forces both outputs low when in the high state~
Po = 305 mW .yp/pkg (No Load)
tpd == 3.5 nltyp (Data to output)
The enable is also useful in wire·DRing several,
multiplexers to achieve additional channel caps-<
bility. Delay from data input to output is typi~
cally 3.5 nanoseconds.

xo 3

X1 5

X2 4 2 Z

X3 6

A 7

B 9

e;;;bi; 14

VO 13

V111
15 W

V212

V310

TRUTH TABLE

VCC1 = Pin 1 ENABLE ADDRESS INPUTS OUTPUTS

VCC2 "" Pin 16 E B A Z W
VEE""Pin8
H L L
L
L
'"
L
L
'"
.L
H
XO
X1
YO
Y1
L H L X2 Y2
L H H X3 Y3
4J - Don't Cere

s •• General Information section for peck aging.

3·170
 :r. >~ _ _ ,_,' __ 4 ____ " ~_ •. ~A""_" .,,~ ... ~ '," t\ .. :.~. ,":'

ELECTRICAL CHARACTERISTICS 3:
Each MECL 10,000 series circuit has been n
~
designed to meet thedcspecifications shown xo 30 ~

in the test table, after thermal equilibrium o

~
has been established in an ambient temper- X, 50 II ~ .....
ature of 25°C, while the circuit is in a test ~
2 Z
socket or mounted on a printed circuit X2 40 III~
board and transverse air flow greater than 8
500 linear fpm is maintained. Outputs are I I I l""'i ....
:::I

-
X3 60
terminated through a 50-ohm resistor to :::I
-2.0 volts. Test procedures are shown for c:
onlv one input, or for one set of input con- A 7 CD
Co
ditions. Other inputs tested in the same
manner. • 9

L SUFFIX
~'40 IIII
CERAMIC PACKAGE
CASE 620
VO'30 Illl~

'''':
Y212
~'" @lTest
,=w,,~""""
(Voltsl

Temp... 'u,. VIH max VIL m;n VIHA m;n VILA max VEE
V3'O -3o"C -0.890 -1.890 -1.205 -1.500 -5.2
+25o C -0.810 -1,850 -1.105 -1.475 -5.2

-
4J
.....
eharact.istic SVmbol
Ur;:;.

Test Min
-lOoe

Mu: Min
Mel0174L Test limits
+25oe

Typ Max Min

+8So C

Max
+8SoC

Unit
-0.700

VIH max
-1.825

Vll min
-1.035

VIHA min
-1.440

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

VILA max
-5.2

VeE
(Vee l

Gnd
Power Supply Drain Current IE 8 - - - 58 73 - - mAdc - - 8 1.16
Input Current ImH 4 220 !JAdc 4 - 8 1,16
14 - - - - 330 - - 14 - - - 8 1.16
1m L 4 - - 0.5 - - - - JJAdc - 4 - - 8 1,16
LogiC "'" VOH 15 -1.060 -0.890 -0.960 - -0.810 -0.890 -0700 Vdc 13 - - - 8 1,16
Output Voltage
Logic "0" VOL 15 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 14 - - - 8 1,16
Output Voltage
Logic "1" VOHA 15 -1.080 - -0.980 - - -0.910 - Vdc - - 13 - 8 1,16
Threshold Voltage
logic "0" VOLA 15 - -1.655 - - -1.630 -1.595 Vdc - - 14 - 8 1,16
Threshold Voltage
Switching Times +1.11 V Pulse In Pulse Out -3.2 V +2.0 V
(50 n Load)

.,opaga"on O.'ay ::;~,';~:~ :: :: :; ;~ :~ :: :: n, = = :; '5 j8 l'j'6

!
t7+15_ 15 1.9 6.4 2.0 5.0 6.0 2.1 6.4 11 - 7
'7_15+
'14+15-
'14-15+
15
15
15
1.9
1.0
6.4
3.1
3.1
2.0
1.0
1.0
5.0
2.0
2.0
6.0
2.9
2.9
2.1
0.9
0.9
6.4
3.2
3.2
11

1
13
-

-
-
7
14
14
j
Rise TIme t+'5 3.4 1.1 2.0 3.3 1.1 3.6 - 14
(20% '0 80%)
Fall Time t- 15 3.4 1.1 2.0 3.3 1.1 3.6 - 14
(20% to 80%)
MC10174 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 26°C

Input

Input Pulse
t+ = t- = 2.0 1.
0.2 ns
(20 to 80%1

50-ohm t .... min.tion to ground lo-

cated in each scope channal input.
I
L----Fi---J
All input and output cabl.s to the
scope are equal lengths of 50-ohm
1:t 0.1 I'F

coaKia' cable. Wire length should

be < 1/4 inch from TPin to input VEE:::;: -3.2 Vdc
pin and TP out to output pin.

Unu.d output connected to a

5O-ohm resistor to ground.

PROPAGATION DELAY

Vout

Vout

3-172
 QUINT LATCH '\ MECL 10,000 series
MC10175 ' - - - - -_ _- - - - - l

The MC10175 is a high speed, low power quint latch.
It filatures five D type latches with common reset and a
eon,mon two-input clock. Data is transferred on the nega-
:tive edge of the clock and latched on the positive edge.
,The two clock inputs are "OR"ed together. Propagation
".ys are typically 2,5 nanoseconds from each data input
11) the output.
Any change on the data input will be reflected at the
.outputs while the clock is low. The outputs are latched
on the positive transition of the clock. While the clock
IS In the high state, a change in the information present
at the data inputs will not affect the output information.
The reset input is enabled only when the clock is in the
high state.
The MC10175 allows storage of five bits of information,
and ~t is useful in temporary storage applications in high
speed central proCessors, accumulators, register files, digital
communication systems, instrumentation, and test equip·
ment.

POSITIVE LOGIC NEGATIVE LOGIC

001o-------------~~ 1400 OOIOI---------------i

01 12'----------i-lf--l 1501 01 12'---------~_I~ 15 01

02 13---------~_I~ 2 02 0213-----------+-~~ 2 02

03 9-----------+-i~ 3 03 03 3 03

04 5,----------i-lf--l 4 04 04 5----------~_I~ 4 01
Co6 CO 6
Ci 7 CI 7
R.Mt11 ___________~~--~ A.Hetl' ___________~~---J

"~------------------------------------------------------------~
TRUTH TABLE
vee1 '" Pin 1
0 CO Cl Reset a n+l VCC2 "" Pin 16
L L L L L VEe" Pin 8
H L L L H
X H X L On

:.! ...
X X H L On Po:c: 400 mW typ/pkg (No Load)
X H X H L tpd c 2.6 ns tvp (Oete to Output)
X X H H L

..... General Information section for packaging and maximum ratings.

3-173
 ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
"
00
:is:
designed to meet the de specifications o....
shown in the test table. after thermal equi-
librium has been established. The circuit is o
....
in a test socket or mounted on a printed ~; I I I " .....

-
0'
circuit board and transverse air flow greater C1I
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor L SUFFIX
n-
O
to -2.0 volts. Test procedures are shown , CERAMIC PACKAGE :J
~,
onlv for selected inputs and outputs. 0' CASE 620 :J
Other inputs and outputs are tested in a c:
similar manner. <1>
.e:
~3 I I I 3
03

~.
R TEST VOLTAGE VALUES
CVOItI)
(IT"t
04 5 a1 Temperatur. VIH m •• VILmin VIHAmin VILA.,... VEE
co 6 C _30 Ge -0.890 -1.890 -1.205 -1.500 -5.2
Cl 7 FI
ReYll11
+25"c -0.810 -1.850 -1.105 -1.475 -5.2
+85"c -0.700 -1.825 -1.035 -1.440 -5.2
MC10175L Test Limits
Pin VOLTAGE APPLIED TO PINS LISTED BELOW,
Under -lOoe +25"1: L +8SoC
I I 1 1
...
~
'-I
I Ch.rc:teristic
I Power Supply Drain Current
II nput Current
Symbol

'E
Test

6
Min M•• Min Typ
78
M ••
97
290
Min MI. Unit
mAdc
.uAdc
I VIH ma.

6
VIL min I VIHA min I VILA m •• I VEE Gnd
1,16
.". I linH I
7 290 7

Input Leakage Current linL

10
11
All 0.5
290
650 !
j..IAdc
10
11
<D - - 8 1,16
Logic "'" VOH 14 -1.060 -0.890 -0.960 -0.810 -0.8901-0.700 Vdc 10 6 - 8 1,16
Output Voltage 15 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 12 6 - - 8 1,16
Logic "0" VOL 14 -1.890 -1.675 -1.850 -1.650 -1.8251-1.615 Vdc 6,10 - - 8 1,16
Output Voltage 15 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 6,12 - - 8 1,16
Logic "1" VOHA 14 -1.080 -0.980 -0.910 Vdc 6 10 - 8 1,16
Threshold Voltage 15 -1.080 -0.980 -0.910 Vdc 6 12 - 8 1,16
Logic "0" VOLA 14 -1.655 -1.630 -1.595 Vdc 6 - 10 8 1,16
Threshold Voltage 15 -1.655 -1.630 -1.595 Vdc 6 - 12 8 1,16
Switching Times +1.11 Vdc +0.31 Vdc Pul_ln Put. Out -3,2 Vdc +2.0Vdc
Data Input t10+14+ 14 1.0 3.6 1.0 3.5 1.0 3.6 6.7 10 14 8 1,16
3.6

!
3.5 6,7

~ .~
10

~ ! l !
110-14- 3.6
Clock Input t6-14+ 4.7 4.3 4.4 7 10,6
ts-14- 4.7 4.3 4.4 7 10,6

1~~
Reset Input t11+4 - 4 0.9 4.0 1.0 3.9 1.0 4.2 ns 5 6 7,11 8 1,16
t11+14- 14 0.9 4.0 1.0 3.9 1.0 4.2 t 10 6 7,11 8 1,16
Setup Time tsetup 14 2.5 7 6,10 14 8 1,16
Hold Time 14 1.5 7 6,10

l t l
thold
Rise Time (20 to 80%) t+ 14 1.0 1.1 - 6,7 10
3.6
11 35 / 11/ 3.7
Fall Time (20 to 80%) t- 14 1"0 3.6 / / 3.5 1.1 3.7 6,7 10

CD Individually test 88Ch input; IPply VIL min to pin under test.
® Output I.tched ttJ h~ logic Itate prior to test. ,r
.- - ... -- ... ",.".- ._-- --.----- .......! .:, :0· ~~ ,.; .
MC10175 (continued)

SWITCHING TIME TEST CIRCUIT

V out

Coax

Data Input
2
02
TP out

PRF == 1.0 MHz

t+ = t- = 2.0 n$
(20% to 80%)
9
VOL = 0.31 V
VOH=1.11V

4
04 5~-------t-t-1 01
CO 6
Cl 7
Reset 11--+________-+__---" J
----f}~~~F
VEEL~'VdC
50-ohm termination to ground lo-
cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TP in to input pin
and TP out to output pin.

3·175
MC10175 (continued)

VOLTAGE WAVEFORMS

RESET INPUT
CLOCK
--+1.11 V

~--1'-----+0.31 V

50%

tl1+14_+0.31 V
~+1.11V
50%
1'----+0.31 V

CLOCK INPUT
DATA INPUT

+0.31 V

r:==-~=h..j:::.!.::::":'::::- + 1. 11 V

+0.31 V

~---~------+1.11 V
50%
o '-----+0.31 V

~------+1.11 V

C------...J'---------+0.31 V

NOTE:
tsetup i, the minimum time before the positive
transition of the clock pulse (C) that information mUlt
be present at the data Input (0),
thold i, the minimum time after the pOlitive
transition of the clock pulse eel that information mUlt
remain unchanged at the data input (0).

3-176
 HEX "0" MASTER-SLAVE MECL 10,000 series
FLIP-FLOP

MC10176

The MC10176 contains six high-speed, mas-

Po - 460 mW typ/pkg (No Load)
f'ogglo 150 MHz (typ)
ter slave lype "D" flip-flops. Clocking is com-
mon to all six flip-flops. Data is entered into
the master when the clock is low. Master to
slave data transfer takes place on the positive·
going Clock transition. Thus, outputs may
change only on a postive·going Clock transition.
A change in the information present at the data
(D) input will not affect the output informa-
tion any other time due to the master-slave
construction of this device.

2 00

3 01
VCCI - Pin 1
VCC2 - Pin 16
VEE - Pin 8

4 02

13 03
CLOCKED TRUTH TABLE
C D a,,+1
L
HO
,. an
L
14 04 L
HO H H

tP '"' Don't Car.

15 06
• A elock H i, • clock transition
Clock 9 from a low to a high .tate.

's.f ~,..r" Information Mction for peckaging.

3-177
 ELECTRICAL CHARACTERISTICS

-
L SUFFIX ~
Each MECL 10.000 series circuit has been CERAMIC PACKAGE
...
n
designed to meet the de specifications
shown in the test table, after thermal
uilibrium has been established. Th e elf·
CASE 620
...
o
on a
M' -

:tJ '" TEST VOLTAGE VALUES

'-I
en
Q"'- =U-"Q,
flow IVol..1
ined.
-ohm OTm "8
::J
s are Temperatur. V.Hme. V'Lmin VIHAmin ViLA ..... VEE ~.
I the
Itr in·
=U-"Q'
~" -
_lODe -0.890 -1.890 -1.205 -1.500 -5.2
::J
C
l3.
~=U-"~
nner.
+2S o C -0.810 -1.850 -1.105 -1.475 -5.2
C_.9
+85OC -0.700 -1.826 -1.035 -1.440 -5.2

Pin MCl0176l Test limits TEST VOLTAGE APPLIED TO PINS LlSTEO BELOW:
Und. -30D e +25OC +8SoC IIICC I
CharKt.ristic Symbol Tm Min Mo. Min Typ Mo. Min M. . Unit VIHma.x V'Lmin V,HAmin ViLA..... VEE Gnd

Power Supply Drain Current IE 8 88 110 mAde; 8 1.16

Input Current 'inH 220 ~Ade; 5 8 1.16

9 310 9 8 1.16

Input Leakage Current rinL 0.5 #JAde 5 1.16

'fJ
..... 9 0.5 ~Ade; 9 8 1.16
~
CD VOH 2t -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 IIde 8 1.16
Logic "'"
Output Voltage 1St -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 llde; 12 8 1.16

Logic "0" IIOL 2t -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 llde; 8 1.16
Outpu t Voltage 1St -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 llde; 12 8 1.18

Logic "'" IIOHA 2t -1.080 -0.980 -0.910 IIde 8 1.16

Threshold Voltage 1St -1.080 -0.980 -0.910 IIde 12 8 1.16

Logic "0" IIOLA 2t -1.655 -1.630 -1.595 llde; 8 1.16

Threshold Voltage 1St -1.655 -1.630 -1.595 llde; 12 8 1.16
-3.2 +2.0
Switching Times +1.11 Vdc +0.3111de; Pulse In Put .. Out llde; llde;
Clock Input
Pr~tion Delay '9+2+ 1.4 5.9 2 8 1.16
4.6 1.5 4.5 1.5 5.0

II
'9+2- 1.4 4.6 1.5 4.5 1.5 5.0
Rise Tim. C20 to 80%)
FoU Time 120'080%1
'2+
'2-
1.0
1.0
4.1
4.1
1.1
1.1
4.0
4.0
1.1
1.1
4.4
4.4
J j
Setup Time tsetup 2.5 n, 5.9 8 1.18

Hold Time 'hold 1.5 n, 5.9 8 1.16

Toggle Fr_oncy f.og 2 125 150 MHz 8 1.16

-\.... . -. ~ '.' - . -. -. - . -.. ," . . ". . . ~ '-

Ou"",t I~ to be .... _red after. clack pu" h. bean -'ied to C inpUt IpIn91JL ~~~ ~~
IVIC10176 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC

VCCI = VCC2 = Gnd

Coax Coax

' T P out
Pulse Generator

Input Pulse
t+ = t-::: 2.0 ± 0.2 ns
(20 to 80%)

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm Unused outputs arG tied to a 50-
coaxial cable. Wire length should ohm resistor to ground.
be < 1/4 inch from TPin to input
pin and TP out to output pin.

VEE::: -3.2 Vdc

PROPAGATION DELAY

r------""'---- +1.11 V
50%
+0.31 V

o
_---JI
.;;....0

f,etup is the minimum time before the positive

transition of the clock pul •• Ie) that information
mu,t be pr ...nt at the data input (0),
thold is the minimum time after the positive tran-
sition of the clock pulse (e) that information must
ramain unchanged at the data input (0). Note that
thold may be a negative number.

3-179
 .,
: ~.

TRIPLE MECL TO
MECL 10,000 series
NMOS TRANSLATOR

MC10177

Advance In:for:rnation

The MC10171 consists of three MECL to MOS tr.nsI~

tors which convert MECL 10,000 logic levels to NM~
levels. It is designed for use in N·channel memory systernt
• Max Load: 350 pF as a ReadlWrite, Data/Address driver. It may also be usee!
• Po = 1.0 W typ/pkg @ 5.0 MHz as a high fanout (30) MECL to TTL translator, or in oth~
• Operating Rate: 5.0 MHz typo applications requiring the capability to drive high capaci-
(all 3 translators in use simultaneously) tive loads. A separate lead from each of the three translei
tors is brought out of the package. These leads may tMi
• INPUT: MECL 10,000 (differential)
connected to VSS or to an external capacitor (0.01 tci
• OUTPUT: NMOS + 0.5 V VOLmax 0.05/lF to ground). for waveform improvement, and shor.
+ 3.0 V VOHmin' circuit protection. When connection is made to an external
capacitor, VSS line fluctuations due to transient currend
are also reduced. '

'May be raised by increasing VSS.

POSITIVE LOGIC NEGATIVE LOGIC

~
---l(--l-
15
2

-
14

13

12
=t>----l>= -l(-~

4
13

12
~
--i(1

11 11

10 10

Vee - Gnd = Plnl 1,16

VEE - Pin B - -5.2 Vdc i5%
VSS - Pin 9 (+5.0 Vdc or +6.0 Vdc ± 10%)

Thl, I, advance Information and 1P8Clflcetlon••r. subject to chenge without notice.

S.. Gen.rel Inform.tlon IeCtlon of pecke"ln,.

3-180
 · ... ~.- .. ~~ .-.... -._ .... _~._ - ..
.. _..

-
3:
15~;
, ELECTRICAL CHARACTERISTICS
(')
Each MECL 10,000 series circuit has been 14 2 ~
designed to meet the de specifications LSUFFIX
0
shown in the test table. after thermal equi-
CERAMIC PACKAGE
.....
.....
13~~
CASE 620
librium has been established. The circuit is
in a test socket or mounted on a printed .....
circuit board and transverse air flow great- 12 n0
er than 500 linear fpm is maintained. TEST VOL TAGE~URRENT VALUES ::J
In general test procedures are shown for
only one input and one output. The other
,,~:
10
liT...
Temper.tur.
Volts

VIHmax VILmin VIHAmin VILAmo: VEE Vsc Vss lOLl 10LZ 10H
mAdc:t1% ~F

C#
:t5" ~.
::J
C
CD
inputs and outputs are tested in a similar
-30"!: -0.890 -1.890 -1.205 -1.500 -5.2 +5.0 +6.0 +1.0 +20 -15 0.05
a.
manner.
+25oC ~.810 -1.850 -1.105 -1.475 -5.2 +5.0 +6.0 +1.0 +20 -15 0.05
+85"C ~.700 -1.825 -1.035 -1.440 -5.2 +5.0 +6.0 +1.0 +20 -15 0.05
MC10177L T.st Limits
Pin TEST VOL TAGE/CURRENT APPLIEO TO PINS LISTED eELOW,
Under -30"!: +25"c +85"C (Vee 1
Charac: .... istic Symbol Te.. Min Max Min Typ Mo. Min Mo. Unit VIHm.x VILmin VIHAmi. VILAmlik Vee Vsc Vss lOLl 10LZ IOH C# Gnd
Power Supply Drain 'E 96 mAde 8 1.16
Negative '550 88 mAde 8 9 1.16

~ ~
Positive
~
Output Low ISSL 9 88 10.12.14 11.13.15
Output High 44
Input Current
ISSH
linH 10 1.0 ~Adc
11.13.15 10.12,14
10 11 8 9
+
1,16
11

I
11 10

j
12 12 13
~
.....
.....
00
13
14
15
13
14
15
12
15
14
j j j
Input Leakage Current ICBq 11 -1.0 ~Adc 10 8.11 9 1,16

~ ~
13
~
12 a,13

Logic "1" Output Voltage

15
2 3.0 3.0 3.0
+
Vdc
,14
15
8,15
VOH 14 8 9 1.16
4.0 4.0 4.0 Vde 15 14 9 1.16
Logic "0" Output Voltage VOL 0.5 0.5 0.5 Vdc 14 15 1.16
0.6 0.6 0.6 Vdc 14 15 9 1.16
Logic "1" Threshold Voltage VOHA 3.0 3.0 3.0 Vde 14 15 8 9 1.16
4.0 4.0 4.0 Vdc 14 15 8 9 1.16
Logic "0" Threshold Voltage VOLA 0.5 0.5 0.5 Vde 14 15 8 9 1.16
0.6 0.6 0.6 Vd. 14 15 9 1.16
Output Short-Circuit Current ISC 50 -90 -50 -90 -50 -90 mAdc 15 14 9 1.2.16
-l,29V -1.69V Pul.ln Pul.Out -5,2V
Switching Times
(350 pF Load)
t15+2+ 6.0 n. 14 11,13 15 9 3.5.7 1.16

!
t1~2_ 14 15
Propagation Delay t14+2- 15 14
t14-2+ 15 14
Rite Time '2+ 12 14 15
110%'090%1
FaU Time '2_ 12 14 15
110%'090%1
Supply Source Current
1@5.0MHzl
ISS 9 B3 mA 10,12,14 11,13.151 I 8 I- I 9 I - I - I- I 3,5.7 I 1.16

1350 pF Loadl

#See test circuit.

MC10177 (continued)

SWITCHING TIME TEST CIRCUIT

Vee = Gnd Vss =: +6.0 Vdc V out

Coax

:;.oo~--+-----. TP out

CL
350 pF

Input Pulse
t+ = t- = 2.0 ±O.2 ns
(20% to 80%)

PRF:: 5.0 MHz

Duty Cycle"" 50%

~­
50-ohm termination to ground lo-
cated in each scope channel input,
and 50-ohm termination to ground
on each unmonitored input.

All input and output cables to the

scope are equal 'engths of 50-ohm
coaxial cable. Wire length should
.'''J l'
be <1/4 inch from TPin to input VEE:: -5.2 Vdc
pin and TP out to output pin.

SWITCHING WAVEFORMS@ 250C

Switching times afe measured after the device under test

reaches a stabilized temperature (air flow ~ 500 .fpm)

,50%
_______ ....1

t++ t+

90%

10%
Vout::::::::::::::J
V out

3-182
 BINARY COUNTER '\ MECL 10,000 series
MCl0178 '---------------'
Advance InforIDation
The MC10178 is a four-bit counter capable of divide-
by-two, divide-by-four, divide-by-eight or a divide-by-
sixteen function_
Po - 370 mW typ!pkg (No Load)
Clock inputs trigger on the positive going edge of the
ftoggl. 150 MHz (typ)
clock pulse_ Set and Reset inputs override the clock,
allowing asynchronous "set" or "clear"_ Individual Set
and common Reset inputs are provided, as well as com-
TRUTH TABLE plementary outputs for the first and fourth bits_ True
outputs are available at all bits_
INPUTS OUTPUTS
R SO 51 52 53 C1 C2 00 01 02 03
H
L
L
H
L
H
L
H
L
H
4>
4>
4>
4>
L IL
H H J LI L
H H
L L L L L H 4> No Count
L L L L L 4>
.. H No Count

......
L L L L L L L L L
L L L L L H L L L
L L L L L L H L L
L
L
L
L
L
L
L
L
L
L .... H
L
H
L
L
H
L
L
L L L L L
.. H L H L

......
L L L L L L H H L
L L L L L H H H L
L L L L L L L L H
vee1 1
......
L L L L L H L L H = Pin
L L L L L L H L H VCC2:S Pin 16
L L L L L H H L H VEe - Pin 8
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
..
....
L
H
L
L
L
H
H
H
H
H
H
H
L L L L L H H H H
f/) -= Don t Care
Clock transition from VIL to VIH
"VIL JV1H may be applied to Cl or C2 or both
for same effect.

50 00 51 01 52 02 53 03
11 15 7 13 6 4 5 2

5 5 5 5
01 A' 01 A' 01 A' 01 A'
12
Clock 1 C1 0' C1 0' C1 0' C1 a

10
Clock 2 C2 a a a
0 0
R R R R

9
R • •t

14 3
Qij Q3

th.ll Is edvance information on • new introduction and .paciflcatlons .r. subject to change without notice.
a.. Gen.ral Information section for packaging.

3·183
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,000 series circuit has been ....o
(")
designed to meet the de specifications
shown in the test ta~e. after thermal
equilibrium has been established. The cir-
11

7
50
51
00
01
15

13
....
....,
6 52 00
cuit is in a test socket or mounted on a

-
02 4
printed circuit board and transverse air flow 5 53 0-
greater than 500 linear fpm is maintained.
12 Cl
03 2
L SUFFIX o
Outputs are terminated through a 50-ohm ::J
resistor to -2.0 volts. Test procedures are 10 C2 00 14 CERAMIC PACKAGE
CA5E 620
a.
::J
shown for only selected inputs and outputs. 9 A 03 C
(I)
Other inputs and outputs tested in the a.
same manner.

TEST VOLTAGE VALUES

IVolts)
(jITest r - - - r-
T emperatur. VIHmlx VILmin V'HAm;n IvILAmex VEE
-30"c -0.890 -1.890 -1.205 -1.500 -5.2
+25o C -0.810 -1.850 -1.105 -1.475 -5.2
+8S oC -0.700 -1.825 -1.035 -1.440 -5.2
MCl0178L Test Limits TEST VOLTAGE APPLIED TO
Pin
Und...
_3)°C +25o C +85 oe PINS LISTED aELOw: 1Veel

':'l
Characteristic I Symbol I Test Min M•• Min Typ M .. Min Max Unit VIHmllx VILmin VIHAmin VILAmlix VEE Gnd
I Power Supply Drain Current IE l 8 88.5 mAde 9 - - - 8 1.16
I
~

(Xl 1.16
~
Input Current
I 'inH
I 12
11
9
245
220
410
/JAde
j.lAdc
#lAde
12
11
9
-
-
-
-
-
-
8
8
8
1.16
1.16
linL 0.5 /JAde 8 1.16

1 l
-
-
....
-
~

Logic "1" Output Voltage VOH 14 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 8 1.16
9 - -
-0.960 -0.810 -0.890 -0.700 Vdc 8 1.16
15 -1.060 -0.890 11
=
~' I I
Logic "0" Output Voltage VOL 14 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 8 1.16
15 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc - - - 8 1.16
Logic "1" Threshold Voltage VOHA 3 -1.080 -0.980 -0.910 Vdc 5 8 1.16
14 -1.080 -0.980 -0.910 Vdc 11 - 8 1.16
15 -1.080 -0.980 -0.910 Vdc 9 - 8 1.16
Logic "0" Threshold Voltage I VOLA I 3
14
-1.655
-1.655
-1.630
-1.630
-1.595
-1.595
Vdc
Vdc
5
11
1.16
1.16
8
8
15 -1.655 -1.630 -1.595 Vdc 9 1.16 8
Switching Times Pul.ln Pul.Out -3.2 Vdc +2.0 Vdc
Clock Input··
Propagation Delav
I '12+15+ 15
13
3.5
6.0
n. 12 15
13
8 1.16

j !!
'12-13-
4

l
t12+4- 8.5 4
t12-3+ 3 11 3
Rise Time (20 to 80%) t15+ 15 2.5 15
Fall Time (20 to 80%) 'H,. 15 2.5 15
Set Input tll-15+ 15 5.2 11 15 8 1.16
Reset Input t9-15+ 15 5.2 9 15 8 1.16
Counting Frequency fcount 15 150 I MHz 12 16 8 1.16

·Jn~ivtdu,"v test each input applving VIL to input under te.t.

.,
;
rt'C1 0178 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 25°C

veel = VCC2::O:: +2.0 Vdc

V out

Coax Coe.

Pulse Generator

I I
Input Pulse L
t+ = t-= 2.0 ± 0.2 ns
(20 to 80%)

50-ohm termination to ground 10·

cated in each scope channel input. VEE
ti
= -3.2 Vdc
0.1 jtF

Unused outputs are tied to a 50-

~.II input and output cables to the
ohm resistor to ground.
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.

PROPAGATION DELAY

~ _ _ _ _""",,!"""-'-_ _ _ +1.11 V

+0.31 V

t+- t-+

3-185
 LOOK-AHEAD CARRY
BLOCK
~ ___________________M_E_C_L__ 1_0_.0_o_0_._r_ie_s~'r
MC10179

The MC10179 device has 12 low power gatIIS

internally connected to perform the look-ahud
carry function. This device has high Z input
Po - 300 mW typ/pkg (No Lood)
pulldown resistors and open emitter ouUlU.1L,
fpd - 3.0 nl typ (Corry, Propogoto) This device has applications in fast look-ahead:
4.0 nl tVP (Oener8t11) adders such as with the MC10181: It can b.-
used also as a boolean function generator.

POSITIVE LOGIC

G3 6

P3 13

G2 9 J
'----"
3 C n +4

P2 12
.-
.-J
~
~>---L ---
en 11
..... ~ >-
1

---
G1 7

P1 10
)
Ir 6 C n+2

~
GO 4

~
PO 14

PG - PO + P1 + P2 + P3 VCC1 - Pin 1
GG - (GO + P1 + P2 + P3) (G1 + P2 + P3) (G2 + P3) G3 VCC2 = Pin 16
C n +2" (en + PO + P1) (GO + Pl) G1 VeE = Pin 8
C n +4 - (C n + PO + P1 + P2 + P3) (GO + P1 + P2 + P3) (G1 + P2 + P3) (G2 + P3) G3

3-186
 EtEeJ;,UCA1io ~(ll t"IStlC& ~
~MCCL IO,QOO lliri. de.,iQO.habeen n
.....
designed to meet· the de specifications
Shown in the test tab~e. after thermal equi- &-----' o.....
....,
::~
~ibrium has been established. The circuit

-
is in a test socket or mounted on I printed 3 cg
circuit board and transverse air flow greater
than 500 lineaf fpm is maintain$d. O~tputs n-
O
are terminated through a SO-ohm resistor 2 :I
to -2.0 volts. Test procedures are shown LSUFFIX ~.
only for selected input5and outputs. Other :I
CERAMIC PACKAGE c:
inputs and outputs are tested in a similar 11 II i [Tffft "
CASE 620 CD
manner. i~) .16 Q.

1;~6 lilT...
TEST VOL TAGE VALUES
(Volts'

14 Temperature VIHm .. VIL min VIHAmin VILAm.. VEE

-30"1: -0.890 -1.890 -1.205 -1.500 -5.2
+25"C -0.810 -1.850 -1.105 -1.475 -5.2
+85"C -0.700 -1.825 -1.035 -1.440 -5.2

TEST VOLTAGE APPLlEO TO PINS LISTED BELOW,

(Vtc'
Ch_.:twimc Symbol Mox Unit VIH m.. I Vil min I YIHA min I VILA max VEE I Gnd

r
Power Supply Or." Current IE 8 mAde 8 1.16
~
.- Input Current 4.7.11 270 4.7.11

~r
linH
00 5.9 225 5.9
..... 10.13 440 10.13

linL
12
14
4 05
395
355
~Adc
12
14
4
11
8 1.16
Lbgic: "I" Output VOI_ VOH 2 -1.060 -0.890 -0.960 ~ -0.810 -0.890 1 -0.700 Vde 4.5.7.9 8 1.16
Logic: "0" Outpu. VoI_ V 3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 1.16
2 - - - 13 -

1
1.080 -0.980 -0.910 5 8 1.16

T
Loge "'" VOHA
Threshold Voltage 2 - - - 5.12 9 -
2 - - - 5.9 12 -

Logic "0"
Threshold VoIUge
VOLA
2
2
2
2
+ -
-1.655
+
-
-
-
-
-
-
-
-
-
-
-1.630
• I-If T
-
-
-
-
5
13

5
5
13 -
5
13
9
• •
8 1.16

• • • •
2 5.9 12
+1.11 V Pul_ln PV_OU, -3.2 V +2.0 V
Swi1iChi"l Tim.
l60nLood' t5+3+ 4.7.9 5 3 8 1.16
3 1.0 5.5
Prop-a-tion Oat8y t5-3- 3 4.7.9 5 3
t11+6+ 6 4.7 11 6
tl1-6- 6 4.7 11 6
15+2+ 2 4.7.9 5 2
'1>-2_ 2 4.7.9 5 2
t10+6+ 6 4.7 10 6
'1D-6-
t10+15+
6
15
t
3.5
4.7
12.13.14
10
10
6
15
'lD-ll>- 15 12.13.14 10 15
Rise Time f2O" to· 80%)
FaU Time 120" to 80%)
'6+
'6_
6
6
1.1
1.1 ~ 4.7
4.7
11
11
6
6
 ELECTRICAL CHARACTERISTICS
s:
Each MECL 10;000 series device has been
daignBd to meet the de specifications
shown in the test table, after thermal &qui·
librium has been established. The circuit
n...
o...
is in a test socket or mounted on a printed 6 i ......
circuit board and transverse air flow greater (C

::~
--
than 500 linearfpm is maintained. Outputs 3
. , terminated through • 5O-ohm resistor 8
to -2.0 volts. Test procedures are shown
only for.lected inputsond outputs. Other 2
'SUFFIX
...:;'
::J

inputs and outputs are tested in 8 similar I:

manner. PLASTIC PACKAGE (II
11 1I1FTff"' ./ CASElla Co
I Lff:!;:::I::j$ ") 15

~.
7 TEST VOLTAGE VALUES
IVoIa)
10
4' o Toot
T."..per"ur. VIHma VILmin VIHAmin VILA mu. VEE
14 -3o"c -0.890 -1.890 -1.205 -1.500 -5.2
+25"c -0.810 -1.850 -1.105 -1.075 -5.2
+85"c -0.700 -1.825 -1.035 -1.440 -5.2
Mel0179P Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
U_. -3O"c +25"c +85"c IVee l
Ch...n.tic Sy_ T... Min M.. Min Min Mu Unit VIH mIX Vil min VIHAmin VILAmu VEE Gnd

II
T
58 i l72
l - - - - 8 1,16
CfJ
.....
Power Supply Drain Current IE 8 mAde
Input Curr,nt linH 4.7,11 270 .Ade 4,7,11 8 1,16
~ - - -

! ! !
5.9 225 5,9
10.13 440 10,13 - - -
12 395 12 - - -
~ 355 14 - -
linL 4 05 ",Adc - 4 - - 8 1,16
Logic ''1'' Output Volt. VOH -Ul60 -0.890 -0.960 - -0,810 -0.890 T-0.700 Vdc 4,5,7.9 8 1,16
Logic "0" Output Volt. V -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vde - - - - 8 1,16
Logic "1" VOHA -1.080 - -0.980 - - -0.910 Vde 13 - 5 - 8 1,16
Threshold Voltage - - - 5.12 - 9 -
- - - 5,9 - 12 -

Logic "0" I VOLA

+ -
-1.655
+
-
-
-
-
-1.630
+
- -1.595
+
Vde
5
13
-
-
13
-
-
5
+
8
+
1,16
Threshold V~tege - - - 5 - - 13
- - - 5 - - 9
+ - - + -
+ + ~
5,9 - -
Pulse In
12
Pul.Out
+
-32V
+
+2.0 V
Switching Tim.
1500 Loodl
15+3+ 3 1.0 - 5.5 ns I 4,7,9 - 5 3 8 1,16
Propagation Delay 15-3_ 3 - 4,7,9 - 5 3
t11+6+ 6 - 4,7 - 11 6

j -
1'1_6- 6 - 4,7 11 6
15+2+ 2 - 4,7;~ - 5 2
15-2_ - 4,7,9 - 5 2

j
2
110+6+ 6 - 4,7 - 10 6
t1()"6- 6
- 4,7 - 10 6
110+15+ 15 - 12,13.14 - 10 15
3.5
'1a-l!>- 15 - 12,13,14 - 10 15

~
-
, Rn. Time 120.'''0 80%1 '6+ 6 1.1 4,7 - 11 6
Foil T .... t~·tq 80%1 .... 6 1.1
-
- 4,7 - 11 6
MC10179 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25"c

vee1 = VCC2::= +2.0 Vdc

!
V out

""t i"'"
r----- ------, Coax

G3 51 I
P3 131 13
G2 91
50-ohm termination to ground lo- P2 121
cated in each scope channel input. C n 111
Pulse Gl 71
Generator
PI 101
GO 41
Input Pulse
PO 141
t+ "" t- '" 2.0 ± 0.2 ns
1 I
(20 to 80%)

PROPAGATION DELAY
L-----ti~,~,J
VEE = -3.2 Vdc

All input and output cables to the

V out scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.

When used with the MC10181, the MC10179 performs

t APPLICATION INFORMATION a second order or higher look-ahead. Figure 2 shows a 16·

, The MC10179 is a high speed, low power, standard
:WlECL complex function that is designed to perform the
lobk-ahead carry function. This device can be used with
:1he MC10181 4-bit ALU directly, or with the MC10180
~ual arithmetic unit in any computer, instrumentation or
'digital communication application requiring high speed
arithmetic operation on long words.
bit look·ahead carry arithmetic unit. Second order carry
is valuable for longer binary words. As an example, addi-
tion of two 32-bit words is imprOVed from 30 nanoseconds
with ripple-carry techniques, to 18 nanoseconds with carry
look-ahead techniques. A block diagram of a 32-bit ALU
is shown in Figure 1. The MC10179 may also be used in
many other applications. It can, for example, reduce sys-
tem package count when used to generate functions of
several variables.

FIGURE 1 - 32·BIT ALU WITH CARRY LOOK·AHEAD

3-189
 3:
...o
(')

........
(D

.. AI'
8:::l
AI
Bl
A2
B2
B5
A6

. A9
.,.
AI. B"
A"
Bl.
AI.
e.
:::l

if
c:

yi r~9' A/f
8fS <D
Q.

A080 A1 81A,282A383
If iii 1'r+.
AD 80 Al 81A282A313 LJ B. AI . , A2 B2 J3enJ3 I
AD 80 .,8'A282 A3 83
I
+. f-o
Cin C. en + .. en en f-o en + • en en
.'-r--"so MelDl81
M
MelDl.'
-M
MelQl8' G_
;--M
MelDl81
Gr-- ;--5. Gf-- r--- 5• -5. Gf--
.-BIT ARITHMETIC .·BIT ARITHMETIC .-BIT ARITHMETIC ".BIT ARITHMETIC
, . - - 51 _51 _51 ~51
LOGIC UNIT
LOGIC UNIT LOGIC UNIT LOGIC UNIT
r- 52 • ; - - 52
• r- 52
53
• -52
53
r-
53 •3 F.
F F1 F2 F3 Fl F2 F3 F. Fl F2 F3 F. Fl F2 F3

M
5.
51
ct>
..... 52
53
8
F. Fl F2 F3 F. F' F6 F7 F. F. FlO Fl' F12 F13 Fl. Fl'

PO GO
II G3
" Gl P2 G2 '3

G--o
MC10178
C. CARRY LOOKAHEAD
.--0
en + 2 en + 4

bCl.

.. ..: ,~.v: ~j,.~ ~ _ '._" .~.,. ".".J. "'""'Rit ... _T Riu.. LOOK-AHIADCARR~~!'...~m."~WJ.L .
 DUAL 2-BIT MECL 10,000 series
ADDER/SUBTRACTOR

MC10180

The MC 10180 is a high speed, low power general-pu r-

pose adder/subtractor. It is designed to be used in special
purpose adders/subtractors or in high speed multiplier
arrays. The MC10180 can be used in any piece of equip-
ment where these operations are necessary.
Inputs for each adder are Carry-in, operand A, and
Po ~ 360 mW typ/pkg (No Load)
operand B; outputs are Sum, Sum, and Carry-out. The
tpd (typ)
common Select inputs serve as'a control line to invert A
Cin to Cout - 2.2 "' for subtract, and a control line to invert B. The speed
AO to SO - 4.6 n'
AG to C out - 4.6 n. is very fast, with Carry-in to Carry-out propagation delay
of 2.2 ns and Operand in to Sum or Carry-out propagation
delay of 4.5 ns.

POSITIVE LOGIC NEGATIVE LOGIC

FUNCTION SELECT TABLE

Vec" Pin 10
\lEe" Pina
SeI,4 Sela Function
S" A pl",l.
I" A mlnu,'
S " . minul A

"••
'2 t3
..
'2
S .. 0 min .... A min .. , •

POlIti". Lotlc Only

/lit' .. A (i) SII" .. A 0 SelA s= f,n lA' 8' + A' j') + Cln IA'" t,,> j'l
C gut - Cln A,' + Cln e' t A' 8'
e' .. B@Se1e-,elf)Stl.

POSTIVE LOGIC DIAGRAM - 1/201 Circuit Shown

TRUTH TABLE

...
!'UNCTION
u. '., "",m
: "
. ''" " . OUTPUTS
0..,

.-. " :" "

"
.
" " "
"
lutTII"'CT " "

.-.0----++-----+--1
c,"
:"
:
"
. ~

" " " "

.IV'"1t
IUITIIACT
.: ..
~

. .:
" "
" " " : ~

.... G ......llnformatlen .alon for pedlealngend .".xlmum ratlng.inform.h)n.

3-191
 -
ELECTRICAL CHARACTERISTICS
SelA I.
s:
0
Each MECL 10,000 series has been de-
signed to meet the de specifications shown Sela -"
in the test table. after thermal equilibrium AO ' , 0
8O -"
has been established. The circuit is in a L SUFFIX CO
test socket or mounted on a printed circuit Cin
CERAMIC PACKAGE 0
board and transverse air flow greater than CASE 620
500 linear 'pm is maintained. Outputs are n
0
terminated through a 50-ohm resistor to ::s
....
-2.0 volts. La. SalA Sl~14
TEST VOLTAGE VALUES 5°
~
I c:
Sela SI-I
Volts

..
It CD
CHest C.
10 81
Temperature VIH max VIL min VIHAmin VILA max VEE
12 Cin
C out - 1 3
-300 e -0.890 -1.890 1.205 1.500 5.2
+25"c -0.810 -1.850 -1.105 -1.475 -5.2
+8S DC -0.700 1.825 -1.035 -1.440 -5.2
MCl0180 L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Under -30"c +2SoC +B5"c
(Vee l
Characteristic I Symbol I Test Min Max Min Typ M •• Min M •• Unit VIH max VIL min VIHAmin VILA max VEE Gnd
Power Supply Drain Current I IE I 70 86 mAde 8 16
I"put Current I linH I 4
5
370
220
jJ.Adc 4
5
8 16

6 220 6
7 290 7
C:'
.....l 9 290 9

CD
(I,.)
10
11
220
220
j 10
11
j
12 370 12
'inL All 0.5 jJ.Adc 8 16
Logic "1" VOH 2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 7,9 8 16
Output Voltage 3 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 4,5,7,9

•
15 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 4,7,9
Logic "0"
Output Voltage
VOL 2
3
15
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.650
-1.650
-1.650
-1.825
-1.825
-1.825
-1.615
-1.615
-1.615
•~
Vdc 5,7,9
7,9
7,9
•
8 16

Logic "1"
Threshold Voltage
VOHA 2
3
-1.060
-1.080
-0.980
-0.980
-0.910
-0.910
Vdc 7,9
4,7,9 5
4
•
8 •I
16

15 -1.080 -0.980 -0.910 7,9 4

Logic "0" VOLA 2 -1.655 -1.630 -1.595
•
Vdc 7,9 4
•
8 16

~
Threshold Voltage 3 -1.655 -1.630 -1.595 7,9 4

•
15 -1.655 -1.630 -1.595 4,7,9
Switching Times
Propagation Delay
+1.11 V Pulse In Pulse Out -3.2 V +2.0 V
•
Operand Input t5+15+ 15
15
1.3 5.8
5.8
1.3 5.4
5.4
1.1
1.1
5.8
5.8
n. 7,9
7,9
15
15
16
t6+15+ 1.3 1.3
Carry·m Input '4+15+ 15 1.0 3.4 1.0 3.3 0.9 3.6 7,9 4 15
14+3+ 3 1.0 3.4 1.0 3.3 0.9 3.6 5.7,9 4 3
Select Input t7+15+ 15 1.3 5.8 1.3 5.4 1.1 5.8 4,9 7 15

!
t9+15+ 15 1.3 5.8 1.3 5.4 1.1 5.8 7.4 9
Ai_Time t15+ 15 1.0 3.8 1.1 3.7 1.1 3.9 7,9 5
(20'080%1
Fall Time '15_ 16 1.0 3.8 1.1 3.7 1.1 3.9 7,9 5

'Indlvll\lolly~IL mlft ...."'.. u - _.' ... ~- -,_._". -....,_..- :..- ~:j~. ...- ".~ .. ~." ~ . . .. ---.. ~.- .... _.. ,
 ELECTRICAL CHARACTERISTICS 3:
Each MECL 10,000 series has been de· SoIA 1.
...
n
signed to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a
Sela
AO
.0 , . .W,," ...
0
00
test socket or mounted on a printed circuit tin PLASTIC PACKAGe 0
board and transverse air flow greater than CASe 648
500 linear fpm is maintained. Outputs are
0-
0
terminated through a 50-ohm resistor to
-2.0 volts. L.. SelA S1~'4
...5'
::J

TEST VOLTAGE VALUES J

~ Sale S'~' c:
Volts ClI
11
10 .,
A1
@Test
Temperature VIH max VIL min VIHAmin VILA mi. VEE
l I .9:
12 . . Cin Cout ~'3
_30 D e -0.890 -1.890 -1.205 -1.500 -5.2
+25 oC -0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2

Pin
MCl0180P Test Limits TEST VOLTAGE APPLIEO TO PINS LISTEO BELOW,
Under -30"1: +250 C +85"1: (Vee l
Ch.rllCteriitic I Symbol I Test Min Mo. Min Typ Max Min Max Unit VIH rna. VIL min VIHAmin VILA max VEE Gnd
Power Supply Drain Current Ie 70 86 mAde 16
Input Current
I 'inH I 4
5
370
220
IJAdc 4
5
8 16

I II
6 220 6
7 290 7
~
....CO 9 290 9
10 220 10
11 220 11
Co)
12 370 12
'inL All 0.5 ",Adc 16
LogiC: "'" VOH 2 -1.060 0.890 0.960 0.810 -0.890 -0.700 Vdc 7,9 8 16
Output Voltage

Logic "0" VOL

3
15
2
-1.060
-1.060
-1.890
-0.890
-0.890
-1.675
-0.960
-0.960
-1.850
-0.810
-0.810
-1.650
-0.890
-0.890
-1.825
-0.700
-0.700
-1.615
t
Vdc
4,5,7,9
4,7,9
5,7,9
t
8
t
16

~ t t
Output Voltage 3 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 7,9
15 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 7,9
Logic: "'" VOHA 2 -1.080 -0.980 -0.910 Vdc 7,9 4 8 16

~ t I
Threshold Voltage 3 -1.080 -0.980 -0.910 4,7,9 5
16 -1.080 -0.980 -0.910 7,9 4
Logic: "0" VOLA 2 -1.655 -1.630 -1.595 Vdc 7,9 4 8 16
Threlhold Voltage 3
15
-1.655
-1.655
-1.630
-1.630
"1.595
-1.595 t 7,9
4,7,9
PuI,.ln
~
-3.2 V
t
+2.0 V
Switching Times +'.'1 V PuI.Out
Propagation Delav
Operand Input '5+15+ 15 1.3 5.4 ns 7,9 5 15 16
'6+15+ 15 1.3 5.4 7,9 6 15
C.ry.m Input '4+15+ 15 1.0 3.3 7,9 4 15
1.4+3+ 3 1.0 3.3 5,7,9 4 3
Select Input 17+15+ 15 1.3 5.4 4,9 7 15

!
19+15+ 15 1.3 5.4 7,4 9
Ri.Time t'5+ 15 1.1 3.7 7,9
1201080%1
Fall T"ime 115- 15 1.1 3.7 7,9

·lndividuaUy apply VIL min to pin under test.

MC10180 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

veel = VCC2"'" +2.0 Vdc V out

Coax
r--'~'j it:-,
I ,
Coal(

7 , SoiA
9, Sole SO
5, .0.0
6, BO
C out
41 Cin

I
TPin
1 ./TP out

I
Pul,. Generator I
11
Input Pul.. 10i------'-!
t+-t;-2.0n •• 0 . 2 n . ' 111
13
(20 to 80") 12/ Cln
50..,hm tormlnotlon to ground
catea in .ach
10'

.~p. channa' input. L.. - - - -

All input and output cabl •• to the
-11-.- __
L -_ _- - '
J
1 UnuMd outputs
connected to •
50· ohm r.,i'tor
to ground.
scope .r. aqua' 'angth. of 50-ohm x_ 0.' ~F
cO•• ia' cabl.. Wlr. length .hould
be < 1/4 inch from TPin to input
pin and TP out to OU1put pin. Vee = -3.2 Vdc

PROPAGATION DELAY

~---,------- +1.11 V

'------+0.31 V

TP out

TP out

3·194
 MECL 10,000 series
4-BIT ARITHMETIC LOGIC
UNIT/FUNCTION GENERATOR

MC10181

The MCIOISI is a high-speed arithmetic logic unit
i:apable of performing 16 logic operations and 16 arith-
metic operations on two four-bit words. Full internal carry
is incorporated for ripple through operation.
Arithmetic logic operations are selected by apply ing the
Bppropriate binary word to the select inputs (SO through
53) as indicated in the tables of arithmetic/logic functions.
Group carry propagate (PG) and carry generate (GG) are
provided to allow fast operations on very long words using
a second order look ahead. The internal carry is enabled by
applying a low level voltage to the mode control input (M).
When used with the MC10179, full-carry look·ahead, as
a second order look ahead block, the MC101Sl provides
high speed arithmetic operations on very long words.

POSITIVE LOGIC NEGATIVE LOGIC

13 13
15 15
17 17
14 14

SO SI S2 S3 S3
21 21
20 Vee1 '" Pin 1 20
Fl 3 VCC2 ::: Pin 24 Fl 3
18 18
VEE - Pin 12
19 19
16 16
F3 6 6
11 11
4 10 4
9 9
Po 8 8
22 22
23 5 23

Po - 600 mW typ/pkg (No Load)

tpel (typ): Al to F - 6.6 n.
C n to C n +4- 3.1 nl
A 1 to Po - 6.0 n.
A 1 to GG - 4.6 nl
Al to C n +4 "" 5.0

POSITIVE LOGIC NEGATIVE LOGIC

Logic Function. ArlthlTWtlc Oper.tion Logic Functions Arithmetic Operation

Function Select M i, Hlth C- D.C. Mi,Low Co I, low Function Select M is High M is Low C n of LSB must be High
S3 S2 51 50 F F S3 52 51 SO F F
L F""A F"Aplu.O P:"A F "A minus'
H F=A+B F "' A plul (A. ill L H F ",ATi F '" A plus (A + iii
H F '" A ... B F '" A plu. IA • BI H L F = A. B F " A plus (A + BI
H H F = Logical " ' " F = A time. 2 H F " LOllical "0" F = A times 2
H L L F=Aei F = IA ... HI plus a H L F ",A";'1j F = (A • BI minus 1
L· H H F = B F = IA ... 8) pi .... (A .81 H H F "8 F = fA • BI olus (A + 81
L·

H
H
H
H
H
F=A
••
F=A+8
F-A'ee
F ;: A plus 8
F • A plus IA + BI
F '" IA ... 81 plus a H
H
H
H
H
F:A(i)B
F '" A.
F=A+H
n
F~Aph.. sH

F - A plus (A .81
F = (A • iiI minus'
H H F = A@ B F ~ A minus B minus 1 H F = A@,)B F = A minus B minus 1
H H F = 8 F = IA + BI plus IA • HI H H F=H F = {A .81 plus (A + Bl
H H H F '" A ... B F '" A plu. IA + iiI H H F"A.B F = (A • BI plus A
H H L L F = Logical "0" F a minus 1 (two'. complement) H F = Logical "1" F = minus 1 (two's complementl
H H H F=Aei F = IA • SJ minus 1 H H H F=A+S F & (A + 81 plus 0
H H H L F"AeH F .. (A • HI minus 1 H H H F"'A+B F = (A + BI plus 0
H H· H H F" A F" A minus 1 H H H F=A F "A plus 0

. . . General Information section for packaging.

3·195
MC10181 (continued)

i·

5313
POSITIVE
5215
LOGIC DIAGRAM
S117

5014

rr:C>
8020)0--
Dt
P f----tL./
~2F o

I-L
~

AO 2 1

~ ,~/
~, .~
Fl

811 90--
Dt W
J

~,
~

All 8

82 llC>--
~
P ~
,~
F2

A2 16~
§P- ~

'~, 6 F3
L...-..; ,~./
83 9C>--
~ "
~~
./

~
A3 10

5 C n +4
22

./
M 23

3·196
MC10181 (continued)

ELECTRICAL CHARACTERISTICS LSUFFIX

E.:h MECL 10,000 series has boon de· CERAMIC PACKAGE
signed to meet the de specifications shown CASE 623
in the test table, after thermal equilibrium
... been established. The circuit is in a PSUFFIX
test lOCket or mounted on 8 printed circuit PLASTIC PACKAGE
board and transverse air flow greater than CASE 649
500 linear fpm is maintained. Outputs are TEST VOLTAGE VALUES
terminated through a 50-ohm resistor to IYoIu)
-2.0 volts. VIHrnp I YtLmln vlHAmln VILArnp VEE
-0.B90 -1.890 -1.205 -1.500 -5.2
-0.810 -1.850 -1.105 -1.475 -5.2
-0.700 -1.825 -1.036 -1.440 -5.2

TEST VOLTAGE APPLIED TO PINS BELOW:

I,
T,. .... M'. .... VILA me", God

I.• I.•
PoMr Su9Ply O,..in Current 12 14S 12 1,24
Input CurNnt 'inH 246 "Ade 12 1,24
220
11 24' 11
200

,.,.
13 13
14
IS

17
266
285
220
286
,.,.
14
15

17
220
2"
"
2. 2.' "
2.
21 220 21
22 290 22

I""", LelkO CUrHnt

I.
2'
9

11
13
•. S
200
pAdc
23

I.•
11
13
12 1,24

14 14

1.
15 15
16
17
18

"
20
21
I.
17
1.

20
21
22 22
2J 23
H~OutpUtYoI . . . VOH -1.060 -O.8SIO -0.980 -0.810 -0.890 -0.700 12 1.24
t.- Output Vol." VOL -2.000 -1.67S -',990 -1.6&0 .1.920 -1.615 Vd, 12 1,24
HWI ThrWIold Voluge YOHA -1.080 -0.980 -0.910 "do 12 1.24
L.ow~Volt8ge VOLA -1.665 -1.630 -1.596 Vdo 12 1,24
-T_ alllnput-outpUt combln-,ions 8CCoromli to Function Tillbil .
•• For m~d IWI! ~, apply dll"llllfloid input I..,.. to only _ input pin It I timl

AC SWitching Characteristics
-lOoe· +2S0C +85D e·
Characteristic Symbol Input Output Conditions t Min Me. Min Typ M.. Min Mo. Unit
Propagation Delay t++, t-- Cn Cn+4 AO,A l,A2,A3 1.0 5.1 1.1 3.1 5.0 1.1 5.4 ns
Rise Time, F~II Time t+,t- Cn C n +4 AO,A 1.A2,A3 1.0 3.2 1.0 2.0 3.0 1.0 3.2 n,
Propagation Delay t++, t+- Cn Fl AO 1.7 7.2 2.0 4.5 7.0 2.0 7.5 ns

Rise Time, Fall Time

t-+, t--
t+, t- I I j 1.7
1.3
7.2
5.3
2.0
1.5
4.5
3.0
7.0
5.0
2.0
1.5
7.5
5.3 I
Propagation Delay t++, t+- Al Fl - 2.6' 10.4 3.0 6.5 10 3.0 10.8 n,

Rise Time, Fall Time

t-+, t--
t+, t- I I -
2.6 10.4
1.3 5.4
3.0
1.5
6.5
3.0
10
5.0
3.0
1.5
10.8
5.3 j
Propagation Delay t++, t-- Al PG 50,53 1.6 7.0 2.0 5.0 6.5 2.0 7.0 ns
Rise Time, Fall Time t+, t- Al PG SO.S3 0.8 3.7 1.1 2.0 3.5 1.1 3.8 ns
Pro~tion Delay t++, t-- Al GG AO,A2,A3.C n 1.1 7.4 2.0 4.5 7.0 1.3 7.7 ns
Rise Time, Fall Time t+, t- Al GG AO,A2,A3,C n 1.2 6.1 1.5 4.0 5.0 1,2 6.3 ns
Prol»9ltion Delay t+-, t-+ Al C n +4 AO,A2,A3,C n 1.7 7.3 2.0 5.0 7.0 2.0 7.8 ns
Rise Time, Fall Time t+, t- Al C n+4 AO,A2,A3,C n 1.0 3,1 1.0 2.0 3.0 1.0 3.2 ns
Propagation Delay t++, t-+ Bl Fl S3,C n 2.7 11.3 3.0 8.0 11 3,0 11.9 ns
Aise Time, Fall Time t+, t- Bl F1 S3,C n 1.2 5.3 1.5 3.5 5.0 1.5 5.3 ns

tLogic high level (+1.11 VdcJ applied to pins listed. All other ·L Suffix Only
input pins are left floating or tied to +0.31 Vdc,
VCCl = VCC2 = +2.0 Vdc, VEE = -3.2 Vdc

3-197
MC10181 (continued)

ELECTRICAL CHARACTERISTICS (continuedl

AC Switching Ch•• cteri.ics

-3O"C· +2SoC +860 C·
Ctt.lcteriltic Symbol Input Output Conditions t Min Mox Min Typ Mox Min M.. Unit
Propeglltlon DeilY 1++, t-- 81 PG 50,53 1.6 7,7 2.0 6.0 7.5 2.0 8.0 n.
Rise Time, Fill Time t+, t- Bl PG 50.53 1.0 3.6 1.1 2.0 3.5 1.1 3.9 n.
Pro~gation Delay t++, t-- Bl GG 53. Cn 1.7 8.2 2.0 6.0 B.O 2.0 8.6 ns
Rise Time, FIll Time t+, t- Bl GG 53,C n 1.4 5.2 1.5 3.0 5.0 1.2 5.4 ns
Propagation Deily t+-. t-+ Bl Cn +4 53,C n 1.8 8.2 2.0 6.0 8.0 2.0 8.7 n.
Rise Time, Fin Time t+, t- Bl C n +4 S3,C n 0.9 3.1 1.0 2.0 3.0 1.0 3.2 ns
Propagation Delay t++. t+- M Fl 2.4 10.3 3.0 6.5 10 3.0 10.8 n,
Rise Time, Fall Time H.1- M F1 - 1.1 5.1 1.5 4.0 5.0 1.5 5.3 n.
Propagation Delay t+-. t-+ 51 Fl Al,81 2.5 10.7 3.0 6.5 10 3.0 10.8 ns
Rise Time, Fall Time 1+, l- SI Fl Al,81 1.0 5.4 1.5 3.0 5.0 1.5 5.4 n,
Propagation Deily t-+, t+- 51 PG A3,83 1.7 8.3 2.0 6.0 8.0 2.0 8.4 ns
Rise Time, Fall Time t+. l- SI PG A3.83 0.8 5.1 1.1 3.0 5.0 1.1 5.2 ns
Propagation DeilY t+-, t-+ 51 Cn+4 A3,83 1.6 9.3 2.0 6.0 9.0 2.0 9.9 ns
Rise Time. Fill Time t+, t- 51 Cn +4 A3.83 0.9 6.3 1.1 3.0 5.0 1.0 6.2 ns
Prop8ption OellV t+-, t-+ 51 GG A3.83 1.6 9.6 2.0 6.0 9.0 1.9 9.7 n.
Rise Time. Fill Time t+, t- 51 GG A3.83 0.8 8.2 0.8 3.0 6.0 0.8 8.6 n.

t~ogic high lovol (+1.11 Vdcl oppliod to pin.linod. All othor · l Suffix Only
Of' tied 10 +0.31 Vdc.
input pin, ere teft fla.ting
VCCI • VCC2' +2.0 Vdc, Vee' -3.2 Vdc

SWITCHING TIMe TEST CIRCUIT AND WAveFORMS., 250C

Von veel • Vee2 • +20 Vdc: V out

PROPAGATION DE~AY

r---~-------+1.tt V
TPin
'------+0.31 V

P ..... Gen.r.,or

'nput Pu'"
t+ ~ t~ .. 2.0! 0.2 n.
(20 to 80%)

l5O-ohm termine, ion 10 .,..oulld 10 TP out

Unu.-d ololtPlol1i
miMi in . .e" IOOpe e .... n,...1 ",put. eonnected to a
50· ohm ,"ino'
AU Input and output eeblft 10 the to .,..ound.
lCoPe e,.
"101" Ientitti. D' 50·."m
co. .... e.... W.,. 'entltI'I .... OUld
tM; < 1/4 'nc" f,om TPln to input
p'n Md TP out to output pin. VEE .. ~J.2 Vdc:

3·198
 2-BIT ARITHMETIC LOGIC
MECL 10,000 series
UNIT/FUNCTION GENERATOR

MC10182

Advance InforDl.atlon
The MC10182 is a high-speed arithmetic logic unit
Capable of performing 4 logic operations and 4 arith-
metic operations on two 2-bit words. Full internal carry
lis incorporated for arithmetic operation.
f Arithmetic logic operations are selected by applying the
ilPPropriate binary word to the select inputs (SO and
511 as indicated in the tables of arithmetic/logic functions.
!Group carry propagate (PG) and carry generate (GG) are
provided for a second order lOok ahead carry using the
MC10179. The internal carry is enabled by applying a low
level voltage to the mode control input (M).
The MC10182 provides an alternate to the MC10181
four-bit ALU for applications not requiring the extended
functions of the MC10181 or for applications requiring
a 16-pin package. The MC10182 also differs from the
MC10181 in that Word A and Word 8 are treated equally
for addition and subtraction (A plus B, A minus B,
Bminus A).

POSITIVE LOGIC NEGATIVE LOGIC

9--------------~ 9

10-------, 10
VCC1 - Pin 1
VCC2 - Pln·1e
SO S1 SO S1
VEE-Pine
13 Cn 13 Cn

FO 4 FO 4
AO e AO
F1 14 F1 14
II BO II 80
Pa 15 Pa 1e

12 A1 aa 3 12 A1 aa 3

C n +2 2 C n +2 2
11 81 11 B1
M M

Po - 575 mw typ/pkg (No Load)

tpd (typ),A1 to F - 7.5 n.
en to C n +2 - 2.7 ".
A1 to'G - 6.S n,
A 1 to 00 - 5.5 n.
A1 to C n +2" 7.0 nl

POSITIVE LOGIC NEGATIVE LOGIC

Function Select Logic Function Arithmetic Operation Logic Function Arithmetic Operation
M i.High M ilLow Mi. High Mi.Low
S1 SO F F F F
L L F-A 0B F - A plu. B plu. Carry F-A 0B F - A plus B plu. Carry
L H F- ~0 B F - A plu. B plUI Carry F- A 0B F - A plus B plu. Carry
H L F- A e B F - A plul i plu. Carry F-A+B F - A plu. i plu. Carry
H H F-A+B F - A tim•• 2 F-AeB F-Atlmft2

See Gen.,.' Inform81ion ..etlon for p.ckagln'8nd maximum r.tln81 'nforrnlltlon.

Thill, advance Inform.tlon .,d tpeclflcetlon, .r. aubJact to ch.ne- without notice.

3-199
MC10182 (continued)

POSITIVE LOGIC DIAGRAM

13

10
SOO-------------~~

9
sl~------------~1~~------,

M O-------------~1 ____6-+_____,

FO

Fl

12
Al o-----~~~--~--~

81 o---~~--~ __~----~
11

3·200
 3:
...o
(')

M L L L
TRUTH TABLE
I. H H H H
...
00
N
Input 51
50
L
I.
L
H
H
L
H
H
L
I.
L
H
H
L
H

H
8
::J
!:!.
Al Bl AO BO Co Fl FO PG Go C n +2 Fl FO PG GG Cn +2 Fl FO PG GG Cn +2 Fl FO PG Go Cn +2 Fl FO PG GG Cn+2 Fl FO PG GG Cn +2 Fl FO PG GG Cn +2 Fl FO PG GG Cn +2 ::J
C
L L L L L L L H L L H H L H L H H L H L L L H L I.. H H H L I. I.. I.. ~
H L L L L H L I.. L L L L to
Q.
L I.. I.. I.. H L H H L L L L I.. H H I.. L I.. H H I.. H H I.. I.. H H IiL' I. L I.. L ~ Ii L L I. N ~ L L I. L L
L L L H L L H H L I.. L I.. H H H H L H I.. L L L H L L H L H L L L H H H Ii L L L L' ,L I.. H H L L
L L L H H H L H L L L H H H H H H H L I.. 'L H H L L H L H L I. I.. H H H. H L I.. L L L L H H L L
L I.. H I.. I.. I.. H H L I.. H I.. H L I.. L L H H H H I.. H I.. I.. H L H L, L I.. H H L L L I.. t H L I.. H H L L
L I.. H I.. H H L H L I.. H H H I.. I.. I.. H H H H H H H L L H L H L t L H ~ L L L L L H Ii I.. H H L L
L L H H I.. H L H I.. L H H L H L H H L H I.. H L H I.. L H H '+V'L L L L L H ·L I.. H H'1i If I.. H H L L
L I.. H H H H H H L I.. L L L H H L I.. L H H H H H I.. L H H ~ L L I.. L L H H L H H H H L H H L L
I.. H I.. L L H I.. H L I.. I.. H H H H L H H I.. L L L H L I.. I.. H H L L H L H L "- L L L L L H L H L I.
L H L L H H H H L L H L H H H H I.. H L L L H H L L L H ~>L. k H L H L L LLL.L J. H L H L I.
L H L H L H H I.. H L H L H H H L L H L L L H L L L L '\:"":' L H H '" L 'L L L L L L' H H H L L
L H L H H L L L H H H H H H H L H H L L L H H L L L L L H H H H.1'I L L L L L L "L H H H L L
L H H L L H H I.. H I.. L L H H H H L H L L H I.. H L L L L 'L H. L H H H I. L L I.. L L. :'-' H H H I. L

w L H H L H L I.. I.. H H I.. H H H H H H H L L H H H L L I.. L !. H :.1:\ H H Ii L L L L L L 'L H H H L L

~ L H H H L L L H H H L H H H H L H H L L H L H L I.. L H ''1'" 't;!. H L H L L L H ... t L H H H .. L
o I.. H H H H I.. H H H H H I.. H H H H L H L L H H H L L L H ~... H HLHI. 'L L H H L! it. H H H L L
H L L L I.. H L H I.. L L H H L I.. L H H H H L L H H H L H 11.. L H L Ii L L L L L H L H I.. H H H
H L L L H H H H L L H L H L L H L H H H L H H H H L H it,·I. L H L H L I. L L .t H H L H H H
H L I.. H L H H I.. H I.. H L H L L L L H H H L L H H H I.. I.. .. H, I- H H H L L L '1.. I.. L H H H H H
H I.. I.. H H I.. L L H H H H H L L L H H H H I.. H H H H L I.. sj H 'H H H H L I.. L I.. I.. I.. L H H H H H
H L H L L H H L H L L L H I.. L H L H H H H L H H H L L L H' L H H H L I.. L L I.. H. L H H H H H
H L H L H L L L H H L H H L L H H H H H H H H H H L L L, H' H H H H L L L L I.. H H H H H H H
H L H H L L L H H H L H H L L L H H H H H L H H H L H 'M '" . 1+ H L It L I.. I.. H H H H H H H H H
H L H H H L H H H H H L H I.. L H L H H H H H H H H I.. H i.'H: Ii H L iii i. .L" I.. H 'H H 'H H H ·H H H

H H I.. L I.. L
I.. H H H H H H
I.. I.. H H I.. H I.. L I.. H H H H H H H; ~ L I.. ~ H L HLHH: H H L H H H
H H L L H L H H H H L 1.. I.. H H L L I.. H H I.. H H H H H H H .!:'~ ,. .Jot, L L L H H H L .... H:H H L H Ii Ii
H H I.. H L I.. H H H H I.. I.. H H H H L H I.. L L L H H H H L H H 'H L H H H H H L H H H H H H H H
H H L H H H L H H H I.. H H H H H H H I.. I.. L H H H H H L ·,"7: H 'H - L H 'H't'-H~")' H' H I.. H H. ,t!. H H Ii H H
H H H L L L H H H H H I.. H I.. L L L H H H H L H H H H L Ii Ii: H I.. H H\",.' L H I.. H H H H H H H H
H H H I.. H H I.. H H H H H H I.. L I.. H H H H H H H H H H L tl.J'L tl .... I.. H H l. L H L H H. .M H H H Ii H
H H H H L H L H H H H H L H L H H L H L H L H H H H H H H "K L I.. !-. H ;l. H H H ...: .. ,1:i H H H H Ii
H H H H H H H H H H I.. I.. L H H L L L H H H H H H H H H H H H I.. L L H H H H .H··H .H H H H H H

The,. outputs ara not normally used during logic operation.

 ELECTRICAL CHARACTERISTICS
3:

.w"g
Each MECL 10,000 series circuit has been
designed to meet the de specifications
...
(')
snown in the tast table, after thermal
equilibrium has been established. The cir-
cuit is in a test socket or mounted on a
printed circuit board and transverse air
.T...
TEST VOL TAGE VALUES
Volts ...
0
00
T. . ..mr. VIH",.. v'Lmin vIHAm", VILAma VEE N
flow greater than 500 linear fpm is main- -30"\: -<1.890 -1.890 -1.205 -1.500 -5.2
tained. Outputs are terminated through a CERAMIC PACKAGE n0
5O-ohm relistor to -2.0 volts. CASE 620 ......,
+25"c -0.810
-0.700
-1.860
-1.825
-1.105
-1.035
-1.475
-1.0W0
-5.2
-5.2
...
::J
MCl0112L T . . Limits VOLTAGE APPLIED TO
Pin ::J
Ct.._rmic I Sy_,1 ':!:'
UT M..
-3O"c
M.. Min
+25"1:
Typ .... Min
+1Ii"C
.... Unk VIH".a
PINS LISTED BELOW:
VILmin VIHAmi VILAma VEE
1Vee)
Gnd
c::
It)

- - -
c..

·r
Power Supply Drain Current I 'E I 8 - . 110 138 - - mAde: - - - - 8 1,16
Input Currlnt
I linH I 7
- I I I - I:: - -
7
- - -
8 1,16

II
5
290 - - 6 - - -
13 I - - - - 350 - - 13 - - -
5 - - 0.5 - - - .Adc - 5 - - 8 1,16
------ -
logiC "'" Output Voltage I VOH I 2 I -1.060 -<1.890 -<1.960 -
-
~.810 -<1.890 -0.700 Vdc 5.6,11 - - - 8 1,16
- - -

I I I I I I I II
12.13
- - - -

Logic "0" Output Voltage I I

:: II
2 -1890 -1.675 -1.850
-
-
- -1.650 -1.825 -1.815 Vdc
I
7,9,10
-
-
-
-
-
-
-
-
- 8 1,16

I I I
VOL
- -

I I I II I8 I
- -
- - - -
CAl
Ir I I 14 - -
-
-
-
-
-

I8 If
-
~ 15
0
r-J
Logtc "'" Threshold Volt. I VOHA I 2 -1.080 - -<1.980 - -0.910 - Vdc 6.7.9 -
-
5 -

I I
- - - - -

I I
3 5,10,13 6
4 - - - - 7,9,10 - 5 -
14 - - - - 9,10 - 5 -
15 - - - - 67" - 5 -
Logic "0" Threshold Voltage I VOLA I 2 - -1.655 - - -1.630 -
-
-1.595 Vdc 6,7,9 - - 5 1.16

I
- - -

II
-

I
-

I I
3 5,10,13 6
4 - - - - 7,9,10 - - 5
14 - - - - 9,10 - - 5
15 - - - - 6.7,9 - - 5
Switching Times +'.11 V Pu"ln Pu'.Out i-3.2V +2.0V
(SO n Load) 2 - - - 2.7 - - - n. - 10 13 2 8 "1.16
1"3+2+
Prepagation Delay "3+4- 4 - - - 2.7 - - - - 5 13
t5+4- 4 - - - 7.0 - - - - 7 5
'&-4- 4 - - - 7.0 - - - - 9,10 6
t12-14+ 14 - - - 7.0 - - - - - 12 14
"'-14- 14 - - - 7.0 - - - - - 11
t5+2+ 2 - - - 7.0 - - - - 9 5 2 "
"2-2- 2 - - - 7.0 - - - - 9,10 12 2
t6-2- 2 - - - 7.0 - - - - 10 6 2
"'+2+
.2 - - - 7.0 - - - - 12 11 2
t5-15- 15 - - - 6.5 - - - - 10 5 15
tti+l5+ 15 - - - 6.5 - - - - 10 6 15
15+3_ 3 - - - 5.5 - - - - 10 5 3
ts-3+ 3 - - - 5.5 - - - - 9 6 3
'7-4+
(11)..4-
• 4
-
-
-
-
-
-
'.0
6.0
-
-
-
-
-
-
-
-
9,10
6,11.13
7
10
A.Time
• ,.,8
I •• I 81
I2m' to 80%) - - - 2.5 - - - n. - -
I .....
'4+ 5
hllTime
1_ .. _1
• - - - 2." - - - n. - - 5 8 1.1'
MC10182 (continued)

SWITCHING TIME TEST CIRCUlf AND WAVEFORMS CiI 25°C

V out

veel '" VCC2 '" +2.0 Vdc

Coax
25 IJ.F J I 0.1 ~F
Coale

"/TP out

Pulse Generator

50·ohm termination to ground lo- UnuMd outputl

cated in .ach 'COp. channel Input. connected to •
50-ohm r.,i,tor
All input and output cabl •• to the to ground.
scope ar. equal length, of 50-ohm
cOlucial cable, Wire length thould
be < 1/4 inch from TPln to input
pin and TP out to output pin. VEE = -3.2Vdc

PROPAGATION DELAY

r-----' '--;---- +1.11 V

+0.31 V

t+- t-+

3·203
 HEX INVERTER/BUFFER MECL 10,000 series

MC10195

Advance InforInation
The MC10195 is a Hex Buffer I nverter which is built
using six EXCLUSIVE NOR gates. There is a common input
to these gates which when placed low or left open alloYfs
them to act as inverters. With the common input connected
to a high logic level the MC10195 is a hex buffer. useful
TRUTH TABLE
for high fanout clock driving and reducing stub lengths
Inputs Output on long bus lines.
B
L L H
L H L
H L L
H H H

POSITIVE LOGIC

A
9

'"
Q

5
B JJ ./
2

Po "" 200 mW typ/pk 9 (No Load)

tpd "" 2.8 ns typ

6 JJ ./
.~
3

7 JJ ./
4

10 JJ ./
13

,....---. Vee1 "" Pin 1

II JJ ./
14 VCC2"" Pin 16
VEE "" PinS

12 JJ 16

Thl. i. advance InformatIon and .paclflcatlon •• r. subject to change without notice.

S. . Gener.1 I "formatIon Metlon for peckaglng.

3-204
 ' ..... _.
ELECTRICAL CHARACTERISTICS
A ...~o
Each MECL 10,000 series circuit has been
designed to meet the dc specifkations
shown in the test table. after thermal
:~2
...c.c
equilibrium has been established. The cir- U1
cuit is in a test socket or mounted on a n
printed circuit board and transverse air flow 6 o

~I'
greater than 500 linear fpm is maintained. :J
Outputs are terminated through a 5().ohm e.
:J
resistor to -2.0 volts. Test procedures are
shown for only selected inputs and outputs. 4 'Y:~ynll!l C
CD
Other inputs and outputs tested in the
a.
same manner,
L SUFFIX
13 CERAMIC PACKAGE
10 CASE 620

14
11

)00" 15
12 TEST VOLTAGE VALUES
Volts
w @Test
~ Temperatur. VIHmax VILmin VIHAmin VILAmu VEE
o -30"1: -0.890 -1.890 -1.205 -1.500 -5.2
U1
+25o C -0.810 -1.850 -1.105 -1.475 -5.2
+850 C -0.700 -1.825 -1.035 -1.440 -5.2
MC10195L Test Limits VOLTAGE APPLIED TO PINS LISTED BELOW,
Pin
U_, -30"1: +25"1: +85"1:
---'---r'---'---~--II !Vee 1
Cheruteristic I Symbol T ... Min Max Min Typ Max Min Max Unit VIHmax IVILminlvlHAminlvlLAmu I Vee GncI

Power Supply Drain Current IE 8 39 49 mAde 1.16

I nput Current
I finH 5
9
265
290
",Adc
",Ade
8
8
1.16
1.16
linL 0.5 ",Ade 1,16
Logic "1" Output Voltage VOH -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 1,16
Logic "0" Output Voltage VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 9 8 1,16
Logic "1" Threshold Voltage VOHA -1.080 -0.980 -0.910 Vdc 8 1.16
Logic "0" Threshold Voltage VOlA -1.655 -1.630 -1.595 Vdc 8 1,16
SWitchIng TIme pUI.lnIPul.outl-3.2Vdcl +2.0Vdc
(50 ohm load)
Propagation Delay t5+2- 2.8 ns 8 I 1,16

!
t7-4+ 4 4
tl0t13+ 13 10 13
'11-14- 14 11 14
Rise Time '2+ 2 2.0 5 2
120%'080%1
Fall Time '2_ 2.0
120%'080%1
MC10195 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2&oC

VCCI - VCC2 - +2.0 Vdc V out

~"' ± It··"
rA--- ---:-1
B Q
Co ••

' T P out

Input Pul ..
t+ E t-- 2.0 t 0.2 nl
'(20 '080%)

50-ohm t.rmin.tion to ground 10'

e.ted In ••ch leope en.nn,'
input.

All Input .nd output cab I•• to the

UnuHd outputs .r. tied to I 50·
tcope .r. equII 'Ingthl of eO-ohm
ohm r.,I,tor to ground.
:I.'
co .. cabl.. Wire I,ngth thould
be< 1/4 Inch from TPin to input
pin .nd TP out to output pin. VeE - -3.2 Vdc

PROPAGATION DELAY

~ _ _ _ _ _ _ L--'---_ _ _ +1.11 V

+0.31 V

.+- .-+

3-206
 HEX "AND" GATE " MECL 10,000 series

MC10197 \.._--------'

Advance Int'or:rnatlon
The MCtOt97 provides a high speed hex AND
function with strobe capability. Open emitter out·
puts allow wire DRing. This high density function is
useful in control, bussing, communications in high
speed central processors, high speed peripherals,
TRUTH TABLE
digital communications systems, minicomputers,
Inputs Output and instrumentation.
A B
L L L
L H L
H L L
H H H

POSITIVE LOGIC

A
9
J~
Q
B 2
5
~

Po - 200 mW typ/pkg (No Loadl

tpd - 2.8 nl typ
~ 3
6 J J

-.--... 4
7 J ./

13
10 J J
..

.~ ..... 14
VCC1 - Pin 1
VCC2 - Pin 16
11 J~
./ VEE"Pln8

12
---...
->oj
~
./ 15

r-''' II advance Information and speciflcatlonl .r. lubject to change without notice.
S- General Information section for packaging.

3-207
 ELECTRICAL CHARACTERISTICS
A
~
Each MECL 10,000 series circuit has been 9
B 2 ....0(")
designed to meet the de specifications
shown in the test table. after thermal ....CD
equilibrium has been established. The cir-
cuit is in a test socket or mounted on a
....,
3
printed circuit board and transverse air flow 6 n-

--
greater than 500 linear fpm is maintained. O
::::I
Outputs are terminated throu!tl a 50-ohm !:t.
resistor to -2.0 volts. Test procedures are ::::I
4 C
shown for only .Iected inputs and outputs.
<1>
Other inputs and outputs tested in the
Slme manner. .e:
L SUFFIX
13
10 CERAMIC PACKAGE
CASE 620

14
11

15
12

TEST VOLTAGE VALUES

ctJ
I'.)
Volts
o @Telt
00 Temperature VIHrnax VILmin VIHAmin VILAm•• VEE
-30OC -0.890 -1.890 -1.205 -1.500 -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+8SoC -0.700 -1.825 -1.035 -1.440 -5.2

1----::::;;::--,--=:.::::';;:'-=-=="'·'l·ir----+S::5:;OC==----,,----t1 VOLTAGE APPLIED TO PINS LISTED BELOW,

(Vee I
Min I Max Unit J VIHm.x I VILminl VIHAminlVILAmax I VEE Gnd

mAde 8 1.16
,lJAdc 1.16
/JAde 8 1.16
j.lAdc 1,16
-0.890 I -0.700 I Vdc 5,9 8 1,16
-1.825 1.1.615 Vdc 8 1,16
-0.910 Vdc 9 8 1,16
-1.595 Vdc 9 8 1.16
1.11Vdcl pUI.lnIPul.outl-3.2VdCI +2.0Vdc

l
ns 9

j j j
9

L,.. _,
MC10197 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 2SoC

veCl - VeC2' +2.0 Vdc

V out

Coal(

"., t
9
Ar-----.,a
8
I 1"" Con;

5 I

I I
I J l 3
6 I

I I
~~
Pulse Generator I 4

+1.11 V o-r-o I I
O.l1'F 1 10 1 J I
13

Input Pulse
I I
t+ = t-= 2.0 ± 0.2 os 11 I J 14
(20 to 80%)
I I
50-ohm termination to ground 10
c:ated in each scope channel input 12
I -~ 15
L _ _ _ _ _ ...J

.to.11 input and output cables to the Unused outputs are tied to a 50·
ohm resistor to ground.
scope are equal lengths of 50-ohm !lo.l1'F
coaxial cable. Wire length should
be <1/4. inch from TP in to input
pin and TP out to output pIn VEE'" -3.2 Vdc

PROPAGATION DELAY

V out AND

3-209
 HIGH SPEED DUAL 3-INPUT
MEeL 10,000 series
3·0UTPUT "OR" GATE

MC10210

The MC10210 is designed to drive up to six

transmission lines simultaneously. The multiple
outputs of this device also allow the wire "OR"·
ing of several levels of gating for minimization
POSITIVE LOGIC NEGATIVE LOGIC of gate and pack age cou nt. ,
The ability to control three parallel lines wi~
minimum propagation delay from a single point

~~2
7 3
makes the MC10210 particularly useful in clod[
distribution applications where minimum clod[
4 skew is desired.
The MC 10210 is a higher speed version cit
1~~1213
11
1~~1213
11
the MC10ll0. It is a pin·for-pin replacemenit
for the device. Three VCC pins are provided
14 14 and each one shou Id be used.

VCCI z Pin 1, 15 Po = 160 mW tvp/pkg (No Load)

VCC2 D ·Pln 16 tpd - 1.5 nl typ (All Output Loaded)
VEE "" Pin8
Output RIM and Fell Time: (All Outputs Loaded)
- 1.6 ns tvp
(20% to 80%)

CIRCUIT SCHEMATIC

16 VCC2
VCCI
50----------------, 1
, - - - - . . - - -.....- - _ 0
6 0---------..,
.........---+---+----0 4

"----+----03

110--+______________- - ,

10 0--+--------, VCCI
,----.....---.,---0 15
~----~---+--_o14

9
~--__II__-o 13

12
8 VEe

See Gen.,el I "formation ..ction for packaging_

3·210
 ~Cl0210 (continued)

EJ,.ECTRICAL CHARACTERISTICS
·beh MECL 10,000 ..rias circuit ha. been LSUFFIX

~~2
dlligned to ....t the de opacification. shown CERAMIC PACKAGE
in the tast table, after thermal equilibrium 7 3
CASE 620
..... been established. The circuit is in a
'te!It lOCket or mounted on a printed circuit 4
160wd end transverse air flow greater than
&00 linear fpm is maintained. Outputs are
_",in8ted through 8 5().ohm resistor to 1~~1219
11
n ..
TEST VOLTAGE VALUES
(Volta!

-2.0 volts. Test procedures are shown for TemperetuN VIH"'b VILmin VIHAmin VILA IMlI I VEE
only one get.. The other get. is tested in 14 -3O"c ~.890 ~1.890 -1.205 -1.500 -5.2
the ame manner. ·21"1: -OSlO -1.850 -1.105 -1.475 -5.2
..."1: -0.100 -, 825 -1.035 -1.440 -5.2
MC,02,OL Tal Limiu
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW.:

C~iI: Symbol
u.""
T_ M ..
-. . .C
.... Min
..."1:
Typ .... M'.
_oc
Ma U •• VIHm_ VILmin VIHAm .... YILAtnP "EE
(Vee'
Gnd
Pow. SUpply
ItipUtCurfWIt
~rain Currlnt 'E
linH
•
5,6,1
JII
410
mAdo
"Ado
1,15,'6
1,15.16
linL 5,8,7 0.' "Ado 1,15,16
L."I" "OH -UJ60 ...0.890 -0.960 -0.810 ...0.890 ...0.700 "do 1,15,.16
OutputVolrage -1.(160 ...0.890 -<>.960 -0.810 ...0.890 ...0.700 Vdo 1,15.16
-1060 ...0.890 -0.960 ~0.810 -0.890 ...0.700 1,15,16
LOIic"O" VOL -1.890 -1.675 -1.850 -1650 -1.825 -1.615 Vdo 1,15,16
Output Volt. -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 V", 1,15,16
-1.890 -1.675 -1.850 -1.650 -1.825 -1.615 "do 1,15,16
LotIc"I" VOHA -1.080 -0.980 -0.910 Vdo 1,15,16
Ttlr.....o!dVolt. . -1.080 -0.980 -0.910 "do 1,15,16
-1.080 -a.980 ...0.910 "do 1,15,16
LagIc"O" VOLA -1.655 -1630 -1.595 1.15,18
l'ttt-tItIoldVolt. -1.655 -1630 -'.595 Vdo 1,15,1&
-1.655 -1.630 -1.595 Vdo 1,15,16
SWitching Timn
15O--oIam1OMt1
'~ionD.,1V ...,.
t6_2_
1.0 I.S 2."
'u'.'n ' . . . Out -3.2 V
S
+2.0 V
1,15,16

'"''
.....
' ..J-
,
·t t5_ ....
.,.Tw.
(20"10%1

F.,T"",
...'2.
'3•

'2-
120.11*1
..-
'3-

-,lIdhoidlHHy.t ~h input ut.ing the pin conn8Ctionllihown.

l ; r -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _SWITCHING
______ TIME
_ _TEST
___ CIRCUIT
_ _ _ _AND
_ _ WAVEFORMS
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

"
"
Coax
,----+1.11 V
Input

Pul .. Generator - - - - - +0.31 V

I
I

r=tt'
: : Vout

-r;:-
e.
, , Input Pulse
,,
~- 1
t+ _ t- _ 1.5.:!:. 0.2 ns ;1 I Unu ..d outputs connected to

.L --
(~ (20 to 80%) a 50-ohm ,esistor to ground.

- - __'_'.0 m , ••0'
cated in each lcope channel input x_ 0.1 ",F
=:-<.
All Input and output cable. to the

be
~r:.~i:a~~;egtl:~;:h5!-:~~
1/4 Inch from TPln to Input
VeE ~ -3.2 Vdc
pin end TPout to output pin.

3·211
 HIGH SPEED DUAL 3-INPUT
MECL 10,000 series
3-0UTPUT "NOR" GATE

MC10211

The MC 10211 is designed to drive up to s.ix

transmission lines simultaneously. The multiple
outputs of this device also allow the wire "OR~(­
ing of several levels of gating for minimization
POSITIVE LOGIC NEGATIVE LOGIC of gate and package count.
The ability to control three parallel lines with
minimum propagation delay from a single point
makes the MC 10211 particularly useful in clook
distribution applications where minimum clock
skew is desired. .

~
'2

,g ~
'2
13 13

11
. 14 1~
11
14
Po = 75 mW typ/gate (Outputs Open)
tpd "" 1.5 ns typ (All Outpuu Loaded)
Output Rise and FeU Time: (All Outputs Loaded)
VCCI = 1. 15 = 1.5 ns typ 120% to 80%)
VCC2 = 16
VEE = 8

CIRCUIT SCHEMATIC

16 VCC2
VCCI
r--'--~-_o 1
6 0--------,

"'---+--+----0 4

---+---03

110--+_ _ _ _ _ _ _ _-,
100--+------, VCCI
.--~---~---O15

'---r--~-_o14

"---+--013

12

See General I nformation section for packaging.

3-212
: MC10211 (continued)

",m'
ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been

~
designed to meet the de specifications shown 2
LSUFFIX
in the test tabli, after thermal equilibrium 5 3 CERAMIC PACKAGE
ha been established. The circuit is in a , I; " CASE 620
test lOCket or mounted on a printed circuit ~ 4
~\ i
~d and transverse air flow greater than

~ ::
500 linear fpm is maintained. Outputs are
TEST VOLTAGE VALUES
terminated through a 50-oh m resistor to
-2.0 volts. Test procedures are shown for 1~ 14
(Volts!

only one gate. The other gate is tested in 11 r',",""a1u •• VIH m •• I Vil min VIHA min VILA m .. I VEE
_lOGe -1.205 -52
the same manner. -0.890 -1.890 -1.500
+2SoC -0.810 -1.850 -1105 -1.475 -S.2
+8SoC -0.700 -1.825 -1.035 -1440 -52
MCl0211L Test Limit.
Pin TEST VOLTAGE APPLi£D TO PiNS LiSTED BELOW,
-lOoe iVec l
Undltr
CharecteristlC Symbol T_
T" M.. ViH m.. ViL min ViHA min ViLA IN. VEE Gnd
30 38 mAde 1.15.16
inputCurrenl "
IInH 5.6.1 410 pAde 1.15.16
r,nL 5.6,7 0' 1,15,16
LogIC"'" VOH 2 -1.060 -0.890 -0.960 -0810 ..o.890 -0.700 1.15.16
OulputVo1tage 3 -1.060 -0.890 -0.960 -0810 ..o.890 -0700 1.15.16

Logie "0" Va'

,
4 -1.060
-1.890
..o.890
-1.675
-0.960
-'850
-0.810
-1.650
-1.650
-0890
-1.825
-0.700
-1.615
1.15.16
1.15.16
OulputVoilage 3 -1.890 -1675 -1850 -1.825 -1.615 1.15.16
_'.890 -1675 -1.850 -1650 -1.825 -1.615 1.15.16
L09IC'"'" VOHA -LOBO -0980 ..o910 1.15,16
Threshold Vollage -lOBO -0.980 ..o.910 1.15.16
-1.080 -0.980 -0910 1.15.16
'LoglC "0" VOLA -1655 -1.630 -'595 1.15.16
Threshold Voltage -'655 -1.630 -1.595 1.15,16
-1655 -1630 -1.595 1.15.16
SWItchIng TImes
(50-ohm load) Pulse'n Pul_Out +2.0 V
ProplJllltion Delay 15+2_ 1.0 1.' 2.' 1.15.16
15-21-
15+3-
15-3+
'51-4-
15_401-
Ri_Tome
120·to.w1 ".
'3'
'4.
F"ITime
120to.w1 "-
'3_
'4_
·Ind.... idu.lly ,., each Inpul USIng Ihe P'" eonnKllons shown

SWITCHING TIME TEST CIRCUIT lIND WAVEFORMS@ 25°C

VCC 1 = VCC2

, , if t""
+2.0 Vdc V out

Coax

r- - - - --,
,_.
, r--4'------~
Input I
V out

Pulse Generator

Input Pulse
t+ t- "" 1.5 ±. 0.2 ns
:E

(20 to 80')6) ~
i-A Unused outputs connected to
850-ohm resistor to ground.
5O-ohm termination to ground lo-
cated in each scope channel input.

All Input and output cables to the

ICOpe ar. aqual langths of 50-ohm
cOIIxl.1 cabl.. Wire length should
C_-!1-;'"
I I

be < 1/4 Inch from TPin to input

VEE = -3.2 Vdc
pin end TP out to output pin.

3·213
 HIGH SPEED DUAL 3-INPUT MECL 10,000 series
3-0UTPUTOR/NOR GATE

MC10212

Advance InforIIlation
The MC10212 is designed to drive up to six
transmission lines simultaneously. The multipl~
outputs of this device also allow the wire "OR"-'
ing of several levels of gating for minimiiatiOn
POSITIVE LOGIC NEGATIVE LOGIC of gate and package count.
The ability to control three parallel lines with
minimum propagation delay from a single point

6
5~:
7
2
makes the MC10212 particularly useful in clock"
distribution applications where minimum clock
skew is desired. ' ,

~
'2

~
'2
9 13 13
10 14 1~ 14
11 11

vee1 = 1. 15 Po ==160mW typ/pkg (No Load)

VCC2: 16 tpd"" 1.5 n. typ (All Outputs Loadad)
Vee: 8 Output Rise and Fall Time: (All Output. Loaded)
= 1.5 ns typ (20% to 80%)

CIRCUIT SCHEMATIC

16 VCC2

6 <>-------,

5 <>-+_--f
......--4--+---0 2

........-+--<>3

Ilo--+_ _ _ _ _ _ _ ~

10o--+---~ VCCI
15

......_-1---+---<> 12
9

......- - 1 - - 0 1 3

14
8 Vee

Thi, i, edwnce information and .peclfleatlon•• re ,ubject to cheng. without notice.

S.. G.n .... ' Information ..ctktn for packaging.

3-214
 ELECTRICAL CHARACTERISTICS 3:
n
.....

-
E.,h MECL 10.000 _ies circuit h.. been
o
~ ~:
designed to !Met thode opecific.tions shown
LSUFFIX
in the test table, after thermal equilibrium
has been established. The circuit is in a
7~2
CERAMIC PACKAGE
CASE 620
....N
N

test socket or mounted,on a printed circuit

board and transverse air flow greater than
'2
n-
~
500 line. fpm is maintained. Outputs are O
:::I
terminated through a 50-ohm resistor to 9 13 ~.
-2.0 volts. Test procedures are shown for 10
11 14 :::I
only one gate. The other gate is tested in C
(1)
the same manner. Q.

TEST VOLTAGE VALUES

(Voltsl
til Test
Tempet'ature VIHmal( VILmin VIHA min 1 VILA mul Vee
-30"1' -0.890 -1.890 -1.205 -1.500 -5.2
+25o c -0.810 ·1.850 -1.105 I -1.475 I -5.2
+85·C -0.700 -1.825 -1.035 I -1.440 I -5.2
MC10212L Test Limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
Under
_lODe +25OC +85o C IVcCI
Characteristic Symbol Tnt Min Max Min TV. Max Min M_ Unit V,H max I V'L min I V'HA min I V,LA max VeE Gnd
w Power SupplV Drain Current Ie 30 38 mAde 1,15,16
~
..... Input Current 'inH 5,6,7 405 #JAde 5,6,7+ 1.15,16
U1 'inL 5,6,7 0.5 !lAde 5.6.7+ 1,15,16
logic "'" VOH 2 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vde 1,15,16
Output Voltage 3 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vde 1,15,16
-1.060 -0.890 -0.960 -0.810 -0.890 -0.100 Vde 1,15,16
logic "0" VOL -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 1,15,16
Output Voltage -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vde 1,15,16
-1.890 -1.675 -1.850 -1.650 -1.825 ":'.615 Vdc 1,15,16
logiC "'" VOHA I -1.080 -0.980 -0.910 Vdc 8 1,15,16
Threshold Voltage -1.080 -0.980 -0.910 Vde 8 1,15,16
-1.080 -0.980 -0.910 Vdc 8 1,15,16
logic "0" VOLA I -1.655 -1.630 -1.595 Vdc 1,15,16
Threshold Voltage -1.655 -1.630 -1.595 Vdc 1,15,16
-1.655 -1.630 -1.595 Vdc 1,15,16
Switching Times
(50-ohm load) Pulse In Pul. Out I -3.2 V I +2.0 V
Propagation DeiaV 15+2+ I 1.5 I 1,15,16
t5-2-
15+3-
15-3+
15+4-
15-4+
Rise Time '2+
1201080%. '3+
'4+
Fall Time '2.
120'.80%1 '3_
'4_
-Individuallv test each input using the pin connections shown.
MC10212 (continued)

SWITCHING TIME TEST CIRCUIT PND WAVEFORMS@ 2SoC

Vee, = Vee2
+2.0 Vdc V out

Input
Coax
!
''-' £ ±" " ""
r'- - - - ---,
I
I
,-+-_----J
+0.31 V
±.10mV

~--+-----+I~~_~~
Pulse Generator

~
I I
Input Puis. I I
t+ '"' t- "" 2.0 ±. 0.2 ns I
Unused outputs connected to
120 to 80%1 I a 50-ohm resistor to ground. - - -
I V out
50-ohm termination

input.
to ground
located in each scope channel

All input and output cables to the

scope are equal lengths of 50-ohm
C_ --fl-'"'"
coaxial cable. Wire length should VEE = -3.2 Vdc
be < 1/4 inch from TP in to input
pin and TP out to output pin.

3-216
 MECL 10,000 series
HIGH SPEED TRIPLE
LINE RECEIVER

MC10216

The MC10216 is a high speed triple differential

amplifier designed for use in sensing differential signals
over long lines. The basa bias supply (VSS) is made
available at pin 11 to make the device usaful as a
Schmitt trigger, or in other applications where a stable
reference voltage is necessary.
Active current sources provide the MC10216 with
POSITIVE LOGIC NEGATIVE LOGIC excellent common mode noise rejection. If any ampli-
fier in 8 package is not used, one input of that amplifier
must be connected to Vee (pin 11) to prevent upsetting
the current source bias network.
Complementary outputs are provided to allow driv-
4~2 4~2 ing twisted pair lines, to enable cascading of several
5~3 5~3 amplifiers in 8 chain, or simplv to provide complement
9~6 9~6 outputs of the input logic function.
10~7 10~7
12~14 12~14
13~15 13~15
~11 ~11
Vaa Vaa
vee1 =Pin 1
VCC2 = Pin 16
VEE::: Pin 8 Po = 100 mW typ/pkg (No Load)
tpd = 1.8 ns typ (Single ended)
= 1.5 nstyp (Oifferential)

CIRCUIT SCHEMATIC

3 6 14 VCC1 15 VCC2
1 16

5 4 9 10 13 12

SM General Information section for packaging.

3·217
 ..s:
ELECTRICAL CHARACTERISTICS

-
Each MECL 10,000 series circuit has been (")
desigred to meet the de specifications shown
in the test table. after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
board and transverse air flow greater than
4~2
5~3
9~6
10~7
L SUFFIX
CERAMIC PACKAGE
CASE 620
..
o
N
en
12~14
500 linear 'pm is maintained. Outputs are
terminated through a 50-ohm resistor to lJ~15 8
-2.0 volts. Test procedures are shown for L~11 ....
::J

only one gate. The other gates are tested

VB B
:i"
c:
in the same manner. <11
3:

TEST VOLTAGE VALUES

(Volts)
lilT ...
Tanper.ture VIH max VILmin VIHAmin VILA max VBB VEE
-3O"c
+25o C
-0.890
-0.810
-1.890
-1.850
-'.205
-1.105
-'.500
-1.475
From
Pin -:H-1
-5.2
~
...,W +85°C -0.700 -1.825 -1.035 -1.440 11

... I
CO
Pm
Undor -3O"c
MCl0218L Test Limits
+2SoC +SSoC
TEST VOLTAGE APPLIED TO PINS BELOW:
1VCCI
Ch.rKte,istic Symbol TOft M'" Mo. Min Ty. Mo. Min M •• Unit VIHmax VILmin VIHAmin VILA max VBB VEE Gnd
Power Supply Drain Current 'E 20 25 mAde 4,9,12 5,10,13 1,16
Input Current linH • 115 /-lAde 9,'2 5,10,13 1,16
IC80 •
9
'.0
'.0
/-lAde
/-lAde
9,'2
','2
5,'0,'3
5,1~,13
8,'
8,9
1,16
1.16
High Output Voltage VOH -1.060 -0.890 -0.960 -0.8'0 -0.890 -0.700 Vdc 4 9,12 5,10,13 1,16
-1.060 -0.890 -0.960 -0.8'0 -0.890 -0.700 Vdc 9,12 4 5,10,13 1,16
low Output Voltage VOL -'.890 -'.675 -1.850 -1.650 -1.825 -1.615 Vdc 9,12 4 5,10,13 ','6

High Threshold Voltage VOHA

-1.890
-1.080
-'.675 -1.850
-0.980
-1.650 -1.825
-0.910
-1.615 Vdc
Vdc
• 9,'2
9,12
5,10,13
5,'0,'3
','6
','6
-1.080 -0.980 -0.910 Vd, 9,12 5,10,13 1,16
Low Threshold Voltage VOLA -1.655 -1.630 -'595 Vd, 9,12 5,10,13 8 1,16
-'.655 -1.630 -1.595 Vdc 9,'2 5,10,13 8 1.16
Ref.rence Voltage V8S 11 -1.420 -1.280 -'.350 -1.230 -1.295 -1.150 Vdc 5,'0,'3 1,16
Switching Tim.. -3.2 +2.0
(SO-ohm LOoecU Pullt ... Pu. . Out Vd, Vdc
Propagation Delay t4+2+ 2 1.0 1.8· 2.5 5, '0,'3 B 1,16
'4-2- 2

I";:
'4+3- 3

j •~ j
3
1.5
Ri.Time
120% to 80%1
FatlTime
(~toemr.1
'3+
'2-
j j 2
3
j j j
'3-
-Deily i. 1.5 ns when inputs •• driwn diHerwntially
Dttey II 1.8 ns when inputt •• driven tingle ended.

~-- ._.--_.-..-
 ~ftECTR1CAt·eHARAtTERts'Tit:s'­
. Each IIIIECL 10,000 series circuit h_ been
3:
(')
designed to meet the de specifications shown .-

•
in the test table, after thermal equilibrium
has been established. The circuit is in a
:~: PSUFFIX 2.-
PLASTIC PACKAGE
9~6
test socket or mounted on a pr-inted circuit
board and transverse air flow greater than
10 7 CASE 648 en
12~14
500 'inear fpm is maintained. Outputs are
13~'5 8
terminated through a 50-ohm resistor to
-2.0 volts. Test procedures are shown for ~"
V BB
...S'
::J

only one gate. The other gates are tested

in the same manner.
c:
CD
.e:

TEST VOLTAGE VALUES

I
(Voltsl
i;>T...
Temper"uN VIHmax VILmin VIHA min VILA max Vaa VEE
-lII"c -1.500 F,om
~
-0.890 -1,890 -1.205
+25o C -1.105
~
-0.810 -1.850 -1.475 Pin
to)
+SSoC -0.100 -1.825 -1.035 -1.440 11 -5.2
N
.... MC1021IP Test Limits
Pin TEST VOLTAGE APPLIED TO PINS BELOW:
to Undo, -3O"c +2SoC +BS"c
IVce'
Characteristic s"mboI Tnt Min Mo. Min Ty. M •• Min Mo- Unit VIH max V'Lmin V,HA min V,LA max Vaa VEE Gnd
Power Supplv Drain Current 'E 8 - - 20 25 - mAde 4,9.12 5,10,13 8 1,16
I "put Current linH 4 115 J.lAde 4 9,12 - 5,10,13 8 1,16
'C80 4
- - - -
1.0 ..
J.lAde 9,12
-
-- 5.10.13 8,4 -1.16
9 10 - .uAde 4.12 5.10.13 8,9 1.16
High Output Voltage VOH 2 -1.()60 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 4 9.12 - - 5.10.13 8 1.16
3 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 9.12 4 - _. 5,10.13 8 1.16
low Output Voltage VOL 2 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 9.12 4 - - 5.10.13 8 1.16
3 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 4 9.12 - - 5.10.13 8 1.16
High Threshold Voltage VOHA 2 -LOBO - -0.980 - - -0.910 Vdc 9.12 4 - 5,10.13 8 1.16
3 -LOBO - -0.980 - - -0.910 - Vdc 9,12 - - 4 5,10.13 8 1.16
Low Threshold Voltage VOLA 2 - -1.655 - - -1.630 - -1.595 Vdc 9,12 4 5,10,13 8 1.16
3 - -1.655 - - -l.630 - -1.595 Vdc 9,12 - 4 - 5,10,13 8 1.16
Reference Voltage Vaa 11 -1.420 -1.280 -1.350 - -1.230 -1.295 -1.150 Vdc - - - - 5.10,13 8 1.16
SWitchi .... Times -3.2 +2.0
I _ m l.... ' Pul.ln Pul.Out Vdc Vdc
Propegltion Oelav t.t+2+ 2 - - 1.0 1.8' 2.5 - - n. - -
-
4 2 5.10,13 8 1,16
2 - - - - - 2

~
'4-2-
'4+3- 3 - - - - - - 3
-
j
-

j
'4-3+ 3 - - - - 3
- - 1.5 - - - -
j
Ri .. Time 2
j j j j
'2+ 2
- - - - - -

!
(20% to 80%) '3+ 3 3
F8IITime '2_ 2 - - - - - - 2
(20%1080%) '3- 3 - - - - - - 3
Oelav is 1.5 n. when inpu1s,,-. driven different.. Uy
O".y is 1.8 ns wt-n inputs ..e driven single ended
MC10216 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

+2.0 Vdc V out

Coax Coax

Input pulse
t+ :II t- '"' 1,5 ±. 0.2 ns
(20 to 80%)

-
I
I

n
I
I
I I
L_- -: 1 /l F
I
lO.l/lF

v:e = -3.2 Vdc

50-ohm termination to ground lo-

Unused outputs connected to
cated In .ach scope channel input.
a 50-ohm resistor to ground.
All input and output cabl., to the
scope are equal lengths of 50-ohm One input from each gate must
C08ICiai cabl.. Wire length should
be tied to Vee (Pin 11) during testing.
be < 1/4 inch from TPin to input
pin and TP out to output pin.

PROPAGATION DELAY

3-220
 HIGH SPEED DUAL TYPE D
MEeL 10,000 series
MASTER-SLAVE FLIP-FLOP

MC10231

The MC10231 is a dual master-slave type 0

flip-flop. Asynchronous Set (5) and Reset (R)
override Clock(Cc)and Clock Enable (CE) inputs_
R-5 TRUTH TABLE
Each flip-flop may be clocked separately by
R S Q n +l holding the common clock in the low state and
L L an using' the enable inputs for the clocking function_
L H H
If the common clock is to be used to clock the
H L L
H H N.D. flip-flop, the Clock Enable inputs must be in the
low state_ In this case. the enable inputs perform
N.D. = Not Defined
the'function of controlling the common clock_
The output states of the flip-flop change on
the positive transition of the clock _ A change
in the information present at the data (0) input
CLOCKED TRUTH TABLE wi II 'not affect the output information at any
C 0 Qn+l other time due to master slave construction.
L q, an Input pulldown resistors eliminate the need
H L L to tie unused inputs to VEE:- Output rise and fall
H H H
times allow high frequency operation over 200
cP "" Don't Care MHL .
e = Ce + ee·
A clock H is 8 clock transition
from 8 low to a high state.

Po"" 270 mW typ/pkg (No Load)

f TOg ~ 225 MHz typ

POSITIVE LOGIC NEGATIVE LOGIC

S1 5--------------' R1 5------------~

01 7 - - - - - - - -.... 2 01 7 ---------""'I
GEl 6 eEl 6

3 3

R1 4--~----------~ 51 4 __~----------~
ee g ee g
R2 13--~----------, 52 13--~----------,

14 14

CE 2 11 ------..___' C E 2 11 -----...__. /
02 10--------..... 15 02 10 --------..J::ot 15

S212--------------~ R2 12--------------~

vee1 == P n 1
VCC2=Pn 16
VEE = P n 8

s-,. General I nformation section for packaging.

3-221
 ELECTRICAL CHARACTERISTICS SI 5----, s:
n
....

-
Each MECL 10,000 series circuit has been 01 7
designa:d to meet thedc specifications shown CEI 6 o
in the test table, after thermal equilibrium
has been established. The circuit is in a
test socket or mounted on a printed circuit
AI. 4~
3· L SUFFIX
CEAAMIC PACKAGE
CASE 620
...
N
W
board and transverse air flow greater than CC~ 8::J
500 linear fpm is maintained. Outputs are
terminated through a 50-ohm resistor to
-2.0 volts. Test prOCedures are shown for
only one input, or for one set of input con·
ditions. Other inputs tested in the same
manner.
"""§)=
CE2
"
0210----

5212
02

Q2
14

15
OTost
T........tur.
_30o e
+25"<:
V,Hm ••
-0.890
-0.810
V'Lmin
-1.890
-1.850
TEST VOLTAGE VALUES
IVolts'

VIHAmin
-1.205
-1.105 ..
V'LAm••
-1.500
-1.475
VEE
-5.2
.-5.2
...3'
t:
CD
0-

+85oe -0.700 -1.825 -1.035 -1.440 -5.2

MC10231L Test Limits VOLTAGE APPLIED TD PINS LISTED BELOW,
Pin
Und.r _30o e +250e +85 o e IVee
eh.rKt.,istic Symbol T., Min Ma. Min Ty. M.. Min M.. Unit V,Hm•• V'Lmin VIHAmin V,LA mi. VEE 0'" "
Power Supply Drain Current 'E 8 - - - 52 65 - - mAde - - - - 8 1',16
Input Current linH 4 410 ",Ade 4 8 1,16
5 - - - 410 - - 5 - - -

Input Leakage Current linL

6
7
9
4,5,·
-
-
-
-
-
-
-
-
-
-
-
0.5
-
-
-
-
220
220
290
-
-
-
-
-
-
-

-
-
!
",Adc
6
7
9
-
-
-
-
-
-
-
-
-
-
-
-
! !
8 1,16
Co) 6,7,9· - - 0.5 - - - - J.lAde - - - 8 1,16

~ Logic "1' VOH 2 -1.060 -0.890 -0.960 -0.810 0.890 -0.700 Vdc 5
-
8 1,16
I\.) Output Voltage 2t -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 7 - 8 1,16
I\.) logic "0" - - - - 1,16
VOL 3 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 5 8
Output Voltage 3' -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 7 - - - 8 1,16
logic ",." VOHA 2 -LOBO 0.980 - -0.910 Vdc - 5 8 1,16
Threshold VQltage 2' -1.080 - -0.98Q - - -0.910 - Vdc - - 7 9 8 1,16
logic "0" VOLA 3 - -1.655 - - -1.630 - -1.595 Vdc - - 5 - 8 1,16
Threshold Voltage 3' - -1.655 - - -1.630 - -1.595 Vdc - - 7 9 8 1,16
Pulse Pulse
SWitching Times +l.llVde In Out -3.2Vck: +2.0 Vdc
Clock Input
P,.opagation Delay t9+2- 2 1.4 3.4 1.5 - 3.3 1.5 3.7 ns - - 9 2 8 1,16
- -

~
2 1.4 1.5 7 6 2

! !
t6+2+ 3.4 1.5 3.3 3.7
Rise Time 120 to 80%' '2+ 2 0.9 3.3 1.0 - 3.1 1.0 3.5 7 - 9 2
Fall Time (20 to 80%) '2- 2 0.9 3.3 1.0 - 3.1 1.0 3.5 - - 9 2
Set Input
p,.opagation Delay t5+2+ ·2 1.0 3.4 1.1 - 3.3 1.1 3.7 nS - - 5 2 8 1,16
- 6 -

+ + ~
t'2+15+ 15 12 15.
t5+3+ 3 - - - 5 3

Reset Input
t'2+14- 14 -
+ + + + 9 - 12 14 + +
- - - 4

!l ! t
P,.opagation Delay t4+2- 2 1.1 3.3 ns 2 8 1,16
t'3+15_ 15 - 6 - 13 15
t4+3- 3 - - - 4 3
t13+14+ 14
+ - + + 9 - 13 14
+ +
Setup Time tSetup 7 1.0 ns 6,7 2 8 1,16
.-
Hold Ti,!,e
T~. Ff'equency 1M•• )
.. ....
tHold
ITog
7
2 200
_ _- --
0.75
200 250' 200
ns
MHz .. 6,7
6
2
2
8
8
1,16
1,16
~~_"'!y,~~,i~~~;~~VLL·miJt'~oJ~,,_......... _.......__ , .___ . ........ ~,_~._
tau.... _ tobo _ _ . _ pujOl ' - boon _'ied to ,fie ~ input Ipin61 n- VIH ....
,.:, .. :.:;-... ,.:•• :.:,;, ':,.' .i .. ::.; J\. .' ,~ .. , : "'.~".. .,__ '''. _':, ',_, :.._'. . : ,,", • '. _'.' . __ ' ;,;:"""', : _,,,,,,,- -v.••, .......
 i
3:

-
ELECTRICAL CHARACTERISTICS S1 5
Each MECL 10,000 serias circuit has been
0...&
01 7 PSUFFIX
designed to meet thade specifications shown CE1 6
PLASTIC PACKAGE
0
in the test table, after thermal equilibrium 3 CASE 648
N
Co)
has been established. The circuit is in a
test socket or mounted on a printed circuit A1 4
.....
n0

"'O':~"
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are
terminated through 8 5(H)hm resistor to
reST VOLTAGE VALUES
....
::J

-2.0 volts. Test procedures are shown for (Voltsl S·

only ona input, or for one set of input con· CE2 11 ii Test
VEE
c::
0210 Q2 15 Temperatu,. VaH max VILmin VIHA min VILA rna. <D
ditions. Other inputs tested in the same _lODe -0.890 -1.890 -1.205 -1.500 -5.2 3:
manner. 5212 +2SoC -0.810 -1.850 -1.105 -1.475 -5.2
+85oC -0.700 -1.825 -1.035 -1.440 -5.2
MC10231P Test Limits
Pin VOLTAGE APPLIED TO PINS LISTED BELOW:
_lODe +2Soc +ssoc IVeel
Characteristic I Symbol I Ur' : ' Min I Max Min I Typ M•• Min M.. Unit VIH mall VILmin VIHA min VILA mall VEE G'"
Power Supply Drain Current ~ IE I - I - - I 52 65 mAde 8 1,16
I nput Current
I linH I I I I 410
410
,uAde 1,16

~ ~ ~
220
220
220
Input Leakage Current l.nL 4,5,- 05 /JAde 1,16
1,16
I
6,7,9- 0.5 /JAde
Logic "1' VOH 2 -'1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 5 1,16
CN Output Voltage 1,16
I
21 -1.060 -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 7
~ 3 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 5 8 1,16
N Logic "0" VOL
CN Output Voltage 31 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 7 8 1,16
Logic "I" VOHA 2 -1.080 -0.980 -0.910 Vdc 1,16
Threshold Voltate 21 -1.080 -0.980 -0.910 Vdc 9 1,16
Logic "0" VOLA 3 -1.655 -1.630 -1.595 Vdc 1,16
Thre$hold Voltage 31 -1.655 -1.630 -1.595 Vdc 9 1,16
Pulse Pulse
Switching Times +1.11 Vdc In Out -3.2 Vdc +2.0 Vdc
Clock Input
Propagation Delay 19+2- 2 2.0 8 1,16

~ ~
2

~
1".2+ 2.0
Rise Time (20 to 80%) '2+ 1.3
Fall Time (20 to 80%) '2- 1.3
Set Input
Propagation Delay '5+2+ 2 2.0 5 8 1,16
t12+15+ 15 6 12 15
15+3+ 3
tI2+14- 14
+ + 9 12 14 + +
Reset Input
Propagation Delay I 14+2-
tI3+15_ 15
2.0 4
13 15
1.16

t4+3_ 3 3
+
• •
14

•
tI3+14+ 13 14
Setup Time 1 'Setup 7 1.0 6.7 1.16
Hold Time 1 'Hold 0.75 6.7 1,16
Toggle Frequency (Maxi I 'T"II 200 2.25 MHz 6 1.16
-IndIvidually test eec:h Input. apply VIL mIn to pin under test.

tOutput level to be menured after'. dock pul. has been epplied to the Ce input (pin 6)
:..fL Vlfj max
VIL min
MC10231 (continued)

FIGURE I-TOGGLE FREQUENCY TEST CIRCUIT

vee1 "" VCC2 :::: +2.0 Vdc V out

Coax

2
Clock Input (Or---I_ _ _ _ _...;6'-jCE of-"----------'
o--_..:.9-l C
3
50-ohm termination to ground lo-
cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm
50
coaxial cable. Wire length should
be < 1/4 inch f ... om TPin to input
pin and TP out to output pin.

Vee"" -3.2 Vdc

FIGURE 2 -SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @2Soc

VCCI = VCC2 =
+2.0 Vdc V out

~ Coax

Clock Input
JTP out

SO~hm termination to ground lo-

cated in .ach SCOpe channa' input.

All input and output cables to the

scope are equal length. of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPjn to input Vee:::: -3.2 Vdc
pin and TP out to output pin.

.~---.....- - - - - + 1 . 1 1 V
C 50%
R Input
----~I \.----+0.31 v
thold

o
50%
5 Input - - - - ' I
t5+2+
0 __ ---'1
a Output ---~f-F NOTE:
t5+3_ t setup is the minimum time before the positive
a Output - - - -......1 transition of the clock pulse (C) that information must
be present at the data input (D). .

thold is the minimum time after the positive tran-

sition of the clock pulse (C) that information must
remain unchanged at the data input (0),

3·224
 HIGH SPEED MECL 10,000 series
2x 1 BIT ARRAY MULTIPLIER
BLOCK

MC10287

Advance InforIllation
The MC10287 is a dual high speed iterative multiplier.
It is designed for use as an array multiplier block. Each
device isa modified full adderlsubtractor that forms a single·
Po = 400 mW typ/pkg (No Load)
tpd: (Outputs loaded- 1 kfl to VeE)
bit binary product at each operand 'input of the adder.
co to C2 1.Tn. typ Internal carry lookahead is employed for high speed
aD to C2 2.8 operation.
aD to SO 2.7 An addition or subtraction is selected by mode controls
bOtoSO 3.1 (MO, Ml). The mode controls are buffered such that they
aD to 51 3.9 can be grounded or taken to a standard high logic level
bO to S1 4.4 to accomplish subtraction. When left open or taken to
MO to 81 8.7 a low logic level, MO and Ml cause addition.
POSITIVE LOGIC NEGATIVE LOGIC

co 9 co 9
.0 6 .0 6
aD' 7
so .0' 7 2 so
bO 4 bO 4
C1 C1
bO' 5 bO' 5
MO 3 Vee = Pin 16 MO 3
VeE = Pin 8

.1 11 .1 11
51
al' 10 .1' 10
b1 13 b1 13
15 C2 15 C2
b1'12 b1' 12
M1 14 M1 14

3 MO
MO

.0
00' so z AO e> BO e> CO

bO
bO'
9
co

NEGATIVE LOGIC
C1- co (AOe> BO e> MO) + AD (BO e MO)

14 M1
M1

.1
.1' A1 eB1 eM1 S1 - A1 e> B1 e> C1

b1
A1 (B1 e Mn
b1'

C2

Thi,l. advance Information end .peciflcatlon. ara .ubJect to change without notice.
S. 0." .... ' I "formation section for peckaglng.

3-225
Me 10287 (continued)

MC10287 FUNCTIONAL TRUTH TABLE

Ml MO bl bl' .1 .1 • bO bO'.o 00' co so 51 C2 Ml MO bl b" .1 .1' bO bO' .0 00' CO 5051 C2

14 3 13 12 11 10 4 5 6 7 9 2 1 15 Word 14 3· 13 12 11 10 4 5 6 7 9 2 1 15 Word
H H H H H H H H H H H H H H 0 L H H H H H L L H H H L H H 68
H H H H H H H H H H L L L L 1 L H H H H H L L H H L H H H 69
H H .H H H H H H L L H L L L 2 L H H H H H L L L L H H H H 70
H H H H. H H H H L L L H L. L 3 L H H H H H L L L L L L L H 71
H H H H H H L L H H H L H H 4 L H H H L L H H H H H H L H 72
H H H H H H L L H H L H H H 5 L H H H L L H H H H L L H L 73
H H H H H H L L L L H H H H 6 L H H H L L H H L L H L H L 74
H H H·'H H H L L L L L L L L 7 L H H H L L H H L L L H H L 75
H H H H L L H H H H H H L L 8 L H H H L L L L H H H L L H 76
H H H H L L H H H H L L H L 9 L H H H L L L L H H L H L H 77
H H H· H L L H H L L H L H L 10 L H H H L L L L L L H H L H 78
H H H H L L H H L L L H H L 11 L H H H L L L L L L L L H L 79
H H H H L L L L H H H L L L 12 L H L L H H H H H H H H L H 80
H H H H L L L L H H L H L L 13 L H L L H H H H H H L L H L 81
H H H H L L L L L L H H L L 14 L H L L H H H H L L H L H L 82
H H H H L L L L L L L L H L 15 L H L L H H H H L L L H H L 83
H H L L H H H H H H H H L H 16 L H L L H H L L H H H L L H 84
H H L L H H H H H H L L H H 17 L H L L H H L L H H L H L H 85
H H L L H H H H L L H L H H 18 L H L L H H L L L L H H L H 86
H H L L H H H H L L L H H H 19 L H L L H H L L L L L L H L 87
H H L L H H L L H H H L L H 20 L H L L L L H H H H H H H L 88
H H L L H H L L H H L H L H 21 L H L L L L H H H H L L L L 89
H H L L H H L L L L H H L H 22 L H L L L L· H H L L H L L L 90
H H L L H H L L L L L L H H 23 L H L L L L H H L L L H L L 91
H H L L L L H H H H H H H H 24 L H L L L L L L H H H L H L 92
H H L L L L H H H H L L L L 25 L H L L L L L L H H L H H L 93
H H L L L L H H L L H L L L 26 L H L L L L L L L L H H H L 94
H H L L L L H H L L L H L L 27 L H L L L L L L L L L L L L 95
H H L L L L L L H H H L H H 28 L L H H H H H H H H H H H H 96
H H L L L L L L H H L H H H 29 L L H H H H H H H H L L H H 97
H H L L L L L L L L H H H H 30 L L H H H H H H L L H L H H 98
H H L L L L L L L L L L L L 31 L L H H H H H H L L L H L H 99
H L H H H H H H H H H H H H 32 L L H H H H L L H H H L H H 100
H L H H H H H H H H L L H H 33 L L H H H H L L H H L H L H 101
H L H H H H H H L L H L H H 34 L L H H H H L L L L H H L H 102
H L H H H H H H L L L H L L 35 L L H H H H L L L L L L L H 103
H L H H H H L L H H H L H H 36 L L H H L L H H H H H H L H 104
H L H H H H L L H H L H L L 37 L L H H L L H H H H L L L H 105
H L H H H H L L L L H H L L 38 L L H H L L H H L L H L L H 106
H L H H H H L L L L L L L L 39 L L H H L L H H L L L H H L 107
H L H H L L H H H H H H L L 40 L L H H L L L L H H H L L H 108
H L H H L L H H H H L L L L 41 L L H H L L L L H H L H H L 109
H L H H L L H H L L H L L L 42 L L H H L L L L L L H H H L 110
H L H H L L H H L L L H H L 43 L L H H ·L L L L L L L L H L 111
H L H H L L L L H H H L L L 44 L L L L H H H H H H H H L H 112
H L H H L L L L H H L H H L 45 L L L L H H H H H H L L L H 113
H L H H L L L L L L H H H L 46 L L L L H H H H L L H L L H 114
H L H H L L L L L L L L H L 47 L L L L H H H H L L L H H L 115
H L L L H H H H H H H H L H 48 L L L L H H L L H H H L L H 116
H L L L H H H H H H L L L H 49 L L L L H H L L H H L H H L 117
H L L L H H H H L L H L L H 50 L L L L H H L L L L H H H L 118
H L L L H H H H L L L H H H 51 L L L L H H L L L L L L H L 119
H L L L H H L L H H H L L H 52 L L L L L L H H H H H H H L 120
H L L L H H L L H H L H H H 53 L L L L L L H H H H L L H L 121
H L L L H H L L L L H H H H 54 L L L L L L H H L L H L H L 122

H L L L H H L L L L L L H H 55 L L L L L L H H L L L H L L 123
H L L L L L H H H H H H H H 56 L ·L L L L L L L H H H L H L 124
H L L L L L H H H H L L H H 57 L L L L L L L L H H L H L L 125
H L L L L L H H L L H L H H 58 L L L L L L L L L L H H L L 126
H L L L L L H H L L L H L L 59 L L L L L L L L L L L L L L 127

H L L L L L L L H H H L H H 60 L L H L L L L L L L L L H L 128
H L L L L L L L H H L H L L 61 L L L H L L L L L L L L H L 129
H L L L L L L L L L H H L L 62 L L L L H L L L L L L L H L 130
H L L L L L L L L L L L L L 63 L L L L L H L L L L L L H L 131
L H H H H H H H H H H H H H 64 L L L L L L H L L L L H L L 132

L H H H H H H H H H L L L H 65 L L L L L L L H L L L H L L 133
L H H H H H H H L L H L L H 66. L L L L L L L L H L L H L L 134
L H H H H H H H L L L H L H 67 L L L L L L L L L H L H L L 135
..

3·226
 ~t;!CT1UCAt: CHAlIACTERlST1CS
~

-
Each MECL 10.000 _ios circuit hils been
. designed to meet the de specifications
3 MO so 2 -.
Lwrnx
shown in the tnt table. after thermal
equilibrium has been .tabUlhed. The cir-
6 eO
.0' CERAMIC PACKAGE
CUE~O
200
cuit is in a test socket or mounted on a 4 bO ......
printed circuit board and transverse air flow bO'
greater man ouu Imear rpm IS mamtam80.
Outputs are terminated through a 50-ohm
5
9 - co
-
TEST VOLTAGE VALUES
8'
::J
1 4 - Ml ~.
resistor to -2.0 volts. Test procedu res are
Ihown for only .Iected inputs and outputs.
11- ., Volts ::J

Other inputs and outputs tested in the 10- .,' OT ...

Temperatur. VIM ...... VILmin VIHAm;' ViLA ..... VEE
c:
CD
c.
.me mannar. 1 3 - bl
-30"1: -0.890 -1.890 -1.205 -1.500 -5.2
1 2 - bl' C2r-------15
+25o C -0.810 -1.850 -1.105 -1.475 -5.2
+85"1: -0.700 -1.825 -1.035 -1.440 -5.2
Met0287 Test Limits
Pin VOLTAGE APPLIED TO PINS LISTED BELOW,
Un_r -30"1: +25"1: +1Ii"l: (Vee 1
Cherec.... illic Symbol T. . Min M•• Min Typ Max Min M•• Unit VIH ..... VILmin V.HAmi VILA...... VEE GncI

Po.,..r Supply Or.in Current 'E 8 - - - 77 96 - - mAde - - - - 8 16

Input Current 'inH 3 - - - - 200 - - #lAde 3 - - - 8 16

~
- -
!
- - -

!
4 - - 220 - - 4
6 - - - - 265 - - 6 - - -
9 - - - - 410 - - 9 - - -

w lint 3 - - 0:5 - - - - j.lAdc - 3 - - 8 16

~
Logic "1" Output Vottege VOH 1 -1.060 -0.890 -0.960 - -0.810 -0.890 -0.700 Vdc 5.9 - - - 8 16
-
I\J
-.J
Logic "0" Output Volt. VOL
2
15
1
~
-1.890
~
-1.675
~
-1.850
-
-
-
~
-1.650
t
-1.825
~
-t.615
t
Vdc
9
6.9.10
-
-
-
-
-
-
-
-
-
~
8
t
16
2
15 ~ t ~
-
- ~ t t ~
-
-
-
-
-
-
-
- ~ t
Logic "1" Thr..... old VOlt. VOHA 1 -1.060 - -0.980 - - -0.910 - Vdc 6.7 - 9 - 8 16

Logic "0" Thr..... old Vol .... VOLA

2
15
I
t
-
-
-
-1.655
~
-
-
-
-
-
-
-1.630
t
-
-
-
-1.595
t
Vdc
-
6.7.10.11
6.7
-
-
-
4
9
-
-
-
9
t 8
~
16

~
- - -
Switching Tim ..
2
15 - t -
-
-
-
- t +
-
6.7.10.11
-
-
+1.t1 V +0.31 V
-
Pul.ln
4
9 t +
u . . Out -3.2 Vd. +2.0Vdc
Prop. .tion Del-v
(50ohmlo~) '9+15+ 15 - - - 2.0 - - - ns 3 . 9 15 8 16
'6-t- 1 - - - 4.5 - - - 3 6 1
14+2- 2 - - - 3.5 - - - 6 4 2
l4-t+ 1 - - - 4.5 - - - 6 4 1
t11+1_ 1 - - - 3.0 - - - 13 11 1
t13+1- 1 - - - 3.5 - - - 3.9 13 1
t3+1+ 1 - - - 8.5 - - - 9 3 1
t3+15+ 15 - - - 8.0 - - - 9.14 3 15
t14+15+ 15 - - - 8.0 - - - 11 14 15
Ri_Tin.
(20%.080%1 '15+ 15 - - - 2.0 - - - - 3 15
F.U Tin.
(20%.080%1 'ts- 15 - - - 2.0 - - - - 3 15

·Apply +0.31 V to all other inputs.

MC10287 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS" 25°C

Vee - +2.0 Vdc V out

COIX
5~F i t 0.1
Coax

MO SO ~
.0
.0'
bO
bO'
Pul •• Ganerator
51 ~
CO
Ml
Input Pulse .1
t+ = t-:: 2.0 ± 0.2 ns .1'
(20 to 80%1
bl
bl' C2 I - - - -
50-ohm termination to ground 10
c:ated in each scope channel input.

Unused outpl.JU .re tied to a 50-

All input and output cables to the
0,1 ~ ohm resistor to ground.

±
scope are equal lengths of 50-ohm
coaxi,1 cable. Wire length should
be < 1/4 inch from TP in to input
pin and TP out to output pin. Vee' -3.2 Vde

PROPAGATION DELAY

_----~~-:---- +1.11 V

+0.31 V

t+- t-+

3-228
MC10287 (continued)

APPLICATION INFORMATION

: The MC10287 is a stand alone fully iterative dual multi· gram" matrix of the single·bit products (or summands)
Plier' cell. It is intended for use in parallel multiplier can be written:
arrays where maximum speed is desired. Each cell is a
X3YO x2YO xlYO xOYO
modified gated adder/subtractor individually controlled
by a mode select line. Internal carry lookahead (also x3Yl x2Yl XlVI xOYl
called anticipated carry) is used to minimize sum and x3Y2 x2Y2 x 1V2 xOY2
carry out delay times. x3Y3 x2Y3 xlY3 xOY3
. The mode controls are specifically buffered such that
Z7 z6 z5 z4 z3 z2 zl zO
they.c'm be grounded. Normally. MECL 10.000 device
inputs should not be placed at ground to establish a high The MC10287 is used in an array summing the single·
logic level. However. MO and Ml can be used at ground bit products to form the final result. It is observed that
potential for ease of layout in large arrays. the arithmetic product of binary digits Xi and Yi is also the
An array multiplier is defined as a multi· input. multi· logical product (Xi times Yi = Xi AND Vi· The AND
output combinational logic circuit that forms the product function on the operand inputs of the MC10287 forms the
of two binary numbers. Binary multiplication can be single·bit products of the matrix directly and sums them
treated in two categories. that is. simple magnitude multi· internally. For magnitude binary multiplication. the
plication and 4·quadrant multiplication (requiring both MC10287 functions as a dual full adder (MO. Ml are
positive and negative numbers). both low).
The partial product array can be summed using a
MAGNITUDE BINARY MULTIPLICATION number of different techniques. The fastest technique is
some form of matrix reduction scheme that prevents
'.;' Magnitude multiplication consists of the product of
carry propagation until the final level of summation.
two binary numbers in which all digits are number bits
Several of these schemes are discussed in detail in
(no sign bit). Magnitude representation then includes only
Reference 1.
positive numbers.
As an example. if the matrix is rearranged and written
Thus. for a 4·bit number X the representation is:
in a different form:
X=X3 x2 Xl xO xOY3
A 4-bit by 4-bit product becomes: xlY3 x3YO x2YO xlVO xOYO
Z = X. Y = (X3 x2 Xl xO) • (Y3 Y2 Yl YO) x2Y3 x3Yl x2Yl xlYl xOYl
x3Y3 x3Y2 x2Y2 xlV2 xOY2
The product consists of the sum of the single· bit prod-
ucts formed by this expression. The standard "parallelo- Z7 z6 z5 z4 z3 22 zl zO

TA8LE 1 - TYPICAL MUL TIPL Y TIME FOR AN n-BIT BY FIGURE 1 - 4-BIT BY 4-BIT MAGNITUDE ARRAY MUL TIPLIER
n.aIT BINARY MAGNITUDE ARRAY MULTIPLIER

Total Multiply Time

Number of Bill Inll
4 14
B. 25
12 39
lB 44

"0

3-229
Me 10287 (continued)

The summation of the partial products for this con·
figuration is shown in Figure 1. The number of MC10287's
for an n·bit by n·bit array is n (n·l)/2. Note also that the
least significant product bit (ZO = xOYOI is formed by an
individual AND gate (negative logicl.
Table 1 gives package count and typical multiplication
in which all inputs are positive quantities. If one input is
negative (such as 8). the outputs Cout and S must be
coded such that they can represent the 4 possible output
conditions. If 8 can be a negative one or zero, .tha-~
output can then be:

I
times for n·bit by n·bit magnitude multiplier arrays. The -~
mUltiply times do not include wiring delays, and the net output =
+1
package count does not include the gate for the least +2
significant product bit.
If Cout, whose weight is twice that of S, is assigned,
FOUR·QUADRANT MULTIPLICATION positive value and S is a negative value, the above vllu.is
can be represented: .;
Sign·magnitude and 2's complement representations
are commonly used for 4·quadrant multiplication. For net output = 2 • Cout - S
sign·magnitude representation, the binary word consists of where:
a sign bit and magnitude bits which indicate the absolute -1 = 0 - 1
value of the number. For a 4·bit example: 0= 0-0
X= Xs x2 Xl xo +1= 2-1
For X. y= Z +2= 2-0
Z = X • Y = (xs x2 Xl xOI • (Ys Y2 Yl YO) If the truth table is written and logic equations gen8/)
An array multiplier for this representation consists of ated, the result is a subtractor. That is, a subtractor uS8Cf
an (n·l)·bit by (n·l)·bit magnitUde multiplier that pro· in place of a full adder produces the proper outputs. The
duces the product of the magnitude bits of X and Y and symbol for the subtractor is: .
of logic that produces the proper product sign bit
A
(zs = Xs @Ys)'
2's complement representation also inclUdes a sign
bit which is a negative bit. That is: ! /-B
X = -x3 x2 Xl xo
G-Cin
where x3 is the sign bit. The product of two 4·bit 2's
complement numbers becomes:
Z = X. Y = (-x3 x2 Xl xO). (-Y3 Y2 Yl YO)
co: ~ -5
The matrix for this expression is:
Also, if the input variables are multiplied by -1, the
-x3YO x2YO xlVO xoyo outputs also are multiplied by -1. Thus, the following
x2Yl xlYl xOYl devices are equivalent:
x1V2 x OY2
A -A

-Z7 z6 Z3 zO
! /B 1/--
G--Ci;'
The product is the sum of this array of single·bit
products. However, notice that several summands are nega· 8- C ;n

tive quantities. Therefore, they can not be simply added

as is the magnitude binary multiplier. The subtraction
capability of the MC10287 is utilized when considering
these negative quantities.
c:U: ~
5
.C:: ~
-5

A standard full adder is symbolized as:

A A -A

! /a ! /-B ! /-
G_-C
G-C;n G-C;n in

c:U: ~ C; ~ ~~ 5
5 -5

3·230
 MC10287 (continued)

A basic adder/subtractor can then handle all the varying IMPROVED SWITCHING DELAYS
situations that appear in the multiplication matrix. The specified ac switching delays are given for output
If the 2's complement matrix is rearranged: loading of 50 n to -2 volts. With lower output current,
-xOY3 propagation delavs will be improved and decreased multi·
-X1Y3 -x3VO x2YO xlVO xOYO ply times can result. For output loading of 1 kn to VEE,
-x2Y3 -x3Yl x2Yl xlVl xOYl the following delavs are typical.
x3Y3 -x3Y2 x2Y2 xlV2 xOY2 Input Output Delay (ns)
-z7 z6 z5 z4 z3 z2 Zl zO CO C2 1.7
AO C2 2.8
The adder/subtractor array for this configuration is AO SO 2.8
shown in Figure 2. Care must be taken to insure that the BO SO 3.1
proper mode of operation (add or subtract) appears at AO 51 3.9
each summing node as a function of the positive and BO 51 4.4
negative weighted inputs. MO 51 8.7
The summand matrix can be altered different ways to
speed up the multiplier array. Reference 2 discusses the
algorithm used with the MC10287 in detail. Also, the
techniques of Reference 1 also apply to 2's complement REFERENCE AND ACKNOWLEDGEMENT
arrays using the MC10287. The techniques for implementing the MC10287 in
Table 2 gives typical multiply times for 2's complement multiplier arrays resulted from work done originally at
arrays for n'bit by n-bit multipliers. M.I.T. Lincoln Laboratories. Also, applications information
presented here developed in part from personal corres-
TABLE 2 - TYPICAL MULTIPLY TIME FOR AN n-BIT BY pondence with P. Blankenship of Lincoln Labs. The
n·BIT 2'.CO~LEMENT ARRAY MULTIPLIER following references are useful in developing multipliers
using the MC10287:
Total Multiply Time
1. A. Habibi and P.A. Wintz, "Fast Multipliers," IEEE
Number of Bits (ns) Package Count
Trans. Computers (Short Notes!. Vol. C·19, Feb.
4 14 6 1970, pp. 153-157.
8 25 28 2. S.D. Pezaris, "A 40-ns 17-Bit by 17-Bit Array
12 39 66 Multiplier", IEEE Trans. Computers, Vol. C·20,
16 44 120
Number 4, April, 1971, pp. 442-447.

FIGURE 2 - 4-BIT BY 4-BIT 2'. COMPL EMENT ARRAY MULTIPLIER

'0

3-231
~f
') MECL 10,000 series
QUAD OR/NOR GATE

~---------'
MC10501

The MC10501 is a quad 2·input OR/NOR

gate with one input from each gate common to
pin 12 in the L package and pin 16 in the F
POSITIVE LOGIC NEGATIVE LOGIC package. Input pulldown resistors eliminate the
need to tie unused inputs to an external supply.

(81 4·· ...----...--~- 2 (6) (8) 4 2 (6)

. / " - - - 5 (9) r--L-~~--5 (9)

(11) 7-'L---r---"'-~-3 (7) (11) 7 3 (71

..--~~~--6 (10) "---L-~~--6 (10)

(14)10 ...L--<:",-"",,,,,,_ _ 14 (2)

. - - , - - _ , , - - - 11 (15)
Po = 25 mW typ/gate (No Load)
(1)13 15(3)
tpd = 2.0 ns typ
(16) 12 _ _--.'---'_ _ _ 9 (13) _ - , - _ . / " - - _ 9 (13) Output Rise and Fall Time:
= 3.5 ns typ (10% - 90%)
= 2.0 ns typ (20% - 80%)
Numbers at ends of terminals denote pin numbers for L package
(Case 620).
Numbers in parenthesis denote pin numbers for F package
(C .... 6501.

CASE VCC1 VCC2 VEE

620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25 0 C

vee1 = VCC2 V out V out

+2.0 Vdc NOR OR

Coax Coax Coax

PROPAGATION DELAY
50 50
Input

Pulse Generator +1.11 V

50%
Input Pulse ' -_ _....J_ ---+0.31 V
t+ = t- = 2.0±. 0.2 ns
(20 to 80%)
t++
Unused outputs
connected to a
V out OR
100.ohm resistor
to ground.

50 ohm termination to ground 10

L_~_ @x_--o I~F ,...
V aut NOR

cated In each scope channel Input

All Input and output cables to the -32 Vdc

~~~~~a~:·a:~81~~~!tl~~;:h5~~~~~ VEE
be <114 inch from TP in to input
pin and TP out to output pin. V out
is 2: 1 attenuated.

See General Information section for packaging.

3-232
 ELECTRICAL CHARACTERISTICS
3:
Each full tamperatura range MECL 10,000
...
o
4~2
series circuit has been designed to meet the 5
de specifications shown in the test table,
~
o...
7 3

-
after thermal equilibrium has been astab--
lished. The circuit is in a test socket or
mounted on a printed circu it board and
10 ~4 L SUFFIX

transverse air flow greater than 500 linear

fpm is maintained. Outputs are terminated
13
11
15
CERAMIC PACKAGE
CASE 620 8
::J
through a 1~ohm resistor to -2.0 volts. 12 9 e.
Test procedures are shown for only one ::J
C
gate. The other gates are tested in the CD
same man ner. 0.

TEST VOLTAGE VALUES

CVoIt.1
ttT...
T ........tur. VIHmn VILmin VIHA min VILA meK VEE
-liIi"c ~.880 -1.920 -1.255 -1.510 -5.2
+:zsoC ~.780 _1.850 -1.106 _"'75 -5.2

MC101i01L T . . Lim.
+126"c ~.83O -1.820 -1.000 -"'00 -5.2

P,n TEST VOLTAGE APPLIED TO PINS LISTED BELOW:

Co)
CherKt..istic
POwer Supplv Or8.n Current
Sy .....
IE
Unci.
Tnt
8
M;.
-
-li6"c
Max
29
Min
-
+25o C
Typ
20
M_
26
Mi.. ....
+125Oc

29
IJn;t
mAde
VIHmu
-
VILmin
-
VIHAmin
-
VILAmla
-
VEE
8
IVeel
GncI
1,16
~ Input Current l.nH 4 - 450 - 265 - 265 "Adc 4 - - 8 1,16
Co)
Co) 12 - 910 - - 536 - 536 ",Adc 12 - - - 8 1,16
- 0.5 - - - - 4 - - 8
l.nL 4
12
0.5
0.5 - 0.5 - -
0.3
0.3 -
,.,Adc
.Adc - 12 - - 8 !:!: I
Logte "',. VOH 5 -UJ80 ~.880 -0.930 ~.780 -0.825. ~.830 Vdc 12 8 1,16
-- -
+ ~
-
~ ~ + ~
Output Voltage 5 4
2 ..
- - -

• • •
2 - - - - -
LogiC "0" VOL 5 -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc - - 8 1,16
Output Voltage 5 - - - - -
2 - 12 - - -
+ +
+ + + -
+ + +
• - - -
2 4
logic "'" VOHA 5 -1.100 -0.950 - -~.845 Vdc - - 12 8 1,16
- - - - - -
~
Threshold Vol lege 5 .. 4
2 - - - - - .. - 12
+ + - + +
•
2 - - - - - 4
Logic "0" VOLA 5 1.635 -1.600 -1.525 Vdc 12 8 1.16
Threshold Voll. 5 - - - - - - - 4
2 - - - - - - 12 -
+
+ +
• • •
2 - - - - - .. 4 -
Switching Times
I1,QO-ohm la.jl Pu"'n PuI.Out -3.2 V +2.0 V
Propagation Delay t4+2- 2 1.0 3.7 1.0 2.0 2.9 1.0 3.7 n, - - 4 2 8 1,16
2 - - 2

I
l4-2+

I II
14+5+ 5 - - 5
+ + +
j j +
j
'4-5- 5 - - 5
Rise Time '2+ 2 4.0 1.1 33 40 - 2
12010_' '5+ 5 - - 5
Fall Time
12010_1
'2_
's-
2
5
+ + ~ +
-
-
-
-
2
5
 ELECTRICAL CHARACTERISTICS s:
B~6~ ....oo
Each full temperature range MECL 10,000
series circuit has been designed to meet the 11.
de specifications shown in the test table,
10 C1'I
after thermal equilibrium has been estab-
14 2 o....

~
lished. The circuit is in a test socket or
15
mounted on a printed circuit board and
1 3
transverse air flow greater than 500 linear
16 13 8:::J
fpm is maintained. Outputs are terminated
throu~ a l00-ohm resistor to -2.0 volts. F SUFFIX ....
CERAMIC PACKAGE
5'
Test procedures are shown for onlv one t:
gate. The other gates are tested in the
~
CASE 650
same manner.

reST VOLTAGE VALUES

I
(Voltsl
@T ...
T ernperatu,e VIH",,, Vll min VIHA min VILAma. VEE
-55"<: -0.830 -1.920 -1.255 -1.510 -5.2
+25o C -0.720 -1.850 -1.105 -1.475 -5.2
+ 125°C -0.580 -1.820 -1.000 -1.400 -5.2
MCl0501F T_ Limits
Pin reST VOLTAGE APPLIED TO PINS LISTED BELOW:
-55"<: +2SoC + 125°C
Unci. IVeel
Charact",istlc Symbol Test Min M.. Min TV. M.. Min M.. Unit VIHmaJ( VIL mm VIHA min V,LA ma. VEE GncI
(.) Power Supply Dram Current 'E 12 - 29 - 20 26 - 29 mAdc - - - - 12 4.5
~ Input Curren I ImH 8 - 450 - 265 - 265 ,..Adc 8 - - - 12 4.5
~ ImL
16
8
-
0.5
910
-
-
0.5
- 535
-
-
0.3
635 /oIAdc
i,.!Adc
16 -
8
-
-
- 12
12
4.5
4.5
16 0.5 - 0.5 - - 0.3 - .Ad, - 16 - - 12 4.5
logIC "1" VOH 9 -1.080 -0.830 -0.930 - -0.720 -0.825 -0.580 Vd, 16 - - 12 4.5
- -
~
- -
~ ~ ~ ~
Oulpul VOltage 9 8
6 - - - - -
6
+ - + - - - -
+ +
LogIC "0" VOL 9 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc: - - - - 12 4.5
- -
~
- -
~
Output Voltagt! 9 -
6 - 16 - - -

Loglc'T' VOHA
6
9 -1.100
+
- +
-0.950
-
- +
- -0.845
+
-
+
Vd,
8
-
-
-
-
16
-
-
+
12
+
4.5
-
~
Threshold Voltage 9 - - - - - 8 -
6 - - - - - - - 16
+ - - - + - + - - -
+
•
6 8
LogIC "0" VOLA 9 -1.635 -1.600 - -1.525 Vd, - - 16 12 4.5
- - - - - - -
~ ~ ~
Threshold Voltage 9 8
6 - - - - - - 16 -
SWltchulg Tlme~
6 - - - - + - - 8 -
+ +
(l00-ohm load) Pulse In PuI.Out -l.2V +2.0V
Propagation Delay t8+6- 6 - - 1.0 2.0 2.9 - - 0, - - 8 6 12 4.5
18-6+ 6 - - - - - - 6

lj
t8+9+ 9 - - - - - - 9
9 - -
+ + - - - -

j
9

j j
t8-9-
RlseTlmt! 16+ 6 - - 1.1 3.3 - - - - 6
(2Ot08O%J 19+ 9 - - - - - - 9
Fall Time
(2010_1
16-
~~ ---
8
9 -
-
~. ~ -
-
-
-
-
- ---- L-
-
- -
6
9
 "') MEeL 10,000 series
QUAD 2-INPUT GATE \..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

MC10502

The MC10502 is a quad 2-input NOR gate.

Input pu IIdown resistors elim inate the need to
tie unused inputs to an external supply.
POSITIVE LOGIC NEGATIVE LOGIC

:~2 :~2
(8) (8)
(6) (6)
(9) (!l)

~~3 ~~3(7)
(10) (10)
(7)
(11) (11)
(14)
10~ 14 (2)
(14)
10~_14(2)
(15) 11 (15) 11~ Po'" 25 mW tvp/gata (No Load)
tpd = 2.0 ns tvp
(16) 12~15 (3) (16) 12~15(3)
Output Rise and Fall Time:
(1) 13 9 113) 11) 13~9(13) = 3.5 nstyp (10% - 90%)
= 2.0 ns typ (20% - 80%)

Number. at end. of terminals denote pin number, for L package

(C... 6201.
Numbers in parenthesis danote pin numbers for F package
(C ... 660>-

CASE VCCI VCC2 VEE

620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS@ 25°C

VCCI = VCC2
+2.0 Vdc V out NOR V out OR

Coax Coax Coax

50 50
Input PROPAGATION DELAY

Pulse Generator

Input Pulse
't+ = t- = 2.0 ±. 0.2 ns
(20 to 80%)

C_--f1:'~'
Unused outputs
V out OR
connected to 8
100-0 h m reli stor
to ground.

50-ohm termination to ground lo-

L3fvdC V out NOR
cated in each scope channal input.
All input and output cables to the
scope are equa' lengths of 50-ohm
coaxial cable. Wire length should
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated.

See General Information section for packaging and maximum ratings.

3-235
 ELECTRICAL CHARACTERISITCS
s:
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
...nc
after thermal equilibrium has been estab· :~2 C1I
C

-
lished. The circuit is in 8 test socket or
N
mounted on a printed circuit board and
~~3
transverse air flow greater than 500 linear
10~ 8
fpm is maintained. Outputs are terminated
through a 1~ohm resistor to -2.0 volts.
Test procedures are shown for only one
11
12~15
" ...3'
:::J

gate. The other gates are tested in the 13~9 L SUFFIX c:

no
same manner. CERAMIC PACKAGE
~
CASE 620

TEST VOLTAGE VALUES

IVoIts)
lilT...
Temperatur. VIH m.x VIL min VIHA min VllAm•• VEE
-SS"C -0.830 -1.920 -1.255 -1.510 -5.2
+25o C -0.720 -1.850 -1.105 -1.415 -5.2 I
+125 0 C -0.580 -1.820 -1.000 -1.400 -5.2
MC10502L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
U..... -SS"C +2SoC +t25°C 1Veel
w Chllract.-istic Symbol T... M;n M. . Min TV. Max Min M. . Unit VIH malIC VILmin VIHA min VllAmn VEE Gnd
r() - -
w Power SupplV Drain Current 'E 8 29 20 26 - 29 mAde - - - - 8 1,16
en Input Current linH 12 - 450 - - 265 - 265 j,lAdc 12 - - - 8 1,16
IlnL 12 0.5 - 0.5 - - 0.3 - j.lAdc - 12 - - 8 1,16

Logic "'" VOt< 9 -1.080 -0.830 0.930 -0.720 -0.825 -0.580 Vd, 12 8 1.16
- - - -
~ ~
Output Voltage

~
13

~
9
15 - - - - -
Logic "0" VOL
15
9 -1.920 -1.655
+
-1.850
-
-
+
-1.620 -1.820 -1.545
+
Vd,
-
-
-
-
-
-
-
-
+8 +
1,16
- -
~
- - -
~ ~
Output Voltage 9
15 - 12 - - -
+ +
Logic "'" VOHA
15
9
+
-1.100 -
-
+
-0.950
-
-
-
-
-
-0.845 -
-
Vd,
13
-
-
-
-
-
-
12
-
-
- • •
8 1,16

~
Threshold Voltage 9 13
15 - - - - - - - 12
15 - + - - + -
+ - - - 13
+ +
logic "0" VOLA 9 - -1.635 -1.600 -1.525 Vd, - - 12 8 1,16
- - -
~
- - -
~
-
~
Threshold Voltage 9 13
15 - - - - - - 12 -
- + +
•
15 - - - - - 13 -
Switching Times
(lOO-ohm loedl Pulse In Put. Out -3.2V +2.0V
Propagation Delay 112+15_ 15 1.0 3.1 1.0 2.0 .. 2.9 1.0 3.1 n, - - 12 15 8 1.16
- -
~
112-15+ 15 15
'12+9+ 9 - - 9

Rise Time
'12-9-
'15+
9
15
j +
4.0
• j
1.1
+
33
j 4.0
j
-
-
-
-
-
- j
9
15
j j
~ ~
(20'0_1 '9+ 9 9
Fall Time '15- 15 - - 15
(20 to 8II%J '9- ~ + + - - 9
 3!:
ELECTRICAL CHARACTERISTICS n
....
Each full temperature range MEeL 10,000
:~6
~

;
series circuit has been designed to meet the
,O~,
de specifications shown in the test table,
after thermal equilibrium has been estab- "~
o
N
lished. The circuit is in a test socket or '4~ 2
mounted on a printed circuit board and
transverse air flow greater than 500 linear
,.~
'6~3
8::l
fpm is maintained. Outputs are terminated 1_~13 ~,
:J
through a 10~ohm resistor to -2.0 volts. c::
Test procedures are shown for only one
gate. The other gates are tested in the
F SUFFIX
CERAMIC PACKAGE
a
same manner. CASE 650

rEST VOLTAGE VALUES

(Voltsl
"'Tnt
T emperatur. VIHmn Vilmin VIHA min VILA mill VEE
-55"<: r-- -0.880 -1.920 -1.255 -1.510 -5.2
+2So C -0.780 -1.850 -1.105 -1.415 -5.2
+12SoC -0.630 -1.820 -1.000 ·1.400 -5.2
MCt0602F Telt Lim"s
w Pin
-SSOC +25 o C + 125°C
TEST VOL rAGE APPLIED TO PINS LISTED BELOW:
N
w CNiract.i5tic Svmbol
Und ..
Te.. Min M.. Min Typ M.. Min M.. Unit VIHmiJ_ VIL min VIHA min VILA m.x VEE
tVeel
Gnd
...... Power Supply Drarn Current 'E 12 - 29 20 26 - 29 mAde - - - - 12 4,5
Input Current IlnH 16 450 - 265 265 j.lAdc 16 - - - 12 4,5
IlnL 16 0.5 - 0.5 0.3 j.lAdc - 16 - - 12 4,5
logic "1" VOH 13 -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vd< '6 - 12 4,5
Output Voltage 13 - 1 - - -
3 - - - - -
- + + +
• • + - - -
•• •
3 -
logic "0" VOL 13 -1.920 -1.655 -1.850 - -1.620 1.820 -1.545 Vd< - - - - 12 4.5
Output Voltage 13 - - - - -
3 - 16 - - -
- + - - + +
• • • • • •-
3 1 -
logic "1" VOHA 13 -1.100 -0.950 -0.845 Vd< - - 16 - 12 4.5
Threshold Voltage 13 - - - - - 1 -
3 - - - - - - - 16
+ - - - - + - - - + +
• •
3 I
LogiC "0" VOLA 13 -1.635 -1.600 -1.525 Vd< - - - 16 12 4,5
Threshold Voltage 13 - - - - - - - 1
3 - - - - - - 16 -
- + - + + +
• • - - -
3 - 1 -
SWitching Times
(100ohm loadl Pulse In PuI_Qut -J.2V +2.0 V
Propagation Delay t16+3- 3 - - 10 20 29 - - 0, - - 16 3 12 4,5
3 - - - - - -

I
'16+3+ 3
t16+13+ 13 - - - - - - 13
- - + + - - - -
j j j
13

j
t16+13- 13
Rise Time
1201080%)
'3+
t13+
3
13
-
-
-- 1.1 3.3 -
-
-
-
-
-
-
-
3
13
Fall Time '3_ 3 - - - - - - 3
120 to 80%) t13-
-
13 - - + + - - - I - 13
 QUAD 2·INPUT AND GATE MECL 10,000 series

MC10S04

The MC10504 provides a very useful low power, high

Po = 35 mW typ/gate (No load)
tpd '" 2.7 ns tYP
Output Rise and Fall Times'
= 3.5 ns typ (10% - 90%)
= 2.0 ns typ (20% - 80%)
POSITIVE LOGIC
(8)4~
(9)5~216)
speed logic AND function. High Z input pulldown resistors
allow high dc and ac fanouts and eliminate the need to
tie unused inputs to an external supply. The open emitter
outputs allow maximum flexibility in the selection of ter·
mination techniques and minimize the power requirements
when driving transmission lines. Open emitter outputs
also allow wire·ORing capability, which is very useful in
control, bussing, and communications in high speed central
~
processors, high speed peripherals, digital communication
systems, minicomputers and instrumentation.

(10)6~3 (7)
1111 7 NEGATIVE LOGIC
(14)10~ ~14(2)
(15)11~ 18)54~ ~2(6)
(16)12~9113)
(9)~
1')'3~'513) 110) 67~- '~317)
(11)~
Numbers at ends of terminals denote pin numbers for
L package (Case 6201.
114)10~1 (2)
115) 11
Numbers in parenthesis denote pin numbers for
116)12~9113)
F package (Case 6501.
(1)13~1513)
CASE

620 Pin 1 Pin 16 Pin 8

650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

Vin veel V CC2 V out V out

To Channel "A" t2.0 Vdc NAND AND

PROPAGATION DELAY
To
Channel
"8"
Input

Pulse Generator
50 50

Input Pulse
tt '" t- =- 2.0 ! 0.2 ns
(20 to 80%)

I I
L ____ ...J
+1.11V~

I
~1:
Unused outputs connected to
O.ljJF
a 1 aD-ohm resistor to ground.
0 1 ~F
50 ohm termmatlon to
ground located in each
VEE -3.2 Vdc
scope channel Input
All input and output cables to the scope are equal lengths of 50-ohm coaxial cable.
Wire length should be <
1/4 inch from TPin to input pin and TP out to output pin.
V out is 2: 1 attenuated.

See General I nformation Section for packaging and maximum ratings.

3-238
 3:
ELECTRICAL CHARACTERISTICS
o
~

-
:~2
Each MECL 10.000 series has been de·
U'I
signed to meet the de specifications shown
in the test table, after thermal equilibrium L SUFFIX
o
:~3
.1=0
has been established. The circuit is in a CERAMIC PACKAGE
test socket or mounted on a printed circuit
board and transverse air flow greater than
,o~ _ CASE 620 8::J
11~14
~ Imear rpm IS maintained. Outputs are
- ~.
terminated through a 1()()..ohm resistor to 12~9 TEST VOLTAGE VALUES ::J
13 15 c:
-2.0 volts'- Test procedures are shown for (Volts) (!)

only one gate. The other gates are tested @Test

c..
in the same manner. Temperatur. VIHme. VILmin VIHAmin VILAmax VEE
_55 0 e -C.880 -1.920 -1.255 -1.510 -5.2
+25o C -C. 780 -1.850 -1.105 -1.475 -5.2
+1250 e -0.630 -1.820 -1.000 -1.400 -5.2
MCl0504L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Under -550 e +2SoC +1250 e (Vee)
Characteristic Symbol Test Min Max Min Typ Max Min Max Unit VIHmax VILmin VIHAmin VILAmax VEE' Gnd
Power Supply Drain Current Ie 8 - 39 - 28 35 - 39 mAde - - - - 8 1.16
I "out Current I· 13 450 265 - 265 ..Adc 13 - - - 8 1.16
12 375 220 220 ",Adc 12.13 - - 8 1,16
linL 12 0.5 - 0.5 - - 0.3 - ",Adc - 12' - - 8 1,16
w
~
Logic "I" VOH 9 -1.080 -0.880 0.930 - -0.780 -0.825 -0.630 Vdc - - - - 8 1,16
Output Voltage 9 - 12 - - -
W
CO 9
15
+ t t -
-
+ + t' ~ 13
12,13
-
-
-
-
-
- t
Logic "0"
Output Voltage
VOL 9
15
-1.920 -1.655 1.850 -
-
-1.620 -1.820 -1.545 Vdc 12,13
-
-
-
-
-
-
- •
8 1,16

Logic "I" VOHA

15
15
9
t
-1.100 -
+ 0.950
t -

- -
t t -C.845
+
-
t
Vdc
13
12
12
-
-
-

-
-

13
t t
8 1,16
Threshold Voltage 9 - - - -
~
- -

i ~
13 12
15
15
-
- t -
-
-
- t -
-
12
13
-
-
13
12
-
-
Logic "0" VOLA 9
•
- -1.635 - -
-
-1.600 -
-
-1.525 Vdc 12 - 13 - 8 1,16

~
Threshold Volt_ 9 - - - -

i
13 12

Switching Times-
15
15
-
-
-

-
-
- t -
-
+
12
13
+1.11 V
-
-
-
-
Pulse In
13
12
purse Out
+
-3.2 V
t
+2.0 V
(l00-ohm load)
Propagation Dalay 112+9- 9 - - 1.0 2.2 4.0 - - ns 13 - 12 9 8 1,16
9 - - - - - 9

~
112-9+
112+15+
112-15-
113+9+
15
15
9
15
-
-
-
-
-
-
-
-
j t 2.7
2.7
-
-
-
-
-
-
-
-
12
-
-
-
-
t
13
15
15
9
113+15- 15
Rise Time
(20%1080%)
Fall Time
(20%1080%)
19+
tl5+
19-
115-
9
15
9
15
-
-
-
-

-Inputs 4, 7, 10, and 13 will behave similarly for ac and I inH values.
Inputs 5, 6, 11, and 12 will behave similarly for ac and linH values.
-
-
-
-
1.5

t ~
2.0 3.5

t
-
-
-
-
-
-
-
-
j
-
-
-
- l 9
15
9
15
 ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000 s:
seriescircuit has been designed to meet the 8~ -6
FSUFFIX
o....
9o-~
de specifications shown in the test table,
after thermal equilibrium has been estab- 10~_
CERAMIC PACKAGE o
11~7
~ ~
CASE 650
lished. The circuit is in a test socket or
mounted on a printed circuit board and
14~ -2 ~
transverse air flow greater than 500 linear 15~
fpm is maintained. Outputs are terminated
through a 100-ohm resistor to -2.0 volts. 16~13 TEST VOL TAGE VALUES
8
::J
1 3 IVoltsl ~.
Test procedures are shown for only one ::J
gate. The other gates are tested in the @Test c:
same manner. Temperature
-550 e
VIHmax
-0.880
VILmin
-1.920
VIHAmin
-t.255
VILAma.
-1.510
VEE
-5.2
a
+2SoC -0.780 -1.850 -1.105 -1.475 -5.2
+12SoC -0.630 -1.820 -1.000 -1.400 -5.2
MCl0504F Test Limits
Pin TeST VOL TAGE APPLIED TO PINS LISTED aELOw:
-55 O e +2SoC +12SoC IVee)
Under
Characteristic Symbol Tes. Min Ma. Min TVp Ma. Min Ma. Unit VIHmax VILmin VIHAmin V.LAme. VEe Gnd
Power Supply Dram Current 'e 12 39 - 28 35 - 39 mAde - - - - 12 4.5
Input Current ImH 1 450 265 265 ,....Adc 1 - - - 12 4.5
16 - 375 - 220 - 220 ,....Adc 1,16 - - - 12 4.5
linL 16 0.5 - 0.5 - 0.3 - ,....Ade - 16 - - 12 4,5
Logic "1" VOH 3 -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vdc 1,16 - - - 12 4,5
- - - - -

i t ~ ~ ~ ~
Output Voltage 13
w
~
o Logic "0" VOL
13
t3
3 -1.920 -1.655 -1.850
-
-
- -t.620 -1.820
i
-1.545 Vdc -
1
16
-
-
-
-
-
-
-

-
- t ~
12 4,5
- - -

~
Output Voltage

~ t
3 1

Logic "1" VOHA

3
13
3 -1.100
t i - -0.950
t -
-
-
!
- -0.845 - Vdc
+
16
1,16
1
-
-
-
-
-
16
-
-
- 12
+
4.5
-

~
Threshold Voltage 3 - - 16 - 1

Logic "0"
13
13
3 -
t -
-1.635 -
-

-
-
-
-1.600 -
t -1.525
-
-
Vdc
t 1
16
16
-
-
-
-
-
-
16

1
1 t t
12 4,5
VOLA
-
t ~
-
~
- -

i
Threshold Voltage 3 - 1 16
13
13
-
-
+
- -
t 16
1
+1.11 V
- 1
16
Pulse In
-

Pulse Out -3.2 V +2.0 V

Switching Times·
(100-ohm load)
Propagation Delay t16+3+ 3 - - 1.0 2.2 4.0 - - ns 1 - 16 3 12 4,5
'16-3- 3 - - - - - 3
'16+13-
'16-13+
'1+3:-
13
13
3
-
-
-
-
-
- j t 2.7
j
-
-
-
-
-
-
t
16
-
-
-
t
1
13
13
3
t1+13+ 13 - - 2.7 - - - 13
-
j
-

j
Rise Time '3+ 3 - - 1.5 2.0 3.5 - 3
- - - - -
~
(20%'08O%) 13 13

~ !
t13+
Fall Time '3_ 3 - - - - - 3
(20% '0 80%) '13_ 13 - - - - - 13

• Inputs 1.. 8 .. 11 and 14will behave similarly for at and linH yalues_
Inputs 9,10,15 and 16 will behave similarly for ec and linH yaJues_
 MECL 10,000 series
TRIPLE 2·3-2 INPUT
OR/NOR GATE

MC10SOS

The Me 10505 is a triple 2-3-2 input gate.

Input pulldown resistors eliminate the need to
tie unused inputs to an external supply.
POSITIVE LOGIC NEGATIVE LOGIC

18)4~317) (8)4~3(7)
(9)5~2(6) (9)5~2(6)
113)9~ (10) (13)9~ 6 (10)
(14) 10 ~ (11) (14)10 7 (11)
(15) 11 (15) 11
(1)13~14(2) (1)13~14(2) Po = 30 mW typ/gate (No Load)
(16)12~15(3) (16)12~15(3) tpd '" 2.0 ns typ
Output Rise and Fall Time
== 3.5 ns typ (10% - 90%)
== 2.0 ns typ (20% - 80%)

Numbers at ends of terminals denote pin numbers for L package

(C. . . 620).
Numbers in parenthesis denote pin numbers for F package
(Case 650).

CAse VCCI VCC2 Vee

620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@250 C

Vee 1 = Vee2
+2.0 Vdc V out NOR V out OR

~",t ii""'
r--- ---,
Coax

50 50
Coax

PROPAGATION DELAY

Input Pulse Unused outputs

t+ "" t- = 2.0 ±. 0.2 ns connected to a
(20 to 80%) 1QQ<thm resistor
to ground.

L---Ff~,:'
1-:!
V out OR

50 ohm '.,monotton '0 .,ound 10- Vdc

cated in each scope channel input. VEE
All input and output cables to the
scope are equal lengths of 50-ohm V out NOR
coaxial cable. Wire length should
be <1/4 inch t.rom TP in to input
pin and TP out to output pin. V out
is 2: 1 attenuated.

$" Genar.1 I nformation section for peck aging.

3-241
 3:
(")
~

o
c.n
~
ELECTRICAL CHARACTERISTICS
n-
O
Each full temperature range MECL 10.000
.... ies circuit has been designed to meet the
4~3
=.
::J
::J
de specifications shown in tne test table,
.~, c::
(I)

,:~~
Co

-
after thermal equilibrium has been estab-
lished. The circuit is in test socket or
8
,,~
mount.. on a printed circuit board and
transverse air flow greater than 500 linear 13~14
L SUFFIX
fpm is maintained. Outputs are terminated 12~15
CERAMIC PACKAGE
through I l00-ohm resistor to -2.0 volts. CASE 620
Test procedures are shown for only one
gate. The other gates are tested in the
same manner.

TEST VOLTAGE VALUES

(Volts)
to) ~T ...

~ Temperatur. VIH mu vlLmin VtHA min VILAm. . VEE

~ -55"C -0.880 -1.920 -1.255 -1.510 -5.2
~
+25o C -0.780 -1.850 -1.105 -1.475 -5.2
+125"C -0.630 -1.820 -1.000 1.400 -5.2
MC10505L Tnt Limits
Pi" TEST VOL TAGE APPLIED TO PINS LISTED BELOW;
U_ -65"C +2SoC +12So C 1Veel
Characteristic $vonbol Test Min M_ Min Typ M.. Min Max Unit VIHmu. VIL min VIHAmin VILA m •• VEE Gnd
Power Supply Drain Current 'e 8 - 24 - 11 21 - 24 mAd, - - - - 8 1,16
Input Current linH 4 - 450 - - 265 - 265 ~Adc 4 - - - 8 1,16
linL 4 0.5 - 0.5 0.3 ~Adc 4 8 1,16

Logic "'"
Output Voltage
VOH 3
2
-1.080 0.880
-1.080 -0.880
-0.930
-0.930 -
-0.780
-0.780
0.825 -0.630
-0.825 -0.630
Vd,
Vd, 4 - -
-
-
8
8
1.16
1.16
Logic "0"
Output Voltage
VOL 3
2
-1.920 -1.655
-1.920 -1.655
-1.850
-1.850
-- -1.620
-1.620
-1.820 -1.545
-1.820 -1.545
Vd,
Vd,
4
-
-
-
-
-
-
-
8
8
1.16
1.16
Logic "1"
Tt-Iresnold VOltage
VOHA 3
2
-1.100
-1.100
-
-
-0.950
-0.950
-
- -
-0.845
-0.845
-
-
Vd,
Vd,
-
-
-
- 4 -
4 8
8
1.16
1,16
logic "0" 3 - -1.635 ~1.600 - -1.525 Vd, - 4 - 8 1,16
Tt-I,eshold Voltage
Switching Times
VOLA
2 - -1.635 - - -1.600 - -1.525 Vd, - - - 4 8 1,16

(l()().ohm load) Pulse In Pulse Out -3.2V +2.0V

Propagation Delay t4+3-
14-3+
3
3
1.0 3.7 1.0 2.0 2.9 1.0 3.7 n, -
-
-- 4 3
3
8 1,16

I! I ! I I I
t4+2+ 2 - - 2
14-2- 2
+ + + + - - 2
Rise Time '3+ 3 4.0 1.1 33 40 - - 3
110%. - -
~
120 to 2 2

1 1
'2+
Fall Time '3- 3 - - 3
C20to~ ___ '2- 2
+ - - 2
 ELECTRICAL CHARACTERISTICS
3:
Each full temperaturo range MECL 10.000
.... i.. circuit h. been designed to meet the
de specification. shown in the te.t table. ..~7
~.
...n
o
U1
,.'3~'0
4.~
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or o
mounted on a printed circuit board and 11 U1
transverse air flow greater than 500 linear
"
fpm il maintained. Outputs are terminated
'~2
'6~3
8::J
through a lQO.ohm resistor to -2.0 volts. F SUFFIX Z.
Test procedures are shown for only one ::J
CERAMIC PACKAGE c:
gate. The other gates are tested in the CASE 650 CD
same manner. Co

TEST VOLTAGE VALUES I

(Volts'
CiIT . .
~ T ..... ,.urtl V,H m •• V,Lmin V'HAmi" VILAmu VEE
i'J
-55"1: ~.880 -1.920 -1.255 -1.510 -5.2
"""
eN +25o C -0.780 -1.850 -1.106 -1.475 -5.2
+t25"1: ~,530 -1.820 -t.ooo -1.400 -5.2
MC106015F T. . Limib
Pi" TEST VOLTAGE APPLIED TD PINS LISTED BELOW:
U'- -li6"1: +25"1: +125"1: IVeel
CMrect... i.ic s.~ T... Mm M. Min TVI' M.. Mm Ma. Unit VIHm8ll V,Lmin VIHAmin V'LAm•• VEE Gnd
Power Supply Drain Current 'e '2 24 - '7 2' - 24 mAd, - - - - '2 4.5
',nput Current IlnH 8 - 450 - 265 - 285 ~Adc 8 - '2 4.5
ImL 8 0.5 - 0.5 0.3 - ,.Adc - 8 - '2 4.5
logic'T'
Output Volt.
VOH 7
6
-LOBO ~.880
-'.OBO -<>.880
~.9;JO
~.930 -
~.780
~.780
~.825
~.825
~,63O
-<>.630
Vd,
Vd,
-8 -
-
- -
'2
12
4.5
4.5
Logic "0"
Output Voltage
VOL 7
6
-1.920 -1.855
-1.920 -1.655
-1.850
-1.850
-- -'.620 -'.820
-'.520 -1.820
-'.545
-1.545
Vd,
Vd,
8
-
-
- -
-
-
-
'2
12
4.5
4.5
LogiC .. ,,, VOHA 7 -1.100 ~.950 -0.845 Vd, 8 4.5
'2
Threshold VOltllge 6 -1.100 - ~.950 - - -0.845 - Vd, - - 8 - 12 4.5
Logic "0"
Threshold Voltage
VOLA 7
6 -
-'.635
-1.635 -
-
-
-',600
-1.600 -
-',525
-'.525
Vd,
Vd, - -
8
- 8
'2
'2
4.5
4.5
Switching Times
(lQO.ohm la.jl Pul.ln Pul.Out -3.2 V +2.0 V
Propagation Delay 18+1_ 7 - - 1.0 2.0 2.9 - -
"' - - 8 7 '2 4.5
- - - - - -
! !
7 7

II
18-7+
18-+6. 6 - - - - - - 6
'8-6- 6 - - - - - - 6
Rise Time '7+ 7 -
-
-
-
1.' 3.3 -
-
-
-
-
-
-- 7

1 ~ 1 1
(2010_' '6+ 6 6
Fall Time '7_ 7 - - - - - - 7
- - - - - -
•
120 •• _ , '&- 6 6
 '--_ _-' f TRIPLE 4-3-3 INPUT GATE
' '--..._ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _____'
MECL 10,000 series

MC10506

The MC10506 is a triple 4-3-3 input NOR

gate. Input pulldown resistors eliminate the need
to tie unused inputs to an external supply.
POSITIVE LOGIC NEGATIVE LOGIC

~~,
181 181
191
1101
:~3171 191
1101
171

(11 ) 7 111)

1:~2161
1131
1:~2161
1131
1141 1141 Po'= 30 mW typ/gate (No Load)
1151 11 1151 11 tpd = 2.0 ns typ
Output Rise and Fall Time
12~ 15131
1161
12~ 15
1161
== 3.5 nstyp (10% - 90%)
111 13 11) 13 13)
= 2.0 ns typ (20% - 80%)
121 14 121 14

Numbers at ends of terminals denote pin numbers for L package

(Case 620).
Numbers In parenthesis denote pin numbers for F package
(Case 650).

CASE VCC1 VEE

620 Pin 1 Pin 16 Pin 8

650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2SoC

VCC1 = VCC2
50-ohm termination to ground 10- +2.0 Vdc V out

"~m"~
catad in each scope channa' input.
All input and output cable. to the
scope ara aqual lengths of 50-ohm Coax
coaxial cable. Wire langth should
ba <1/4 inch from T'Pin to input
pin and TP out to output pin. V out
il 2: 1 attenuated. r------, 50

I
I

Input Pulse
PROPAGATION DELAY t+= t- = 2.0 ±. 0.2 ns Unused outputs
120 to 80%1 connected to a
100-ohm resistor
to ground.

~----+1.11V

'---~ 1-----+0.31 V

V out

See General Information section for packaging.

3-244
 3:
o
..a
ELECTRICAL CHARACTERISITCS
~
Each full temperature range MECL 10.000 o
series circuit has been designed to meet the
de specifications shown in the test table,
after thermal equilibrium has been estab-
:~3
7
en
8
=.
::l

-
lished. The circuit is in a test socket or
mounted on a printed circuit board and 9~2 ::l
,O~
transverse air flow greater than 500 linear 11 c:
~
fpm is maintained. Outputs are terminated 12
~
through a 100-ohm resistor to -2.0 volts. '3~
Test procedures are shown for only one '4~15
gate. The other gates are tested in the L SUFFIX
same manner. CERAMIC PACKAGE
CASE 620

TEST VOLTAGE VALUES

(Voltst
@Test
Temperature VIH mall( VILmlR VIHA min VILAm . . VEE
-55"c -0.880 -1.920 -1.255 -1.510 -5.2
w +2SoC -0.780 -1.850 -1.105 -1.475 -5.2

~
tTl MC10506L Test limits
+l25 o C -0.630 -1.820 -1.000 -1.400

TEST VOLTAGE APPLIED TO PINS LISTED BELOW:

-5.2

P,n
Under -55°C +2S0C +l25 o C tVecl
Characteristic Svmbol T." Min I Max Min I Typ Max I Min Mo. Unit VIH max Vll min VIHAmin VILA max VEE Gnd
Power Supply Drain Current 'E 24
t--
I 17 21 I 24 mAde 1,16
I nput Current Im H
~ 265 1 .. 265 /-lAde 1,16
0.5 1---05 0.3 1,16
T
Ilnl /-lAde
log.c "". VOH -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vd, 1,16
Output Voltage -1.080 -0.880 -0930 -0.180 -0.825 -0.630 Vd, 1.16
logiC "0" -1920 -1.655 -1.850 -1.545 Vd, 4 1,16
VOL -1.620 1-1.820
Output Voltage -1920 -1.655 -1.850 -1.620 -1.820 -1.545 Vd, 9 1.16

VOHA -1.100 -0.950 -0.845 Vd, 1.16

L99 l c "'"
Threshold Voltage -1.100 -0950 -0.845 - Vd, 1,16
logiC "a"
Threshold Voltage
VOLA -1.635
-1.635
-16~1 -
-1.525 Vd,
Vd,
4
9
1,16
1,16
-1.600 -1.525
SWitching Times.
Pulse In Pulse OUI -3.2 V +2.0 V
(l00-ohm loadl
Propagation Delay 14+3_ 3 1.0 3.7 1.0 2.0 2.9 1.0 3.7 1,16
'4_3+ 3.7 10 2.9 3.7
Rise Time 4.0 1.1 3.3 4.0
1201080%.
Fall Time
1201080%)
'3'
,~
1 1 4.0 11 1 3.3 1 4.0 1 1 1 1I 1
 3:
n
.....
ELECTRICAL CHARACTERISITCS
o
Each full temperature range MECL 10,000
:~7 c.n
series circuit has been designed to meet the o
de specifications shown in the test table, ,o~ C)
after thermal equilibrium has been estab- " n-
O
lished. The circuit is in a test socket or '3~.
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
.
'4~
~
,
# .. •./.~'
//&y ::J
~,
::J
c:
through a l()().ohm resistor to -2.0 volts. '~~3 ~.;.;. ~
<D
Co
Test procedures are shown for only one ,
F SUFFIX
gate. The other gates are tested in the CERAMIC PACKAGE
same manner.
CASE 650

TEST VOLTAGE VALUES

~VOlt5)
.. Tea
T emper.ture VIH max VILmin VIHA min VILAm,. VEE
-55"C -0.830 -t.920 -1.255 -1.510 -5.2
+25o C -0.120 -1.850 -1.105 -1.475 -5.2
ctJ +l25OC -0.580 -1.820 -1.000 -1.400 -5.2
'""'" I
O'l Pm
MC10506F Test limR$ TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Und.. -55°C +2SoC +125°C tVee l
Char.. cteristic Svmbol Tost M,n M. . Moo TVO Ma. Min Ma. Unit VIH max VIL min VIHAmin VILA max VEE Gnd

Power Supply Dram Current 'E 12 24 17 21 2' mAdc 12 4,5

I nput Current l,nH 8 450 265 265 ,.,Adc 12 4,5
I,nl 0.5 05 0.3 ,.,Adc 12 4,5
Logic .. ,., -1.080 -0.830 -0.930 -0.720 -0.825 -0.580 Vdc 12 4,5
VOH
Oulput Voltage -1.080 -0.830 -0.930 -0.720 -0.825 -0.580 Vdc 12 4,5
Logic "0" VOL -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 8 12 4.5
OutPUt Voltage -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 13 12 4,5

Logic .. ". VOHA -1.100 -0.950 -0.845 Vdc 8 12 4,5

Threshold Voltage -1.100 -0.950 -0.845 Vdc 13 12 4,5
Logic "0" VOLA -1.635 -1.600 -1.525 Vdc 12 4,5
Threshold Voltage -1.635 -1.600 -1.525 Vd, 13 12 4,5
SWitching Times. Pulse In Pulse Out -3.2V +2.0 V
(1OG-ohm load)
Propagation Delay 19+7_ 1.0 2.0 2.9 8 12 4.5
t9-7+ 1.0 2.9
Rise Time '7+ 1.1 3.3
t2O'ollO%I
Fall Time
(201080%)
'7_ 1.1 1 3.3 1 1 1 1 1
 MECL 10,000 series
rRIPLE 2·INPUT EXCLUSIVE
"OR"/EXCLUSIVE "NOR"

MC10507

POSITIVE LOGIC NEGATIVE LOGIC

(8)4~216) (8)4~2(6) The MC10507 provides three positive logic

(9)5~317) (9)5~317) Exclusive OR and Exclusive NOR functions for
113) 9~11115) (13) 9~11(IS) high speed applications. Input pulldown resistors
(11 ) 7~10(14) 1111 7~10(14) eliminate the need to tie unused inputs to VEE.
(2)14~12(16) 12)14~. 12(16)
(3)15~13(1) (3)15~13(1)

Z = (A. B) + (A. B) z ~ (iii • B) + (A • B)

Y = (A. B) + (A. B) y= (AeS)+(AeS)

Numbers at ends of terminals denote pin numbers for L package

IC••• 620).
Po = 40 mW typ/gate (No Load)
Numbers in parenthesis denote pin numbers for F package
tpet "" 2.5 ns typ
IC... 650).
Output Ri. and Fall Tim..
"" 2.0 nstyp (20% to 80")
CASE VCC1 VCC2 ~ 3.S nl typ (10% to 90%)
620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS I!iI 2SoC

VCCI ~ VCC2
Vin +2.0 Vdc V out NOR V out OR

Coax Coax
50-ohm termination .to ground lo-
cated in each scope channel input.
All input and output cables to the so
scope ara equal length, of 50-ohm
coaxial cable. Wir. length should
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated. Input Puis. Unused outputs
t + "" t- = 2.0 ± 0.2 ns connected to 8
(20 to 80%) 100-ohm resistor
to ground.

PROPAGATION DELAY
L_-
Ff :·"
LJVdC
VEE

V out NOA

V out OR

See General Information section for packaging.

3·247
 ELECTRICAL CHARACTERISITCS s:
n
~
Each full temperature range MECL 10.000
series circuit has been designed to meet the 0

-
de specifications shown in the test table, '~2 U1
after thermal equilibrium has been estab-
5 3 0
lished. The circuit is in a test socket or
mounted on a printed circuit board and
9~'1
7 10 "0
n
transverse air flow greater than 500 linear 14~'2 ::J
15 13
fpm is maintained. Outputs are terminated !:to
L SUFFIX ::J
through a 10()..ohm resistor to -2.0 volts.
CERAMIC PACKAGE c:
Test procedures are shown for only one CD
gate. The other gates are tested in the
same man nar.
CASE 620
e:
TEST VOLTAGE VALUES
Ivotttl
II Test
TemJMr.tur. VIHm •• VIL min VIHA min I VILAmu 1 VEE
-56"<: -0.880 -1.920 -1.255 -1.510 -5.2
+ZSoC -0.780 -'.850 -1105 -1.475 I -5.2
+l2!iOc -0.630 -1.820 -1.000 -1.400 -5.2
MC10507L Tnt limits
'in TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
_56°C '25"<: +lZSoC tVcel
Und"r
Ch.rKterislec Svmbol T ... Min M •• Min M •• Min M .. Unit VIHm.x VIL min VIHAmin VILAmu VEE Gnd
Pow", Supply Dntln Current 'E 31 28 31 mAd< All Inputs 1,16
Input Current lin H 4,9,14 450 265 265 ,u.Adc 1,16
5,7,15 375 220 220 ,u.Adc 1,16
W
IL lin L 0.5 0.5 0.3 ,u.Adc
• 1,16
~
~
Log~ "1"
Output Voltage
VOH -1.(80 -0,880 -0.930 -0.780 -0.825 -0,630 Vd, 4.5
• 1.16

CXI
+ + + + + + +
Logic "0"
Output Voltage
VOL
• •
-1.920 -1.655 -1850 -1.620 -1.820 -1.545 Vd,
•
5
'.5
• 1.16

LogiC "1" VOHA

+
1 -1.100
+ +
-0.950
+ +
-0.845
+ +
Vd,
+ +
1,16
Threshold Voltage
I
+ + + + + +
LogIC "0"
Threshold Voltage
I
VOLA
I I
-1.635 -1.600 -1.525 Vd,
• 1,16

+ + + + + +
SWltchmg Times (100 n load)
Propagation Delav ..."- I Inputs 10 4.5
Min
11
TVO
2.0
M ••
37 1.0 '.5
Unit +1.11 V
5,7,15
PulMln
Input
Pul.. OUI
Cor,esponding
-3.2 V +2.0V
1,16

,. Ex.QA/EIiI·NOA

~ ~
4, 90r 14 4.9, or
10 either Outputs
Output

H
Inputs
5,1, or 15
to ellher
1
2.8

~
j j 4,9,14 Input
5.1, or
15
Corresponding
Ex.QA/EIiI·NOA
Outputs

AlseTlme
(20 to 80%1
Fall Time
(201010%.
,-- Output
'.3

4.3
2.5

2.5
3.5

35
4.3

4.3
j Any Input

Any Inpul
I Corresponding
Ex.QA/Ex·NQA
OutPUts

-Individuallv lesl neh Inpul8PplYlng VIH or VIL 10 inpul under tesi.

·-AnV Output
 s::
ELECTRICAL CHARACTERISITCS ...
(")

~
Each full 'temperature range MECL 10,000
series circuit has been d~igned to meet the .~.
de specifications shown in the test table, '~7
o
......

~
after thermal equilibrium has been eltab· 13~15
liShed. The circuit is in a test socket or
mounted on a printed circuit board and
1'~14
2~16
n-
O
transverse air flow greater than 500 linear 3~, ':J
fpm is maintained. Outputs are terminated F SUFFIX ~o
:J
through a 1~ohm resistor to -2.0 volts. CERAMIC PACKAGE c:
Test procedures are shown for onlv one CASE 650 CD
0.
gate. The other gates are tested in the
same manner.
TEST VOLTAGE VALUES
!Voh.1
@TeS1
Temper.tur.. VIHmu' VIL min YIHA min I VILA m.. VEE
-SSoC -0.880 -1.920 -1.255 -1.510 -5.2
+2SoC
1-1ZSoC
-0.780 -1.850 -1.105 I -1.475 -5,2
-0.630 -1.820 -1.000 -1.400
P,n MC10601F rut limit, --5.2
-5SoC TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Ch.racteristic Symbol
U ....,
T .., Min M", Min
'25"1:
M •• Min
+ 12SoC
M .. Unit VIHm •• VIL min VIHA min VILAm..
-VEE (Veel
Gnd
Power Supplv Oram Current

l,npv, Cv"en,
'E
lin H
'2
2,8,13
3'
450
- 2. 31 mAd< All Inputs 12
--,-, I :::
W 265 265 ~Adc
3,9,11 - 375 - 220 220 ~Adc 12 'oS
r() D,S
~
I.n L Os 03 ,..Adc 12 'oS
to I LO~~;~:'~ Voltage
VOH 6
6
-1.esO -0.880 -0.930 -0.780 -0.825 -0.630 Vdo .,9 12 'oS

~
LogIC "0"
Output Voltage I VOL
I
6
6
I • •+
-1.920 -1.655 -1850
• •
-1.620 -1.820
+
-1.545
+
Vdo
9•
.,9
+
12
+
'oS

+
logiC "'"
Threshold Voltage I VOHA
I 6
6
! •
-1100 -
-
-
-0.950
+
-
+
-0.845
+
-
+
Vdo
+
12
+
',S

+ + + +
•
- -

•
-
logIC "0"
Threshold Volt. I VOLA
I
6
6
I -
-1.635 -
-
-1.600

-
-1.525 Vdo '2 'oS

SWllct'llng Times (100 11 load' I + + - + + + +

Mo. TV> M .. Unit +1.11 V Pulse In Pu . . Out -3.2 V +2.0 V
Propagation Delav
".
t+ ~ I Inputs
2.80r 13
-
-
-
-
1.1 20 3 7 3,9,11 Input Co"npondlng 12 ',.
i
Ex.QR/Ex·NOA

~
2.80r 13
to either - - Outputl
Output - -

i j
Inputs - - 2. 2,8,13 Inpu1 Corrnpondi r-.
3,9 or 11 - -
,-. 3,9 or 11 Ex.QRJEx·NOR

j
to either - - OutpyU
,-- Output - -
Rise Time ,. oo - -
1201080%1
Fall Time ,- o. - -
25

2S
35 Any InPlJ1
I Corresponding
EII.QRIEII·NQR
35 Any Input OutPUts
flO to 80%1
elndwldually test each Inpu18PpiVing V1H or VlllO Input under test
··Any Output
 DUAL 4-5-INPUT
MECL 10,000 series
"OR/NOR" GATE

MC10509

The MC10509 is a dual 4-5 input OR-NOR

gate which is pin compatible with the MECL III
MC1660L dual OR-NOR gate. All inputs are
POSITIVE LOGIC NEGATIVE LOGIC terminated by a 50 k ohm resistor to VEE
eliminating the need to tie unus,ed inputs low.

::::~3
(10) 6 2
(7)
(6)
(B)4~
(9) 5

(10)
3

6 2
(7)

(6)
(Ill 7 (Ill 7

(1319~
(14110
(13)9~
(14) 10 .
14 (21 14 (2) tpd = 2.0 ns typ
(15) 11 (15) 11
15 (31 15 (31 Po == 30 mW tvp/gate (No Load)
(16) 12 (16112 Output Rise and Fall Times
(1113 (1113 (10% to 90%) 3.5 ns
(20% to BO%I 2.0 ns
Numbers at ends of terminals denote pin numbers for L package
(Co. 6201.
Numbers in parenthesis denote pin numbers for F package
(Case 6501.

CASE VCCI
620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@250C

veel - VCC2
+2.0 Vdc V out NOR V out OR

~"'m"'"'
Coax Coax Coax

Input r--- ---, 50 50

I
I
Pulse Generator

Input Pulse
I PROPAGATION DELAY

~
t- "" 2.0 ±. 0.2 ns
t+ "" I
(20 to 80%) I I

I Unused outputs
I connected to 8
I 100-ohm resistor
to ground.
L ___ ~__ J
50-ohm termination to ground 10
cated in each scope channel input :J; 0
1 jJF
V out OR

All input and output cables to the

seop • •,. equal lengths of 50-ohm -3 2 Vdc
coaxial cable. Wire length should Vee
b. <1/4 inch from TPin to input V out NOR
pin and TP out to output pin. V out
is 2: 1 attenuated.

See General I nformation section for packaging.

3-250
 3:
ELECTRICAL CHARACTERISTICS
o
..&

Each fuJi \a!1IP8rature range MECL 10,000 ~

l81"iescircuit has been designed to meet the
de specifications shown in the test table, :~3
6 2
ocg
after thermal equilibrium has been estab~ 7
'ished. The circuit is in a test socket or 8::J
.~

-
mounted on 8 printed circuit board and '0 ~,
transverse-air flow greater than 500 linear 11 14
::J
fpm is maintained. Outputs are terminated 12 15 c::
(1)
through a l00-ohm resistor to -2.0 volts. 13 c..
Test procedures are shown for only one
gate. The other gates are tested in the L SUFFIX
same manner. CERAMIC PACKAGE
CASE 620

TEST VOLTAGE VALUES

«Volts)
Test
(iI
T emperetur. VIH ma. V'Lmin VIHAmi" VILAnNIC VEE
_55°C -o.SIIO -1.920 -1.255 -1.510 -5.2
+25 o C -0.780 -1.850 -1.106 -1.475 -5.2 I
+125 GC -0.630 -1.820 -1.000 -1.400 -5.2
CrJ
I\.) Pin
MC10601L T_ Limits
TEST VOLTAGE APPLIED TO PINS BELOW:
-55"<: +25o C +125 o C
....
U1
Characteristic 5vmbot
Under
T..t Min Max Min Ty. M •• Min M •• Unit VIH ma" VILmin VIHA min VILA ma. VEE
(Veel
Gnd
Power Supply Drain Current 'E 8 16 11 1. 16 mAde - 8 1.16
Input Current ImH • 450 265 265 ,!.lAde
• - 8 1.16
linl 4 0.5 05 0.3 ,!.lAde
• - 8 1.16
High Output Voltage VOH 2
3
-1.080 -O.SIIO
-1.080 -O.SIIO
-0.930
-0.930
-
-
-0.780
-0.780
-0.825 0.630
-0.825 -0.630
Vdc
Vdc
•- -
-
-
-
-
8
8
1.16
1.16
Low Output Voltage VOL 2 -1.920 1.655 -1.850 1.620 -1.820 -1.545 Vdc ~-
8 1,16

High ThreshOld Voltage VOHA

3
2
-1.920 -1.655
1.100
-1.850
-0.950
- -1.620
-
-1.820 -1.545
-0.845 -
Vdc
Vdc
•
-
-
4
- 8
8
1.16
1.16
3 -1.100 - -0.950 - - -0.845 Vdc - - - 4' 8 1.16
Low Threshold Voltage VOLA 2 - -1.635 - - -1.600 - -1.525 Vdc .- - - 4 8 1.16
3 - -1.635 - - -1.600 - -1.525 Vdc - - 4 - 8 1.16
SWitching Times
1100 ohm load) Pulse In Pulse Out -3.2 V +2.0 V
Propagation Delay 14+2+ 2 1.0 3.7 1.0 2.0 2.9 1.0 3.7 ns -
-
-
-
• 2 8 1.16

l !
14_2_ 2 2
t4+3_ 3
t ~ - - 3

Il I I I
14-3+ 3 - - 3
Rise Time '2+ 2 4.0 1,1 3.3 4.0 - - 2
(20 to l1li%1 - -

~
3 3

l !
t3+
Fall Time '2_ 2 - - 2
(20'0l1li%1 t3- 3 - - 3
- - -
 s:
ELECTRICAL CHARACTERISTICS
....
(')

o
B3=t= c.n

· ~
Ea<;h full temperature range MECL 10,000
series circuit has been designed to meet the • 1
10 •

V
de specifications shown in the test table,
after thermal equilibrium has been estab- 11 8::J
lJ~ 2
lished. The circuit is in a test socket or
mounted on a printed circuit board and
:::,
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated
through a 1()().ohm resistor to -2.0 IIolts.
I.
"IS
1
J
~~-" -'.
::J
c:
~
~
Test procedures are shown for only one
gate. The other gates are tested in the F SUFFIX
same manner. CERAMIC PACKAGE
CASE 650

TEST VOLTAGE VALUES

(Volts)
@Test
Temperature VIH max Vil min VIHA min VILA max I VEE
-5SoC -0.830 -1.920 -1.255 -1.510 -5.2
+25 o C -0.720 -1.850 -1.105 -1.475 -5.2
W
N
+ 125°C -0.580 -1.820 -1.000 -1.400
I -5.2
(JI
r-.)
I CharactenSllC Symbol
Pin
Under
Teo.
-5SoC
Min Ma. Min
MC10509F Test Limits
+2So C
Typ M •• Min
+125 o C
Ma. Unit VIH max
TEST VOLTAGE APPLIED TO PINS BELOW:

VILmin VIHA min VILA ....ax VEE

tVee l
Gnd
Power Supply Oram Current 'E 12 16 11 14 16 mAdc 12 4,5
Input Current IIIlH 8 450 265 265 /JAde 12 4,5
ImL 0.5 05 0.3 /lAdc 12 4,5
High Output Voltage VOH -1.080 -0.830 -0.930 -0.720 -0.825 0.580 Vdc 12 4,5
-1.080 -0.830 -0.930 -0.720 -0.825 -0.580 Vdc 12 4,5
Low Output Voltage VOL -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 12 4,5
7 -1920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 12 4,5
High Threshold Voltage VOHA 6 -1.100 -0.950 -0.845 Vdc 12 4,5
-1.100 -0.950 -0.845 Vdc 12 4,5
Low Threshold Voltage VOLA -1.635 -1.600 -1.525 Vdc 12 4,5
-1.635 -1.600 -1.525 Vdc 12 4,5
SWItchmg Times
(100 ohm load) Pulse In Pulse Out -3.2 V +2,0 V
Propagation Delay t9+6+ 1.0 2.0 29 8 12 4,5

l
t9-6_

!
I
t9+7_
t9-7+
Rise Time '6+ 1.1 3.3
(20 to 8O%t 7

l
'7+
Fall Time
t2O'.8O%1
'6-
'7-
6
!
 MECL 10,000 series
TRIPLE LINE RECEIVER
(HIGH COMMON MODE)

MC10514

The MC10514 is • triple line receiver designed for

use in sensing differential signals over long lines. An
active current source and translated emitter fOllower
inputs provide the line receiver with a oommon mode
noise rejection limit of one volt in either the positive
or the negative direction. This allows a large amount
POSITIVE LOGIC NEGATIVE LOGIC
of common mode noise immunity for extra long lines.
Another feature of the MCt0514 is that the OR
outputs go to a logic low level whenever the inputs are
left floating. The outputs are each capable of driving
(8)4~2(6) (a)4~2(6) l()(k)hm transmission lines.
(9)5~317) (9)5~3(7) This device is useful in high speed central processors.
minicomputers, peripheral controllers, digital commu·
(13) 9~6 (10) (13) 9~6 (10)
nication systems. testing and instrumentation systems.
(14)10~7 (11)(t4)tO~7 (11) The MC10514 can also be used for MOS to MECL
(16)12~t412) It6)12~1412) interfacing and it is ideal as a sense amplifier for MOS
RAM's.
(1)13~t513) (1)13~1513) A Vee reference is provided which is useful in
~11(15) ~11(15) making the MC10514 a Schmitt trigger, allowing single-
Vea Vae ended driving of the inputs, or other applications where
a stable reference voltage is necessary.

[CAsEivcc11vcc2JVEE
620 Pin 1 Pin 16 Pin 8
J

tpd":: 2.4 ns typ (Single Ended Input)

tpd '" 2.0 ns typ (Differential Input)
PO'" 145 mW typ!pkg (No Load)
Numbers at ends of terminals denote pin numbers for L package (Case 620),
Numbers in parenthesis denote p'in numbers for F package (Case 650).

SWITCHING TIME TEST CIRCUIT ANO WAVEFORMS il250C

PROPAGATION DELAY
Coax

50

Input pulse
t+ = t - = 2.0
±. 0.2 ns Unused outputs
connected to 8
(20 to 80%)
100-0hm resistor
to ground.
I
I
o--~f---t----l VB B I
50-ohm termination to ground lo-
cated in each scope channel input.

All input and output cables to the

L -1]- J
I
One Input from each gate must
be tied to V SB during testing

scope are equal lengths of 50·ohm

coaxial cable. Wire length should J O l jJ F I0 1jJF
be < 114 inch from TPin to input
pin and TPoutto output pin. V out - 32 Vdc
1.2: 1 attenuated. VEE

See General Information section for packaging.

3-253
 ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000 s
series circuit has been designed to meet the
de specifications shown in the test table,
....
C')

o
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
mounted on a printed circuit board and
4~2
....
0'1
~
5~3
transverse air flow greater than 500 linear L SUFFIX
9~6
8

"""
fpm is maintained. Outputs are terminated CERAMIC PACKAGE
10~7 :J
through a 100-ohm resistor to -2.0 volts. CASE 620
12~t4 !Z.
Test procedures are shown for only one :J
input, or for one set of input conditions. 13~15 c:
Other inputs or outputs are tested in the ~"
VBB
ct>
C-
sarne manner.

TEST VOLTAGE VALUES

(Volts)
@IT.lt
Temperature VIHmax VIL mill VIHA min VllAm.x VBB VIHH-I V'lH-l VIHl-1 VILL -I VEE
-5SoC -0.880 -1.920 -1.255 -1.510 From +0.170 -0.920 -1.830 -2.920 -5.2
+2SOC -0.780 -1.850 -1.105 -1.475 Pm +0.280 -O.B50 -1.720 -2.B50 -5.2
+12SoC -0.630 -1.820 -1.000 -1.400 11 +0.420 -0.B20 -1.580 -2.820 I -5.2
MC10514L T.t Limits
Pin TEST VOLTAGE APPLIED TO PINS BELOW:
-6SoC +2SoC +12So C
Under (Veel
CharKteristic Symbol T .., Min M.. Min Ty, M.. Min M.. Unit VIH malt VIL min VIHA min VILA max VB. VIHH· VllH· VIHL· Vlll· VEE Gnd
W Power Supply Drain Current 'E 3. 28 35 3. mAde 4,9,12 5.10.13 8 1,16
r\J Input Current linH BO 45 45 /JAdc 9,12 5,10,13 1,16
01 ICBO 1.5 1.0 '0 /JAdc 9,12 5,10,13 8,' 1.16

"'" Logic "1" Output Voltage

VOH

VOL
-1.080
-1.080
-1.920
-0.880
-0.880
-1.655
-0.930
-0.930
-1.850
-0.780
-0.780
-1.620
-0.B25
-0.825
-1.B20
-0.630
-0.630
-1.545
Vdc
Vdc
Vdc
9,12
9,12
9,12
4
5,10,13
5,10,13
5,10,13
8
8
1,16
1,16
1,16
Logic "0" Output Voltage
-1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 4 9,12 5,10,13 1,16
VOHA -1.100 -0.950 -0.845 Vdc 9,12 5,10,13 1,16
logic "1 'Threshold Voltage
-1.100 -0.950 -0.845 Vdc 9,12 5,10,13 1,16
VOLA -1.635 -1.600 -1.525 Vdc 9,12 5,10.13 1,16
Logic "0' Threshold Voltage
-1.635 -1.600 -1.525 Vdc 9,12 5,10,13 1,16
Aeference Voltage VBB 11 -1.440 -1.320 -1.350 -1.230 -1.240 -1.120 Vdc 5,10,13 1,16
Common Mode AeJection Test VOH -1.080 -0.830 -0.930 -0.720 -0.825 -0.580 Vdc 1,16
-1.080 -0.830 -0.930 -0.720 -0.825 -0.580 Vdc 1,16
VOL -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 1,16

I I -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 1,16

,
Switching Tintel (l00-ohm Load) Min M.. Min Ty, M.. Min M.. Pulse In Pulse Out -3.2 V +2.DV
Propagation Delay·· t4+2+ 1.0 25 4.0 4 5,10,13 8 1,16
t4_2_ I
t4+3_
+ +
j j j j j
t4_3+
A ise Time (20% to 80%1 '2' '5 21 3.5

~
'3'
Fall Time (20% to 80%1 '2_
~
'3_
•
·VI HH = Input logic "1" level shifted positive one volt for common mode rejection tests.
VILH = Input logic "0" level shifted positive one volt for common mode rejection tests.
VIHL = I nput logic "1" level shifted negative one volt for common mode rejection tests.
VILL = Input logic "0" I~vel shifted negative one volt for common mode rejection tests,
• -Delav is 2.0 ns with differential input.
 ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000
3:
(')
series circuit has been designed to meet the .....
de specifications shown in the test table, o
U1
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or .....
.;a

~
mounted on a printed circuit board and 8~6
transverse air flow greater than 500 linear 9~7 n-
O
fpm is maintained. Outputs are terminated 13~10
::J
through a 100-ohm resistor to -2.0 volts. 14~11 d.
Test procedures are shown for only one 16~2 ::J
input, or for one set of input conditions. 1~3 F SUFFIX c:
CD
Other inputs or outputs are tested in the ~15 CERAMIC PACKAGE Cl.
same manner. VBB CASE 650

TEST VOLTAGE VALUES

(Volts)
@Test
T emper0ill1ure VtHmaK VILmm VIHAmin VILAm ... VBB VIHH· V'LH-l VIHL -I YILL -, VEE
-5SoC -0.880 -1.920 -1.255 -1.510 From +0.170 -0.920 -1.830-2.920 -5.2
+25"c -0.790 -1.850 -1.105 -1.475 Pm +0.280 -0.850 -1.720-2.850 -5.2
+12SoC -0.630 -1.820 -1.000 -1.400 IS +0.420 -0.82"l-1.580~ -2.820~ -5.2
MC10S14F Test Limit5
Pon TEST VOLTAGE APPLIED TO PINS BELOW:
Under
-SSoC "'2So C "'12So C 1VCC'
Chaf.:te,istic Symbol T ... Min M.. Min TVO M.. Mon M.. Unit VIHmali Vll min VIHA min VllAmu VBS VIHH- VllH- VIHl e Ville VEE Gnd
eN
r:.,
C11
I
Power Supply Dram Current
Input Current
'E
IlnH
ICBO
12
8
3.
SO
1.5
28 3S
45
1.0
39
45
10
mAdc
j.lAdc
j.lAd..:
8,13,16
13,16
13,16
1.9,14
1,9,14
1,9,14
12
12
8,12
4.5
4.5
4.5
C11
VOH -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vd, 8 13,16 1,9,14 12 4.5
LogiC "1" Output Voltage 13,16
-1.080 -0.880 -0.930 -0.780 -0,825 -0.630 Vd, 8 1,9,14 12 4.5
VOL -1.920 -1.655 -1850 -1.620 -1.820 -1.545 Vd, 13,16 1.9,14 12
LogiC "0" Output Voltage 13,16
-1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 8 1,9,14 12
VOHA -1.100 -0.950 -0.845 Vd, 13,16 1,9,14 12
L(i9lc "1" Threshold Vall.
-1.100 -0.950 -0.845 Vd, 13,16 1,9,14 12
VOLA -1.635 -1.600 -1.525 Vd, 13,16 1,9,14 12
LogiC "0" Threshold Voltage
-1.635 -1.600 -1.525 Vd, 13,16 1,9,14 12
Reference Voltage V88 15 -1.440 -1.320 -1.350 -1.230 -1.240 -1.120 Vd, 1,9.14 12
Common Mode Rejection Test VOH 6
, -1.080
-1.080
-0.830
-0.830
-0.930
-0.930
-0.720
-0.720
-0.825
-0.825
-0.580
-0.580
Vd,
Vd,
12
12
VOL 6 -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vd, 12
-1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vok 12
Switch"" TinMI l100-ohm lOMt11 Min M.. Min TVO M.. Min M.. Puis. In Pul.-Oul -3,2 V +2.0 V
Prop8pIIOn Deley··
....,-
18+6+ 1.0 2.5 4.0 8 1,9,14 12 45

18+7-
~ + +
j j j j j
18-7+
Rise Time (20% to 80%1 'B' 1.5 21 3.S

Fall Time (20% to 80%1 '"'B-

"- ~ ~ ~
·VIHH::: Input logic "1" level shifted positive one volt for common mode rejection tests.
VILH = Input logic "0" level shifted positive one volt for common mode rejection tests,
VIHL = Input logiC "1"level shifted negative one volt for common mode rejection tests.
VILL = Input logic "O"level shifted negative one volt for common mode rejection tests.
··Delay is 2.0 ns with differential input,
 " MECL 10,000 series
L--..-;f QUAD LINE RECEIVER

MC10515 '--------

The MC10515 is a quad differential amplifier

designed for use in sensing differential signals
POSITIVE LOGIC NEGATIVE LOGIC over long lines. The base bias supply (VBB) is
made available to make the device useful
as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
(SI 54~ 2 (SI (SI 54 ~~ 2 (SI Active current sources provide the MC10515
(91~ (gl~
with excellent common mode noise rejection.
(1117~ (1117~ If any amplifier in a "ackage is not used, one
(10IS~3(71 (1016~3(71 input of that amplifier must be connected to
(14110~ 14 (21
(14110~ VBB to prevent upsetting the current source
14 (21
(15111 (15111 bias network.
(1113~ 15(31 (1113~
~15(31
(16112~ (16112 L - g (131
Vse 9 (131
Vee
Numbers at ends of terminals denote pin numbers for L package
(Casa 620).
N umbers in parenthesis denote pin numbers for F package tpd = 2.0 ns typ
(Case 650).
Po = 110 mW tvp!pkg (No Load)

CASE VCCI VCC2 VEE

620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 250 C

+2.0 Vdc Vout

Coax

50 PROPAGATION DELAY

Input Pulse
t+ = t- = 2.0 ±. 0.2 ns Unused outputs
(20 to SO%I connected to 8
1 OO"hm resistor V out
to ground.

One input from each gate must be tied to Vee

50-ohm termination to ground lo- dur Ing testing.
cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable, Wire length should
be <1/4 inch from TP in to input
pinandTPouttooutputPin. V out
is 2: 1 attenuated.

See General I nformation section for packaging.

3-256
 3:'
n
....
ElECTR ICAL CHARACTER ISITCS
Each full temperature range MECL 10,000
~
....
• ries circuit has been designed to meet the
de specifications· shown in the test table,
after thermal eQuilibr~um has been estab-
:=::t>---2 trI
n
lished. The circuit is in a test socket or
mounted on a printed circuit board and
:=::t>--- J.
o
:::l
::!.
transverse air flow· greater than 500 linear 10~ I. :::l
11 C
fpm is maintained. Outputs are terminated (I)

through a 100-ohm resistor to -2.0 volts. 13~15 C:.

Test procedures are shown- for only one 12 ~9
gate. The other gates are tested in the v ••

~.
same man ner.

i'
"f1~~~nr Ii
j
I'
L SUFFIX
CERAMIC PACKAGE
CASE 620

w li'T ... TEST VOLTAGE VALUeS

r:., Temperature V,HmllX V,L min V,HA min V'LAm .. V88 VEE
U1 -ssOC -0.880 -1.920 -1.255 -1.510 -6.2
From

'" +25"c
+12SoC
-0.780
-0.630
-1.850
-1.820
-1.105
-1.000
-1.475
-1.400
Pin
9
~
~
-6.2
MC10515L Test Lilnits
Pin TEST VOLTAGE APPLIED TO PINS L1STED BELOW,
Und.r -!SoC +25"c +125o C 1Veel
Charect.,iltic Symbol Test Min Max Min Max Min M •• Unit VIH max VIL min VIHA min VILA max VB8 VEE GNI
Power SupplV Dr.in Current IE 8 29 26 - 29 mAde - 4,7,10,13 - - 5,6,11,12 8 1.16
Input Cur,ent I," H 4 165 - 95 - 95 IJAdc 4 7,10,13 - - 5.6.11,12 8 1.16
leBO 4 1.5 1.0 - 1.0 JJAdc - 7,10,13 - - 5,6.11,12 8.4 1,16
Logic ",.. Output Voltage VOH 2 -UlBO -O.BBO -0.930 -0.780 -0.825 -0.630 Vd, 7,10,13 4 - - 5.6,11.12 8 1,16
Logic "0" Output Voltage VOL 2 -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 4 7,10,13 - - 5,6,11.12 8 1,16
Logic "'" Threshold Voltage VOHA 2 1.100 -0.950 - -0.845 - Vd, 7,10,13 - 4 5,6,11.12 8 1.16
logic "0" ThreshOld Voltage VOLA 2 - -1.635 - -1.600 - -1.525 Vdc - 7.10,13 4 - 5,6.11,12 8 1,16
Reference Voltage Vee 9 -1.440 -1.320 -1.350 -1.230 -1.240 -1.120 Vd, - - - - 5.6,11,12 8 1,16
Switching Tjmes~ l000hm load) Min Max Min M •• Min Max Pul.ln Pul.Out -3.2 V +2.0 V
Propagation Delav 14_2+ 2 1.0 3.5 1.0 2.9 1.0 4.0 ns 4 2 5,6,11.12 8 1,16

~ ~ ~ ~ ~
3.5

~ l
2 2.9 4.0

~
14+2_ 1.0
Rise Time (20% to 80%1 '2+ 2 3.9 1.1 3.3 4.4
Fall Time (20% to 80%1 '2_ 2 3.9 1.1 3.3 4.4
-- - -
 ..
~
(")

ELECTRICAL CHARACTERISITCS
Each full temper.ture range MECL 10.000
series circu it has been designed to meet the :~6
..
~
U'I
de specifications- shown in the test table,
after thermal equilibrium has been estab- "~
10~7 8::J
lished. The circuit is in a test socket or
14~2 !:!.
mounted on a printed circuit board and ::J
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated '~~ 3
c:
(D
Co
through a l~ohm resistor to -2.0 volts. 16~13
Test procedurlts are shown for onlv one v ••

~
gate. The ot!"!er gates are tested in' the
same manner.

F SUFFIX
CERAMIC PACKAGE
CASE 650

w TEST VOLTAGE VALUES

~ OT ...
U1 'hmper.ture VILmin VIHA min VILA_ V_ VEE
CO -55"c -1.920 -1.255 -1.510 ~.2
.2$"c -1.850 -1.105 -1.475
From
Pin r-:rr-
+l25 DC -1.820 -1.000 -1.400 13 ~
MC10515F T_ Limits
Pin TEST VOLTAGE APPLIED TO 'INS LISTED BELOW,
_55°C +25OC +125o C
Ch.rKt."ic
Power Supply Drain Current
SVmbol
IE
U ....,
Toot
12
Min I M~' mAde
VIH rna I VIL min
l,B,l'.14
I \lIHA min VILA mb: V_
9.10.15.16
VEE
12
(Vee)
Gn1I
4.5
I nput Current II~ H 8 165 #JAde 1,11.14 9.10.15.16 12 4.5
IC80 8 1.5 #JAde 1.11.14 9.10.15.18 8.12 ••5
Logic "1" Output Volt. VOH 6 -1.080 I -0.880 I -0.930 Vde 1.11,14 8 9.10.15.16 12 4.5
Logic "e" Output Volt.... VOL 6 -1.920 I -1.655 I -1.850 Vde 8 1,11,14 9.10.15.18 12 4.5
Logic "1" Threshold VOl..,. VOHA 6 -1.100 -0.950 Vde 1,11,14 8 9.10.15.16 12 4.5
Logic "0" Threshold VOlt. VOLA -1.525 Vde 1.11.14 9.10.15.16 12 4.5
Reference Voltage V88 13 -1.440 -1.120 Vde 9.10.15.16 12 4.5
Switching Times! 1000hm loed) Min Mo. Pul.ln Pu"Out -3.2 V +2.0 V
PropagahGn Del.,. '8-6. 6
6
8 '.10.15.16 '2 4.5

~ ! 1 ! l l
'8-6-
Rise Time·i2O% too ~I '6. 6' 1.1 3.3
hI! Time (20% to ..,., t&- 8 1.1 3.3
 TRIPLE LINE RECEIVER MECL 10,000 series
MC10S16

The MC10516 is a triple differential amplifier

designed for use in sensing differential signals over long
lines. The base bias supply (VSS) is made available
to make the device useful as a Schmitt trigger,
POSITIVE LOGIC NEGATIVE LOGIC or in other applications where a stable reference
voltage is necessary.
Active current sources provide the MC10516 with
excellent common mode noise rejection. If any ampli·
(8)4~2 (6) (8)4~2 (6) fier in a package is not used, one input of that amplifier
(9) 5 3 (7) (9) 5 3 17) must be connected to VaB to prevent upsetting
(13)9~6 110) 113)9~6 110) the current source bias network.
(14)10 7 (14) 10
Complementary outputs are provided to allow driv-
1111 7 1111
ing twisted pair lines. to enable cascading of several
1'6)'2~'412) 1'6)'2~'4(2) amplifiers in a chain, or simply to provide complement
(1) 13 15 (3) 11113 1513) outputs of the input logic function.
L-'11'5) L - 11115 )
Vaa Vaa
Numbers at ends of terminals denote pin numbers for L package
(Case 620), tpd = 2.0 ns typ
Numbers in parenthesis denote pin numbers for F package Po = 85 mW typ/pkg (No Load)
(Case 650).

CASE VeCl VEE

620 Pin' Pin 16 Pin 8

650 Pin 5 Pin4 Pin 12

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 25°C

50-ohm termination to ground lo-

cated in each scope channel input. VCC1 = VCC2
Vin +2.0 Vdc V out V out
All input and output cables to the
scope are equal lengths of 50·ohm
coaxial cable. Wire length should

""dJ'"
be <1/4 inch from TP in to input Coax Coax
pin and TP out to output pin. V out
is 2: 1 attenuated.

r- --, 50 50

PROPAGATION DELAY Input pulse

t+ = t- = 2.0 ±.
0.2 ns Unused outputs
connected to a
(20 to aO%)
l00-ohm resistor
to ground.

I
I
I
IlOne input from each oate must
L. ....J betted to VBBdurtngtestlng.

J;" "'-11::,"
Vee

See General I nformation section for packaging.

3-259
 s:
n
..A
o
U1

-
..A
ELECTRICAL CHARACTERISITCS 0')
Each full temperature range MECL 10,000
series circuit has been designed to meet the
de specifications shown in the test table,
4 =:::.r.:t:='
5 - 3 , 8
::J
~,
after thermal equilibrium has been estab- 9~6 .,1\ ::J
lished. The circuit is in a test socket or 10~7 "
L SUFFIX c:
(1)
mounted on a printed circuit board and 12~t4 CERAMIC PACKAGE
Q.
transverse air flow greater than 500 linear '3~15 CASE 620
fpm is maintained. Outputs are terminated ~11
vBe
through a l00-ohm resistor to -2.0 volts.
Test procedures are shown for only one
gate. The other gates are tested in the
TEST VOLTAGE VALUES
same man ner.
tVolts)
@Test
Temperature VIHmalII VILmin VIHA min VILAmax VBB Vee
-SSoc -0,880 -1.920 -1.255 .-1.510 From -5.2
-t-2SoC -0.780 -1.850 -1.105 -1.475 Pin ~
+ 12SoC -0.630 -1.820 -1.000 -1.400 11 ~
MC10516L Ted Limits
Pin TEST VOLTAGE APPLIED TO PINS BELOW:
w Under -SSoC +250 C +125 o C
~ Char~tenstM: Symbol Test Min M •• Min TVO M .. Min M.. Unit VIH max V'Lmin VIHAmin V,LA max VBB Vee Gnd
0)
o Power Supply Drain Current Ie 8 24 14 21 24 mAdc 4,9,12 5,10.13 8 1.16
Input Current IlnH 4 165 95 95 ,u.Adc 4 9,12 5,10,13 8 1,16
ICBO 4 1.5 1.0 1.0 /JAdc V2 5.10.13 8,4 1,16
High Output Voltage VOH 2 -1.080 -0,880 -0930 -0.780 -0825 -0.630 Vdc 4 9,12 - - 5.10.13 8 1,16
3 -1.080 -0.880 -0,930 - -0.780 -0.825 -0,630 Vdc 9,12 4 - " 5,10,13 8 1,16
Low Output Voltage VOL 2 -1.920 -1.655 -1.850 .. -1.620 -1,820 -1.545 Vdc 9,12 4 - - 5,10,13 8 1,16
3 -1.920 -1.655 -1.850 .. -1.620 -1.820 -1.545 Vdc 4 9,12 - - 5,10,13 8 1,16
High Threshold Voltage VOHA 2 -1.100 - -0,950 - - -0.845 ~dc - 9,12 4 - 5,10,13 8 1,16
3 -1.100 - -0,950 - - -0.845 - Vdc 9,12 - - 4 5,10,13 8 1,16
Low'Threshold Voltage VOLA 2 - -1.635 -. - -1.600 - -1.525 Vdc - 9,12 - 4 5,10,13 8 1.16
3 - -1.635 - - -1600 - -1.525 Vdc 9,12 - 4 - • 5.10.13 8 1,16
Reference Voltage VBB 11 -1.440 -1.320 -1.350 - -1.230 -1.240 -1.120 Vdc - - - 5.10.13 8 1,16
SWitching Times
t l00-ohm load) Min M •• Min TVO M.. Min M •• Pulse In Pu •• Out -3,2 V +2.0 V
Propagation Delay t4+2+ 2 1.0 3,5 1.0 2.0 2.9 1.0 4.0 ns - - 4 2 5.10.13 8 .1,16
- -

~
2

~ !
2

~
'4-2-

I
t4+3_ 3 - - 3
t4-3+ 3 - 3
RlseT.me 3,9

j ~
2 4,4

j ~ ~ j
1.1 3.3 2

j
12+
120% to 80%)
Fall Time
120% to 80%1
'3+
'2-
13-
.3
2
3 !
-
-
-
-
-

-
3
2
3
j j j
 3:
n
~

o
U'I
~
ELECTRICAL CHARACTERISITCS 0)
Each full temperature range MECL 10,000
series circuit has been designed to meet the
.=::tt=6 8
~
de specifications shown in the test table, ::J
~.
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
mounted on a printed circuit board and
13=::tt=10
9 - 7

14 11
::J
c:
(I)
F SUFFIX Co
transverse air flow greater than 500 linear 16~2
CERAMIC PACKAGE
fpm is maintained. Outputs are terminated 1~3
CASE 650
through a 100-ohm resistor to -2.0 volts. ~'5
v ••
Test procedures are shown for only one
gate. The other gates are tested in the
same man ner. TEST VOL T AGE VALUES
(Volts)
@T.st
Temperature VIHmax VllmIR VIHAmin VILA ma. VS8 VEE

~
-SSoC -0.880 -1.920 -1.255 -1.510 From
+250 C -0.780 -1.850 -1.105 -1.475 Pin -5.2
+ 125°C -0.630 -1.820 -1.000 -1.400 15 ~
Me 10516F Test Limits
w J,:;., I _55°C I +250 e I +125 0 e
TEST VOLTAGE APPLIED TO PINS BELOW:
1Veel
~ Characteristic I SYmbol I rest Min I Max Min 1 Tvp I Maw: M
'" Ma. Unit Va8 VEE Gnd
....
en 17 21 24 mAde 1,9.14 12 4,5
4,5
11 95 95 j.lAdc 1.9,14 12
-,- 1.0 1.0 j.lAdc 1.9,14 8,12 4,5
High Output Voltage VO H -1.080 -0.880 -0930 -0.780 -0825 -0.630 Vd< 13,16 1.9,14 12 4,5
-1.080 -0.880 -0930 -0.180 -0825 -0.630 Vd< 13.16 8 1,9,14 12 4,5
Low Output Voltage VOL -1.920 -1.655 -1.850 -1620 -1.820 -1.545 Vd< 13,16 1,9,14 12 4,5
-1.920 -1.655 -1.850 -1620 -1.820 -1.545 Vd< 9 13,16 1,9,14 12 4,5
High Threshold Voltage VOHA -1.100 -0.950 -0.845 Vd< 13,16 1.9,14 12 4,5
-1.100 ~50 -0.845 Vd< 13,16 1,9,14 12 4,5
Low Threshold Voltage VOLA -1.635 -1600 -1.525 Vd< 13.16 1,9,14 12 4.5
-1.635 -1600 -1.525 Vd< 13,16 1,9,14 12 4,5
Reference Vortage
1~40
V88 -1.320 -1350 -1230 -1240 -1.120 Vdc 1,9,14 12 4.5
SWitching Times
fl00-ohm load) Min Max Moo TyO M. . Min Max Pulse In Pul.Out -3.2 V +2.0 V
Propagation Delay t8+6+ 6 10 20 2.9 - - 8 1,9,14 12 4,5
- -

~
18-6_ 6
18+7_ 7 - -
18-7+ 7 - -

Rise Time
(20% to 80'"
Fall Time
120% to 80%.
16+
'7+
'6_
17_
1.1

~
j 3.3

*~
-
-
-
-
-
-
-
-
j j j j j
 DUAL 2-WIDE 2-3-INPUT
MECL 10,000 series
"OR-AND/OR-AND-INVERT"
GATE

MC10517

The Me 10517 is a general purpose logic ele-

Po = 100 mW typ/pkg (No Load) ment designed for use in data control, such as
tpd = 2.3 ns typ digital multiplexing or data distribution. Input
Output Rise and Fall Times:
E is common to both gates.
'" 3.5 ns (10% to 90%)
= 2.2 ns (20 0 ,," to 80%)

POSITIVE LOGIC NEGATIVE LOGIC

(8) 4 (8) 4
(9) (9) 5
L.~.r-~"",,, __ 3 (7) 3 (71
2 (6) r--,--~~-~ 2 16)
('0) 6 110) 6
( 11) Ill) 7

('3) 9 113) 9

(14) 10 1'4) '0

('5) 11 115) 11
' - - . . - -.....- - 1 4 (2) 14 (2)
15 (3) ~~--<>15 13)
(16) '2 116) 12
(1) '3 111 13

Y = (A + B) • (e + 0 + E)
Y = (A • S) + (C. 0 • E)

X = (A + B) • (C + 0 + E)
X = (A • B) + (C. 0 • E)

Numbers at end of terminals are pin numbers for L package (Case 620),
Pin 8
Numbers in parenthesis denotes pin numbers for F package (Case 650),
Pin 12
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C
V out
Vee 1 = VCC2 OR·AND V out

"·'i It,,·,
+2.0 Vdc INVERT OR AND

PROPAGATION DELAY
r---- -----,
(~__~~~I~~
50
I
I 50
~~---+1.11 V

--~~-+0.31 V

V out OR-AND
Input Pulse
t+ = t- = 2.0! 0.2 ns
(20 to 80%) t+
t-

V out OA·ANQ·INVERT

50-ohm termination to
cated In
9roun~l~
each scope channel
All input and Output cables to the
scope are equal lengths of 50-ohm
Input
- - -h-__ I-= 0.1 ~F
J
Unused outputs
connected to a
100-ohm resistor
to ground.

coaxial cable. Wire length should

be < 1/4 Inch from TP in to Input -3.2 Vdc
pinand TPoutto output pin. V out VEE
is 2:1 attenuated.

See General Information section for packaging and maximum ratings.

3-262
 ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000
3:
C')
series circuit has been designed to meet the ~

~
de specifications shown in the test table,
after thermal equilibrium has been estab-
4.-r---....
~
lished. The circuit is in a test socket or
mounted on a printed circuit board and ......
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated 6
2 n-O
through a l00-ohm resistor to -2.0 volts. ....
::J

-
Test procedures are shown for only one ::J
gate. The other gates are tested in the c:
~
9
same manner.

10
11
L SUFFIX
~14 CERAMIC PACKAGE
15 CASE 620
12
13

TEST VOL TAGE VALUES

(Volts)
@Test
w Temperature VIH max VIL min VIHA min VILA max VEE

'" -5SoC -0.830 -1.920 -1.255 -1.510 -52

0> +2SoC -0.120 -1.850 -1 105 -1475 -52
W
+ 125°C -0.580 -1.820 -1.000 -1400 -52
MC10517L Test limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
Under -55°C +25 oC +12SoC (Vee)
Characteristic Symbol Teo. Min Mox Min TVp Ma. Min Ma. Unit VIH max VIL min V,HA min VILA mall; VEE Gnd
Power Supply Drain Current 'E 29 20 26 29 mAdc 8 1.16
Inpul Current lin H 450 265 265 /JAdc 1,16
630 370 370 /JAdc 1,16

'm L 0.5
05
/JAdc
/JAdc
1,16
1.16
LogiC "1" Output Voltage VOH -1.080 -0.830 -0.930 -0.720 -0.825 -0.580 Vdo 4,9 1,16
-1.080 -0.830 _0.930 -0.720 -0.825 -0.580 Vdo 4,9 1.16
LogiC "0" Output Voltage VOL -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdo 4.9 1,16
-1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdo 4,9 1 16
LogiC "1" Threshold Voltage VOHA -1.100 -0.950 -0.845 Vdo 4,9 1.16
-1.100 -0.950 -0.845 Vdo 4,9 1,16
LogIC "0" Threshold Voltage VOLA -1.635 -1.600 -1.525 Vdo 4.9 1,16
-1.635 -1.600 -1.525 Vdo 4,9 1,16
SWitching Times (l00-ohm load) +1.11 V Pulse In Pulse Out -3.2 V +2.0V
Propagation Delay t4+2+ 1.1 3.5 1.4 2.3 3.4 1.2 3.5 8 1.16
14_2_
14+3-
14-3+
+ + i ~ ~ i ~
AlseTlme '2+ 1.0 4.1 1.1 22 4.0

~
0.9

i
4.1
j j j j j
~ i ~ ~
(201080%1 13+
Fall Time '2_ 2
(20 to 80%)
-
'3_
'--
3
- +
 ELECTRICAL CHARACTERISTICS
s:
Each full temperature range MECL 10,000
series circurt has been designed to meet the ...o
("')

de specifications shown in the test table,

after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
mounted on a printed circuit board and
8
9
------r--... ...
(J1

-..J

;
transverse air flow greater than 500 linear ~7
8
fpm is maintained. Outputs are terminated
through a ·lQO.ohm resistor to -2.0 volts.
10
11
6
...
::J

:i'
Test procedures are shown for only one
t:
gate. The other gates are tested in the (I)
same man ner. 13
0.

14 F SUFFIX
15 CERAMIC PACKAGE
CASE 650
3
16
11

TEST VOLTAGE VALUES

lVoltsl
@Test
trJ T emperatu rll VIHmu Vil min VIHA min VILA max VEE

'"
0)
~
-5SoC
+25 o C
-0.830
-0.720
-1.920
-1.850
-1.255
-1 105
-1.510
-1.475
-5.2
-5.2
+1ZSoC -{).S80 -1.820 -1.000 -1.400 -52
MC10517F Test limIts
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
Under -5SOC +25"1: +125 oC
IVee l
Characteristic I Symbol Tes. Min M.. Min TV. MaN Mon M.. Unit VIH max Vll min VIHA min VILA max VEE Gnd
Power SupplV Dram Current
J 'E 12 29 20 26 29 mAdc 12
12
4,5
Input Current
I 1m H 8
'3
450
630
265
370
265
370
"Ad<
/.IAdc 13 12
4.5
4.5
1m l 8 0.5 ,!JAdc 12 4,5
13 0.5 ,!JAdc 13 12 4,5
logic "1" Outpt:lt Voltage VOH 6 -1.080 -0.830 -0.930 -0.720 -0.825 -{).580 Vd, 8.13 12 4,5
-LOBO -{).830 -0.930 -0.720 -{).825 -{).580 Vd, 8,13 12 4.5
Logic "0" Output Voltage VOL -1.920 -1.655 -1.850 -1.620 -1.820 -1545 Vd, 8.13 12 4,5
-1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vd, 8,13 12 4,5
logic "1" Threshold Voltage VOHA -1.100 -0.950 -0.845 Vd, 8,13 12 4,5
-1.100 -{).950 -0.845 Vd, 8.13 12 4,5
Logic "0" Threshold Voltage VOLA -1.635 -1.600 -1.525 Vd< 8.13 '2 4.5
-1.635 -1.600 -1.525 Vd, 8,13 12 4.5
SWitching Times (l00<»hm load) +1.11 V Pul_ln PuJseOut -3.2 V +2.0V
Propagation Delav t4+2+ 1.4 2.3 34 13

~ ~ ~
'4-2_
'4+3_

j j j j j
t4-3+
Rise Time '2+ 1.1 2.2 4.0
l20t~80%)

~ ~ ~
'3+
FeU ·'lime '2_
120 to 80%) '3_
 DUAL 2-WIDE 3-INPUT
MECL 10,000 series
"OR-AND" GATE

MC10518

The MC10518 is a basic logic building block

Po = 100 mW typ/pkg (No Load) providing the OR·AND function, useful in data
tpd = 2.3 ns typ control and digital multiplexing applications.
Output Rise and Fall Times:
= 3.5 ns (10% to 90%)
= 2.5 ns (20% to 80%)

POSITIVE LOGIC NEGATIVE LOGIC

(7) 3 (7) 3
(8) 4 (8) 4
(9) (9)
2 (6) 2 (6)
(10) 6 (10) 6
(11) (11 ) 7
(13) 9 (13) 9
(14) 10 (14) 10
(15) 11 (15) 11
15 (3) 15 (3)
(16) 12 (16) 12
(1) 13 (1) 13
(2) 14.. (2) 14

Numbers at end of terminals are pin numbers for L package {Case 6201-
Numbers in parenthesis dEmotes pin numbers for F package (Case 650).

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2SoC

v c el = VCC2
+2.0 Vdc VOIJt

""m""'
Coax

,---- ---l
I
50
I
Input I PROPAGATION DELAY

Pulse Generator

Input Pulse
t+ ::0 t- = 2.0 ±. 0.2 ns
(20 to 80%)

sb-ohm termination to ground 10- 100

i C8ted in .ach tcOp. channal input.
V out
~II inpl4t and output cables to the
o -.cope are equal lengths of 50-ohm
coaKiat cable. Wire length should
h c; 1/4 inch from TPin to input
pin and TPoutto output pin. V out
: "2:1 attenuated. '

See G"neta1 Information section for packaging and maximum ratings,

3-265
 ELECTRICAL CHARACTERISTICS s:
Each lull temperature range MECL 10.000
series circuit has been designed to meet the
...
n
o
de specifications shown in the test table,
after thermal equ il ibrium has been estab-
lished. The circuit is in a test socket or 3
...
C11
00
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are·terminated .
4
8
::J
through a 100-ohm resistor to -2.0 volts.
2 !:!.
6 ::J
Test procedures are shown for only one c:
CII
gate. The other gates are tested in the Q.
same manner. 9

-
10
11
15
12
13
14 LSUFFIX
CERAMIC PACKAGE
CASE 620

w TEST VOLTAGE VALUES

~
Ol @!Test
(Volts)

Temperatur. VIH max VIL min VIHAmin VILA max VEE

-56°C -0.880 -1.920 -1.255 -1.510 -5.2
+2SoC -0.780 -1.850 -1.105 -1.475 -5.2
+125"c -0.630 -1.820 -1.000 -1.400 -5.2
MC10518L Test limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Pi"
Und. -55·C +25o C + 125°C CVCCI

,,
VIHA min VEE

,
Ch,...ct.,istic Symbol TOS1 Min Max Min Typ Max Min Max Unit VIH max VILmin VILA max Gnd
Power Supply Drain Current IE 8 - 29 - 20 26 - 29 mAde - - - - 8 1.16
- - -

, ,
6 - - - -

, ,
Input Current lin H 450 265 265 ",Ade 6 8 1.16

,
7 - 450 - - 265 - 265 7 - - -
9 - 630 - - 370 - 370 9 - - -
lin L 6 0.5 - 0.5 - - 0.3 - .$JAde - 6 - - 8 1.16
7 - - - - - 7 - -

Logic "'" Output Voltage

9
2 -1.080 -0.880
-
-0.930
-
-
-
-0.780
-
-0.825 -0.630 Vdc
-
3.9
9
-
-
-
-
-
+
8 1.16
VOH
Logic "0" Output VOltage VOL 2 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc - 3.9 - - 8 1.16
Logic "1" Threshokt Voltage VOHA 2 -1.100 - -0.950 - - -0.845 - Vdc 9 - 3 - 8 1.16
Logic "0" Threshold Voltage VOLA 2 - -1.635 - - -1.600 - -1.525 Vdc - 9 - 3 8 1.16
Switching Times (1QO-ohm load) +1.11 V Pulse In Pulse Out -3.2 V +2.0 V
Propagation Oelay 16+2+ 2 1.1 3.5 1.4 2.3 3.4 1.2 3.9
3.9
n. 3 -
-
6 2 8 1.16
'6- 2- 1.1 3.5 2.3 3.4 1.2

~ l
1.4

I Rise Time C20 to 80%1

Fall Time C20to 11*)
'2+
'2_
1.3
1.3
4.1
4.1'
1.5
1.5
2.5
2.5
4.0
4.0
1.2
1.2
4.0
4.0 l +
-
- l l l
 ELECTRICAL CHARACTERISTICS
3:
Each full temperature range MECl 10,000
series circuit has been designed 'to meet .the ...n
...
0
de specifications shown in the test table,
after mermet equilibrium has bea:n esteb- (JI
lished. The circuit is in a test. sOcket or
mounted on a printed. circuit board and 00
8
transverse air flow greater than 500 linear
9 8
fpm is maintained. Outputs are ~erminated
through a l00-ohm resistor to -2.0 volts.
Test procedures are shown for only one
10
6
...
~

:;'
11 ~
gate. The other gates are tasted in the CD
same manner.
13 a.
14
15
3
16

F SUFFIX
CERAMIC PACKAGE
CASE 650

w
~ TEST VOL rAGE VALUES

....,
O'l
@Test
IVolts•

Temperatur. VIH max VIL min VIHAmin VILA max VEE

-5SoC -0.830 -1.920 -1.255 _1.510 -5.2
+2SoC -0.720 -1.850 -1.105 -1.475 -5.2
+125"c -0.580 -1.820 -1.000 -1.400 -5.2
MC10518F Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Pin
Unci. -55"c +25o C + 125°C 1Veel
Characteri.ic Symbol Min M•• Min TVp M.. Min M.. Unit VIH max Vil min VIHA min VILA max VEE Gnd

,
Tos'
Power Supply Drain Current 'E 12 - 29 - 20 26 - 29 mAde - - - - 12 4.5

,
input Current lin H 10 - 450 - - 265 - 265 jJAdc '0 - - - 12 4.5
11 - 450 - - 26~ - 265 11 - - -
'3
10
-
0.5
630
-
-
0.5
-
-
370
-
- 370
-
+ '3
-
-
10
-
-
-
-
+
lin l 0.3 }.lAd\: 12 4,5
11 - - - - - '1 - -

logic "'" Output Voltage VOH

13
6 -LOBO -0.830
- +
-0.930
-
-
-
~.720
+ -
-0.825 -0.~80
+
Vdc
-
7. '3
'3
-
-
-
-
-
+
'2
+
4,5
logic "0" Output Voltage VOL 6 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc - 7,13 - - 12 4.5
logic "'" Threshold Voltage VOHA 6 -1.100 - -0.950 - - -0.845 - Vdc 13 - 7 - '2- 4,S
Logic "0" Threshold Voltage VOLA 6 - -1.635 - - -1.600 - -1.525 Vdc - '3 - 7 '2 4,5·
Switching Times 1100-0hm 10.U +1.11 V Pulse In Pulse Out -3.2 V +2.0V
Propagation Delav 1'0+6+ 6 - - 1.4 2.3 3.4 - - n. 7 - 10 6 12 4,5
- - 3.4 - - -
~
2.3

~ ~ ~ ~ ~
'10-6- 1.4
Rise Time 420 to 8O%J '6+ - - 1.5 2.5 4.0 - - -
Fall Time e20 to 8Q%) '6_ ~- '-- - - ~~ ~- 4.0 - -
+ -
 4-WIDE 4-3-3-3 INPUT
MECL 10,000 series
"OR-AND" GATE

MC10519

The MC10519 is a 4-Wide 4-3-3-3 Input OR-

AN D gate with one input for two gates com-
POSITIVE LOGIC NEGATIVE LOGIC mon to pin 10 (14). Input pulldown resistors
eliminate the need to tie unused inputs to an
(7)
external supply.
(7) 3
(8) 4 (8) 4
(9) 5 (9) 5
(10) 6 (10) 6

(11) 7 (11) 7

(13) 9 (13) 9

(14)10 2(6) (14)10 2(6)

Po =.100 mW typ/pkg (No Load)
(15)11 (15)11 tpd ::: 2.3 ns typ
Output Rise and Fall Time:
(16)12 (16)12
= 3.5 ns typ «10% - 90%)
(1) 13 (I) 13 = 2.5 ns typ (20% - 80%)
(2) 14 (2) 14
(3) 15 (3) 15

Numbers at end of terminals are pin numbers for L package (Case 620).
Numbers in parenthesis denotes pin numbers for F package (Case 650),

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 2SoC

vee1 VCC2
+2.0 Vdc V out

I~
n coa •
' ">$''">
r--------.,
I
Cqax

I
50
Pulse Generator I PROPAGATION DELAY
I
I
I
I
Input Pulse
t+ = t- :: 2.0 ±. 0.2 nt
(20'080%) I
I
I V out

I
I
I
50-ohm termination to ground lo- I

l1~~"~
cated in each SCO.p9 channel Input.

All input and output cables to the

L ___
SCOpe are equal lengths of SO-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TPout to output pin. V out
is 2: 1 attenuated.
LfvdC
VEE

See General Information section for packaging and maximum ratings.

3-268
 ELECTRICAL CHARACTERISTICS 3:
Each full temperature range MECL 10,000 ...
o
o
serincircuit has been designed to meet the
de specifications shown in the t8St table,
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
3
4
...
C11
<C
mounted on a printed circuit board and
transverse air flow greater than 500 linear 6
8
::J
fpm is maintained. Outputs are terminated ~,
through a 100-ohm resistor to -2.0 volts. ::J
Test procedures are shown for only one 9 c:
(I)
gate. The other gates are tested in the Cl.
2

-
10
same man ner.
11
12
13
14
LSUFFIX
15 CERAMIC PACKAGE
CASE 620

w TEST VOLTAGE VALUES

N
0'1 (Volts)
CO @Test
Temperature VIH max Vil min VIHA min VILA max VEE
-SSoC -0.880 -1.920 -1.255 -1.510 -5.2
+2SoC -0.780 -1850 -1.105 -1.475 -5.2
+12SoC -0.630 -1.820 -1.000 -1.400 -5.2
MC10519l Test Limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW,
Und., -5SoC +25 o C +12SoC (VCCI
Characteristic Symbol Test Min Max M.. VIHmii. Vil min VIHAmin VILA mall( VEE

,,
Max Unit Gnd

,
Min TVp Min
Power Supplv Drain Current IE 8 ~

29 ~ ~

20 26 29 mAde 8 1.16
I nput Current lin H 7 450 265 265 j.lAdc 7 8 1,16

, ,
~
~ ~

, , ,,
9 450 ~

- 265 - 265 9 - -
10 ~

630 - 370 370 10 - -

lin L 7 0.5 0.5 - 0.3 - ,uAdc 7 .~

8 1,16
9 - 9
10 10 - ~

Logic "1" Output Voltage VOH 2 -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vdc 3.10.15 - - 8 1,16
LogiC "0" Output Voltage VOL 2 ~1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 3.10.15 ~
- 8 1,16
~iC "1" Threshold Voltage VOHA 2 -1.100 ~

-0.950 -0.845 - Vdc 10.15 3 ~

8 1,16
Logic "0" Threshold Voltage VOLA 2 ~

-1.635 - ~

-1.600 -1.525 Vdc 10,15 ~

3 8 1,16
Switching Times' lOO-ohm load) +1.11 V Pulse In Pulse Out -3.2V +2.0 V
Propagation DeiaV t4+2+ 2 1.1 3.5 1.4 2.3 3.4 1.2 3.5 ns 10.13 4 2 8 1,16
3.4

~
1.4 2.3

~ ~ ~
1.1 3.5 1.2 3.5

~ ~
t4-2- 10,13
Rise Time (20 to 80%) ,+ 1.3 4.1 1.5 2.5 4.0 1.2 4.3 ~

,
foall Time (20 to 80%. 1- 1.3 4.1 1.5 2.5 4.0 1.2 4.3 ~

-
 ELECTRICAL CHARACTERISTICS s:
Each full temperature range MECL 10.000
series circuit has been designed to meet the
...g
(")

de specifications shown in the test table,

after thermal equilibrium has been estab-
lished. The circuit is in a test socket or 8
...
CD
mounted on a printed circuit board and 9--;-
transverse air flow greater than 500 linear H) 8:::l
fpm is maintained. Outputs are terminated
11~ !:'.
through a 10o-ohm resistor to -2.0 volts. :::l
Test procedures are shown for onlv one 13 C
gate. The other gates are tested in the
6
~
same manner. 14

15
16 F SUFFIX
CERAMIC PACKAGE
CASE 650
2
3

w TEST VOLTAGE VALUES

~ eVolts)

"o @Test
Temperature VIH max Vil min VIHAmin VILAm. . VEE
-5SoC -0.880 -1.920 -1.255 -1.510 -5.2
+2SoC -0.780 -1.850 -1.105 -1.475 -5.2
+12SoC -0.630 -1.820 -1.000 -1.400 -5.2
MC10519F Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Pin
Und.. -55"<: +25o C + 12SoC (VCCI
Characteristic Symbol Test Min Ma. Min Typ Ma. Min Ma. Unit VIH max VILmin VIHA min VILA mlk VEE Gnd
Power Supply Drain Current IE 12 - 29 - 20 26 - 29 mAde - _. 8 1.16
I nput Current lin H 11 - 450 - - 265 - 265 /JAde 11 - - - 8 1,16
13 - 450 - - 265 -
265 13 - - -
14
11
- 630
-
- .- 370 - 370 + 14 - - -
-
+ +
'in L 0.5 0.5 - - 0.3 - /.lAde - 11 - 8 1.16
-

•
-
13
14
-

- +
-
-
-
- t -
-
+
-
-
13
14 - - + +
Lagle "1" Output Voltage VOH 6 -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vdc 3.7,14 - - - 8 1,16
Logic "0" Output Voltage VOL 6 -1.920 -1.655 -1.B50 - -1.620 -1.820 -1.545 Vdc - 3,7,14 - - 8 1,16
Logic "'" Threshold Voltage VOHA 6 -1.100 -0.950 - - -0.845 - Vdc 3,14 - 7 - 8 1,16
Logic "0" Threshold Voltage VOLA 6 -1.635 -1.600 -1.525 Vdc 3,14 - 7 8 1,16
Switching Times (l00-ohm load) +1.11 V Pulse In Put. Out -3.2V +2.0 V
Propagation Delay t7+6+ 6 - - 1.4 2.3 3.4 - - ns 1,14 - 7 6 12 4,5
'7-6- - - 3.4 - - -
~ ~ ~
1.4 2.3

! !
1,14
Rise Time (20 to 80%)
Fait Time (20 to .O%J
'6+
16- ! -
-
-
-
1.5
1.5
2.5
2.5
4.0
4.0
-
-
-
-
-
-
-
_.
 4-WIDE MECL 10,000 series
"OR-AND/OR-AND-INVERT"
GATE

MC10521
The MC10521 is a basic logic building block
Po = 100 mW typ/pkg (No Load) providing the simultaneous OR-AND/OR-AND-
tpd = 2.3 ns typ INVERT function, useful in data control and
Output Rise and Fall Times: digital mUltiplexing applications.
= 3.5 ns (10% to 90%)
= 2.5 ns (20% to 80%)

POSITIVE lOGIC NEGATIVE lOGIC

:~:~--~~~r---------, (8)4
(g) 5
( 1 0) 6 ----'---../----, ( 1 0) 6 ----,L..../----,

(11) 7 --~\~>--+-__, (11) 7

(13)9 (13)9

2 (7)
(14)10 (14)10 2(7)
3(6) 3(6)
(15) 11 (15)11
( 16) 12 ----<-....------,. ( 16) 12 ----,~../"---.

(1) 13 - -.......\~r_-t------.J (1)13

(2)14 (2)14
(3) 1 5 ----,c....___---- (3) 15 ----,--../----
Logic equation using pin numbers for L package Logic equation using pin numbers for L package
2= (4+ 5+6)-(7 +9+ 10)- (10+ 11 + 12)_(13+ 14+ 15) 2~ (4. 5.6) + (7 .9.10) + (10.11. 12) + (13.14.15)

3= (4+ 5+6).(7+9+ 10)- (10+ 11 + 12).(13+ 14+ 15) 3= (4e5_6) + (1e9.10) + (10.11.12) + (13.14.15)

Numbers at end of terminals are pin numbers for L package (Case 620),
Numbers in parenthesis denotes pin numbers for F package (Case 6501.

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C

VCC1 = VCC2
+2.0 Vdc
V out

""ffJ'"
r---- ----- - --,
CoaJIC

I
CoaJIC

50

I nput Pulse
50 PROPAGATION DELAY
t+ = t- = 2.0 ± 0.2 ns
(20 to 80%)

+1.11 V
I Vin

I
I
50-ohm termination to ground 10' ~-~"\"""..,.....-f------..J
I
I V out OR-AND
cated in each scope channel input.
L ______________ .J
All input and output cables to the t+
,cope are equal length, of 50-ohm t-
coaxia' cable, Wire length should
be < 114 inch from TPin to input
V out OR·AND·INVERT
pin and TP out to output pin. V out
I, 2: 1 anen uated.

S" Gen"a' I nformation section for packaging end maximum ratingt.

3-271
 ELECTRICAL CHARACTERISTICS s:
n
Each full temperatura range MECL 10,000
series circuit has been designed to meet the
;~
6
....
o
de specifications shown in the test table, U1
after thermar equilibrium has been estab-
lished. The circuit is in 8 test socket or
mounted on a printed circuit board and 7~
....
N

-
9
transverse air flow greater than 500 I inesf o
fpm is maintained. Outputs are terminated :J
2 ~,
through. l00-ohm resistor to -2.0 volts. 10
3 :J
Te,t procedures are shown for only one c:
(I)
gate. The other gates are tested in the 11
12~
c.
same manner.

L SUFFIX
CERAMIC PACKAGE
13~
14 CASE 620
15

TEST VOL TAGE VALUES

(Volts)
@Test
Tamperature VIH max VIL min VIHA min VILA maw. Vee
I
-55"<: -0.830 -1.920 -1.255 -1.510 -52
+2SoC -0.720 -1.850 -1.105 -1.475 -5.2
w +lZS o C -0.580 -1.820 -1.000 -1.400 -52
N
...... MC10521L Test limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
N Under -55°C +25"<: +l25 o C (Vee)
Characteristic: Symbol Test Min Max Min TVp Max Min Max Unit VIH max VIL min VIHA min VILA max Vee Gnd
Power Supply Drain Current Ie 8 - 29 - 20 26 - 29 mAde - - - - 8 1,16
Input Current lin H 7 - 450 - - 265 - 265 ,uAdc 7 - - - 8 1,16

,
9 - 450 - - 265 - 265 9 - - -
10 - 630 - - 370 - 370 + 10 - - - + +
lin L 7 0.5 - 05 - - 0.3 - ,uAdc - 7 - - 8 1,16
9 - - - - - 9 - -
+
Logic "1"
Output Voltage
VOH
10
3
2
-1.080
-1.080
-
-0.830
-0.830
+
-0.930
-0.930
-
-
-
-
-0.720
-0.720
-0.825
-0.825
-
-0.580
-0.580
+
Vdc
Vdc
-
10,13
4.10.13
10
4
-
-
-

-
-
-
-
+
8
8
•
1,16
1,16
Logte "0" VOL 3 -1.920 -1.655 -1.850 - -1,620 -1.820 -1.545 Vdc 4,10,13 - - - 8 1,16
- - -
Output Voltage
Logic "1" VOHA
2
3
-1.920
-1.100
-1.655
-
-1.850
-0.950 -
-1.620
-
-1.820
-0.845
-1.545
-
Vde
Vdc
10.13
10,13
4
- - , 8
8
1,16
1.16
- - - - -
Threshold Voltage
Logic "0" VOLA
2
3
-1.100
- -1.635
-0.950
- - -1.600
-0.845
- -1.525
Vdc
Vdc
10,13
10.13
-

- ,4

,
-
8
8
1.16
1,16
Threshold Voltage 2 - -1.635 - - -1.600 - -1.525 Vdc 10.13 - - 8 1.16
Switching Times
(100-ohm loadl +1.11 V Pulse In Pulse Out -3.2 V +2.0V
Propagation Delay t4+3_ 3 1.2 3.6 14 2.3 3.' 1.1 3.5 ns 10,13 - 4 3 8 1.16
-

t
t4-3+ 3 3
t4+2+ 2 - 2
t4-2- 2
+ + + + + + - 2
Rise Time
120 to 80%1
Fall Time
t20 to 80"')
'3+
'2+
'3_
'2_
3
2
3
2
1.0

~
4.5

~
11

~
2.5

~
4.0

~
0.9

~
4.4

~
j j -
-

-
-
j 3
2
3
2
j j
 ELECT,"GAL CHARACTERISTICS
s:
Each lUll temperature range MECL lO,OOO
series circuit has been designed to meet the
de specifications shown in the test table,
~~
10
...o
(')

c.n
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
mounted on a printed circu"it board and
~~~
...
N

~
transverse air flow greater than 500 linear
8
fpm is maintained. Outputs are terminated
through a 1OQ-ohm resistor to -2.0 volts. 14
7
6
...
:::l

:::l
Test procedures are shown for only one
c::
gate. The other gates are tested In the
same manner.
15
16~
FWH~
a
CERAMIC PACKAGE
CA~~O

~~
TEST VOLTAGE VALUES
(Volts)
@Test
Temperature VIH max VIL min VIHA min VILA mall( VEE
_56°C ~.83O -1.920 -1.255 -1.510 -5.2
+2SoC ~.720 -1.850 -1.105 -1475 -5.2
W +l25 o C ~.580 -1.820 -1.000 -1.400 -5.2
i\.)
-...J
W I Char.ctertstfc Symbol
Pin
Unde,
Test Min
_56°C
Ma. Min
MCl0521F Test Limits
+25"C
Tv. Ma. Min
+ 125°C
Ma. Unit
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:

V,Hmax V,L min V,HA min V,LA max VEE

IVeel
Gnd
Power Supply Drain Current IE 12 ·29 20 26 29 mAde 12 4.5
Input Current linH 11 450 265 265 j.J.Adc 11 12 4.5

, , , ,
13 450 265 265 13
14 630 370 370 + 14 + +
lin L 11 0.5 0.5 0.3 j.J.Adc 11 12 4.5
13 13

LogiC "1" VOH

14 +
-1.080 ~.830 ~.93O ~.720
+
~.825 ~.580 Vdc 1,14
14
8 12 4.5
Output Voltage -1.080 ~.830 ~.930 ~.720 ~.825 ~.580 Vdc 1.8.14 12 4.5
Logic "0" VOL -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 1,8,14 12 4.5
Output Voltage -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vde 1.14 12 4.5
LogiC "1" VOHA -1.100 ~.950 -0.845 Vdc 1.14 12 4.5
Threshold Voltage -1.100 ~.950 --0845 Vdc 1,14 12 4.5
Logic "0" VOLA -1.635 -1.600 -1.525 Vde 1,14 8 12 4.5
Threshold Voltage -1.635 -1.600 -1.525 Vdc 1,14 12 4.5
Switching Times
(1()(k)hm loadl +1.11 V Pul.'n Pul.Out -3.2 V +2.0V
Propagation Delay t8+1_ 1.4 23 3.4 1,14 8 12 4.5

~ ~ ~
t8-1+
t8+6+
t8-6-
Rise Time
120'.80%1
Fall Time
(20'.80%1
'7+
'6+
'7_
'6_
1.1

~
25

~ ~
4.0

j j j j j
 QUAD MTTL TO MECL
MECL 10,000 series
TRANSLATOR

MC10S24

Advance In:forIDation
The MC10524 is a quad translator fQ( interfiw:ing
data and control signals between a saturated togic
section and the MECL section of digital systems. The
MC10S24 has MTTL compatible inputs, and MECL
complementary open-emitter outputs that allow use as
an inverting!non·inverting translator or as a differen-
POSITIVE LOGIC NEGATIVE LOGIC tial line driver. When the common strobe input"is at
the low logic level, it forces· all true outputs to a
MECL low logic state and all inverting outputs to a
MECL high logic state. .
(9) 5 4 (8) (9) 5 4 (8) Power supply .requirements are ground, +5.0 Volts,
(10) 6-T""""-"""L_~--2 (6) (10) 6-..--,--~~--2 (6) and -S.2 Volts. Propagation delay of the MC10S24 is
(11) 7 3 (7) (11)7 3 (7)
typically 3.S ns. The dc )evels are standard or
Schottky TTL in, MECL 10,OOOout .
..---"'--_~--1 (5) 1 (5)
An advantage of this device is that MTTL level
(14)10 12(16) (14110 12(161 information can be transmitted differentially. via
~-,-_~--15(3) 15 (3)
balanced twisted pair lines, to the MECL equipment.
where the signal can be received by the MC10515 o~
(15111 13 (1) (15)11 13 (1) MC1051S differential line receivers. The MC10524 i.
14 (2) 14 (2) useful in computers, instrumentation, peripheral
controllers, test equipment, and digital
Numbers at end. of terminals denote pin numbers for communications systems.
L package (Case 620).
Numbers in parenthesis denote pin numbers for
F package (Case 650),
Po = 380 mW typ/pkg (No Load)
tpd "" 3.5 n·, typ (+1.5 Vdc in to 50% out)

Output Rise, Fall Times;

2.5 ns typ (20% to 80%)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C

V out V out
+6.0 Vdc Vee NAND AND
50-ohm termination to ground lo-

''''t rF~
cated in each scope channel input.

All ioput and output cables to the

Co.x Coax

""J
C0811C
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
50
be < 1/4 inch from TPln 10 input
r---'---, pin and TP out to output pin. V out
is 2: 1 attenuated.

Input

Pulse Generator
PROPAGATION OELAY
Input Pul . .
t+ = t- ~ 5.5 ±.D.S ns
(10 to 90%1

Unused outputs
con "ected to a
10G0hm resistor
to ground.
O.lI'F
L._

--11,,,, V out AND

+2.0 Vdc
L3+VdC
VeE VoutNAND

This il advance Information and 'Pacifications .r. subject to change without notlc •.
S . . Ganaral Information Metlon for PRk."lng.

3·274
 ELECTRICAl.. CHARACTERISTICS s:
Each full ~ure range MECL 10,000
_i_ circuit h_ been designed to meet the ....
(')

o
de opecificlrtions shown in th" t . table,
lifter thermal equilibrium ~ been estob- U'I
lilhed. The circuit is in 8 tett socket or
mounted on 8 printed circuit board and
4
~
6~
tranlVene air flow greater than 500 linear ~3 8::J
fpm is maintained. Outputs are terminated
...:i'

-
through 0 1OQ.ohm r_istor to -2.0 volts.
LSUFFIX
Test procedures . •8 shown for only one 10 12
c:
CERAMIC PACKAGE
input, or for one set of input conditions. CIl
~15 CASE 620 c..
Other inputs or. outputs are tested in the
11 13
same nwnner.
~14

• T_
TEST VOLTAGEICURRENT VALUES
V_ ...
T.......MUr. VIH",'" VIL .... VWH
.....
VF Vw
.....
Vee VIE 'II',. I ...
..... .,. ...
. .. ..........,
• oo"c .2.CI! +1.10 "4.0 .2.40 ~.2 ·1' ·211 +ID

...
+2Ii"c
+I2Ii"c
+1.110
·'.80 .....
+1.10 +4.0 +2.40
+2.40 ..... ~.2

~.2 .".1."
+ID
-1 +ID
W
"-:I
....,
C11
-
II ..........
,.....~ppty
Dr_mC,,"1Int
~iwe"""SutIPfy
Or.inCun'enl
..-
"
'CCH
..-
TM

• - ... -III"<:
....
IE'ClUtLT_Umili
+2ri°C
T. . ........
.."
- +1"'"
. ... ....
mAd,

mAd,
VIH ......
TEST YOlTAGEJCURRENT APPLIED TO PI" LIlTED .LOW:

Vll ..... V WH

5,e,7,10,1t
VF V. Vee VEE 'II '"
... ....
I•

I.

'CCl • mAd< S.8.1,10,1',"

R_CutTent
'. • 200 ,.Adc 5,1,10,11
"'
......
1 50 ,IoIAdc 6 I.
F~C""rem 'F • -12.8 mAd< ~7.1Q." I.

Inpul~VOIt ... 8V,n

.1

...
I.' ... -3.2 mAd,
Vd,
• I•
I.

-
I.' Vd, I•
Ce.mp 1.....1 Volt... V, -1.& Vd< I.

H. . OU....IVoltail VOH -1.,*,

-UBI .......
... ....830
....830
-1.5
'-0.780
.... 180
..g.825 .......
....... .......
Vde
Vd,
Vd,
••1
1
I.
I.
I•
LOIOII Ovtpul Voh... VOL -1.120 -1.856
-1.856
·1.850
-1.850
-1.820
-1.820
-1.820
-1.820
-1.545
-t.545
Vd,
• I.
I.
-1.120
.......
.......
Vd, '.1
H" TtnItIoId V~

L... Ttw........ VDh...

VOHA

VOLA
-1.000
-1.000
-1.836
-1.835
-1.100
-1.6QD
-0.845
-0.845
-1.525
-1.525
Vd,
Vd,
Vd,
Vd,
....•,. .........
."
I.

I •.
.............. '1 .... 3.0_
~
...OV• .7.0'1*
Pr. . . . . ian~
'+3.5 Vck 10 ~t(j)
110+6+
11o-&-
1.0 3.' •.0
6
I
• I.

111+" 1

+ +
tlt_&-
t11+7_ 3
1 1 1
j j
111-7" 3

. . . T_'...... _ , j '6+ 2' 3.' j

Fill Time"" to 28U '&- 2.' 3.'
Ci) ........... *- _ciraHt. ............ ~ for IhiI circuit . . . . if'-i f,om +1.5 Vdc in to the!iD% point on the outpl,lt --'Ofm. The +3.5 Vdc is II--. .... '**'- 811 . . .rId 1UPPY ....... 1hHtId 2 ............
 ELECTRICAL CHARACTERISTICS s:
(")
Each ·full temperature range MECL 10,000 ~
series circuit has been designed to meet the
de specifications shown in the test t&bte,
o
U'1
after thermal equilibrium has been estab- N
lished. The circuit is in a test socket or
mounted on a printed circuit board and 1~~8 ~
n-O
transverse air flow greater than 500 linear 11~6
fpm is maintained. Outputs are terminated
through a 100-0hm resistor to -2.0 volts.
....
::J
5'
Test proc;edures .e shown for only one 14 16 FSUFFIX c:
CERAMIC PACKAGE (1)
input, or for one set of input conditions. Q.
~3 CASE 650
Other inputs or outputs are tested in the
same ITlIIInner. 15

TEST VOLTAGE/CURRENT VALUES

VoIII mA
ill",
Tempe,.fur, VtH ",in Vil ""'. VAH V. VA Vee VEE 100 ',2 I I~
-SS°c'" -200 +1.10 +"'.0 "'40 -240 -500 -5.2 -.0 -12 +1.0
+2So C +1.80 +110 +4.0 "'40 +2.40 -500 -S.2 -10 -12 +1.0
+12SOC -180 +0.80 .4.0 -040 +2.40 -500 -5.2 -'0 -12 +1.0
MC10624F Tefl' Limits
W
II. ......
Po.

....
-SSoC +25~C

.... .,25oC
....
TEST VOL TAGEICUARENT APPLIED TO PINS LISTED aELOW:

l
~ ett..xtltnsuc S, ..... T", M" Mo" T,. M,"
""" VIHmin VIL m.1I VAH V. VA Vee VEE I"TI'2T ,;" G...
......
en
Nl'9d! 'v" Pow~. SupplV
a'don CU''''n!
'E 02 -66 mAde 03 12
•
POS,hvl' Power Supply IC~H 03 mAde '.10,11,14.1 03 12
ar~,n Curlen! "
ICCL 03 25 mAde 12 I - I - I - 14.9.10.11,14.15
A"v"'w Curr*1n! 'A 10 200 uAde 9.11,14.15 I~ 03 12
uAde 10 13
forward Curr~n! I, 10
50
·128 mAde 10 "
9,11,14,15 13
02
02
-3.2 10 13 02
'npu! B'~akdown Vollage BV,n "10 5.5 5.5 5.5 Vd, " 13
02
12 1 -1 -1
_ _ '0
11
5.5 5.5 55 Vd, 10 13
CI~mp Inpu! Vollag*1 V, "
10 -15 Vd, 13 02 1 I 10
-1.5 Vd, 03 12 "
H'9n Output Vollage VO" -1080 -0.880 -0.930 -0.180 -0.825 -0.630 Vd, 10.11 03 02
-0,180 -0825 -0.630 Vd,
LowOulpu! VollagP VOL
-1.080
-1920
-0.880
-1655
-0.930
·1850 -1620 -1820 -1.545 Vd,
10
"
10
13
13
02
12
-1.920 -1.655 ·1850 -1.620 -1820 -1545 Vd, 10 ..11 13 12
Hogh Th't~hold Vollage Vd,
'.(OHA -1.000 -0.950 -0845
" 10 03
" ""
-1.000 -0.950 -0845 Vd, 10 13
Low Tn,,'sholc1 VOlldgl;' -1600 -1.525 Vile
VOLA -1635
-1635 -1600 -1.5:15 Vd,
" " 10
10
03
13
""

n~
Sw.ldu", TimelSO-ll loadl t4i.OVdc Pulse In Pulse Out +7.0 Vdc ·3.2 Vdc
P'Op"'!IilI,on OI#I~V 10 13
1'35Vdc!oS""",G)
1)0"'6'"
tlo-5-
l5 60
""10 10
5 02

tl1 ... 5 ...

" +
111-5-
111+-7-
1 1 1
I '.-
111-7"t

A~T'm.''''%'o80~1
Fatl Timit (8)% to 2CWd .' ~~
25

25
3.'

3.
j j
m.s..'r"~~~~ I~ \at fi,cl.lit: ~~~tion "'ey ' !'" '"","Circuit" specified from "".5 Vde In to the 50% polnl on Ihe output w ....,form. Tne"'3.5 Vde i,lhQwn hllfe bec*-t. ell logic endlUpply Itve!,.,.ttliftecl 2voeb positivi.
 QUAD MECL TO MTTL MECL 10,000 series
TRANSLATOR

MC10525

Advance InforIDation
The MC10525 is a quad translator for interfacing
data and control signals between the MECL section
and saturated logic sections of digital systems. The
MC10525 incorporatasdifferential inputs and Schottky
TTL "totem p>le" outputs. Differential inputs al-
POSITIVE LOGIC NEGATIVE LOGIC low for use as an inverting/non-inverting translator or
as 8 differential line receiver. The Ves reference volt-
age is available for use in single-ended input biasing.
The outputs of the MC10525 go to a low logic level
(6)
(7)
:=::.:t>--- 4 (S)
(6)
17)
:~4(S) whenever the inputs are left floating.

~ =::.:t>---
Power supplV requ irements are ground, +5.0 Volts
~~5(9)
(10) 110)
5 (9) and -5.2 Volts. Propagation delay of the MC10525
(11) (11)

(14) 10
(15) 11
=::.:t>--- 12 (16)
(14)10~
(15) 11
12 (16)
is typically 4.5 ns. The MC10525 has fanout of 6
MTTL loads. The dclevels are MECl, 10,000 in and
Schottky TTL, or MTTL out. This device has an

(2)
(3)
14
15
=::.:t>--- 13 (1)
(2)

(3)
14~ 13
15
11)
input common mode noise rejection" of ±1.0 Volt.
An advantage of this device is that MECL level
information can be received, via balanced twisted pair
L--l (5) L - 115 ) lines, in the MTTL equipment. This isolates the MECL
Vaa Vaa logic from the noisy MTTL environment. This device
is useful in computers, instr·umentation. peripheral can·
trollen, tBst equipment ~nd digital communications
Numbers at end of terminals denote pin numbers for $Vstems.
L package (Case 620).
Numbers in parenthesis denOte pin numbers for
F package (Case 650),

Po = 380 mW tvp/pkg (No ~ood)

I CASE I VCC I VEE I
I 620
650
I Pin 9
Pin 13
I Pin 8
Pin 12
I tp::t - 4.5 ns typ (50% to +1.6 Vdc out)
Output Rise, Fall Times;
2.5 ns typ (20% to 80%)
VCCmax::: +7.00 Vdc

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 2SoC

vee "out vee

+50 Vde

Input
Coa~

r--
5"" J O 1 p.F

--,
I
4.0
280

Pulse Gen •• ato.

Input Pulse
t+ '" t- '" 2 0 1.0.2 ns
(20 to 80%)
fL All DIodes
MM07000
or Equlv

_1 69 \Ide o--+.....--1-.....~

50'Ohm termination to ground 10· One 'I'IDut from e,1ch gate must be tied to Vee
cated In each $COpe channel Input during test,ng

All input and output cabllils to the

scope are equal lengths 01 SO-ohm
coal'llal cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin. V out
il 10: t attenuated

PROPAGATION DELAY

V out

This is advance information and specifications are subject to change without notice.
See Goimerat Information section for packaging.
3-271
 ELECTRICAL CHARACTERISTICS
3:
Each full temperature range MECL 10,000 n
~
series circu it has been designed to meet the
de specifications shown in the test table, C
after thermal equilibrium has been estab-
fished. The circuit is in a test socket or
:~4 c.n
N
U'I
~~5

-
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Test procedures are
8
shown for onlv one input, or for one set of 10~ 12 L SUFFIX
CERAMIC PACKAGE
....
::J

input conditions. Other inputs or outputs 11 ::J

are tested in the same manner.
CASE 620 c::
14~ 13
(1)

15
a.
L---,
VBB
TEST VOLTAGE VALUES
(Voltsl
t>T...
T""pet'etur. VIHm.. VILmin VHAmin VILA",.. VIHH VILH VIHL 1 1v,LLl Vu I Vee I VEE
-5.2
-56OC -0.880 -1.920 -1.256 -1.510 100·11 -0.920 -1.8301-2.920 F,om .50
'2sOC -0.180 -1.860 -1.106 -1.476 100·281: -0.860 - •. 1201-2.860 Pin +5.0 -5.2
+1260(: -0.630 -1.820 -1.000 -1.400 100.4'" -0.820 -1.580 -2.820 1 +5.0 .1 -5.2

......,
.-
MC10U5L T_ Limita TEST VOLTAGE APPLIED TO PINS LISTED 8ELOW:

C~ad"''''ic
Pin
Undo<
Toot
....""
Min M.. Min
'>sOC
Ty. M•• Min M.. Unit VIHmu V'Lmin VIHAmin VILAm.a VIHH VILH VIHL VILL Vu Vee VEE Gnd
IOutput
Condition
l Neptive Power Supply 'E e 40 mAde 3.7.11.15 9 e 16
W
N
--.I
l Dr.ln Current
POSttive Power Supply
Dr.in Current
ICCH
ICCL
52
39
mAde
mAdc
2,6,10,14 3,7,11,15
3,7,11,15
16
'6
IX) Input Current 2,6,10,14 3,7,11,15 16
'in H (J) 115 J'Ade
3,7,11,15 .6
Input L . . . . . Current 'eBoll) 2 ""
1.0
,.Ade
/JAde
2,6,10,14
3.7,11,15 2,6.8,10,14 .6

Short-Circuit Current 'OS

3
4. 40
'.0
100
,.Ade
mA 2,6,10.14
2,6,10,14
3,7,11,15
3,7,8,1115
B
••
4,16
HilJh Output VOlt. VOH CD 2.5 2.5 2.5 Vd, 2,6,10,14 3,7,11,15 16 -2.0mA
Low Output Volt. . VOL 0.5 0.5 0.5 Vd, 2,6,10,14 3,7,11,15 16 12,0 rnA
High Threshold Volt. VOHA 2.5 2.5 2.5 Vde 6.10,14 3,7,11,15 16 -2.0mA
Low Threshold Volt. VOLA 0.5 0.5 0.5 Vd, 6,10.14 3,7,11,15 16 12.0 rnA

1~,~'~::4~'5
1",,""ln. Input VOLSI 0.5 0.5 05 Vd, 16 12,0 rnA
Protct ion T lISts

Reference Vat .... Tv••

VOLS2
-'.440
0.5
-1.320 -1.350
0.5
-1,230 -1.240
05
-1.120
Vd,
Vde 3.7,11.15
• 16 12,OmA

Common Mode
. Re;ectton Tests l VOH
2.5
2.5
2.5
2.5
2.5
2.5
Vd, 16
16
-2.0mA
-2.0mA
VOL 0.5 0.5 05 Vde 16 12.0mA
0.5 0.5 0.5 .6 12.0mA
...itdI.... T .....
Pt-opegetion Oel-V
I~ to +1.5 Vdcl
I......~~ '.0 4." 6.0
Pul.'n
6
6
Pu ... Out CL IpFI
25 3,7,11,15 9
• 16

d>
R" Time l+l.0Vdc to 2.0 Vdd
F•• Time(+1.0Vdc t~2.0Vdc)
'2+4-

....... ~
t2--4+

IndiwiduMty wt IKh input, epp6y VIH ...... to pin undlr ,-"

fa) 1~1y_1Kh Input, ~ VEe to pin u""~
+ + +
3.3
3.3 ! 2

~ ~ ! !!! 1
• IndMdulllty,. ~ oulDUl. foMcMI,. ............. for Din 4.
 ELECTRICAL CHARACTERISTICS 3:
Each full temperature range MECL 10,000 ...
o
~~8 o
series circuit has been designed to meet the
de specifications shown in the test table. U1
after thermal equilibrium has been estab- I\,)
lished. The circuit is in a test socket or 10~ 9 F SUFFIX U1
mounted on a printed circuit board and 11~ CERAMIC PACKAGE
0-
CASE 650
transverse air flow greater than 500 linear o
fpm is maintained. Test procedures are 14~ 16 ::J
15 ~.
shown for only one input. or for one set of ::J

:~1
input conditions. Other inputs or outputs C
are tested in the same manner. CD
Q.
~5
Vss

TEST VOL rAGE VALUES

(VollS)
@Test
Temper,ture VIH m'~ VIL min VIHAm,n VILAm,. VIHH VllH IVIHL IVILL I v.. I Vee I VEE
-SSOC -osao -1.920 -1.255 -1510 +0.170 -0.920 -1.830 -2.920 From
'50 -52
-0.780 -',05 p," '50 -52
+2SoC -1.850 -1.475 +0.280 -0.850 -1.720 -2.850
, .1 1
p," MC10525F Tnt Limltl
+12SoC -0.630 -1.820 -1.000 -1400 +0.420 -0.820 -I 580 -2.810

TEST VOL TAGE APPLIED TO PINS LISTED BelOW

'50
"
-SS"c
Ch....I... mu: Symbol
Unci ••
T.., M •• M .. M,"
+ZSoC
M .. M,"
+12SOC
M .. UOIt VIHAmlll VILAm,. VIHH V'LH VIHL VIU v •• Vee VEE 1 G... Ic~;::-;n
'i')
-fJ I Neg,t,1o'e Powe-r Supply
Dr"n Cun.nl
'E 12
T"
40
VIH rn •• VILm,n
3 J 1115 13 12
-..I
CO I POJ'llIIt Pow.r SUPP'y
Dr"nC"rrenl
leeH 13
"39 261014 3711.15
) 1.1115
13 12
12
leCL 13 mAdc 13
'tlPul Cun.nl ',nH (J) 6 115 ).JAdc 261014 37.11.15 13 12
13 12
Inpul leo. . . . Currenl IC80<2) "'
10
... Adt
.. Adt
3,7.11.15 2.6,10,14
3/1115 13 2.6.10,12,14

Shon·C"eu.1 Cunenl 'os 40

10
100
... Ade
261014
2.6,10.14
3 J.lt 15
13
13
3.1,11,12,15
12
•
',8
HI~ OutPUt Voll. 10mA
lOW Output Volu.Je
VO H Q)
VOL " 05 " 05
25
05 Voll 261014
761014 3.7.11.15
3)1115
13
13
12
12 12.0mA
High Threshold Volt. VOHA 25 15 25 2,10.14 37.111!l 13 12 10 mA
Low ThrntlOld Voli. VOLA 05 05 05 2.10.14 3.111.15 13 12 12.0mA
I'*-"".n_ InpUt VO l Sl OS 05 05 13 2.3.6,7.10, 12.0mA
ProtteltOn Tftll 11.12.14.15
VO LS2 05 05 05 Vde 13 12 120mA
Re'tf~ItVoll_ V •• -1.440 -1.320 -1.350 -1.230 -1240 -1120 3.11115
Cummon Moc1lt 13 12 10mA
Rejection Tests
VO"
" "
25 " 13 12 ·10mA

VOL " 05 05
25
05 13 12 12.0 rnA
05 05 05 13 12 12.0mA
Sw.lCh.,.,_
Prop.llon D ......
(~IO +1 5 Vde.
I '1 . .9-
110-9+
, .. 9-
.0 45 60
Puhlt In

.0
.0
PUI580UI

9
9
CL IpFt
25 3} 11.15 13 12

I
6 8
t~8+
+ + + .~
R'$@'T,mel·'0Vrkto20V •.kl
Fall T,mel" OVde lo20Vde)
t8+
t8_
33
33 ~ 1 1 1 1I 1
<D IndlVldUlilly tlllSt uch Input, apply VIH milt to pin under ttst
I%) Individually tnt lt8Ch IIlPUt. applv VeE 10 pin unci., lesl
0'1 Indlyi~ltv tetteach output. folloM", '''Imple shown for Pin 8.
 '\ MECL 10,000 series ·1
DUAL LATCH
' - - - -_ _- - - - - - . J .

MC10530
Advance InforDl.ation
The MC10530 is a clocked dual D type latch.
Each latch may be clocked separately by holding
POSITIVE LOGIC NEGATIVE LOGIC
the common clock in the low state, and using
the clock enable inputs for the clocking function.
., (fill !Ii
" (91 !Ii
If the common clock is to be used to clock the
Ot 11111
latch, the clock enable (CEI inputs must be in
Ot 11111 2UII 2(8)

~El (1018 eEl 1101 e the low state. In this mode, the enable inputs
3(71 3(7)
perform the function of controlling the common
clock (el.
Any change at the D input will be reflected
"'C t81 ..
(13)' " (81 ..
C (1:)19
S2 (1)'3
at the output while the clock is low. The out·
"' (1)13
puts are latched on the positive transition of the
14(2) '.(2)
clock. While the clock is in the high state, a
CE2(15111
change in the information present at the data
i!E211!1illl
02 (1.)10 l!1i(3) D2(14110 115(3) inputs will not affect the output information.
Input pulldown resistors eliminate the need
52 (18112 i!i2116112 to tie unused inputs to VEE.
Output rise and fall times have been opti·
mized to provide relaxation of system layout
and design criteria.
TRUTH TAllLE
The set and reset inputs do not override the
0 c Co 0..,
clock and D inputs. They are effective only
L L L L
H L L H when either C or CE or both are high.
••
L H 0"
H L 0"
Po ~ ;45 mW tYP/pkg (No Load)
• H

<1>"' Don"te •••

H
a"
tpd :::: 2.5 ns typ

Numbers at end of terminals ar. pin number. for L package (Ca•• 620).
Numbers In parenmnia denotes pin number. for F package (Ca .. 650).

CIRCUIT SCHEMATIC

This is advance information and specifications are subject to change VIo!ithout notice.
S.e General Information section for packaging.

3·280
 m~ f..,t: (·,i.~;'I··f iCI "f_! t:ft."ci-~''''t:.,;

ELECTRICA[· CHARACTERISTICS S, 5~--~-------,

Each full temperature range MECL 10,000

series tircuit has been designed to meet the
~
....
0' 7 MPoj 2 o

-
dc specifications shown in the test table,
CE' 6 U'I
after t.hermal equilibrium has been estab· W
lished. The circuit is in a test socket or
3 o
mounted on a printed circuit board and
transverse air flow greater than 500 linear
LSUFFIX
CERAMIC PACKAGE
n-
O
fpm is maintained. Outputs are terminated CASE 620 ::J
r+
through a l00-ohm resistor to -2.0 volts. R'4j
::J

R~ ,:~~-+----------,
Test procedures are shown for only one C
(I)
input, or for one set of input conditions.
Other inputs or Ol.,ltputs are tested in the ~
same man ner.
14

CE211~
02'0
"1 Q2r--'5 TEST VOLTAGE VALUES

S2'2
1 @Test
Temperature VIHmax VILmin
(Voltsl

VIHAmin VILAm.x VEE

-550 e -0.880 -'.920 -'.255 -'.5'0 -5.2
+2So C -0.780 -1.850 -1.'05 -1.475 -5.2
+125 O e -0.630 -1.820 -1.000 -1.400 -5.2
w
..:., Pin
MC10530L Test Limits TEST VOL TAGE APPLIED TO PINS LISTED BELOW,
CX) Und. -550 e +2Soe +125o C (Vee l
Char.ct .. irtic Symbol T.. Min MI' Min Typ Mo. Min MI' Unit VIHmax VILmin VIHAmin VILAmax VEE Gnd
Power Supply Drain Current IE 8 - 39 - 28 35 - 39 mAde 9 - - - 8 '.16
Input Current linH 6 - 375 - - 220 - 220 /JAde 6 - - - 8 1.16
9 - 450 - - 265 - 265 9 - - -
4 - 485 - - 285 - 285 4,9 - - -
+ +
Logic "1"
Output Voltage
'inL
VOH 2
7
4·
-
0.5
-1.0BO
485
-
-0.880
-
0.5
-0.930
-
-
-
285
-
-0.780
-
0.3
-0.825
285
-
-0.630
~Ade

Vdc
7,9
-
7
9
4
-
-
-
-
-
-
-
8
8
•
1,16
1,16

Logic "0" VOL 2 -1.920 -1.655 -1.850 - -1.620 -1.820 -'.545 Vdc - 7 - - 8 1.16
Output Voltage
Logic·"1" VOHA 2 -1.'00 - -0.950 - - -0.845 - Vdc - - 7 - 8 1.16
Threshold Voltage
Logic "0" VOLA 2 - -'.635 - - -'.600 - -'.525 Vdc - - - 7 8 1,16
Threshold Voltage
S'!Vitching T~mes (50 n Load) +1.11 V Pulse In Pul. Out -3.2 V +2.0 V
(See Figure 11
Propagation Delav t7+2+ 2 - - 1.0 2.7 3.5 _. - ns - - 7 2 8 1,16
_. - - - 6 - 5
t
I II
t5+2+ 2.7

I l
t4+2_ - - 2.7 - - 6 - 4

Rise Time (20% to 80%1

'&-2-
'2+
-
-
-
-
+
1.1
-
2.7
4.0
3.5
-

-
-
-
-
-
-
-
6
7
Fall Time (20% to 80%1 '2_ - - 1.1 2.7 3.5 - - - - 7
Setup Time tsetup 2 - - 2.5 - - - ns CD - 6,7 2 8 1.16
Hold Time thold 2 - - 1.5 - - - - ns (j). - 6,7 2 8 1.16
-

-All other inputs are tested in the same manner

CD See test circuit for test procedures.
 ELECTRICAL CHARACTERISTICS 519 3:
Each lull temperature range MECL 10,000
series circuit has been designed to meet the
....
0
0
01 11 6

~
de specifications shown in the test table, U1
after thermal equilibrium has been estab- CEllO W
lished. The circuit is in a test socket or 0
mounted on a printed circuit board and
transverse air flow greater than 500 linear 8
fpm is maintained. Outputs are terminated ....
::l

through a 10Q.ohm resistor to -2.0 volts. R18 F SUFFIX 5'

Test procedures are shown for only one C 13 CERAMIC PACKAGE c:
(1)
CASE 650
input, or for one set of input conditions.
Other inputs or outputs are tested in the
R21 .eo
same manner.

L.r-J Q2~2
CE2 '5
0214
"1 Q2r-- 3 TEST VOLTAGE VALUES

5216 ~ @Te...
Temptrlltur.
eVolts)

VIHmn VILmin VIHAmin VILAmlx VEE

-SSoC -0.880 -1.920 -1.255 -1.510 -5.2
+2SoC -0.7BO -1.850 -1.105 -1.475 -5.2
+12SoC -0.630 -1.820 -1.000 -5.2
w -1.400
,:., Pin
MCl0530F Test Limit.
TEST VOLTAGE APPl1ED TO PINS LISTED BELOW,
CO -55°C +2SoC +l25°C
"-l Und.. '''eel
Chllr.ct.istic Symbol Test Min Ma. Min Typ Ma. Min Mo. Unit VIHmlx VILmin VIHAmin VILAmlx VEE Gnd
Po~r Supply Drain Current IE 12 - 39 - 28 35 - 39 mAde 13 - - - 12 4,5
Input Current 'inH 10 - 375 - - 220 - 220 /JAde 10 - - - 12 4,5
13 - 450 - - -
~
- 265 13 - -
~
265
-

•
8 485 - - 285 - 285 8,13 - - -
11 - 485 285 285 11,13
linL 8' 0.5 - 0.5 - - 0.3 - /JAde - 4 - - 12 4,5
Logic "1" VOH 6 -1.0BO -0.880 -0.930 - -0.780 -0.825 -0.630 Vde 11 - - - 12 4,5
Output Voltage
Logic "0" VOL 6 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vde - 11 - - 12 4,5
Output Voltage
Logic "1" VOHA 6 -1.100 - -0.950 _. - -0.845 - Vde - - 11 - 12 4,5
Thntshold Voltage
Logic "0" VOLA 6 - -1.635 - - -1.600 - -1.525 Vde - - - 11 12 4,5
Threshold Voltage
Switc;:hing Times {SO n Load) +1.11 V Pul.ln Pul.Out -3.2 V +2.0Y
(See Figure 1)
Propagation Oel8Y t11+6+ 6 - - 1.0 2.7 3.5 - - ns - - 11 6 12 4,5
- - 2.7 - - 10 -

~
I II
'9+6+

I j
9
'11+6-
'10-6_
-
-
-
-
2.7
- +
4.0
-
-
-

-
10
-
-
-
8
10
Rise Time (20% to 80") '6+ - - 1.1 2.7 3.5 - - - - 11
Fen Time (20% to 80%) '6- - - 1.1 2.7 3.5 - - - - 11
Setup Tin. t.tup 6 2.5 - - n. (j) .10,11 6 12 4,5
Hold Time thold 6 1.5 - ns (j) 10,11 6 12 4,5

-All other inputs.re tilted in the ..me ".nner

(i) s.._ circu~ IOf , . . " ' _ " -
MC10530 (continued)

FIGURE 1 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@l250 C

veC1 = VeC2 =
+2.0 Vdc V out

Input Pulse
t+ = t- ::: 2.0 nl ± 0.2 "S
""ll'' '
r--- ---,

S
I

(20 to 80%) Clock Input lot----~'--o O--I---1D a

50-ohm termination to ground lo-

cated in each scope channel input. A

All input and output cables to the

scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be <
1/4 inch from TP in to input
pin and TP out to output pin. V out
is 2; 1 attenuated.
+1.11 Vdc
V'H

+'.11 V

CIOCk'~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
+0.31 V .~---.... - - - - - +1.1 1 V
C 50%
----", '-----+0.31 V
thold
-----+1.11 V

R'npu,~
- - - - - - - - +1.11 V
D '--_ _ _ _ _ _ _ +0.31 V
'-----+0.31 v tsetup

+ _____JI
r-+ 1 . 11V . a ~
I
S Input 50% '--_ _
- +0.31 V
------:::r--~ to+o:--
NOTE:
'2+ t setup is the minimum time before the positive
transition of the clock pulse (e) that information must
be present at the data input (0).

thold is the minimum time after the pOSitive tran·

sition of the clock pulse (e) that information must
remain unchanged at the data input (0).

3-283
 DUAL TYPE D MASTER-SLAVr MECL 10,000 series
FLIP-FLOP

MC10531

The MC10531 is a dual master-slave type 0

flip-flop. Asynchronous inputs Set (51 and Reset
R-5 TRUTH TABLE
(RI override the Clock (CCI and Clock Enabie
R S On+l (CEI inputs. Each flip·flop may be clocked sep-
L L Qn
arately by holding the common clock in the low
L H H
state and using the enable inputs for the clocking
H L L
function. If the common clock is to be used to
H H N.D.
clock the fli poflop, the Clock Eiia1iie inputs mllst
N.D.;::: Not Defined
be in the low state. In this case, the enable
inputs perform the function of controlling the
CLOCKED TRUTH TABLE
common clock.
The output states of the flip·flop change on
C 0 °n+l
Qn
the positive transition of the clock. A change
L 4>
H L L in the information present at the data (01 input
H H H will not affect the output information at any
other time due to master slave construction ..
¢ = Don't Care
Input pulldown resistors eliminate the need
C = CE + Cc·
A clock H is a clock transition
to tie unused inputs to VEE. Output rise and fall
from a low to a high state. times have been optimized to provide relaxation
of system design and layout criteria.

CASE VCCI VCC2 VEE

620 Pin 1 Pin 16 Pin 8
Po = 235 mW tvpipkg
650 Pin 5 Pin 4 Pin 12 f Tog ", 160 MHz typ

POSITIVE LOGIC NEGATIVE LOGIC

51 191

01 (111
5

7
..
, Ql ~2 161
Al 191

01 1111
5

7
r--
b
Ql ~2 161

CEI 1101
6~ CEI 1101
6~
01 ~3 171 01 ~3 171

Rl 181 4 1 51 181 4 4
Cc 1131 9--< Cc 1131 9-<
R2 111 13 52 11113
~
• 02 ~14121 02 ~14121

CE2 115111 ~ CE2115111

::;;r-
----;.
02 114110 Q2 ~15131 02114110 Q2 ~15131

52 116112
~ A2116112 4

Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650),

See General 1nformation section for packaging_

3-284
 ELECTRICAL CHARACTERISITCS S1 (9) 5 =:J

-
Each full temperature range MECL 10,000 01 (II)
eEl (10)
7
6
2 (6) L SUFFIX 3:
series circuit has been designed to meet the CERAMIC PACKAGE (')
de specifications shown in the test table, 3 (7) ...&
CASE 620
after thermal equilibr.um has been estab- o
lished. The circuit is in a test socket or Rt (8) 4-+--- U'1
Cc (13) 9 W

~
...&
rEST VOL TAGE VALUES

152 14(2)
@Test
Vdc +"1%
8
:::J
Temperature VIH max VILmin VIHA min VILA max VEE
~.
'__ Q2 15(3) -5So C -0.880 -1.920 -1.255 -1.500 -5.2 :::J
+25 oC -0.780 -1.850 -1.105 -1.475 -5.2
c:
<D
+12SoC -0.630 -1.820 -1.000 -1.400 -5.2 .e:
MC10531L Test Limits
Pin VOLTAGE APPLIED TO PINS LISTED BELOW:
Under -55°C +2S o C +125 oC (Vcel
Characteristic Symbol Tes. Min Ma' Min TVp Ma. Min Max Unit VIH max VIL min VIHA min VILA max Vee Gnd
Power Supply Dratn Current 'E 8 62 45 56 - 62 mAde - - - - 8 1,16
Input Current l,nH 4 - 565 - - 330 - 330 #JAde 4 - - - 8 1,16
5 - 565 - - 330 - 330 5 - - -

~ ~ ~
6 - 375 - - 220 - 220 6 - - -
7
9
-
-
420
450
-
-
-
-
245
265
-- 245
265
7
9
-
-
-
-
-
-
Input Leakage Current IInL 4,5,-
6,7,9'
0.5
0.5
-
-
05
0.5
-
-
-- 03
0.3
-
-
}JAde
/JAde
-
-
-
-
-
-
8
8
1,16
1,16
LogiC "1" VOH 2 -1.080 -0.880 -0.930 -0.780 0.825 -0.630 Vdc 5 8 1,16
Output Voltage 21 -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vdc 7 - - - 8 1,16
w LogiC "0" VOL 3 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc 5 -- - - 8 1,16

~
Output VOltage 31 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc 7 - - 8 1,16
LogiC "1" VOHA 2 -1.100 - -0.950 - -- -0.845 - Vdc - - 5 - 8 '1,16
C11 Threshold Voltage 21 -1.100 - -0.950 - -0.845 - Vdc - - 7 9 8 1.16
Logic "0" VOLA 3 - -1.635 -1.600 - -1.525 Vdc - - 5 - 8 1,16
Threshold Voltage 31 - -1.635 - - -1.600 - -1.525 Vdl.: - - 7 9 8 1,16
Pulse Pulse
SWitching Times(l00-ohm load) +1.11 Vdc +0.31 Vck In Out -3.2 Vdc +2.0 Vdc:
Clock Input
Propagation Delay 19+2- 2 1.4 4.6 1.5 3.0 4.5 1.5 5.0 ns - - 9 2 8 1.16
-

~
2 7 9 2

~
19+2+

Rise Time (20 to 80%'

16+2+
16+2-
2
2 ~ ~ +
7
-
-
-
-
-
6
6
2
2

Fall Time (20 to 80%)

'2+
'2-
2
2
1.0
1.0 J 1.1
1.1
2.5
2.5 J 1.1
1.1
4.9
4.9 J - -
9
9
2
2 J J
Set Input
Propagat Ion Delay 15+2+ 2 1.1 4.5 1.2 2.8 4.3 1.2 4.9 ns -
-
-- 5 2 8 1,16

~
15

~ ~
112+15+ 15 12
t5+3_ 3 - - 5 3
112+14- 14
+ + + + + - - 12 14
+ +
Reset Input
Propagation Delay 14+2- 2 1.1 4.5 12 2.8 4.3 1.2 4.9 ns - - 4 2 8 1,16
- -
~-
'13+15- 15 13 15
14+3+ 3 - - 4 3
+ + + + - - 13 14
+ +
• -• •
113+14+ 14
Setup Time tsetup 7 - - 2.5 1.5 - - ns - - 6,7 2 8 1,16
Hold Time
Toggle Frequency (Max)
thold
fTog
7
2 115
1.5
125
-0.5
160 125 MHz
ns
.. 6.7
6
2
2
8
8
1,16
1.16
Individually test each input;.apply V, L min to pin under test.
··Pin 3 is tied to pm 7 for these tests.
- . , rI- VtH max
tOutput level to be measured after a clock pulse has been applied to the CE mput (pin 6~ L
VIL min
 SI 9
ELECTRICAL CHARACTERISITCS

~
Each full lemperalure range MECL 10,000
Dl
s:C")
...
GEl ~ -~
series circuit has been designed to meet the ~--~ r F SUFFIX
de specifications shown in the test table, ""~"'--"'"
""'/,:.,=
CERAMIC PACKAGE
after thermal equilibrium has been estab- Rl 8 CASE 650 0
CJ1
...
lished. The circuit is In a test socket or Cc 13
mounted on a printed circuit board and R2 1 - - - W
transverse air flow greater than 500 linear TEST VOLTAGE VALUES
fpm is maintained. Outputs are terminated 5;1..-2
I @Test
Vdc:t.l% n
0
through a 100-ohm resistor to -2.0 volts. CE2 15
Test procedures are shown for only one D214-- Q2}- 3 Temperature VIH max Vilmin VIHA min VILA mak VEE ....
::J
_55°C -0.880 -1.920 -1.255 -1.500 -52 ::J
input, or for one set of input conditions.
Other inputs are tested in the same manner.
S2 16----- _. +25 o C -0.780 -1.850 -1.105 -1.475 -5.2 c:
<I>
+12SoC -0.630 -1.820 -1000 -1.400 -52
8:
MC10531F Test Limits
Pm VOL TAGE APPLIED TO PINS LISTED BELOW:
-SSoC +2SoC +l25 oC
uTne~~r
1Veel
Charactenstlc I Svmbol I Min M.. Min Typ M .. Min M .. Unit VIH maM VIL min VIHA min VILA mu VEE Gnd
Power Supply Dram Current I 'E 12 62 45 56 62 mAdc 12 ',5
I nput Current
I l,nH I 565 330 330 j..IAde 12 '.5
565 330 330

~ ~ ~
10 375 220 220 10
11 420 245 245 11
13 450 265 265 13
Inpul Leakage Current IInL 8,9· 0.5 05 03 ;.lAde 12 ',5
10,11,13- 0.5 05 0.3 .uAdc 12 ',5
~-"1" VOH 6 -1080 -0.880 -0.930 -0.780 -0.825 -0.630 Vdt: 12 ',5
Output Voltag!! 6f -1080 -0.880 -0.930 -0.780 -0.825 -0.630 Vdc 11 12 ',5
W LogiC "0" 7 -1920 -1.655 -1850 -1.620 -1.820 -1.545 Vdc 9 12 '.5
r:.., Output Voltage
VOL
7t -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 11 12 ',5
to
en LogiC "1"
Threshold Voltage
VOHA 6
6f
-1100
-1.100
-0.950
-0.950
-0.845 Vdc
Vd('
9 12 ',5
-0.845 13 12 ',5
LogiC "0" VOLA 7 -1.635 -1600 -1.525 Vdc 12 ',5
Threshold VOltage 7t -1635 -1600 -1.525 Vdc 13 12 ',5
Pulse Pulse
SWitching Tlmes(100-ohm load) +1.11 Vdc +0.31 Vde In Out -3.2 Vde +2.0 Vdc
Clock Input
Propagation Delay 1.5 30 4.5 13 6 12 4,5
t13+6-
11

~
6

l l
13

~
l l
t13+6+
11 6

I t10+6+ 10
10 6
tlO+6-
Rise Time (20 to 80%) 1.1 2.5 13 6
'6+
Fall Time (20 to 80%) '6_ 1.1 2.5 13 6
Set Input
Propagation Delay I t9+6+ 1.2 28 43 9
16
6
3
12 4,5

~ ~ ~ ~ ~ ~
'16+3+
t9+1- 9 7
t16+2- 16 2
Reset Input
Propagation Delay I '8+6- 1.2 28 4.3 12 4,5

~ ~ ~ ~ ~
t1+3-
t8+2+

Setup Time
t1+2+
T lsetup '11 15 25 10,11 6 12
+
4,5
Hold Time I 'hold 11 1.5 -0.5 10,11 6 12 ',5
Toggle Frequency (Mad I 'Tog 6 125 160 MH, 10 6 12 ',5
-lndlVlduallv test each Input, apply VIL min to pm under test.
··Pin 3 is tied to pin 7 for these tests
_ ~VIHmak
tOU!PUt level to be mees~red after a elock pulse has been applied to the CE input (pin 10)
VILmin
MC10531 (continued)

FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT

V out

Coax

t+ '" t--~1.0ns
(20% '080%) 50

Clock Input ot----~--------~CE Qf-------'

O---------lc
50-ohm termination to ground lo-
cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm
coaxial cable. Wire length should 100
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated.

FIGURE 2 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C

vee1 '" VCC2 '"

Input Pulse +2.0 Vdc
t+ = t- "" 2.0 ns ± 0.2 ns
(20 to 80%)

PW = ~2.0 ns
PRF = 1.0 MHz

Clock Input (Ot------;~-<l

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm
::J: 0.1 IlF
coaxial cable. Wire length should
be <1/4 inch from TPin to input
pin and TP out to output pin. V out VEE = -3.2 Vdc
is 2: 1 attenuated.

.~---..... - - - - - - + 1 . 1 1 V
C 50%
____-'1 '-----+0.31 V
R Input ~ .r\-+1.11 V
'----------'1 '----+0.31 V
r\! j+111 V
o
-----'I
S Input
+l '----+----"----+0.31 V

a Output
t 5 +2

50%P
0[[=
r-
'2+ nr-1r8~~-
--;

1
t4+2-

"tt,._!;.~20:::.0:::Yo _ __
Q __

NOTE:
----..J/
'5-3_ --I ~ t setup is the minimum time before the positive
a Output ----...,.1 transition of the clock pulse (el that information must
be present at the data input (0).
50%
thold is the minimum time after the positive tran-
sition of the clock pulse (C) that information must
remain unchanged at the data input (0).

3-287
 "\ MEeL 10,000 series
QUAD LATCH
'--------------'
MC10533

The MC10533 is a high speed, low power,

MECL quad latch consisting of four bistable
latch circuits with D type inputs and gated
Q outputs. Open emitters allow a large number
TRUTH TABLE of outputs to be wire-O Red together. Latch
G C D 0"+1 outputs are g~ted, allowing direct wiring to
H Q <I> L
Qn
Po '= 310 mW typ a bus. When the clock is high, outputs will
L L <I>
tpd = 4.0 ns typ follow D inputs. Information is latched on neg-
L H L L
L H H H ative going transition of the clock.
¢ -
- Don t Care
C==CC+ Ce

POSITIVE LOGIC

DO (7) 3
2 161 QO

GO 191
6 1101 Ql
01 1111 7

CE 181 4

Cc (1113

CE 116112

02 1131 9
11 1151 Q2
Gl (14110

15 131 Q3
03 12114

Numbers at end of terminals are pin numbers for L package (Case 6201-
Numbers in.parenthe'i~ denotes pin numbers for F package (Case 6501.

Ca .. VCC1 VCC2 VEE

620 Pin 1 Pin 16 Pin 8
650 Pin 5 Pin 4 Pin 12

See General I "formation section for packaging.

3·288
 '1i...,\/OM."" 'IOlt.tI.'~,* ti.t: UiM....~·i..,orqlii<i..:lI'i'i "I~""

~~~~~;_~_'~"_«_:~_~'_"_.'_;_~,_j+-~_.'"
:;:"'~2 i~~::';~l:~
after thermal equilibrium has beeq estab-
lished. The ci{cuit is in a test socket or
mounted on a printed circuit board and
CE4
c,.. 13
' i ' '''': '~""."" ',' ."'.',, .. :'... ,'.-

6
.""'i ,•.c':'

O~:
"'
..
~
.. _., .. _ ..

I f I
.... '
.
:~;:,;;.~~~,.~~':f:~:::::::.~~~~~::::::~:'~~2~;?~: !::?2:~:~~~~=~!:~!:?:~~~~~~!?~r.F~~;~~~~~~~~~~~

CASE 620
.-
LSUPFIX
CERAMIC PACKAGE
.
~.
, 'I
n
.....
C

~
n-
~<';~
tEST VOLTAGE VALUES O
fpm is main.tained. Outputs are terminated :J
through •. 100-ohm resistor to -2.0 volts. a .. IVoltsl
029 02 11Q2 !:t.
Test procedures are shown for only one @Test :J
ilIH~i~
input, or for one set of input conditions.
Other in"puts are tested in the same manner.
~110 ~'15Q3 Tempera1,ure
·SoC
VIHmax VILmin
-0.880 ·1.920 ·1.255
VIHAmo.
-1.510
VEE
-5.2
C
ct>
~
0314 0.3 +25"1:: -0.780 -1.850 -1.105 ·1.475 -5.2
+12SoC -0.630 -1.820 -1000 _1.400 -5.2
MCl0533L Test Limits TEST VOL TAGE APPLIED TO
Pin PINS LISTED BELOW:
Under -SSoC +2SoC ..
+12SoC
Characteristic Symbol Test Min Max Min Typ' Ma. Min Ma. Unit VIHmax VILmin VIHAmin VIHAmox VEE Gnd
Power Supply Drain Current 'E 8 - - - 60 75 - - mAde - 13 - - 8 1.16
Input Current lin H 3 245 .uAdc 3 8 1.16
4 - - - - 265 - - 4 - - -
·5 - -- - - 350 - - 5 - - -
- - +
•
13 - - - 350 - 13 - - -
lin l 3 '- 0.5. - - - - ,uAdc
• -- 3 - - 8 1.16

.~
ro.J
~
logic "1" Output Voltage

logic "0" Output Voltage

logiC "1" Threshold Voltage

VOH

VOL

VOHA
2
2
2
2
2
2
·2
,
-1.080
-1.080
-1.920

-1.100
-0.880
-0.880
-1.655

• •
-
-
-0.930
-0.930
-1.850

-0.950 .
-
-
-
-
-
..
-0.780
-0.780
-1.620
,,,•
-
-
-0.825
-0.825
·1.820

-0.845
-0.630
-0.630
-1.545

-
-
Vdc
Vdc
Vdc

}ldc
3,4
3.13
13
3.5.13
4
3,4
4
-
3
-
3
-
-
-
-
-
-
-
3
-
-
-
-
5
-
.8
,
8
8
8

•
1.16
1.16
U6

1.16

I
2 - - - - 3,4 - - --
2t
2tt
2tt
2
2
j
-
-
-
-
- 1 -
-
-
-
-
--
-

-
-
-

1
-
-
-
-
- 1
3

3
3
-
-
-
-
-
-
-
-
-
-
4
13
-
-
4
-
-
j
logic "0" Threshold Voltage VOLA 2 - -1.635 - - -1.600 - -1.525 Vdc 3,4 - 5 --3 8 1.16
- -

j .)
-

j j
- - - 4

j
2
2
2t
2tt
-
-
-
-
j -
-
-
-
-
-
-
-
-
-
-
-
4
-
3
-
-
-
-
-
-
-
-
-
-
-

,
2tt 3 13
PulSBln PulsaOut -3.2 V +2.0 V
. Switching Times
1100-ohm Load)
~
Propagation Delay t3+2+ 2 -- - 1.0 - 5.4 - - ns 4 - 3 2 8 1.16
t4-2+ 2 - - - 5.4 - - 3· - 4 2
-

1j
- - - - - -

j
t5-2+ 2- 3.1 5 2
3 - - 2.5 - - - - - - 3 2
tsetup
3 - - 1.5 - -- - - -- - 3 2
thold ,
--
Rise Time (20% to 80%1 '2+ 2 - - 1.1 - 3.5 -- - 4 -- 3 2
Fall Time (20% to 80%) '2- 2 - - 1.1 - 3.5 -- - 4 -- 3 2

tOutpu~ level to be measured after a clock Dulse has been applied.to the clock input. (Pin 41. ILVIH max
ttData input at proper high/low level while clock pulse is high so that device latches at proper VIL min
high/low level for test. Levels are measured after device has latched.
~ Latch set to zero state before test.
 00
ELECTRICAL CHARACTERISITCS 6 00
Each full temperature range MECL 10,000 3:
~
series circuit has been cfltsigned to meet the
de specifications shown in the test table,
llo
10 Q1
F SUFFIX
CERAMIC PACKAGE
n
....
01 11 I ...
after thermal equilibriu"m has been estab· CASE 650 o
~
CE
lished. The circuit is in a test socket or
mounted on a printed circuit board and Cc ·W

::~~'502 8
TE$T VOLTAGE VALUES

@Tnt
(Voltsl
...5'
::J

,. ~303 Temperatur.
-55"C
VIHlnlx
-0.880
Vilmin V.HAmin VIHAmII.
-1.920 -1.255 -1.510
VEE
-5.2 IiCo
2 Q3 +25"1: -0.780 -1.105 -1.475 -5.2
"'.850
+l25o C -0.630 -1.820 -1.000 -1.400 -5.2
MC10633F Tnt Limi.. TEST VOL TAGE APPL1EO TO
Pin PINS L.STEO BELOW:
Under -SSoC +25"C +l2SoC
Chlr.cte,i5tic Symbol Tnt Min M.. Min TVp MI. Min MIX Unit VIH.,... VlLmin VIHAmin VIHAmII. VEE Gnd
Power Supply Drain Current Ie 12 - - - 60 75 - -' mAde - 1 - - 12 4,5
Input Current lin H 7 - - - - 245 - - J,lAdc 7 - - - 12 4,5
8
9
-
-
-
-
-
-
-
-
265
350
-
-
-
-
8
9
-- -
-
-
-
- - - - - - - - +
• +
-
•7 350 1
- - 0.5 - - - - J,iAdc - 7 - - 12 4,5

,,,
lin L
w
~
8
Logl(~ "1" Output Voltage

Logic "0" Output Voltage

Logic "1" Threshold Voltage

VOH

VOL

VOHA
6
6
6
6
6
6
Ii
,•
-1.080
-1.080
-1.920

-1.100 .
-0.880
-0.880
. -1.655

-
-
cO.930
-0.930
-1.850

-0.950•
-
-
-
-
-
-
-0.780
-0.780
-1.620

-
-
-0.825
-0.825
-1.820

-0.845
-0.630
-0.630
-1.545

-
-
Vdc
Vdc
Vdc

Vdc•
7,8
1,7
1
1,7,9
11
7,8
8
-
7
-
7·
-
-
-
-
-
-
-
7
-
-
-
-
9
-
,,
12
12
12

12
4,5
.';5
4,fi.

4,5

Ij
6 - - - - 7,8 - - -

j -
j - - -
6t - 7 - -
- -
1
- - - - -

J
6tt -
6tt - - - - - - - B
6 - - - - 7 - 7 -
6 - - - - 7 - 1 -
Lo.gic "O!' Th.reshold Voltage VOLA 6 - -1.635 - - -1.600 - -1.525 Vdc' 7,8 - 9 - J2 4,5
-

! ,!
6 - - - - -

! !
8 1
6 - - -

! 8 - - -
~

Switching Tinw.
l1oo..hmLOI.CII
6t
6tt
6tt
-
-
-
-
-
-
-
-
-
-
-
- J -
7
7
I +1.11 V
.-
-

-
-
-
-
-
-
1
Pu . . ln PuI.Out -3.2 V +2.0 V

Propagation Delay 13+2+ 6 '- - 1.0 -. 5.4 - - ns 8 - 7 6 12 4,6

-
~
6 - - 5.4 - - 7" - 8 6

I
14-2+
'5-2+ 6 - - - 3.1 - - - - 9 6
t.tup 7 - - 2.5 - - - - - - 7 6

Rise Time (20% to 80%.

f'aHTimo 120% .0'_1
'hold
·'2+
'2-
7
6
6
-
-
-
-
-
-
1.5
1.1
1.1
-
--
-
tOulpUt_1 to 1I......and.f. . . .lock pul. . . . bIo8n """lied 10 tlw oIacIi l"Pllt'!,"''''' . .IJ:VIH.....
-
3.5
3.5
-
-
-
-
-
- 1, .
-
8
.
-
-
-
7
7
7
6
8
8 1
;::~
r.11i~~e="'~~~,_t~"·_~'''''~"""",~.,,~~ ,.,~.,l ~ ~,~"i"~ 2~:,;":'1 ;
'-::"'7-~" "':--:-:""~
.- MC10533 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C

'-.,\

VCC1 = VCC2
+2.0 Vdc V out

Coax Coax

Input Pulse
Input

Pul,sa Generator
50

""$''''
r----- ----.,
I
50
PROPAGATION DELAY

+1.11 V

tt"'t-=- 2.0±O.2ns
. (20 to 80%)
V out from 0 Input

L----n--.J
V out from G Input

5O-ohm termination to ground 10

cated !"
each scope channel Input ~ 0.1 IJF
C
All Input and output cables to the
scope are equal lengths of 1 CO-ohm VEE = ~3.2 Vdc Unused outputs
coaxial cable. Wire length should connected to 8
be < 1/4 ,inch from TP in to input 100-ohm resistor o
pin and TP out to output pin. to ground.

t setup is minimum time before the negative transitiorl of the clock

pulse ee) that information must be present at the data input (OJ.
thold is the minimu~ time after the positive transition of the clock
pulse ee) that information must remain unchanged at the data input (0).

APPLICATION INFORMATION
. The Me 10533 device consists of four bistable latch
citcuits with D type inputs and gated a outputs. When
the clock is high the outputs will follow the D inputs.
The latch will store the data on the falling edge of the
clock. The outputs are gated when the output enable is
low. All four latches may be clocked at one time with the
common clock, or each half may be clocked separately
with its clock. This devil:!! is useful as a temporary storage
element in high speed central processors, accumulators,
register files, digital communication systems, instrumenta·
tion and test equipment:

3-291
 MECL 10,000 series
DUAL J.K MASTER-SLAVE
FLIP-FLOP

MC10535

Advance In~orIDatlon
-,
POSITIVE LOGIC NEGATIVE LOGIC
The MC10535 is a dual master-slave de coup'
led J-K flip-flop. Asynchronous set (5) and
(R) are provided. The set and reset inputsover- j
re.tlI
51 (9t 5 - - - - - , 51 (9) 5 - - - - - , ride the clock.
Jl (11.) 7 2 (6)
A common clock is provided with sep....
Jl (11) 7 2 (6)
J-K inputs. When the clock is static, the j.j(
Kl (10) 6 3 (7) Kl (10) 6 3 (7)
inputs do not effect the output. .
The output states of the flip-flop change
Rl (B) 4----1'----' AI (B) 4 -1---' the positive transition of the clock. .
e (13) 9 C(13) 9 Input pulldown resistors eliminate the need
52 (16)12-+--~ 52 (16) 12 -1------, to tie .unused inputs to VEE. Output rise
J2(14)10 15 (3) J2 (14)10
fall. times have been optimized to provide relax.
15 (3)
tion of system desi9F1 and layout criteria_
K2 (15)11 '4 (2) K2 (15) 11 14(2)~'_· ____--,________________________________~.

Rl (1)13-----" AI (1) 1 3 - - - - - - ' CLOCK J-K TRUnt

R-S TRUTH TABLE TABLE'
Num~ers at eods of terminals denote pin numbers for
L package (C•• 620), L'

Numbers in parenthesis denote pin numbers for

H
F package (ease 650), N.D. o
(1.= Not.Qellned 'Output .1at.. change on"";
CASE V CCI V CC2 VEE t;1I8 trentilion of cJack for j
K ,nput condition p_~l.
620 Pin 1 Pin 16 Pin 8 Po ~ 280 mW tvp/pkg (No Loedl
650 Pin 5 Pin 4 Pin 12 'Tog· 1.0 MH, tVa

FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT

vee, "Vee2 =
+2.0 Vdc V out

Coax

All input and output cables to the

seops are equal lengths of 50-ohm
(Ot---~-----(~-;
coaxial cable. Wire length should
Clock Input
be < 1/4 Inch from TPin to Input
pin and TP out to output pin. V out
Input Pul .. is 2: 1 attenuated.
t+::: t-= 1.0n.
Duty Cycle""' 50%
Unu.d outputs connected to •

SO.ohm termination to ground 10· *O,'jlF 50-ohm resistor to ground.

cated in each scope channel"input.

VEE = -3.2 Vdc

r
...__________________________________________________________________~--------------------------..-.:'#,~: i
;.·;rl~; 1
-::,i
SH Generel Information Nctlon for peckaging.
Thla la advance Information end speclflcatlona ere subject to chano- without notice.

3·292
 ': -,
' .. "-.~,..,..; .. • ...; ••_ _ ..... :;;~.~~~~ .. .:.~~ •• N" •• : ••
"?':~:.~~,.~r-,:,:, t :.,~p"'" '~~':;~;':"';"., '~'.;7::

~
;~~P'81AA..."C\f~j:RISTICS
~

-
~.th(f~1I temp8'.fJ1ii'"r.ntli'MECL '111,odo .rfli.'cit-' J, ,
...A
",,1t"tI8i; been' deslgnOd tbi'ineet tl18 dC".peciflCatlonS LSUFFIX
o
i(1 a
shown in 'the u.f'tablil,efter ther";'l equilibrium he, CERAMIC PACKAGE
been established. The circuit i. in e test socket or CASE 620 ~
mounted on a printed circuit board and transverse air U'1
flow lII'elter ihen 500 Iineerfpm i. maintained. Out-
8
""y"
puts ere terminated through • 1QO-ohm resistor to TEST VOL tAGE VALUES
-2.0 volts. Test procedures Ire shown for only one :J
(VOLTSI ~.
input, or for one sat of in put conditions. Other inputs lilT... :J
~211
or outputs are tested in the same manner. 15.2"
Temperatur. VIH ma. VILmin VIHAmin VILA me. VEE c:
(t)
-5Soc -0.880 -1.920 -1.255 -1.510 -5.2 a.
1'1213
+250 C -0.780 -1.850 -1.105 -1.475 -5.2
+12&oC -0.630 -1.820 -1.000 -1.400 -5.2
MC10536L Tilt Limits
Pin VOLTAGE APPLIED TO PINS LISTED BELOW,
Undo< -550 C +26"c +1250C (VCCI
Cheric_ittic Symbol Toot Min Ma. Min Typ Mo. Min Mo. Unit VIH me. VIL min "IHAmin VILA me_ VEE Gnd
POMr Supply ~r.in CU~"t 'E 8 75 ·54 68 75 ,'mAde - - - 8 1.16
Input Cur,.". \ lin H 6.7.9.10.11 - 450 ' - -- 265 - 265 J.lAdc CD - - - 8 1.16
4.5.12.13 - 665 - 390 - 390 J.lAde CD - - - 8 1.16
Input LNk.., Current 'Iin L 4.5.6.7.9.
10.11.12.13
0.5
0.5
-
-
0.5
0.5
-- -
-
0.3
0.3
-
-
J.lAdc
J.lAde
-
- $ -
- -- 8
8
1.16
1.16
·~.·T"
Outpu.VaI • •
VOH 2
2C1>
-1.080 -0.880
-1.080 -0.880
·0.530
-0.930 -
-0.780
-0.780
-0.825
-0.825
·0.630
-0.630
Vdc
Vdc
5
6
-- -- -- 8
8
1.16
1.16

-- -- -
Lotic:·O" VOL 3 ·1.920 -1.655 -1.850 -1.620 -1.820 -1.645 Vdc 5 -. 8 1.16
Co)
~
Outpu.VoI_ j@ -1.920 -1.655 :1.850 -1.620 ·~1.820 -1.645 Vdc 6 - - 8 1.16

= Logic
_"1"_ Vol_ VOHA. 2 -UOO' -- -0.950 -- - .. -0.845 - Vdc -6 - 5 -- 8 1.16
Co) 2@ . -UOO -0.950 ~ -0.845 '- Vdc - - 8 1.16
. Logic "0" VOLA 3. -- -1.635 -. _1.800'- -- -1.525 Vdc -6 5 -.., 8 1.16
Thnihokl Volt.... 3@ " -1.635 - - -1.800 -1.525 Vdc - - 8 1.16
. .hoIIInt TI.... Pul.. ln Pul.. Out -3.2 Vdc +2.0 V.dc
Clock Input
ProtMlltion Delay t9+2+ 2 -
- -
-
1.0 .3.0 4.5 -- -
-
ns -
-
-
-
9
9
2
2
8 1.16

~ .~ ~
2

~
t9+2- 1.0 3.0
Ri. Ti .... (20'0 BOlli t2+·tJ+ 2.3 - - U 2.0 - - - - 9 2,3
... fall Time (20'0 BOlli t2_·t3"-
.-.
2.3 - - 1-1 2.0 - - - - 9 2.3
Set 'np'it
--
-- -- -
PropegIition Del-V t5+2+ 2 1.0 3.0 5.0 - ns - 5 2 8 U6
- -- -
t ~
12 15
.~
'12+15+ 15
'5+3- 3 -- - -- -
- -- 5 3

R_t Input
t12-+14- 14 - - + 12 . ·14
+ +
- -- - -- --
Pr. .tiO!' o.-v '4+2- 2 1.0 3.0 5.0 ns - 4 2 8 1.16
- - -- 4 3

~ ~ ~
3

~
1.4+3+
'13+15- 15 -- -
- - -
-
-
-
13 15

Setup Tim.
'13+14+ 14
7' - - 1.5
- +
ns
- 13
6.9 \§)
14
2 8
+
1.16
•.. tuP
Hold ime 'hold 7 - - 2.5 ns 6.9 @ 2 8 1.16
To.a!' Frequ.ency fT~. -
2
- '--
- 125 140 MHz 9 2 9 1.16

NOTES.
(i) ,ridividuelly '"feach input; .,ply vui max to pin under test.
(%) IndiYidu.lly test e~h input; apply V,L min to pin und~r test. Sl: VIH max
@ Output ,..,.. to I» m ...... red .her a clock pulse has been applied to the C input (pin 91 VI L min
<i)' OU~.,It levI' to be measured after 8 clock pulse has been applied to the C input (pin 9) -IL' VIHA min
<Sl Set Figure 2 for timing test diagr.m.' VILA mal(
 ELECTRICAL CHARACTERISTICS 51 9
s:
n
Each fulrtemperature range MECL 10.000 series cir· J111
~
FSUFFIX
cuit has been desiW'ed to meet the de specifications
shown in the test table, after thermal equilibrium has i<110 CERAMIC PACKAGE o
CASE 660
CTI
been established. The circuit is in a test socket or
AI.
W
mounted on- 8 printed circuit board and transverse air CTI

.... ~
C 13
han 500 linear fDm is maintained. Out
I TEST VOLTAGE VALUES 8:::I
J214 Q2 3
,
!
@l Test
Temper.tur.
(VOLTSI
~.
:::I
K2 lS C52 2 V'H mu: VILmin VIHAmin VILA ..... VEE c:
-ssoe -0.880 -'.920 -1.255 -1.5'0 -5.2 <D
A21 Co
+2So C -Q.7lD -1.850 ~I.I05 -1.475 -5.2
+1250 C -0.630 -1.820 -1.000 -1.400 -5.2

_Supply
InputCurfWl'

1_'~CunonI
-- DNin eu.....,
50_
IE·
linH
I';n
Uo*r
T. .
12
10.11.13.14.15
1.8.8.11
8.9.10.".13
--
-
0.5
-55"c
Moo
75
450
665
-
Min

-
-
0.5
MC' • •F T_ Lim'"
.2II"e
Typ
54

-
-
Mo.
68
265
390
-
Min
-

-
0.3
.,2I5"c
M..
75
265
390
-
Unit
mAde
.Adc
.,Adc
VIH max

<D
<D
-

-
VOLTAGE APPLIED TO PINS LISTED BELOW,

VILmin
-
-
-
VIHA .....
-

-
-
ViLA .....
-

-
-
VEE
12
12
12
12
(Veel
Gnd
4.5
4.5
4.5

LQ(Iie","
'in L
1.14.15.18 0.5
-1.080
- 0.5
-0.930
- - 0.3 -
-0.630
.Adc
~Adc - $ - - 12
4.5
4.5
VOH 8 -0.880 -0.780 -0.825 Vdc 9 12 4.5
0..""""",- 8(3) -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vdc 10 - - - 12 4,5
LQ(Iie'V'
.000"""V.._
VOL 7 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc 9 - - - 12 4,5
7Ci) -1.820 -'.655 -1.850 - -1.620 -1.820 -1.545 Vdc 10 - - - 12 4,6
w LQ(Iie .. , ..
VOHA 8 -1.100 - -0.950 - - -0.845 - Vdc - - 9 - 12 4.5
~ T h _ V.. _ 8@ -1.100 - -0.950 - - -0.845 - Vdc 10 - - - 12 4,5
CO.
.r. LQ(Iie "0"
.._ VOLA 7 -1.635 - -1.600 -1.525 Vdc 9 12 4.5
~V

7@ - -1.635 - - -1.600 - -1.525 Vdc 10 - - - 12

..........
Cleek Input
~ "'he In PulleOut
4.5
-3.2Vdc +2.0Vdc

",-""0Uy - - .. 1.0 3.0 4.5 - ns - - 13 6 12 4.5

to_. '13+8+ 6
- - - - - - 8

~
13

~ l l
'13+8- 8 1.0 3.0
Riot Ti_ (20 '&+7+ 8,7 - - 1.1 2.0 - - - - 13 8.7
FeU Time (20 to ""') ....7- 8.7 - - 1.1 2.0 - - - - 13 8.7
set I....,·
" ' - ' " " ' Ooley 8 - - 1.0 3.0 5.0 - - ns - .. S 8 12 4.5
'9+8+
- - - - - - 3

~
18

~
'16+3+ 3
ts-7- 7 - - - - - - S 7
'18+2_ 2 - - + + + - -
+ - - 16 2
R~lnput
",-""Ooley '8+8- 8 - 1.0 3.0 5.0 - - ns - - 8 8 12 4.5
t8+1+
t1+:J-
7
3
-
-
-
--
-
-
-
-
-
-
-
- ,
8 7
3

SotupTi_
t1+2+
'-tup
2
."
-
- -
+
1.5
+ -+
-
-
-
+ ns
- - I
lO.I3(§)
2
8
+
12
+
4.5
- ns
HokIr..".
T.... F _
"old
fTog
"8 2.5
125 140 MH,
10.13 (§)
13
II
8
12
12
4,5
4,5
NOTES,
CD IndMdullIV wt'-=h input;~ly VIH m81C to pin under test.
eI: I.......ck..lly _-=" input;.-pIy VIL min to pi" under.test.
c» .O"... t ..... to be
.
~.~. clOCk put. h. been ~ltId to the C i~put (pin 91
Ji: VIH mal(
~I L min ": .
• "O"..t ..... to"l'I~r.i""""clClltk pul"h.blln ••~tHId to th. C input tplntt J1.:V1HA min
."M~~"~,c;,;.,:.:",.;, ' . ViLA .... ..~:~f~~/'.:,
:-rel0636 (continued)

FIGURE 2 :-SWITCHING TIME TEST CIRCUIT AND WAVEFORMS" 25°C

VCCI • VCC2-
+2.0 Vdc V out

nco..
''fotp - t-· 2.0 ns ± 0.2 nl
(20 to 80%) All Input and output cables to the
:]iTPout scope .re equal lengths of 50-ohm
Clock Input (O+----#--<> coaxial cable. Wire length should
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated.

All unused outputs are tied to 100

ohm resistor to ground.

VEE' -3.2 Vdc

NOTE:
t ..tup is the minimum time before the positive
tr8n,itlon of the clock pulse (el that information must
be pr.sent at the input. J or K.
thold i'the minimum time after the positive tran·
Iition of the clock pulse (e) that information must
remain unchanged .t the Inputt J or K.

3-295
 ;"i J1p1

UNIVERSAL HEXADECIMAL
MEeL 10,000 series
COUNTER

MC10536

The MC10536 is a high speed synchronoul coune.

that can count up, count down, pre.t, or stop count.
frequencies exceeding 100 MHz. This binar{ COU ......
is useful in high speed central processors and per. . . . .
controllers. minicomputers, high speed digital comtnu-
nieations equipment Wid instrumentation. Theft.,. ..
u.
1
bility of this device allows the designer to pile
basic counter for most ..plications, and the .,nchrOft-
SEQUENTIAL TRUTH TABLE' ous count f""ture makes the MC10536 suil8bie for
either computers or instrumentation. . ~---.._

Th~ro
INPUTS OUTPUTS
Carry Clock Carry ••
the operation ' " -of
mode " 'the
.,, .... ' " Lines
counter. " '"' S1 ...
SI S2 DO 01 D2 D3 in ., ao 01 02 03 Out determine one of four operations; preset {progrll'nl
L L L L H H I/l H L L H H L increment (count up). decrement (count downl. Of
L H I/l I/l I/l I/l L H H L H H H hold (stop count I. Note that in the pr_t _
L H I/l I/l I/l I/l L H L H H H H clock pulse is necessary to load the counter. _ dIej
L H I/l I/l I/l I/l L H H H H H L information presant on the data inputs (DO, Dl. D2#
L H I/l I/l I/l I/l H L H H H H H and D31 will be entered into the counter .. Caory au
L H <I> I/l I/l <I> H H H H H H H goes low on the terminal count, or when the
coun~
H H I/l I/l I/l I/l I/l H H H H H H is being preset. .
L L H H L L I/l H H H L L L When an output is not needed, it can be left ~
H L <I> I/l I/l I/l L H L H L L H to conserve system pow.. (The open emitter outpUt
H L I/l I/l I/l I/l L H H L L L H will require no power if left open). The cau~ter ~
H L <I> I/l I/l I/l L H L L L L L st-ate only on the positive going edge afl the clock.
H L I/l I/l I/l I/l L H H H H H H Any other input may change at any time except durilll
the positive transition of the clock.
tfJ "" Don't care. This device is not designed for use with _ _
• Truth tabla shows logic Itates assuming inputs vary in sequence
shown from top to bottom.
clocks. Control. is via 51 and 52.. I
•• A clock H is defined as a clock input transition from a low to a A prosealer can be constructed using the MC10531
high logic level. in conjunction with the MC10631 which w~1 oper_
at over 200 MHz input frequency. A 500 MHz pr-.:'"
is possible using an MC1690 500 MHz D Flip-FlOP. 1ft
MC1670 300 MHz D Flip-Flop. and the MC10536.

FUNCTION SELECT TABLE

114110- Cin QO '--14(21 SI S2 Operating Mode
(1)13- C L L " Preset (Program)
Ql -15(31 L H I ncrement (Count Up)
(16112- 00
H L. Decrement (Co .... nt Down)
( 1 5 ) l t - 01
Q2 - 2 (61 H H Hold (StOP Count)
(10) 6 - 02
(91 5 - 03 Q3 - 3 m
(13) 9 - St
(11) 7 - S2 C out - 4 18) --'f-
Po = 625 mW typ/pkg (No Load)
f count = 150 MHz typ

Numbers at ends of terminals denote pin numbers for L package

(Case 620).
ICose I VCCI I VCC2 I VEE J
Numbers in parenthesis denote pin numbers for F package
1620 I Pin 1 I Pin 16 I Pin 8 J
(Co.e 6501. 1650 I Pin 5 I Pin 4 I Pin 12 I

See General I nformatlon section for packagIOg.

3·296
 ,_"T,·-·,:'
'fL'I'm'iexeTBiA'fiJ:M1ft~TICi' .....,.. W,"'" ',.", ",~"""",.,, " \ , . ' ':-"""1S"'",,!,".'I'7¥1 _t"It~~""':.~.~

",' i

-
:t'iiifi:fuliliiTiji8retU,.'ri,.geMECLfO 000 .. "4 .. '
_lei c/rwlt h.. been designed to ~ the 'n
...a
Q:,tp8Clflcatlonl shown In the toot table, Q1' 15' ' LSUFFIX Q
12 00 CERAMIC PACKAGE
after thermal equilibrium h.. been _I>- CJ1
~
lisheil· The circuit is in a toot lOCket or 11 01 . CA5E 620
Q2 2
mounted on a printed circu it board and ..s 02
transversa air flow groater than' 500 linear
fpm is maintained. Output""e terminated
5
9 - 51
03 Q3,-- 3 ,--- TEstVOLTAOE VAWES 8::J
through a 1QO.ohm resistor to -2.0 yolts. IVofbl ~.
Toot procedures are shown for Only one 7 - 52 C out f--:4 eT.. ::J
inp~t. or. for one set of input conditions.
TMftper"lIre VIH",. . Vll",,,, VIH.""ft I ~ILA me. I VEE c:
<'D
Othor inputs or output. are tested in tho -51"1: -<1.880 -1.920 -1.255 -1.510 ·u Q.
.•2I"c -(l.780 -1.850 -1.105 ~. -1.475 -5.2'
same manner.
+12&'>C -0.830 -1.820 -1.000 -1.400 -5.2
MC10138L T... limha .

0Wect8r...
PoWer"Suppty Drain Current
1...-1":
'E
Pi.

8
...
-
-I&·C
....
165
' ...
-
+26Q C
Ty.
'20
....
'50
... .
-
+laoC
...
165
Unit
m,Adc -
TEST VOLTAGE APPLIED TO "NILISTED BELOW

VIH ..... VILmin

-
VtHAmtn
-
ViLA .....
-
VEE
8
IVcc·
.....
1,16
Input Current
lin H I 5.6.~'~12
-
315 -- -- 220
-
220 /oIAdc 5,6,11,12
- - -
8 1,16

l l ~
450 265 265 1
9,10 - 41. - .. 2" - 2•• 9,10 - -
13 - 4gS - - 290 - 290 13 - - -
.......,..
Out~1 Volbgl
lin L.
VOH
All
'4<Zi
0,5
-1.080
-
-O.a90
0.5
-0.930
-
-
-
~.780
0,3
-0.825
-
-0.630
"Ad,
Vd,
-
12
CD
1,9
- - 8
8
1.16
1,16

.......0 .. ..
VOL "<Zi -1.920 -1.656 -1.850 -1.620 -1.820 -1.645 Vd, 1,9 8 1. IS
. Output Vol ....
<tJ
N
L.......,.
,",,",,o.ld VoU", .
VOH~ 140 -1.100 - -0.950 - - -0.845 - Vd< - 1,' 12 8 1,16

CO
..... 1....... °"
Thrlilhotd .VoItaII
VOLA "<Zi - -1.636 - - -1.600 - -1.525 Vd, - 1,' 12 8 J.18

Switchi . . Til"Ml
1100-0ttm lotd)
+1.11 V -to.31V
"'''In _Out -3.2 V +2.0 V

Pra,...tton o.t.y
Cloc:k Input I 1.13+14'- 1.
••
0.1 4,6 1.0 3,3
..•
4,' 1.' 5,2 12 13
,.
.4 1,16

t
'13+'4- 0.8 '.6 1,0 3,3 1.' 6.2
t'3+4. 4
•
2.0
2,0
11.0
11.0
2,5
2.5
1.0
1,0
10.6
10.5
2.'
2.'
1:l.6 •
!,.
113+4- 12.6
C.r~ In To c.,ry Out 1.6 7;1 1.6 5.0 8.9' 1.9 1.6
"0-4- 4~ 13 '0

"UpTi.,..
t'O+4+
• 1.6 1,1 1.6 50 6,. I,. 1,6 13 '0

. OM. InpUt. 112+13; 3,5 1.9 12,13

112-13. '"
14 3,' 1,.9 12,13

,.,.,.
SeIKt InpUlS 19+13. 1,' 9,1l
14
17+''3+ ·7.S 7,13
c;;;:;Tn InpUt "0-13+ 3,1
-1.0
•
9
10,13
10.13

.
'13+10+
HoldTi""
o.t.lnlXlt,
1'3+12+ ,.,. -1.0 7,9" 12,13

Select Inpull
1 13+12_

1'3-+Q. ,.,. -1.0

-2.5
" 12,.13
'.13

c;;;;-inI"put
' 13+7+
113+10- ,.,. -2.5
-1.6
3.'
7,13
10,13

,,
1'0+13. 10,13
Counting Frequency feountup 115 125 150 115 MH, 13
'cOuntdown 115 '25 '50 115 MH,
Ri.. Ti,..
1_ .. _ , t ••

...
',4+
0.9 3.3 1.1 2,0 3,3 1,2 3,1
,.
FeU Time
120% to 80%» t14_
",.• ~ ~ l ~ l 1 ,.•
(J) IndividUllly appfy V I L min to Pin unctlr test, (b Measure output after clock pulse Vll f VIH appears at clock Input (pm 13) (3) Before test set 11111 a outputs to III logic high.
 ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000 Cin 00 2 3:
...
14

~
series circuit has been designed to meet the C
(")
F SUFFIX
de specifications shown in the test table, 01 3
16 DO CERAMIC PACKAGE 0
after thermal equilibrium has been estab-
lished. The circuit is in 8 test socket or 15 01
CASE 650 U1
mounted on a printed circuit board and
02 6 W
10 02 0)
transverse air flow greater than 500 linear
fpm is maintained. Outputs are terminated 9 - 03 03 - 7
TEIT VOLTAGE YALUES
n0
through a 1()().ohm resistor to -2.0 volts.
Test procedures .8 shown for onlv one
1 3 - 51
.r..
IV... I
...;5'
::J

--
input, or for ana set of input conditions.
1 1 - 52 Caut r--8 T..........ure VIH .... vlLlllin VIH ...... VILA_ v..
c:
Other inputs or outputs are tested in the ~.8110 -1.920 -1.256 -1~5'O ....2 CI)
same manner. .2&"c -0180 -1.850 -1.105 -1.475 .... 2 Co
.,;aoc -0.830 -1.820 -1.000 -1.400 ... .2
MC1D538F T. . Lirni1l

....-
""1.
I_I~
Pi.

Mi.
-eeoc
.... Mi.
.a"c
T., .... 00;.
+12fiOc
.... ....
TEST VOL TAG! APPLIED TO ,'INS LIlTED _LOll

VIH ...... VILllllin VIMA..- ViLA .... v.. ...

lVeel

......
Power Drein Cur,.n, I " I 12 165 120 150 165 mAdc 12 '.5
Inpul CUrtwnl
I Ito H 19.10;~5.16 36. 21S 21S .Adc 9.10.15.16 12 4.5

~
11

~
260 260
13,14
1
"0 2""
26.
2""
285
13,14
1 1
......,..
Outpu. Vol~
I,n L
VOH
All
2~
O.S
-1.080 -<1.660
O.S
-0.930 -0.780
0.3
-0.825 -0.630
.Adc
Vdc 16
(j)
11,13
12
12
'.'
'.5
..... '0'. VOL 21Z -1.120 -1.655 -1,850 -1.620 -1.820 -1.545 Vdc 11.13 12 4.5

'..
Output VOltllll
W
~
Lotic "1" VOHA 2C1 -1.100 ~.950 -0.845 Vdc 11.13 III 12
ThNlhold VoI_
CO .....'0'. VOLA 21Z -1.636 -1.600 -1.526 Vdc 11.13 18 12 '.5
~Vol"
Swrritcfti,.Ti"..
tl~mLOIdJ
+1.11 V .0.31 V ........ _0.. -3.2 V +Z.V

~tOf'IOrtI.y
Clock Input '1+2+ 2 1.0 3.3 4.S 16 I 1. '.5
t1+2- 2 1.0 3.3 4.S
"+8+ I 2.5 7.0 10.5 11
11+8- I 2.5 7.0 t(}.S 11
c;;;;TnTo~ "4+ ICI) I." 5.0 6.9 11 1.
'''+9+ I 1.6 5.0 6.9 11 1.
art Up Tim.
o.u Inputs 118+1+ 3.S 11.13 1.18
118-1+ 3.S 11.13 1.16
Stfect Inputl 113+1+ 7." 1,13
111+1+ 7.' 1.11
c;;;Tn Input ·114-H 3.7 11 13 1,1:4
11+14+ -1.0 11 13 1,14
Ho6d TifM
Oat. Inputs 11+18+ -1.0 11.13 1,11
1.1+1&- -1.0 11.13 '1.18 .
Sttect InPf,ttl 11+13+ -2.5 1.13
11+11- -2.5 1,11
~Inpul t1+1 ..... -1'.6 11 13 1.14
114+1+ 3.1 11 13 1,14
Countj,. F,.quency fcountup 125 150 MH, 11 1

...
-.-
'countdown 126 150 MH. 13

'. J
RiliTima 1.1 2.0 3.3 11

I•
I

~ ~
1 - .. - 1
l
'2+ 2
PolIn.... ta-
'2- J I

"-":(;""
~i~;,.,,~~~,t~ ....~,~~: "II~!"'l!!"oho!:!'OC"~~I&.£V1H~"~~tl~j31 G,~-""'Q"""''' •.__ ,
.,,:.
\;'
MC10536 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS .. 25"c

NOTE:
.tup i, the minimum time before the pOliti.... e
tranlition of the clock pulse Ie) that informetlon "('Ult VCC1 '" VC;:C2 '" .2.0 Vdc Vout
be Aretant at the input 0 or S .
thold' i. ttte minimum time after the pOliti.... e tran·
.ition of the clock pul .. ICI thet information mUlt
remain unchenged et the input 0 or S.
Co••

50
In~ut Pul..
t+ :: t- "" 2.0 ns ± 0.2 ns
(20 tb 80%)
Clock Input @--.....- " - o

\ \ TP out
Ctock
.0.31 V

Q Output

VEE = -3.2 Vdc

c
r-----__-- .'.1, V
+0.31 V

SO·ohm termination to ground lo-

cated In each scope channel input.
o DrS
All Input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 114 Inch from TPln to input
pin and TP out to output pin. V out
is 2: 1 anem.Jated.

Unused outputs are connected to

8 100-ohm resistor to ground.

SET UP AND HOLD TIMES

'e) il the minimum time to WIIlt eft.,. the

counter hu ~n enebl~ to eJodt it.
Ib) I. the minimum 'tlme before the
counter ..... tt.-, dl.bled t ....t It rn.y
be elodled. Clock
Ie} i. the m6nlmum time b4rfore t ....
count.r I, enabled tNt' a IOlock pul.
may be applied with no eftect on the
IUIte of the countllr.
, Id} I, the minimum time to welt eft_
the counter .. d_bled that • elodl
pul. rNY be applied with "0 effect In
the 1UIt. Of the count_.
(b) .,.d lei rn.sy be neeatlve "um",

3-299
MC10536 (continued)

COUNT FREQUENCY TEST CIRCUIT

Vee,· VCC2" +2.0 Vdc V out

Co.x

Clock Input @)--.....----<>--t

Input Pull.
t+ .. t- .. 1.0 n. All input and output cables to the
Duty Cve'. - 5o" ~ scope are equal lengths of 50·ohm
coaxial cab! •. Wire· length shou~d
O.'''F
l be <
1/4 inch from TPjn to input
pin and TP out to output pin. V out
60-ohm termlnetlon to ground 10- ...,... 0.1 "F is 2:1 attenuated.
co," .n Neh ...... chon ...' 'nput. ~
Unused outputs are connected to
• 100-ohm r.,istor to ground.

UNIVERSAL BINARY UP/DOWN COUNTER i

r-------------------------------------~--~----------------------~

51 •

52 1 <>-1>-+-L__ "--+---,

12 DO 14QO 1101 16Q1 602 202 503 303

3-300
j'tr MC10536 (continued)
":-' f

APPLICATIONS INFORMATION
iiTo provide more than four bits of counting capability several
~. ~10638 counter. may be cascadad. The Carry In input overrides
'. clock when the counter is either In the increment mode or the
t mode of operation. This input aUows several devices to
c-=eded in a fuliV synchronous multistage counter as illustrated
Figure 1. The carry is advanced between stages IS shown with
external gating. The CiiTyTri ofthe first device may be left open.
".,..; . . system clock is common to all devices.
~~: j I The various operational modes of the counter make it useful
. :. '.t=.
-I
wide variety of applications, If used with MECL III davices.
with input toggle frequencies in excess of 300 MHz are
. ~ . Figure 2 shows such a prescaler using the Me 10536 and
~' ~ 1 requires In additional glte. such os %MCI0609 Ind I flip-flop such
$!
MC1670. Usa of the MCI0631 in place of the MCI670 permit.
200 MHz operation.
The MCI0536 may .Iso be used I I a programmable counter.
The configuration of Figure 3 requires no additional gatas, although
maximum frequency is limited to about 50 MHz. The divider
modulus is equal to the program input plus one 1M - N + II. there-
fore. the counter will divide by • modulus varying from 1 to 16.
A second progr.-nmabl. configuration is also illustrated in
Figure 4. A pulse swallowing technique is used to speed the counter
operation up to 110 .MHz typically. The divider modulus for this
figure is equal to the progrem input 1M z NI. The minimum
modulus is 2 because of the pulse swallowing technique•• nd the
modulus may vary 'from 2 to 1S. This programmable confitJJration
os%MCI053I.

FIGURE 1 - 12 BIT SYNCHRONOUS COUNTER

LSB MSB

~r:!:m----~~------------------------~--------------------------~
Note: 51 and 52 are set either for Increment or decrement operation.

FIGURE 2 - 300 MHz PRESCALER

Logic High

MC101i311
SI
S2
o aJ--t-------1~C ________ ~~~
'-_________ t nput Frequency
32

MC1670

3-301
MC10536 (continued)

FIGURE 3 - &8 MHz PROGRAMMABLE COUNTER

Progr.m I"put

fin - - -.....----1 C
Cln
<:out 1---....- - - f out
S2

Sl

1 f out "" ::-_ _..,f:;.ln:...-._-:

Program Input +1
2 f m•x ~ 50 MHz Typ.
3 Divide Ratio is from 1 to , 6.

FIGURE 4 - 100 MHz PROGRAMMABLE COUNTER

Program Input

I I I I
DO 01 02 03
C

- S2 MC10536

; - - - ~1
00 02 03

L
- 1--, 0 0
1 f out
~
%MC10509
%MC10531

°l
C

fin
f out = ::----"':---
Program Input
2 1m.x ~ 1'0 MHz Typ.

3 Divide Ratio i. from 2 to 15.

3-302
 MEeL 10,000 series
UNIVERSAL DECADE
COUNTER

MC10S37

The MC10537 is a high speed synchronous counter

thatca" count up. count down, preset, or stop count at
frequencies exceeding 100 MHz. This decade counter
is useful in high speed central processors and peripheral
controllers, minicomputers, high speed digital commu-
, SEOUENTIAL TRUTH TABLE" nications equipment and instrumentation. The flexi-
L INPUTS OUTPUTS
bility of this device allows the designer to use one
I basic counter for most applications. The synchronous
Carry Clock Carry count feature makes the MC10537 suitable for either
51 52 DO 01 02 03 Til 00 01 02 03 Out computers or instrumentation.
,-- L L H H H L H H H H L L
Three control lines (51,52, and carry In) determine

''"" ''"" ''"" '"

L H ¢ H L L L H H the operation mode of the counter. Lines 51 and 52
L H determine one of four operations; preset (program),
L H ''"" L
L
H
H
H
L
L
L
L
L
H
L
L
H increment (count up), dea-ement (count down), or
L H '" 'q,<P" '" L H H L L L H hold (stop count). Note that in the preset mode a
L
L
H
H
''"" '<P" <P
'<P"
<P
H
H
L
H
H
H
L
L
L
L
L
L
H
H
clock pulse is necessary to load the counter, and the
information present on the data inputs (DO, 01, 02,
H
L
H
L
<P
H
'" '"
<P
H
<P <P
L
<P
<P
H
H
H
H
L
H
-L
L
L
L
H and 03) will be entered into the counter. C8riV0ut
goes Iowan the terminal count. The Carry Out on the
H L <P <P <P L H L H L L H MC 10537 is partially decoded from 01 and 02 directly.
H
H
L
L '" '" '" ''""
<P
<P <P H
H
H
L
L
L
L
L
L
L
H
L
so in the preset mode the condition of the Carry Out
after the Clock's positive excursion will depend on the
, -, '" condition of 01 andlor Q2.
= Don't care.
fJJ When an output is not needed, it can be left open to
-Truth table shows logic states assuming inputs vary in sequence
conserve system power. (The open emitter output will
shown from top to bottom.
require no power if left open,) The counter changes
•• A clock H is defined as a clock input transition from a low to
a high logic level.
state only on the positive going edge of the clock.
Any other input may change at any time except during
the positive transition of the clock. The sequence for
counting out of improper states is as shown in the
State Diagrams.
A prescaler can be constructed using the MC 10537
in conjunction with the MC10631 which will operate
at over 200 MHz inputfreuqency. A 500 MHz prescaisr
is possible using an MC1690 500 MHz 0 Flip,Flop. an
MC1670 300 MHz 0 Flip,Flop. and the MC10537.

(14)10- Cin 00 -14(2)

(1) 1 3 - C FUNCTION SELECT TABLE
01 - t 5 ( 3 )
(161 1 2 - 00 51 52 Operating Mode
(15) 1 1 - Ot L L Preset (Program)
I 02 - 2 (6) Increment (Count Up)
r' (10) 6 - 02
L
H
H
L Decrement (Count Down)
i· (91 5 - 03 03 - 3 (7) H H Hold (Stop Count)
(131 9 - SI
( 11) 7 - S2 Cout - 4 (8)

Po ~ 625 mW typ/pkg (No Load)

150 MHz typ
,- Case VeCl VCC2 VEE
fcount =

620 Pin 1 Pin 16 Pin 8

650 Pin 5 Pin 4 Pin 12

Numbers at end of terminals are pin numbers for L package (Case 620),
Numbers in parenthesis denotas pin numbers for F package (Case 650).

a.·General Information section for packaging.

3·303
 ELECTRICAL CHARACTERISTICS

..
3:

--
Each full temperature range MECL 10,000 10 Cin 00 14
0
series circuit has been designed to meet the 13 C L SUFFIX
de specifications shown in the test table,
12 DO
01 15
CERAMIC PACKAGE
0
after thermal equ il ibriu m has been estab-
IIshed. The circuit is in a test socket or 11 01 CASE 620 gJ
"
02
mounted on a printed circuit board and 6 02
transverse air flow greater than 500 linear
03
0-
0
fpm is maintained. Outputs are terminated
through a 100-ohm resistor to -2.0 yolts.
Test procedures .e shown for only one
9 - S1
03 3

TEST VOlTAGE VALUES ...5'

::J

I
7 - 52 C out f---- 4 lVatta. J
input, or for one set of input conditions. "T. . c:
Other inputs or outputs are tested in the
. T.... per.tu,. VIH",.. VILmin VIH"I'ftin ViLA .... vEE I (II
Q.
same manner. -55"<: -0.... -1.920 -1.255 -1.510 -5.2
....c -0.780 -1.850 -1.10S -1.475 -5.2
+1:zsGC -0.1130 -1.820 -1.000 -1.400 ~.2

MC10531l Tet limits

............
Power Supply Dr.in Cur,.nt
100mOolI'='
'E
Pi.

8
...
-
-RiDe
....
16.
...- +2S"<:
TyO
120
....
150
... ....
+12fiOe

16.
Unit
mAde
TEST VOLTAGE APPLIED TO 'INS LISTED BELOW

VIHftUlx VILmin VIHAmin VILA"... VEE

8
.....
1Vcc·

1,16
Input Cur,.,.t
I lin H I 5 .•. 11.12
13
7
9.10
-
-
-
-
.,.
37'
450

49.
-
-
-
-
-
-
-
220
26'
24'
290
-
-
-
220
26S
24S
290
.Ade

~
5.6.11.12
7
9,10
13
-
-
-
-
-
-
-
-
-
8

l
1.16

!
lin L All D.' - D.' - - 0.3 - ,Ade - <D - - 8 1.16
7, • 1,16
'.~
Logic'T' VOH -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vd, 12 8
Output Volt...
W 1....' ..0 ..
Output Vol...,.
VOL 14(2) -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vde 7 .• 8 1.16

W
0
~
ILoaic "'"
Thres:holdVolt.
VOHA 1412) -1.100 -0.950 -0.845 Vde 7 .• 12 8 1.16

14~ Vdc 12 8 1.16

I~.:!:Id VOlt...
VOLA -1.635 -1.600 -1.525 7 .•

Switching Timft +1.11 V -to.31 V Pul.ln Put. Out -3.2 V +2.0 V

(100-0hm LOKII
~o .....tion OtI.y
Clock Input I "3+14+ 14 0.8 4.6 1.0 3.3 4.' 1.4 '.2 12 13 1.16
tt3+'4- 14 0.8 4.6 1.0 3.3 4.' 1.4 '.2 "14
113+4+ 4 2.0 11 2.' 7.0 10 , 2.4 12.6
113+4_ 2.0 11 2.' 7.0 10.5 2.4 12.6
+
c;;;vTn To c;;;;Oui 1'0-4-
ltQ+4+ :$ 1.6
1.6
7.1
7.1
1.6
1.6
'.0
.0
6 .•
6."
I."
1.9
7.6
7.6
13
13
10
10
Set Up Time
0.•• Inputs 112+13+ 14 3.' 7." 12.13 14
t12-13+ 14 3.' 7." 12.13
Stl.ct Inputs 19+13+ 14 7.' 9,13

~Inpul
'7+13+
110_13+
113+10+
,.
14

14 -1.0
7.'
3.7
7,13
10,13
10.13
Hold Time
0.1. Inputs tI3+12+ -1.0 7 .• 12.13
113+12- " -1.0 12.13
StIec1 Inputs 113+9+
" -2.5
7. "
9.13

Clrry In InpU1
'13+7+
113+10-
""
I.
-2.5
-1.6
7,IJ
10,13
'10+13+ 3.1 10.13
"

.
12.
Counting FNqWncy fcountup liS
II. 125
ISO
ISO "'
II.
MH,
MH,
13

_w_ 11
'countdown
R_TilM
, 0.9 3.3 1.1 2.0 3.3 1.2 3.7 7
•
, _ .. _ I
.fll' ""- ...'"
"4+

,·ot,... •
t4. t + ! ! ! ~ + ..J
"•
" L_.~ ....
 fLiCTRicA-CciiAI'ACTERisTics-- "~"""""-"'-"'-"~1 , ; ... ..
-.",,~-,.....~'.~~'~ ~~~'~~~ .. '~~-"":""-~-.'~~-:-~

, .... full temper8tur. renge MECL 10,000 14 co;; OO~2

~.
...1. circuit ha been cIeIigned to meet the
de _Iflcetionl thown in tho test tabl., C
F SUFFIX
CERAMIC PACKAGE
(!)
01~3
efter thermal lI<Iuilibrium has been estal>-
IIthad. Tho circuit i. in 0 test socket or
1Ii
16
DO CASE 650 ~
......
Dl
mounted on ". printed circuit boIird and 02~6
10 n-
93
transverse air flow groator than 500 linear D2
O
fpm II maintained. Outputs ore terminated 031--7 TEST VOLTAGE-VALUES ::J
1hrough • l()().ohm raslltorto -·2.0 volts. D3 !!.
13 .51 IV~I
Tast procadur..... shown for only one ::J
fOT. . c:
input, or for one"sat of input conditions. 11 52 Cout.r- 8 TMft.,.,et""e VEE (I)
Other inputs or outputs are tested in the _550C -5.2 ~
~. ma""IH'. +2SoC -5.2
+12S oc ~5.2
MC10637F T... Limm

aw-._ S,mbol
......
P;n

T.. Min
_56°C
I Mall M;n
+250 C
Typ I Mi. Min
+1moc
I M.. Unit
TEST' VOLTAGE APPLIED TO PINS LJSTED BELOW

VII'I rna. I VIL min I VIHA min I VILA INa I VEE

Wec·
Gnd
Power Supply ~.in Cur,ent 12 165 120 150 165 mAd, 12 '.5

r
Input Current " 220 22Q
~r
lin H 9,10,15,16 376 9,10,15,18
11
13,1.
4SO
415
26.
>45
265
245
11
13,14
4f
1 406 290 290 1
lin L All 0.5 I 0.5 0.3 I ,&lAde (i) 12 4.5
Logic "'" VOH 2(2) -1.080 I -0.880 I -0.930 -0.180 I -0.825 I -0.630 I Vdc 16 11,13 12 4.5
Output Vol ....
Logic "0" VOL 2(2) -1.920 I -1.855 , -1.850 -1.620 I -1.820 I -t.545 I Vdc ",13 12 4.5
~ OutPUt "Vol ....
I I ",,3
~ Logic "'." VOHA 2(2) -1.100 -0.9SO -0.845 I I Vdc 16 12 4.5
Threlhold Votlell
tTl ........0 .. VOLA 2~ -1.636 -1.600 I' I -1.525 I Vdc 11,13 18 12 4.5
Thrlllhoid Voll...
Switching Times +1.11V 1.a.31V Pu".ln Pu_Out -3.2 V +2.0 V
(l00-0hm LOIdI
Propepnon Del• .,
Clock InPUI 11+2+ 2 1.0 3.3 4.5 16 2 12 4.5
11+2- 2 1.0 3.3 4.5 2
11+8+ 8 2.5 7.0 10.5 11 8
1'+fIr 8 2.5 7.0 10.5 11
ca;;;Tn To c;;;;ow
SIt UpTime
o.,.lnpUlt
1'4_fIr
1'4+8+

116+1+
116-1+
:~
1.6
1.6

3.5
3.5
5.0
5.0
6.9
6.9
11
11

11,13
11,13
14
14

1,16
1.16
!
Select Inputs tI3+'+ 7.5 1,13
111+1+ 75 I,ll
~lnPUI 114-1+ 3.7 11 13 1,14
11+14+ -1.0 11 1,'4
Hold Time
Oet.lnputt 11+16+ -1.0 11,13 1,16
11+16- -10 11,13 1,16
~ect Inpull 11+13+ -2.5 1,13
11+11+ -2.5 I,ll
Cetrv In Inpul 11+14_ -1.6 11 13 1,14
114+1+ 3.1 11 13 1,14
Counting Frequency 'counlUP
fcountdown
•8
125
125
150
150
MH,
MH,
11
13
1

RiM Time 18+ 1.1 3.3 11

~
(2OK to 80%) '2+
Fell Ti....
(2OK 10 al'%)
IS-
12_ T l
CD IndividueliV .PPlv Vil min to pin unelllr test, ~ Me_ure output after clock pulse VIL ..r V1H appears at clock i~ut Ipin ,) a> Before test counter must be stt to a zero count condition lall outputs low)
MC10537 (continued)

COUNT FREQUENCY TEST CIRCUIT

Coax

60

Clock Input@--....- - - o - - j
5O-oh." terminatIon to ground lo-
cated In each ICOp. channel input.

Input PutN.
t+-t--1.0n. All Input and output cables to the
Duty Cycle - 51H1. ~ scope are equal lengths of 5()..ohm
coaxial cabl •. WI,. length shOuld
O.II' F I be < 114 Inch from TPln to Input
pin "and TP out to output pin. V out
Is 2: 1 attenuated.

Unused outputs are connected to

+1.11 V
a 100-ohm resistor to ground.
Vee =- -3.2 Vdc

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

,
~'
(a) Is the minimum time to walt after the counter
has been enabled to c:lock It.

(b) I. the minimum tim. before the counter has been

disabled that it may be clocked.

(e) is the minimum time before the counter is en-

abled that 8 clock pulse may be applied with no ef-
fect on the .tate of the cou owr.

(d) I, the minimum time to walt after the counter

I_ disabled that B clock pul_ may be applied with no
effect In the state of the counter.

(b) .,d (c) may be negative numbers.

Vln VCC1""VCC2-+2.0Vdc V out

NOTE:
"setup is the minimum time before. the positive Coax Coax
transition of the clock pulse (C) that Information
must be present at the Input 0 or S.

tra:~f1~n I~ft~~e r::~~,;up':I'::'7~) a::.:~ ;~:0~;:~~1:~ 50 ;.

~.
must remain unchanged at the Input 0 or s.
,
;
~;

~
+1.11V
Clock 50% Clock Input@--....--o
+0.31 V Input PUIM \ \TP
tc + Q+ tc + Q- t+ - t- a 2.0 ± 0.2 ns TP ln out
(20 to 80%)

r-----~-- +1.11 V
C
VEE = -3.2 Vdc
+0.31 V
50-ohm termination to ground located in each seope
channel Input. .
OarS
All input and output cables to the scope are eq~al
lengths of 50-ohm coax lal cable. Wire length shou-Id
be <114 Inch from TP in to Input pin and TP out to
output pin. V out Is 2:1 attenuated.

Unused outputs are connected to a 100-ohm resistor

to ground.

3-306
 MC10537 (continued)

UNIVERSAL DECADE UP/DOWN COUNTER

12 DO 1400 1101 1501 602 202 503 3Q3 4~

STATE DIAGRAMS
COUNT UP

COUNT DOWN

(.;,.

3·307
 MECL 10,000 series
FOUR-BIT UNIVERSAL
SHIFT REGISTER

MC10541

The MC10541 is a four-bit universal sbift

register which performs shift left. or shift riam.
serial/parallel in. and serial/parallel out ope~
11113 tions with nO external gating. InputsS1 and 52
OL control the four, possible operations of •
181 4 C 00 14121 register without external gatill9 of the cloc:lt.
116112 DO The flip·flops shift information on the positiYe
115111 01 01 15131 edge of the clock. The four operations ~re st~'
1131 9 02 shift. shift left, shift right, and parallel entry f
1101 6 03 02 '2 161 data. The other six inputs are all data type i,
114110 51 puts; four for parallel entry data, and one ,f9r
1111 7 52 03 3 171 shifting in from the left (DL) and one fOr shift·
DR ing in from the right (DR). All four out~
are capable of driving 100 ohm lines. '
191 5 - - - - ' - '
When the register is used for serial output
only, the unused emitter follower outputs cljn
TRUTH TAILE
OllTPIJTS
be left open.
rT,=E~ OPERATING MODE 00"+1 Qln+l Q2n+1 Q3n +1
P.,."" Entry 00 02 D.
Shift Right- Q1". a', a', PR
Shih Left" OL 00, a', 02,
StopS""' 00, a', 02, a', :a: 425 mW typ/pkg (No Load)
• Outputs ..... In .fter pul .. IIPpe.,. M "c" Input with Input eoncUtlon • fShift 150 MHz typ
.. 1tI_n. Wul.... PotJt ..... trantltion of .c:loclil Input).

ea•• VEE
Numbers at end of terminals .!!Ire pin numbers for L package (Case 620). 620
Numbers In parenthesis denotes pin numbers for F package (Case 650), 650

LOGIC DIAGRAM

D. 02

52

OR~------H----L~

03 02 01 00

See General Information section for packaging.

3-308
 nrtmfl~t'CM••""~. .. t3----..
'.'~, u..1J'J8'rt."?\!'•. r.~,,m~:~'.~...
:,", i~';~l""..
."
~
Co:",
£.c"h-lulfi~u"i"'iiiit~lcL';O.OO(f .
i""'iHcireart .... beenrttlllGl'*! to me.t "' ......~
de _ilicadon •.¥.!9.\Nn in tit. test tabl.;
r- . ,-" .•
'1 0 " ' . •.•." . '.
' . . ..
;.,.
' ,

00.&
.I" C

~...
after thermal equilibrium has been astab- . 12 DO
lish.ct . .Tht -~irct..lit i$ in a test socket "Qr . :. LSUFFIX
11 01 01L-15
mounted on a printed circuit board and CERAMIC PACKAGE
transverse air flow greater than 500 linear 9 02
fpm is maintained. Outputs are terminated 6 03 02
CA5'E 620
8
through a 100·ohm resistor to -2.0 volts.
1 0 - - 51 ....
:J
Test procedures are shown only for se-
lected inputs and outputs. Other inputs 7 - - 52 03r--- 3
TEST VOLTAGE VALUES
(Volts)
:i'
c:
and outputs are tested in a similar manner. DR lilT... CD
Co
T Temperature
_55°C
VIHmax
-0.880
VILmin VIHAmin VILAmllX VEE
-1.920 -1.255 -1.510 -5.2
+25o C -0.780 -1.850 -1.105 -1.475 -5.2
+12SoC -0.630 -1.820 -1.000 -1.400 -5.2
MCl0541L Test Limits TEST VOLTAGE APPLIED TO
Pin
-SS"C +2S o C + 125"c PINS LISTED BELOW, tVee l
Characteristic I Symbol I u.;:' .Min Max Min TVp Ma. Min M •• Unit VIHm•• VILmin VIHAmi VILAm..: VEE PI P2 P3 Gnd
Power SupplV Drain Current I 'E 8 - 110 - - 100 - 110· mAde: - - - - 8 - - - 1.16
Input Current , linH I 5 -
I 375 - - 220 - 220 ~Adc 5 - - - 8 - - .- 1.16

~ ~.
- - - - - - - - -

~
375 220 220 6
415 - - 245 - 245 7 - - - - - -
4 - 450 - - 265 - 265 4 - - - - - -
linL 12 0) - 0.5 - - 0.3 - ",Adc 4.5.6.7.9 12 - - 8 - - - 1.16
W I 10,11.13
W I LOgie "1'~ Output Voltage 3 -1.080 -0.880 -0.930 - ,0.780 -0.825 -0.630 Vdc 6 - - - '8 '4 - - 1.16
g LLogic "a.. Output Voltage VOH
VOL 3 -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc - - - - 8 4 1,16

V~A 3 -1.100 - -0.950 - - -0.845 - - - 6 - 8 4 1.16

T
Lt.gic "'" Threshold Voltage

~ ~ ~
-
~ ~- ~
- - - 6 - 7 4 - -
- - - - 6 - - - 4 -
- + - - - - - - - - 4
logic "0" Threshold Voltage
I 3· - -1.635 - - -1.600 - -1.525 Vdc - - - 6 8 4 - -

T
I V8)A
-
~ ~ ~ ~- ~
4' - -

- -
- -
-
+ -
~
- - - 7
- - - - - - 4 -
- - 6 - - - - 4

~
Switching TiI'nH (100 n Load) I +2.0V
Propagation Delav
1'4+3+ 3 - - 1.0 2.9 3.8 - - n, @ - - - 8 - - - 1.16
Setup Time It setup ) 112+4+ 14 - - 2.5
112-4+ - - 2.5
'10+4+ - - 5.0

j
tl~4+ - - 5.0
Hold Time fthold) .'1 t4+12+ - - 1.5
14+12- - - 1.5
- - 1.0

I I ILl
14+10+

I
14+10- - - 1.0
Rise Time (20% to 80%)
Fall Time (20% to 80%) 1. 3+
'3-
3
3
-
-
-
- 11
11
1 71
1 7 33
33
-
-
-
-
@
@
Shift Frequency

P ' - . r - L V1H
V,L
'Shift

P2-.r-LVIHA
:
- -

VIL
- 150

P3-.r-LVILA

V,L
I - -
<D
@
These tests to be performed tn sequence as shown.
S.. ,wi.ching .ime Ie .. ci,.uillo, •• " pmcedu«,.
3 See shift frequency test circuit for test procedures.
4 Reset to zero before performing test.
5 Reset to one before performing test.
 ELECTRICAL CHARACTERISTICS s:0
~
Each full temperature range MECll0,OOO
series circuit has been designed to meet the ~
OL
de specifications shown in the test table, 8 C 00 2 C
after thermal equilibrium has been estab- U1
lished. Th.e circuit is in a test socket or 16 DO
FSUFFIX ~
~
mounted on a printed circuit board and 15 01 01 3 CERAMIC PACKAGE
transverse air flow greater than 500 linear 13 02 CASE 650
8
fpm is maintained. Outputs are terminated
through a 100-0hm resistor to -2.0 volts.
10_03
1 4 - 51
02 f - - 6
TEST VOLTAGE VALUES I
...
::J

:;'
Test procedures are shown only for se-
lected inputs and outputs. Other inputs
nd outputs are tested in a similar manner.
1 1 - 52

9
DR
I
03 f - - 7
OTet
T......ratuN
-li&"c
.m"c
(VoI ..1

VIHIM. VILmin ViHAmin VILAma. VEE

~.880

~.780
-1.920 -1.255 -1.610 -5.2
-1.860 -1.105 -1.476 -5.2
I
I I II I c:
(1)

-
Q.

+lm"c ~.630 -1.820 -1.000 1.400 -5.2

~10&41r:: Test Limits TEST VOLTAGE APPLIE D TO
Pin

a.••wistic ISVmbo11 u: Min

-s5"c
Max Min
+25"C
Typ Max M..
.,H"c
Max Unit
PINS LISTED BELOW:
VIHmu VILmin VIHAmi. VILAmox VEE PI P2 P3
!Veel
Gnd
POwef Supply Drain Current Ie 12 - 110 - - 100 - '110 mAde - - - 12 4,5
Input Current I linH I 9 -
-
365 - - 220 - 220 ~Adc 9 -
-
-
-
- 12
- - -
4,5

~
- - - -

~
10 365 220 220 10
11 - 420 - - 245 - 245 11 - - - - - -
- - - - - - - - - -
•
8 455 265 265 8
16 0.5 - 0.5 - - 0.3 - ",Adc ~,9,10"" 16 - - 12 - - - 4,5
to)
I linL

...
W I Logic "1" Output Vol. . 7 -1.080 ~.880 ~.930 - ~.780 -0.825 ~.630 Vde
3,14,15,1
10 - - - 12 8 - - 4,5

I.
VOH
0 L Logic "0" Output Voltage VOL 7 -1.920 -1.655 -1.860 -1.620 -1.820 -1.646 Vde 12 8 4,5
Logic "1" Thrashold Voltage
V'(f)A 7 -1.100 - ~.950 - - -0.845 - Vde - 12 8 4,5
-
~ ~ ~ ! ~ ~- ~ ~
- - - - 10 - 11 8 -
- - - - 10 - - - 8 -
- - - - - - - - - 8
~ogic "0" Threshold Voltage
I V&LA I 7 -
-
-1.635 -
-
-
-
-1.600 -
-
-1.525 Vde -
-
- - 10 12 8 -
-
4,5

~ ~ ~ ~ ~
- -
- - - - - $ -
-
11
-
-
8
-- 8 -

• - + -
- - - 10 - 8
S";'ching Tlmos (100 n Laod'
Propagation Delay
Setup Time (tsetup)
I '8+7+
t16+8+
t1fr8+
7
2
-
-
-
-
-
-
I .•
2.5
2.5
2.9 3.8 - - n. (3) - - - ~
12 - - -
.2.0 VI
4,5

t14+8+ - - 5 .•
-
j
t14-8+ - 5.•
Hold Tiroe (thold) I '8+16+ - - 1.5
t8+16- - - 1.5
t8+14+ - - 1.0

A ise Time (20% to 80%1

Fall Time (20% to 80%)
I t8+14-

'?+
'7_
7
7
-
-
-
-
-
- :~ I
1.1 171
1~1
33
33 I I ILl
-
-
-
-
(3)
(3)
Shift Frequency

P~VIH;
.
,
,'....
'.:"'~ '"" '.'
""I'L: .
'/",. ;1)
f~hift

".~JL~::A
- - - 160

P3JLVILA
VIL
I - -

See ..ift
@)
G) The.. tests to

',_ncy
be performed in IIQU.nce as !hown.
See -;tching ';me ."c,t<~u.I' ,or .. , pro...t......
tal\ ~itfat ~prpooctur.~
A••t to zero befor. ~1tIt'~"."':.'''.
-,
R..tlO_boI_~_'il~~'
t:iECl.i:.!'GVi- CH'li:1\f.c.i..i:t:ii~~llt,;
jMC10541 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C

Vcc, • VCC2
+2.0 Vdc V out

fl( 50.0hm termination to ground 10-

Input Puis.
:J: 0.' /IF Coax
catad in each scope channel Input.

Alf Input and output cables to the

tT .. t- -2.0 ±.O.2
120 to 80%1
n.
teOpe ara equal lengths of 50-ohm 50
col"ie' cab I•. Wire 'angth should
~ <
1/4 inch from TPln to input
prn and TP out to output pin. V out
112: 1 attenuated. Puls.Oenerator

Clock

10.,jlF
Q Output VEE = -3.2 Vdc

MC'O,02

SHIFT FREQUENCY TEST CIRCUIT

VCC, = VCC2
+2.0 Vdc V out

All input and output cables to the

scope are equal lengths of 50-ohm
Coax coaxial cable. Wire length should
be < 1/4 inch from TPin to i,nput
pin and TP out to output pin. V out
Is 2: 1 attenuated.
50
Input

Puis. Generator
Test Procedure.:

SO-ohm termination to ground 10 1. Set 01. 02, 03 = +0.31 Vdc (Logic L)

ceted in each scope channel input. DO "" + 1.11 Vdc (Logic H)
2. Apply Clock pulse n~:~ to set 00 high.

3. Maintain Clock Low.

Set 51 = +0.31 Vdc (Logic L)
52 = +1.11 Vdc (Loyic H)

4. Test Shift Frequency

IO.,jlF
All unused outputs are connected
to 100-ohm resistor to ground.

Vee = -32 Vdc

3-311
 12-BIT PARITY MECL 10,000 series
GENERATOR-CHECKER

MC10560

The MelOS60 consists of nine EXCLUSIVE-

OR gates in a single package, internally con-
nected to provide odd parity checking or gen-
eration. Output goes high when an odd number
(7) 3 of inputs are high. Unconnected inputs are'
(8) 4 pulled to low logic levels allowing parity de-
(9) 5
tection and generation for less than 12 bits.,
(10) 6
(11)
(13) 9
2 (6) INPUT OUTPUT
(14) 10
Sum of
(15) 11
High Level Pin 2(6)
(16) 12 Inputs
(1) 13 Even Low
(2) 14 Odd High
(3) 15
Po = 320 mW typ/pkg (No Load)
tpd = 4.0 ns typ

Numbers at end of terminals are pin numbers for L package (Case 620),
Numbers in parenthesis denotes pin numbers for F package ICase 650),

APPLICATION INFORMATION· FIGURE 1 - 48-BIT PARITY CHECKER

Tho MC 10560 is usolul in any systom

requiring high speed detection or generation
01 parity. Tho MC10560 can gonorato parity
for twelve bits in four ns. A large number of
functions on one chip reduces package count
and saves system power. As shown in Figure
I, by using tho MC10560'sand one MC10507
parity can be checked or generated on 48
bits in 9.5 ns, or 7.5 ns il tho MC10507 is
replaced by a MECL III MC1672 or MC1674,
although those MECL III parts are not guar-
anteed over the full temperature range.
If parity detection or generation is re.-
quired for less than twelve bits, the unneces-
sary inputscanbe left open. Input pulldown
resistors will insure that the unused inputs
are pulled to the low logic level.

See General Information section for peekaging and maximum ratings

3-312
 EHcTRICAL CHARActERI~TiCs

Each fiJlllempera'u,. ,arige MECL 10.000

3---"-"'" ~
-'
4
C

-
series circuit has been designed to meet the

:~
de specifications shown in the test table, U1
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
~
L SUFFIX
mounted on a printed circuit board and
transverse air flow greater than 500 linear 9~
CERAMIC PACKAGE 8
fpm is maintained. Outputs are terminated 10 ----n----- 2 CASE 620 ::J
~.
::J
through a lOo-ohm resistor to -2.0 volts. 11~ c:
Test procedures are shown for one set of <II
12
conditions.
13-
E:
14 -~ TEST VOLTAGE VALUES

15 • TOOl (Vol'"
T......tur. VIHm .. VILmin VIMArRin ViLA...... VEE
-55"C -0.880 -1.920 -1.255 -1.510 -5.2
-+25oC -0.780 -1.850 -1.105 -1.475 -5.2
+125"C -0.630 -1.820 -1.000 -1.400 -5.2

- -
1E1058)L T. . Limit.
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
U_, -ss"C +25"C +125"C (VCC)
Ch ....cteristic Symbol TOOl Min Min Typ M;n M.. Unit VIHm." VILmin VIHAmin VI LAme. VEE Gnd
Power SupplV Drain IE 8 85 62 78 85 mAde 4.5.9,10.13.14 8 1.16
Current
(.oJ Input Current 'inH 3 - 450 - - 265 - :166 J'Adc 3 - - - 8 1.16
W 4 - 375 - - 220 - 220 ",Adc 4 - - - 8 1.16
(.oJ linL 3 0.5 - 0.5 - - 0.3 - jolAdc - 3 - - 8 1,16
Logic "1" VOH
Output Volt. 2 -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vdc 3 4.5.6.7,9.10. - - 8 1.16
11.12,13.14.15
Logic "0" VOL
Output Voltage 2 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc - 3.4.5.6,7,9.10. - - 8 1.16
11.12.13.14.15
Logic "1" VOHA
Threshold Volt. 2 -1.100 - -".950 - - -0.845 - Vdc - 4.5.6.7.9.10,11. 3 - 8 1.16
12.13,14,15
logic "0" VOLA
Threshold Voltage 2 - -1.635 - - -1.600 - -1.525 Vdc - 3.5.6,7,9.10,11 - 4 8 1,16
12.13,14.15
Switching Times
tl()()'ohm loadl
Propagation DeilY +1.11 V Pulle'n PuI_Out -3.2 V +2.0 V
13+2+ 2 1.6 7.5 2.0 4.0 7.5 1.4 7.5 ns - - 3 2 8 1,16
-
~
t3+2_ 4

II II
- -

j j
13-2-

Rise Time
13-2+
t4+2+
4+2-
t4-2_
t4-2+
j 4
-
3
-
3
-
-
-
-
-
4

~
(20% 10 80%' '2+ 1.0 3.4 1.1 2.0 3.3 0.9 3.4 - - 3
Fall Time
(20%1080'" '2_ 1.0 3.4 1.1 2.0 3.3 0.9 3.4 - - 3
 ELECTRICAL CHARACTERISTICS 3:
Each full temperature range MECL 10.000
series circuit has been designed to meet the
8
...no
U'I

~.:~
de specifications shown in the teSt table, 9.
after thermal equilibrium has been estab- 10 ~
lished. The circuit is in a test socket or 11 F SUFFIX
mounted on a printed circuit board and
13
CERAMIC PACKAGE 8:I
tranlVers8 air flow greater than 500 linear CASE 650
6 !:!.
fpm is maintained. Outputs are terminated 14~
:I
throuWt a 1~ohm resistor to -2.0 volts. C
15
Test p-ocedures •• shown for one set of <II
16 C.
conditions.

:~
TEST VOLTAGE VALUU
.T_ IV-.
T _... VI_ VII"".. VI_ VIa.- VEE
..."1: ~.880 -1.920 -1.265 -1.610 -5.2
+21"1: ~.780 -1.850 -1.106 -1.475 -5.2
+121"1: ~.830 -1.820 -1.000 -1.400 -6.2
MCl0660F T_ Lima
Pin TEST VOLTAGE APPLIED TO PINS LISTED IIILOW:

OIencteriltic
POONer Supply Or.in
5,<,"i00i
Ie
~
T. .
12
Min
-
....
..."1:

86
Min
-
+2I"e
Typ
62
Max
78
Min
-
+121"1:
Max
86
Unit
mAde
VI_
1.2.8.9.13.14
VILmIn VIH_ VI~
-
VEE
12
IVCCI
G_
4.6
Cu"lnt
~
W
Input Cu"ent 'inH 7
8
-
-
460
375
-
-
-
-
265
220
-
-
:116
220
..-
..- 1
8
-
-
-
-
-
-
12
12
·4.6
4.5

--
01:>
Logic "I"
Output Vol_
'inL
VOH
1

6
0.5

-1.090 ~.880
- 0.5

-11.930
-

-
-
-11.780
0.3

~.825 ~.830
- ""de

Vde
-

1
7

1.2.3.8.9.10. - -
12

12
4.&

4.5
11.13.14.15.16
Logic "0" VOL
Output Voigge 6 -1.920 -1.6&5 -1.850 - -1.620 -1.820 -1.545 Vde - 1.2.3.1.8.9.10. - - 12 4.5
11.13.14.15.16
Logic "1" VOHA
Thr.... old VoIt.ge 6 -1.100 - -O.9S0 - - -O.B45 - Vdc - 1.2.3.8.9.10. 7 - 12 4.5
11.13.14.15.16
Logic ''0'' VOLA
Threlhold Voltage 6 - -1.635 - - -1.600 - -1.525 Vdc - 1.2.3.7.9.10. - 8 12 4.5
11.13.14.15.16
Switching Times
II0000m loadl
Pr~tion C.'ay +1.11 V _In _Out -3.2 V +2.0 V
t7+6+ 6 - - 2.0 4.0 7.5 - - n. - - 7 6 12 4.&
t7+6- - - - - 8 -
'7-6- - - - - - -
t7-6+
t8+6+
t8+6-
'8-6-
t8-6+
-
-
-
-
-
-
-
-
-
-
jjj -
-
-
-
-
-
-
-
-
-
8
-
7
-
1
-
-
-
-
-
+
8

+
Rise Time
I_to_ ts+ - - 1.1 2.0 3.3 - - - - 1
F..tTime
,;:I~.'" .,11":" "
'(' - - 1.1 l~ L~ - - .~
- 7 -~
L - ___ ---
~10560 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC

VCCI = VCC2
Vin +2.0 Vdc V out

fj ±~=--,
Coax

,""",,",.J-·ru
Generator 0--0

+0.31 V
r---"---.-_2.....
'"
I
I
60 PROPAGATION DELAY

Input Pulse I
t+ = t- = 2.0± 0.2 n. I
(20 to 80%)

V out

5O-ohm termination to ground lo-

cated in each scop. chennel input. V out

All input and output cabl.s to the

1COp8 ar. equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TPout to output pin. V out
Is 2: 1 attenuated.

3·315
 BINARY TO '·8 DECODER
(LOW)
~,__________________M_E_C_L__10_,_oo__o_~_r_ie_s~1
MC10561

The Me 10561 is designed to decode a three

bit input word to a one of eight line output.
The selected output will be low while all other
outputs will be high. The enable inputs. when
either or both are high, force all outputs high.
POSITIVE LOGIC

EO (6) 2

El (3) 15
6(10)00

6 (9) 01

4 (8) Q2

A 111) 7
3 (7) 03

13 (11 04

B (13) 9

12(16)Q5

11 "5106
Po'"' 315 mW typ/pkg (No Load)
tpd = 4.0 "I typ
c (2) 14 10(14)07

Number. at end of terminal •• re pin numben for L package (Ca" 620).

Number. In parenth.,I, danot•• pin number. for F packa"e (Ca" 660).
Ca .. VCCI VCC2 VEE
620 Pin 1 Pin 18 Pin 8
860 Pin 5 Pin 4 Pin 12

TRUTH TABLE

~~t~ii INPUTS OUTPUTS

El Eo C B A 00 01 02 03 04 05 06 07
L L L L L L H H H H H H H
L L L L H H L H H H H H H
L L L H L H H L H H H H H
L L L H H H H H L H H H H
L L H L L H H H H L H H H
L L H L H H H H H H L H H
L L H H L H H H H H H L H
L L H H H H H H H H H H L
H ~ ~ ~ ~ H H H H H H H H
~ H II> II> II> H H H H H H H H

t/J • Oon't Cara

See Gen ... 1 Information section for packaging.

3·316
 ELECTRICAL CHARACTERISTICS
3:
Each full temperatura range MECL 10.000
series circuit has' been designed to meet the
de specifications shown in the test table.
...
n
o
after thermal equilibrium has been estab-
lished. The circuit is in a test socket or
mounted on a printed circuit board and
...
C11
0)

c;-
transverse air flow grealer than 500 linear

-
fpm is maintained. Outputs are terminated O
:J
through a lOO-ohm resistor to -2.0 volts. ....
Test procedures are shown only for se- S'
lected inputs and outputs. Other inputs c:
(1)
and outputs are tested in a sim ilar manner. a.

L SUFFIX
CERAMIC PACKAGE
CASE 620

TEST VOLTAGE VALUES

lVolts'
lilT...
Temper.ure VIH max VILmin VIHAmi" VILA mIX I VEE
-&&"C -0.880 -1.920 -1.255 -1.510 I -5.2
w +:ZSOC -0.780 -1.850 -1.105 -1.475 -5.2
W +,25"c -0.630 -1.820 -1.000 -1.400 -5.2
......

- -
MCl0&61L Tat Limits TEST VOLTAGE APPL'EO TO PINS LISTED BELOW,
P;n
Undor -a"C +25"C +1260 C lVee'
Ch.racteristk; Symbol Test Min MHo Typ Min Max Unit VIHm_ VIL min VIHA min VILA max VEE Gntl
Power Supply Drain Current 'E 8 84 61 76 84 mAde 2.7,9,14,15 - - - 8 1,16
I nput Current linH 14 374 220 220 .Ade 14 8 1.16
14 0.5 0.5 0.3 - - -
logtc .""
Output Voltage
linL
VOH 13
13
-1.0B0
-LOBO
-{I.880
-{I.880
-{I.930
-{I.930
-{I.780
-{I.780
-{I.825
-{I.825
T-0.630
-{I.630
.Ade
Vdc
Vde
2
15
14

-
-
-
-
-
8
8
8
1,16
1,16
1,16
logic "0" Output Voltage VOL 13 -1.920 -1.855 -'.850 -1.620 -1.820 I -1.545 Vde 14 - - - 8 1,16
Logic "'" VOHA 13 -1.100 -{I.950 -0.845 Vde - - 2 - 8 1,16
Threshold Voltage 13 -1.100 -{I.950 -0.845 Vde - - 15 - 8 1,16
Logic "0" Threshold Voltage VOLA 13 I -1.835 -1.600 I -1.525 Vde - - 14 - 8 1,16
SWltdling TUMI
1100 o Load' Pul.ln PuI.Out -3.2 V +2.0 V
Propagation Celay
It14+1~ I 13 1.5 4.0 6.0
- -
14 13 8 1,16

~
13 4.0

~ I ~
1.5 6.0

~
t14-13+
Rise Time (20% to 80%)
Fall Time (20% to 80%1
t13+
tl~
13
13
1.1
1.1
2.0
2.0
3.3
3.3 I
-
- I -
- ~
 ELECTRICAL CHARACTERISTICS
Ea:h full temperature ran,," M ECl 10,000 s:
n
.rie. circujt hI. been designed to meet the ......
de _ifi""tion. Ihown in the toll tabla,
eftor thermol equilibrium ha. baan estab-
o
lished. The circuit i, in 8 test socket or ~
......
mounted on 8 printed circuit board and
,,.."Mr. lir flow gr.t., than 500 linear n-
!pm i. maintained. OutpUt. ore terminated O
::J
through a l000hm miotor to -2.0 volts.
:!.
Tilt pr~um are Ihown onlv for II- ::J
l.:tld inputo and output •. Other inputs C
and output.ar. tested in a similar manner.
... (II
C.

F SUFFIX
CERAMIC PACKAGE
CASE 650

TEI;r VOLTAGE VALUES

'fl I
...
to)

co .T. .
T _.. VIH_ VILmin
CVohll

VIHAmln VILA_ VEE

....C -4.880 -1.920 -t.256 -1.610 -5.2
+211"1: -4.780 -1.850 -1.105 -1.475 -5.2
+1a"C -4.630 -1.820 ~1.000 -1.400 -5.2

- - -
MC10&81F Tett Limitl ,
PIn TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
U_ -II"c +211"1: +ta"C CVCCI
~ Symbol T. . Min Min Typ Min UMt VIH ..... VILm" V'HAmin VlLAma: VEE GIld
Pow.- Supply Onin Cu"..,t Ie 12 - 84 - 61 76 - 84 mAde 2.3.6.11.13 - - - '12 4,5
Input CUrTent I .. H 2 - 374 - - 220 - 220 .Ade 2 - - - 12 4,5
I .. 2 0.6 - 0.6 - - 0.3 - ."de - 2 - - 12 4,5
Logic "1" VOH 1 -1.0B0 -4.880 -4.930 - -4.780 -4.825 -4.630 Vde 6 - - - 12 4,5
Outpu.VoI_ I -LOBO -4.880 -4.930 - -4.780 -4.825 -4.630 Vde 3 - - - 12 4,6
Logic "ft' Outpu. Vol_ VOL I -1.920- -1.855 -I.B50 - -1.820 -1.820 -1.646 Vde 2 - - - 12 4,5
Logic "I" VOHA I -1.100 - -4.950 - - -4.845 - Vde - - 6 - 12 4.6
Th_oIdVol_ -1.100 - -4.950 - - -4.846 - Vde - - -
Logic "ft'Th_VoI_ VOLA
,
I
- -1.836 - - -1.800 - -1.526 Vde - -
3
2 -
12
12
45
4.&
_"'T_
...._OU.
1100 n LolIIl
"'-Ion DoIoy 12+1- , - - 1.5 4.0 6.0 - - os - -
Pu.. ln
2 I
-3.2 V
'2
+2.0 V
4,5
- - - - -
12-1+
,
I 1.5 4.0 6.0 -
11_ Timo 120'''0_1
F.I Timo 1_10 80!11
'1+
"- I
-
-
-
-
1.1
1.1
2.0
2.0
3.3
3.3
-
-
-
- ~ -
-
-
- ! ! ! !
;~ 1,> •
MCl0561 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C

Vee,· VCC2
+2.0 Vdc V out

Input
Coax
,,,.± j t""
r---- ----,
~.. PROPAGATION OELAY

I I
I
50

Input Pul ..
1+ - t-· 2.0t.. 0.2 n. V out
(20 to 80")

. IO-ohm t ... mln~k)n to ground 10-

ceted In Hch ICOpe ch.nnel Input.

All Input end output Clbl., to the UnuMd outputs I:onnected to I

IC" .r. equal I.",~ of 50-ohm 1 OO-ohm ,.Iltor to ground.
coa.'aI e..,I.. Wlr. 'enath Ihould
be < 1/. inch from TPln to in~ut
pin and TPout to output pin, VEE· -3.2 Vdc
VOU! I, 2:1 .ttenueted.

A complete mux/demux operation on 16 bits for data

APPLICATION INFORMATION
The MC10561 is a true parallel decoder. No series
gating is used internally, eliminating unequal delay times
fOund in other decoders. This design provides the identical
.. lIS delay from any address or enable input to any
Cl!-'tput.
distribution is illustrated in Figure 1. This system, using
the MC10536 control counters, has the capability of in·
crementing, decrementing or holding data channels. When
both SO and Sl are low, the index counters reset, thus
initializing both the mux and demux units. Thefour binary
outputs of the counter are buffered by the MC1050ls to
send twisted·pair select data to the multiplexer/demulti·
plexer units.

3-319
 FIGURE 1 - HIGH SPEED 16-BIT MULTIPLEXERIDEMUL TlPLEXER
s:
n
~

c
Control Selection en
en
~
MC10501 MC10515

I::J } X'")(i) n-
~ - L SO 1514131211109 8 76543210
O
::J
!:!-
::J

~
r-- c:
51 MC10536 CD

CR E:
A B C 0

t:J"} 'CJ. i
H> .--- C
r--
E1

B
MC10564
~

.---- C
r--
E1

B
MC10564

r-A .-A
DO DO

w
W
'"o MC10501 MC10515
H
W)~
50

~
50
51 ~ ~H>---
J 2. J"~~
X I
.
51
CR
MC10536

A B C 0
CR
~

)("""X. I
LL
~
EO EO
E1 ~ E1

~: rfr=:
MC10561 MC10561

1514131211109 B 76543210
 MECL 10,000 series
BINARY TO '-8 DECODER
(HIGH)

MC10562

The MC10562 is designed to convert three

linesof input data to a one-of-eight output. The
selected output will be high while all other out-
puts are low. The enable inputs, when either
or both are high, force all outputs low.
POSITIVE LOGIC

EO (8) 2

E1 (3) 15
6 (10100

5 (91 Q1

4 lSI Q2
A ,1') 7

3 (7) Q3

13 (1) Q4

8 (13) 9

Po = 315 ns typ/pkg (No Load)

tpd = 4.0 nl typ
C (2) 14

Numbers at and of terminals ar. pin number. for L package (C.se 620).
Numbers in parenthesi, denote. pin numbers for F package (ca. 650).
I Ca ..
I VCCI VCC2 VEE
I 620 I Pin 1 Pin 16 Pin 8

I 660 I Pin 6 Pin 4 Pin 12

TRUTH TABLE
INPUTS OUTPUTS
~O £1 C B A 00 01 Q2 OJ 04 05 ae 07
L L L L L H L L L L L L L
L L L L H L H L L L L L L
L L L H L L L H L L L L L
L L L H H L L L H L L L L
L L H L L L L L L H L L L
L L H L H L L L L L H L L
L L H H L L L L L L L H L
L L H H H L L L L L L L H
H L L L L L L L L

~
'" ''Car.
H
'" Don't
&
"" ''"" ''"" L L L L L L L L

S .. G~.'lnform.tion section for packaging.

3·321
 ELECTRICAL CHARACTERISTICS
3:
Each lull temperature range MECL 10.000
.riescircuit has been designed to meet the n
~
de specifications shown in the test table. o
after thermal equilibrium has been estab- at
lished. The circuit is in 8 test socket or m
mounted on 8 printed circuit board and N
transver. air flow greater than 500 linear n-

-
fpm is maintained. Outputs are terminated O
through 8 l00-0hm resistor to -2.0 volts. ::J
~.
Test procedures ar. shown only for se- ::J
lected inputs and outputs. Other inputs c:
and outputs are tested in a similar manner. CD
Q.
L SUFFIX
CERAMIC PACKAGE
CASE 620

TEST VOLTAGE VALUES

(Volt.1
f l ...
T ...per.tur•. VIH ..... Vil min V'HAntin ViLA .... VEE
....C -0.8111 -1.920 -1.256 -1.510 -5.2

~
+25°C -0.780 -1.850 -1.105 -1.475 -5.2
+121i"C -0.630 -1.820 -1.000 -1.400 -5.2
"l
"l MC10512L Test Limit,
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Und. -se"C +2&oC +121i"C
(Veel
Ct.,.ct.i.ic Symbol TOIl Min Mo. Min Typ Mox Min Mo. Unit VIH mil. V,Lmin VIHAmin ViLA .... VEE Gnd
Power SupptV Drain Current Ie 8 84 81 78 84 mAde 8 1.16
I nput Current linH 14 - - - - 220 - - IoI Adc
"- - - - 8 1.16
linL 14 0.5 - 0.5 - - 0.3 - ,..Adc I. - - 8 1.16
Logic ''1'' VOH 13 -1.080 -0.8111 -0.930 - -0.780 -0.825 -0.630 Vde 14 - - - 8 1.16
Output Voltage
Logic "0" VOL 13 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc 2 - - - 8 1.16
Output Voltage 13 -1.920 -1.665 -1.850 - -1.620 -1.820 -1.545 Vde 15 - - - 8 1.16
logiC"1" VOHA 13 -1.100 - -0.950 - - -0.845 - Vde - - 8 1.16
Threshold Voltage "
Logic "0" VOLA 13 - -1.835 - - -1.600 - -1.526 Vde - - 2 8 1.16
Threshold Voltage 13 - -1.835 - - -1.600 - -1.525 Vde - - 15 - 8 1.16
SVJitching Times
I1CJO.ohm loadl Pul .. ln PulteOut -32 V +2.DV
ProJ)9tion Del.v t14+13+ 13 - - 1.5 4.0 6.0 - - ns - - 14 13 8 1.16
-
j j
- - - - -

!i
1.5

!
'14-13- 13 4.0 6.0
1.1 3.3
Rise Time ,+ 13 - - 2.0 - - - -
(20% to 110%1
F.U Time ,- 13 - - 1.1 2.0 3.3 - - - -
(20%'080"1
 ELECTRICAL CHARACTERiSTICS··· .
e..h full tom_.turo ,.ngo MECL 10.000
.rielcircujt hi. been designed to meet the
~
....
de lPfICificationl shOwn in the test table. o
~
after thermal equilibrium has been Istabo-
IIshed. The circuit is in 8 test lOcket or
mounted on a printed circuit board and N
trlnlYer. air flow greater than 500 lir)8ar
fpm is maintained. Outputs are terminated 8:::s

~
th,ough 8 l00-0hm , .. isto, to -2.0 volts. ~.
Test procedures are shown only for se- :::s
lected inputs and outputs. Other inputs
and outputs are telted in 8 similar manner.
5i
Co
F SUFFIX
CERAMICPACKAGE
CASE 650

TEST VOLTAGE VALUES

(Vah,)
.rOIl
T....per8tur. VIHmIX VILmin VIHAmin VILA_ VEE
-55"c -0.880 -1.920 -1.255 -1.610 -5.2
ctJ
to) - +ZSoC -0.780 -1.850 -1.105 -1.415 -5.2
p..) +1211"C -0.830 -1.820 -1.000 -1.400 -5.2
to)
I I I Pin
MC1068ZF T. . Limill
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Und... · -55"c +2SoC +l21oC
'Vee
Chlr.ct.,istic I Svmbol T... Min Mo. Min TV' Mo. Min Mo. Unit VIHmelII VILmi" VIHAlllin VILA . . . VEE Gnd
Power Supply Dram Current tE 12 - 84 - 61 16 - 84 mAde - - - - 12 4.5
I nput Current
L linH 2 - - - - 220 - - ,..Adc 2 - - - 12 4.6
linL 2 0.5 0.5 - - 0.3 - ,..Adc - 2 12 4.5
LogiC "1" VOH 1 -LOBO -0.880 -0.930 - -0.180 -0.825 -0.630 Vde 2 - - - 12 4.6
Output Voltage
LogiC "0" VOL 1 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.645 Vde 6 - - - 12 4.5
Output Voltage 1 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.645 Vde 3 - - - 12 4.5
LogiC "1" VOHA 1 -1.100 - -0.950 - - -0.845 - Vde - - 2 12 4.5
Threshold Voltage
lOgiC "0" VOLA 1 - -1.635 - - -1.600 - -1.525 Vde - - 8 - 12 4.6
Threshold Voltage 1 - -1.635 - - -1.600 - -1.525 Vde - - 3 - 12 4.5
Switching Times
(l00-0hm loed) Put_In Pu. . Out -3.2 V +2.0 V
Propeglltion Delay t2+1+ 1 - - 1.6 4.0 6.0 - - n. - - 2 1 12 4.6
'2_1_ - - - -

I I !!
1 - -

!
1.5 4.0 6.0
I. 1.1 3.3
Rise Time 1 - - 2.0 - - - -
(20%1080%1
Fall Time
(20% '0 80%1
I '- 1 - - 1.1 2.0 3.3 - - - -
MC10562 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS ~ 2SoC

Vcc, = VCC2
"'2.0 Vdc Vout

Input
.::±1t'~" ,. . PROPAGATION DELAY

I I
Pulse I
~
O% +'.11 V
Generator I 50 Von
- ----+0.31 V
I
Input Pul ..
ti- ., t- ::: 2.0
(20 to 80%)
±. 0.2 "S
I -----..
t--
I 80%
t++

I V out

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the Unused outputs connected to •

scope are equal lengths of 50· ohm l00-ohm resistor to ground.
coaxial cabl.. Wire length should
be < 1/4 inch from TP in to input
pin and TP out .t~ output pin. veE = -3.2 Vdc
V out i. 2: 1 attenuated.

FIGURE 1 _. DEMULTIPLEXER (1 OF-S LOCATIONS)

APPLICATION INFORMATION

The MC10562 is a true parallel decoder. No series Data Select

gating is used internally, eliminating unequal delay times 00 a, 02

found in other decoders.

This device is ideally suited for demultiplexer applica-
tions as shown in Figure 1. One of the two enable inputs c
Data In
is used as the data input, while the other is used as a data MC'0552
enable input. Enable E,
A complete mux/demux operation on 16 bits for data
distribution is illustrated in Figure 2. This system, using
the MC 10536 control counters, has the capability of incre-
menting, decrementing or holding data channels. When Oata Output
both SO and Sl are low, the index counters reset, thus
initializing both the mux and demux units. Control infor-
mation via twisted pair lines is sent through MC10501
gates to the MC10515 line receivers to provide select
data to the multiplexer/demultiplexer units.

3-324
 ~....
FIGURE 2 - HIGH SPEED 18-8IT MUL TIPLEXERIDEMULTIPLEXER

C
Control Selection ~
N
MC10501 MC10515 0-
o
~-.XJ. I :J
~.
:J
Lso 1514131211109 8 76543210 C
(I)
r-
~Sl MC10536 C.
CR
A 8 C 0
~
......
tU- ~ El r - El
,---- C -C
MC10564 MC10564
;-- 8 -8
~A r-A
DO DO

w
W
"l

~
U1 MC10601 MC10515
so .-- ......
-L)~
SO

~
Sl
j )~ ~'---V
Sl MC10636
CR
A 8 C 0
CR ~

XX I
--L
~
~
EO EO
El r - - - El

~: ~:
MC10562 MC10562

1514131211109 8 76543210
 a·LlNE MULTIPLEXER l . ._____________________--'·.1 MECL 10,000 series

MC10564

The MC10564 is a high speed. low power

MECL eight·channel data selector which routes
data present at one·of·eight inputs to the out·
put. The data is routed according to the three
TRUTH TABLE bit code present on the address inputs. An en·
DATA able input is provided for easy bit expansion.
----
ENABLE
ADDRESS INPUTS
ROUTED
C B A FROM:
L L L L xo
L L L H Xl
L L H L X2
L L H H X3
L H L L X4
L H L H X6 Po - 310 mW tvp/pkg (No Lo.d)
L H H L X6 tpd - 3.0 nl tvp
L H H H X7
H 4> 4> 4> L
til - Don't Cere

.:",
POSITIVE LOGIC

.,

A (11) 7 )
:=.
B (13) 9
1.
C (14)
10~
En.bi8 (6) 2
-----
) 15 (3) ..
XO (10) 6 J
Xl (9) 5
-r-;-
.;:

(B)
R :J
B'r
X2 4

..
X3 (7) 3

X4 (16) 11 r
X6 (16) 12 r
X6 (1) 13
~
R
r
X7 (2) 14 ~
Case VCC1 VCC2 VEE
620 PinT Pin 16 Pln8
Numbers at end of terminals are pin numbers for L package (Case 620)
660 Pin 5 Pin 4 Pin 12
Number. in parenth..is denot.. pin numbers for F package (Case 6501

S .. Ganar.1 Information section for peckellnlend mexlmum r.tlnge.

3-326
 ~,'" /0': .":~. ·.1~. ,:',"~:~r- '~"~"':~'~':~::'~:~~~~~.~~'.' !~:~::'::~~~:=':~~:'t~~~:~~:~~::~:j~~'~~~~.r~~~~~~
,-'!'.":
••

E'r'CT~L~ACf&RIUjCS.
~.
hchfuU _ _.tur. r _ MECL 10.000
....i.. circ~it h. been designed to meet the A 1 ....
o
de specification. thaw" in the test table,
en
after tharme' equilibrium h. been estab-
lished. The circuit il in a test socket or
•• ~
mounted on a printed circuit bo.d and
tranwerse air flow gr••ter than 500 line.r
c '0 c;-
o
fpm il maintained. Outputs are terminated
through 8 l()().ohm resistor to -2.0 volts.
En"'. 2 I I I I I I "'" ,s ...5'
:::J

t Imn ,/
Test procedures are shown for only one
input, or for one set of input conditions.
Other inputs are tested in the same manner.
xo.

x,

X'
5

4
I I fTTT=L..--
t I I fTF1-.-.-
"", LSUFFIX
CERAMIC PACKAGE
CASE 820
c:
It)

.eo

X33 IllfTn--
X4 " I fTTT=L..--

IliE
TEST VOLTAGE VALUES
X612
(Votul
fi_
xe 13
T ......... ViLA .... VEE
V.Hmax VILmin V'HAmin
)(7,. ..."1: -0.880 -1.920 -1.265 -1.510 -5.2
~ +25"c -0.780 -1.850 -1.105 -1.475 -5.2
Co)
+12&"1: -0.830 -1.820 -1.000 -UOO -5.2
N
-...I MC10684L T_ Llmilo
Pin TEST VOLTAGE APPLlEO TO PiNS LISTED BELOW
U_
_Oc +2SoC +12&"1: (Vee I
Ct.rect.. iltic Symbol TOM Min M.. Min Typ Mo. Min M.. Ik* VIH_ VILmin VIHAmin VILA miX VEE Gnd
Power Supply Drain Current IE 8 - 83 - 60 75 - 83 ""'de - - - - 8 1.16
I nput Current lin H 4 455 265 265 ,.Adc 2 .8 1.16
lin L 4 0.5 - 0.5 - - 0.3 - ,.Ade - 4 - - 8 1.16
Logic "1" VOH 15 -1.080 ~.880 -0.930 - ~.780 ~.825 ~.630 Vde 4.9 2.7.10 - - 8 1.16
Output Voltage
Logic ''0'' VOL 15 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc 9 2.4.7.10 - - 8 1.16
Output Volt.
Logic "1" VOHA 15 -1.100 - -0.950 - - -0.845 - Vdc 9 7.10 4 2 8 1.16
Threshold Voltage
Logic "0" VOLA 15 - -1.635 - - -1.600 - -1.525 Vde - 4.7.10 9 2 8 1.16
Threshold Voltage
Switching Times +1.11 V Pue-In PuI.Out -3.2 V +2.0 V
l1000hm loedl
Pro~tton Delay '4+15+ 15 1.3 4.6 1.5 3.0 4.5 1.2 4.5 n. 9 - 4 15 8 1.16
'4-15- 15 1.3 4.6 1.5 3.0 4.5 1.2 4.5 9 - 4
17+15+ 15 1.8 6.1 2.0 4.0 6.0 1.9 6.0 5 - 7
'7-15- 15 1.8 6.1 2.0 4.0 6.0 1.9 6.0 5 - 7

j j j
12+16- 15 0.9 3.0 1.0 2.0 2.9 0.9 2.9 7.5 - 2
15 3.0 -

~
12_15+ 1.0 2.9 2.9 7.5 2
Rise Time
(2O%108O'W.1
FeI'Time
(2O%1080'l1.1
1+

,-
15

IS ! 3.3

3.3
1.1

1.1
3.3

3.3 ! 3.4

3.4 1
9

9
-

-
4

4
 ELECTRICAL CHARACTERISTICS
s:
Each full temperature range MECL 10.000
series circuit has been designed to meet the
de specifications shown in the test table,
A 11
...o
(")

after thermal equilibrium has been estab· • 13 C1I

lished. The circuit is in a test socket or
mounted on a printed circuit board and C 14
~
transverse air flow greater than 500 linear 0-
fpm is maintained. Outputs are terminated
En.iii'8 6 o
:::1
mrouWl a lOO-ohm resistor to. -2.0 voltl. !:!.
Test procedures are shown for onlv one XO 10 t I I I I I L-- :::1
c:
input, or for one set of input conditions. F SUFFIX CD
Other inputs are tested in the same manner. XI 9 CERAMIC PACKAGE a.
CASE 650
X2 •

X3 7

X415 I~
TEST VOLTAGE VALUES

IIgj
X5 16
(Volts)
CPT . .
X6 1 TemfMr·tur. VIH milK VIL min VIHAmill ViLA .... VEE
-$"1: -0.880 -1.920 -t.255 -t.510 -5.2
~ X7 2 +~e -0.780 -1.850 -1.105 -1.475 -5.2
CAl +125"1: -0.630 -1.820 -1.000 -1.400 -5.2
I'.)
CD MC10664F T_ Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW
U_ ~5"1: +25oC +125"1: (Veel
C..... ct.istic Symbol T... Min Mo. Min Typ Mo. Min Mo. Unit VIHmn VILmin VIHAmin VILA mil. Vee Gnd
Power Supply Drain Current IE 12 83 60 75 83 mAde 12 4,5
Input Current lin H 8 - 455 - - 265 - 265 ,.Ade 6 - .- - 12 4,5
lin L 8 0.5 - 0.5 - - 0.3 - ,.Ade - 8 - - 12 4,5
Logic "1" VOH 3 -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vde 8.13 6.11.14 12 4.1
Output Voltage
Logic "0" VOL 3 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vde 13 6.8.11.14 - - 12 4,5
Output Voltage
Logic "1" VOHA 3 -1.100 - -0.950 - - -0.845 - Vdc 13 tt. 14 8 8 12 4.1
Threshold Voltage
Logic "0" VOLA 3 - -1.635 - - -1.600 - -1.525 Vde - 8.11.14 13 6 12 4.1
Threshold Voltage
Switching Times +1.11 V Pu"ln Pul.Out -3.2 V +2.0 V
1100.ohm loedl
Pro~hon Delay '8+3+ 3 - - 1.5 3.0 4.5 - - ns 13 - 8 15 12 4,5
'8-3- - - 1.5 3.0 4.5 - - 13 - 8

I III
t11+3+ - - 2.0 4.0 6.0 - - 9 - 11
- - - - -

j
'11-3- 2.0 4.0 6.0 9 11
'8+3- - - 1.0 2.0 2.9 - - 9.11 - 6
'8-3+ - - 1.0 2.9 - - 9.11 - 6
Rise Time
(20"'0_)
F ... Time
(20%'080%1
" .. '
t3+

t3+
-

-
-
-
1.1

1.1 t 3.3

3.3
-

-
-
-
13

13
-

-
8

8
MC10564 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 2SoC

VCCI = VCC2
+2.0 Vdc V out

Coax

r-------- --------,

I
I
~
)-
""Cm"" ]Coax

50

I _1-

L
Input
~
I ~"
) ./
i Pulse Generator ~

I )

Input Pulse
I r
t+ '" t- = 2.0 ±. 0.2
(20 to 80%)
ns
: R -:;
: R r
: -:;
~-:;
50-ohm termination to ground lo-
cated in each scope channel input i
All input and output cables to the
scope are equal lengths of 50-9hm 1
~ 8;
coaxial cable. Wire length should
be < 1/4 inch from TP in to input
I ~;
I
pin and TPoutto output pin. V out
is 2: 1 attan uated.

VEE = -3.2 Vdc

PROPAGATION DELAY

O%
~
+1.1111

- ----+0.31 V
t--

---"..L- 80%
I t++

V out

t+

3-329
 MC10564 (continued)

eight data inputs and an enable. A high level on the enable!

APPLICATION INFORMATION
The MC10564 can be used wherever data multiplexing
or parallel to serial conversion is desirable. Full parallel
gating permits equal delays through any data path. The
output of the MC10564 incorporates a buffer gate with
forces the output low. The MC10564 can be connected!
directly to a data bus, due to its open emitter output andi
output enable. !
Figure one illustrates how a 1-of-64 line multiplexer can:
be built with eight MC10564'swire ORed at their outPUt~
and one MC10161 to drive the enables on each multi-j
plexer, without speed degradation over a single MC10564:
being experienced. '

FIGURE 1 - HIF-&4 LINE MULTIPLEXER

ABC

The Bit chosen is dependent on six-bit

code pre.nt on inputs 1. 9, 14 of the
MC10161 and the A. B. C inputs of the
MC10564.

3-330
 DUAL BINARY TO MECL 10,000 series
1-4 DECODER
(LOW)
MC10571

The MC10571 is a binary coded 2 line to

dual 4 line decoder with selected outputs low.
With either Eo or E1 high, the corresponding
I
POSITIVE LOGIC selected 4 outputs are high. The common enable
E forces all outputs high.
T-- All propagation delay ti mes are equal due to
fo (2) 14
the internal emitter dotting techniques used.
10(14) QO 3 High impedance 50 k ohm resistors on all inputs
eliminate the need to tie unused inputs to VEE.
i ...Q
tl(le) QO 2
i
t2(16) QO 1

I- A(13)9
r- 13 (1) QO 0

..
i
-, Po - 330 mW typ/pkg (No Lood)
3 (7) Ql 3 fpd - 4.0 n. typ
B(II)7
4 (8) Qt 2

,
;

\
1"--' E (3) 16 e (9) Ql 1

6 (10)Ql 0
El (6) 2

Number•• t end of termlnall .r. pin number. for L pickage (C ... 620).
Number. in parenthesis denot.. pin numa. for F pickage (ca. 650).

t ..

TRUTH TABLE

ENABLE INPUTS INPUTS OUTPUTS

E EO Et A B atO att at2 a13 000 oot 002 a03
L L L L L L H H H L H H H
L L L L H H L H H H L H H
L L L H L H H L H H H L H
L L L H H H H H L H H H L
L L H L L H H H H L H H H
L H L L L L H H H H H H H

,.to. H ~ ~ 4> ~ H H H H H H H H

tP""' Don't Car.

See Generel Information section for Pick aging and maximum rating •.

3-331
 ELECTRICAL CHARACTERISTICS
EO 14 s:
n
Each MECL 10.000 series circuit has been
designed to meet the de specifications
10 003
....
o
shown in the test table. after thermal &qui·
librium has been established. The circuit is
in 8 test socket or mounted on a printed
11 002
...~
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs 12 001
g
::J
ar. terminated through a 1()().ohm fesistor d.
to -2.0 volts. Test procedures ar. shown ::J
only for _Iected inputs and outputs. Other c:

-
13 000 <D
inputs and outputs are tested in a similar a.
manner.

3 013
L SUFFIX
B 7 CERAMIC PACKAGE
4 012 CASE 620

E 15 5 all

I I~
w El 2 1 1~6010
TEST VOLTAGE VALUES
IVo/III
W
w
• Toot
Temper.tur. VIH ..... VILmln VIHAmln VILAm .. VEE
I\)
-6&"c -0.880 -1.920 -1.266 -1.610 -6.2
+2lioC -0.780 -1.860 -1.106 -1.476 -6.2
+126"c -0.630 -1.820 -1.000 -1.400 -6.2
MCl0671L Toot Llm~.
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
U_ -16"c +26"c +l26o C IVeel
Char8CtM'istic Symbol Toot Min Max Min Typ Max Min M.. Un~ VIHmax VILmin VIHAmin VILAma VEE Gnd
Power Supply Or.in Current 'E 8 - - - 64 77 - - mAde 2.7.9.14.16 - - - 8 1.18
I nput Current linH 14 220 - ~Adc 14 - 8 1.18
linL 14 0.5 - 0.5 - - 0.3 - ,!.lAdc - 14 - - 8 1.18
Logic "1" Output Voltage VOH 8
13
-1.080
-1.080
-0.880 -0.930
-0.930
- -0.780
-0.780
-0.825 -0.630 Vdc 15 - - - 8 1,16
-0.880 -0.826 -0.630 Vdc 15 8 118
Logic "0''' Ou1put Voltagll VOL 13 -1.920 -1.665 -1.860 -1.620 -1.820 -1.645 Vdc 2.7.9.14.15 8 1.16
Logic: "1" Threahold Voitaga VOHA 8 -1.100 -0.960 -0.846 Vdc 15 8 1.16
13 -1.100 - -0.960 - - -0.845 - Vdc - - 15 - 8 1.16
Logic "0" Threshold Voltagll VOLA 6 -1.635 -1.600 -1.525 Vdc 2.9.14.15 7 8 1.16
13 -1.635 -1.600 -1.525 Vdc 2,7.14.15 9 8 1.18
Switching Tim.. +1.11 V +0.31 V Pu_ln ~IooOu' -3.2 V +2.0 V
1100,n Loodl
Propegation Delay t7+8+ 8 - - 1.5 4.0 6.0 - - n. 14 2.9.15 7 6 8 1.18

~
'7-6- 6 - - - - 14 2,9.15 6

I I.
I II
t7+13+ 13 - - - - 2 9.14,15 13
'7-13- 13 - - - - 2 9.14.16 13
- -
I.
te+ 6 - 1.1 2.0 3.3 - 2.9.16 6

.~
- - - -
*~ ~*
At. Time f2Q% to ~) t13+ 13 2 9.14.16

Foil Tlmo (20% '0 BOlli

'6- 8
13
- - - - 2.9,1&
13
8
'13 2 i.1416
r __ ._ •••
13
_. - -.

~
.
~
.
 ~eCTRicAL:.c"'ARiCT£RtmCs::"- EO 2
3:
14003
Each MECL 10,000 series circuit ha. been
n
-"
designed to meet the de specifications o
shown in the test table, after thermal equi~ 15 002 U1
librium has been established. The circuit is ......
in a test socket or mounted on a printed -"
circuit board and transverse air flow greater 16 001 0-
than 500 linear fpm is maintained. Outputs o
::J
are terminated through a 10o-ohm resistor ~,
to -2.0 volts. Test procedures are shown ::J
only for selected inputs and outputs. Other 1 000 c:
CD
inputs and outputs are tested in a similar
manner.
~

7 Q13

B 11 F SUFFIX
8 012 CERAMIC PACKAGE
CASE 650

E 3 9 all

I I
w El 6
1 1 ) 10 010
OT...
TEST VOLTAOEVALUES
(Volts)

W Temper.tur. VIHm. . VILmin V'HAmi" VILAm.. VEE I

w
w -Ss"C ~,880 -1.920 -1.255 -1.510 -5.2
!
+25o C ~.78O -1.850 -1.105 -1.475 -5.2
'125"1: ~.630 -1.820 -1.000 -1.400 -5.2
MC10611F Tnt Limita
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Un'"
_56°C +25o C +l25o C IVCCI
ChII_1tt1c Symbol T... Min Mo. Min Typ M•• Min M .. Unit VIHm.. VILmin V1HAmin VI LAma VEE Ond
Power SupplV Drain Current IE 12 64 77 - - mAde 2,3,6,11,13 - - - 12 4,5
Input Current linH 2 - - - - 220 - - #Adc 2 - - - 12 4,5
linL 2 0.5 - 0.5 - - 0.3 - #Adc - 2 - - 12 4,5
Logie "'" Output Voltage VOH 10 -1.080 ~.B80 -0.930 - -0.780 ~.825 ~.630 Vdc 3 - - - 12 4,5
1 -1.080 ~.880 ~.930 - ~.78O ~.825 ~.630 Vdc 3 - - - 12 4,5
Logic "0" Output Voltlge VOL 1 -1.920 -1.855 -1.850 - -1.620 -1.820 -1.545 Vdc - 2,7,9,14,15 - - 12 4,5
Logie "'" Threshold Voltage VOHA 10 -1.100 -0.950 ~.845 - Vdc 3 - 3 - 12 4,5
1 -1.100 - -0.950 - - -0.845 - Vdc 3 - 3 - 12 4,5
Logie' '0" Threshold Voltaga VOLA 10 -1.635 -1.600 - -1.525 Vdc - 2,9,14,15 - 11 12 4.5
1 - -1.635 - - -1.600 - -1.525 Vdc - 2,7,14,15 - 13 12 4.5
Switching Times +'.110V +0.31 V PuIe)ln PuI.Out -3.2 V '2.0 V
1100 n Load)
Propagation Oelay .t11+'o. 10 - - 1.5 4.0 6.0 - - n. 2 3,6,13 11 10 12 4,5
'l1-1D- 10 - - - - 2 3.6,13 10
t11i-1+ 1 - - - - 6 2,3,13 1

• • +
t11_1_ - - - -

j j j j
1 6 2,3,13 1
'10+ 10 - - 1.1 2.0 3.3 - - 2 3.6,13 10

~ l
Ri. Time (20% to 80%) 'I' 1 - - - - 6 2,3,13 1
'lD- 10 - - - - 2 3,6,13 10
hI! Time (20% to 80%) 'I- I - - - - 6 2,3,13 1

• -
MC10571 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS (j[I25oC

VCCl • VCC2
V out
+2.0 Vdc

Input

o
Pul .. PROPAGATION DELAY
Generator
50

Input Pul,.
t+ .. t- 20 2.0±' 0.2"s
(20 '080%)

1-1=-0-:"-;-_...1
I
L------- Unuted outputs connected to
II 100-ohm r •• lstor to ground.

= +0.31 Vdc
VEE· -3.2 Vdc

All input end output cabl .. to the

scope .,. equal lengthl of 50·ohm
c08xlal cable. Wlr. 'ength should
be < 1/4 inch from TPin to input
pin end TP out to au tput pin.

3·334
 DUAL
MECL 10,000 series
BINARY TO 1-4-DECODER
(HIGHI

MC0572

The MC10572 is a binary-coded 2 line to

dual 4 line decoder with selected outputs high.
POSITIVE LOGIC With either rO or £"1 low, the corresponding
selected 4 outputs are low. The common en-
able £, when high, forces all outputs low.
All propagation delay times are equal. High
~0(2) 14
10(14) 003 impedance 50 k ohm resistots on all inputs
eliminate the need to tie unused inputs to VEE.
11(16)002

12 (16) 00 1

A (13) 9
13 (1) 000

3 (7) 01 3 Po -= 325 mW tvp/pkg I No Load)

tpet = 4.0 nl typ
B (11) 7
4(8) 012

E(3) 15 5 (9) 011

6(10) 01 0
'~1 (6) 2

Number. at and of terminal I ar. pin number. for L package (CaM 620).
Number. in parenthesis danote, pin number. for F package (CaM 650).

TRUTH TABLE
E El EO A B 010 all 012 013 000 001 002 003
L H H L L H L L L H L L L
L H H L H L H L L L H L L
L H H H L L L H L L L H L
L H H H H L L L H L L L H
L L H L L L L L L H L L L
L H L L L H L L L L L L L
H ~ ~ ~ ~ L L L L L L L L

tP - Don't Car •

. . . G"""".I Information section for packaging and maximum ratings.

3-335
 ELECTRICAL CHARACTERISTICS s:
n
Each MECL 10,000 series circuit has been ....
o
designed to meet the de specifications E014
shown in the test table, after thermal equi- 10 00 3 U1
librium has been established. The circuit is
"'-I
N

-
in a test socket or mounted on a printed
circuit board and transverse air flow greater
11 ao 2
n-
O
than 500 linear fpm is maintained. Outputs ::J
are terminated through a 100-ohm resistor 12 aD 1
e.
to -2.0 volts. Test procedures are shown ::J
A. c:
only for .Iected inputs and outputs. Other 13 aD 0 CIl
inputs and outputs are tested in a similar Co
manner.
3 Q1 3
L SUFFIX
• 7 CERAMIC PACKAGE
4 Q1 2 CASE 620

"
_~6alO
., 2
BT...
TEST VOLT ...GE V...LUES
IVoI..1

Temp......ur. VIHm .. VILmin VIHAinin VILAmu VEE

-H"c -0.880 -1.920 -1.255 -1.510 -5.2
w -1.106 -1.475 -5.2
W
w
+25"c -0.780 -1.850
-1.820 -1.000 -1.400 -5.2
+125"C -0.830
0)

-
MCl~2L T ... Limits
,In TEST VOLT...GE APPLIED TO PINS LISTED BELOW:
U_ -a"c +2Ii"c +125"C IVeel
a..-Ic 1IIr- Toot Mia Min Typ Max Min M.. Unit VIM",,, VILmin VIHAmin VIL ........ VEE Gnd
'ower Supply Dl1Iin Current IE 8 62 77 mAde: 8 1,16
Inpu.eu ...... linH 14 - - - 220 - - "Ade: 14 - - - 8 1,16
linl 14 0.5 - 0.5 - - 0.3 - "Ade: - 14 - - 8 1,16
LogIc'·I·· VOH 8 -1.1110 -0.880 -0.930 -0.780 -0.825 -0.630 Vdc 2 8 1,18
OulPU.Vol_ 13 -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vdc 14 - - - 8 1,16
Logic ""0"" OulPU' VoI_ VOL 13 -1.920 -1.855 -1.850 - -1.620 -1.820 -1.545 Vdc 15 2.7,9,14 - - 8 1.18
1.ogIc:'·I"" VOH ... 8 -1.100 -0.950 - - -0.845 - Vde: - - 2 8 1.18
llI .... oId VoI_ 13 -1.100 - -0.950 - - -0.846 - Vdc - - 14 - 8 1,16
Logic ""0". VOLA 8 -1.635 -1.600 -1.525 Vdc 2.9.14 7 8 1.18
llI .... oId Vol • • 13 - -1.&35 - - -1.600 - -1.525 Vde: - 2,7.14 - 9 8 1.18
SwitIClfintTi ....
iloo n Loodl +1.11 V +0.31 V 'ul_ln PuI_Out -3.2 V +2.0 V
P~onDol.." '7+&- 8 - - 1.5 4.0 6.0 - - ns 2 9.14 7 6 8 1.18
'7~ 6 - - - - 2 9.14 6
'7+13- 13 - -
~ i ~ -
-
- 14 2.9 13

j j
'7-13+ 13 - - - 14 2.9 13
t&+ 8 - - 1.1 2.0 3.3 - - 2 9.14 6
- -
Rile Time 12O!I to 80111

Fill Time 12O!I to_I

....
'13+

'13-
13
8
13
-
-
-
- ~ ~.
-
-
-
-
-
-
14
2
14
2.9
9.14
2.9
13
8
13

•
 .' elECTRICAL ClfARACT1RISTtCS .
3:
Each MECL 10,000 series circuit has been
designed to meet the de specifications
shown in the test table, after thermal equi-
'.2 , . 003
...
(")

o
CJ1
librium has been established. The circuit is
in a test socket or mounted on a printed
circuit board and transverse air flow greater
15 aD 2
"
N
n-
than 500 linearfpm is maintained. Outputs 16 aD 1 o
~
are terminated through a 1 ~ohm resistor
to -2.0 volts. Test procedures are shown
A 13
1 000
e.
~
only for selected inputs and outputs. Other t:
(I)
inputs and outputs are tested in a similar Q.
manner.
7 013

8 11 F SUFFIX
8 a12 CERAMIC PACKAGE
CASE 650
E 3 9 all

10 010
El 6
L-/ -
TEST VOLTAGE VALUES
IVoitsl
1fT...
Temp.,.ture VIHmu YILmin VIHAmin VILAmo VEE
w -H"c -0._ -1.920 -1.255 -1.510 -5.2
W -1.105
w +215oC -0.780 -1.850 -1.475 -5.2
~ -1.820 -1.000 -1.400 -5.2
+125"C -0.630

- -
MC1CB72F T_ Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
U_ -.-c +m"C +125"C IVCC I
CIweee..-ie ey- T_ Min Min Typ Min M •• Unit VIMm •• VILmin VIHAmin VILAm•• VEE Gnd
PCWIIer Supply Orllin Current IE 12 - - - 62 77 - - mAde - - - - 12 4.5
Inpu,Cu,,",,' linH 2 - - - - 220 - - .Ade 2 - - - 12 4.5
linL 2 0.5 - 0.5 - - 0.3 - .Ado - 12 - - 12 4.5
Logic "I" VOH 10 -1.(11) -0.880 -0.930 -0.780 -0.825 -0.630 Vdc 6 '12 4.5
OU ..... 'VoI_ 1 -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vde 2 - - - 12 4.5
Logic "0" Outpu, VoI_ VOL 1 -1.920 -1.656 -1.850 - -1.620 -1.820 -1.545 Vde 3 2.6.11,13 - - 12 4.5

--
LogIc "I" VOHA 10 -1.1110 - -0.950 - - -0.845 - Vde - 6 - 12 4.5
n.....oIcIVoI_
Logic "0" VOLA
1
10
-1.100 -
-1.835
-0.950 - -
-1.600
-0.845 -
-1.525
Vde
Vdc
-
2.6.13
2 -
11
12
12
4.5
4.5

, ,
n.....oIdV...... 1 - -1.635 - - -1.600 - -1.525 Vde - 2.6.11 - 13 12 4.5
SwitdaingTiI"Ml
It 00 n Loodl +1.11 V +0.31 V PUI_ln Pu . . Out -3.2 V +2.0 V
P~onDtlOV '11+6- 10 - - 1.5 4.0 6.0 - - n. 6 2.13 11 10 12 4,&
'11~ -
~
10 - - - 6 2,13 10
t11+1- 1 - - ~ - - 2 6.13 1

---
t11-1+ 1 - - - 2 6,13 1
'10+ 10 - - 1.1 2.0 3.3 - 6 2,13 10
Rill Time C2O!' to_I - - -
~
'1+ 1

~
2 6.13 1
--
Fill Time C2O!' to _ I
'10-
'I-
10
I
-
-
-
-
-
-
2
14
2.13
6.13 1 10
1 1 1
MC10572 (continued)

_ITCHING TIME TEST CIRCUIT AND WAVEFDRMS • 25"c

VCC,-VCC2

Ito., ~F
+2.0 Vdc V ou ,

21 ~F t
r------- - - - - - - ,
50 PROPAGATION DELAY

~
+""V
Pyl. Vin 50%
Generator +0.31 V
,--
,++
V out

V out

V out

Input Pul ..
t+ • t- - 2.0±. 0.2 "$
(20 to 80%)

I
I
L------[1-=-O.-:F __ ...
-.J
Unused outputs connected to 8
+1.11 Vdc 100-ohm resistor to ground.

:r+!!!\~~:. Vee - -3.2 Vdc

All Input and output cabl •• to the lCOPl!
.r. aqual lengths of 50-ohm cOlxial
cabl•. Wlr. length should be < 1/4 Ineh
from TPin to input pin and TP out to
output pin. Vout I, 2:1 ettenUlted.
Unu_d outputt; connected to • 100-ohm
r.,I,tor to ground.

3-338
 MECL 10,000 series
DUAL 4 TO 1 MULTIPLEXER

MC10574

The MC10574 is a high speed dual channel

..~ multiplexer with output enable capability. The
select inputs determine one of four active data
inputs for ear.h multiplexer. An output enable
forces both outputs low when in the high state.
Po = 305 mW typ/pkg (No Load)
The enable is also useful in wire-ORing several
'tpd ... 3.5 ns typ (Data to output)
multiplexers to achieve additional channel capa-
bility. Delay from data input to output is typi·
cally 3.5 nanoseconds.

xo (7) 3

Xl (9) 5

X2 (8) 4 2 16) z

X3110) 6

All1)

B 113) 9

Enable (2) 14

VO 11) 13

VI 115) 11
15 13) w
V2116) 12

V3114) 10

TRUTH TABLE

ENABLE ADDRESS INPUTS OUTPUTS

E B A Z W
I Case I VCC1 I VCC2 VEE
4> L L
H 4>
I 620 I Pin 1 I Pin 16 PinS
L L L XO vo
I 650 I Pin 5 I Pin 4 Pin 12 L L H Xl VI
L H L X2 Y2
L H H X3 Y3
til = Don't Car.
Numbers at end of terminals are pin numbers for L package (Ca .. 620).
Number. in parenthesis denotes pin numbers for F package (C• • 650),

t
, ...,
0 . . . . 1 Inform.tion ..ction for p.ckaging •• nd maximum r.tings.

3·339
 ELECTRICAL CHARACTERISTICS
each full temperature range MECL 10,000 s:
sari.. circuit his been designed to maet XC 30 r----. ....
(")

-
the de specifications shown in the test
table, after thermel equilibrium hes been II ~
o
~
X150
elt8biilhed. The circuit is in 8 test
socket or mounted on 8 printed circuit
board and transverse air flow greater than
X240 III ~ 2 Z
-'="
500 linear fpm is maintained. Outputs are
terminated through a l000hm resistor to X3 60 IIII '\""'- 8
-2.0 volts. Test procedures are shown for
L SUFFIX
CERAMIC PACKAGE
....
::J

only one input, or for one set of input con- CASE 620 ::J
" 7 c:
ditions. Other inputs tested in the same CD
Q.
manner. • 9

En;bi'; 140 II I I

YO 130

....
Y212

Y310
: III I L...---

~ ... T '::"":.ur.
.s5"c
VfHmax
-{I.SBO
TEST VOLTAGE VALUES

Vil min
-1.920
(Voltsl

VIHAmin
-1.255
VILA miX
-1.510
VEE
-5.2
+25o C -{I.780 -1.850 -1.105 -1.475 -5.2
Co)
+125°C -{I.630 -1.820 -1.000 -1.400 -5.2
W MCl11574L T . . Limits
~ Pin
Unci. -65"e +25o C +125o C
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(Vcel
Chlrut.istic Symbol Test Min M.. Min Typ Mo. Min Mo. Unn VIHmax VIL min VIHA min VILA miX VEE Gnd
Power Supply Drain Current IE 8 - 80 - 58 73 - 80 mAde - - - - 8 1.16
I nput Current lin H 4 375 - - 220 - 220 .,Ade 4 8 1.16
14 - 565 - - 330 - 330 14 - - - 8 1.16
lin L 4 0.5 - 0.5 - - 0.3 - .,Ade - 4 - - 8 1.16
Logic "1"
Output Voltage
VOH 15 -1.080 -{I.880 -0.930 - ~.780 -0.825 -{I.630 Vde 13 - - - 8 1.16

Logic "0" VOL 15 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vde 14 - - - 8 1.16
Output Voltage
Logic '.,.' VOHA 15 -1.100 - -{I.950 - - -{I.845 - Vde - - 13 14 8 1.16
Threshold Voltage
Logic "0" VOLA 15 -1.635 - - -1.600 - -1.525 Vde - - 14 - 8 1.16
Threshold Voltage
Switching Times +1.11 V Pul .. ln Pul.Out -3.2 V +2.0 V
(100 n Loadl
Propagation Delav '13+15+ 15 1.3 4.6 1.5 3.5 4.5 1.2 4.5 ns - - 13 15 8 1.16
113-15- 15 1.3 4.6 1.5 3.5 4.5 1.2 4.5 - - 13

I II
17+15_ 15 1.8 6.1 2.0 5.0 6.0 1.9 6.0 13 - 7
17_15+ 15 1.8 6.1 2.0 5.0 6.0 1.9 6.0 13 - 7

j
114+15_ 15 0.9 3.0 1.0 2.0 2.9 0.9 2.9 13 - 14
15 3.0 2.0 -

!
114-15+ 1.0 2.9 2.9 t3 14

l
Rise Tune .+ 15 3.3 1.1 2.0 3.3 3.4 13 - 14
(20%'080%1
Fait Time
·1~.o8O!l1
.- 15 3.3 t. t 2.0 3.3 3.4
.....
13 - 14
.-
 ~L~TRlG+&. oCM~""tSTICS, ,--"";-,,.-
i:
Each full temperature range MECL 10,000
series circuit has been designed to meet
the de specifications shown in the test
xo

X1
7 0

'0 II
'"

~
...o
n
table. after thermal equilibrium has been ~
established. The circuit is in a test X280 III ~ 6 Z
~
socket or mounted on a printed Circuit
board and transverse alT flow greater than X3100 IIII ~ 8
500 Imear fpm IS maintained. Outputs are
terminated through a 100-ohm resistor to <-~~
...5'
::l

-2.0 volts. Test procedures are shown for

only one input, or for one set of Input con-
813
~~ r:::
It)

.e:
ditions. Other inputs tested in the same
manner
e;;;,bie 2 0 IIII F SUFFIX
CERAMIC PACKAGE
CASE 650
YO 1 0 I I I I L---
VI 150 I I I

Y216: ~'. TEST VOLTAGE VALUES

IVoial
liT...
Y314 T.,...,.t... VIH .... VILmin VitIA min VILA_ VEE
-55"c -0.880 -1.920 -1.255 _1.510 -5.2
+25"c -0.780 -1.8&0 -1.105 -.1.475 -5.2
4J +125"C -1.820 -1.000 -1.400 -6.2
~
-0.630
.- Pin
MC10674F T_ Limit,
TEST VOLTAGE APPLlEO TO PINS LlSTEO BELOW
Undor -5s"C +26"c +l25o C (Vee l
Charact.istic Symbol T ... Min M.. Min Typ Max Min Max Unit VIH .... VILmin VIHAmin ViLA .... VEE Gnd
Power Supply Drain Current Ie 12 80 58 73 80 mAde 12 4,5
Input Current lin H 8 - 375 - - 220 - 220 "Adc: 8 - - - 12 4,5
2 - 555 - - 330 - 330 2 - - - 12 4,5
lin L 8 0.5 - 0.5 - - 0.3 - "Adc - 8 - - 12 4,5
Logic "'" VOH 3 -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vdc 1 12 4,5
Output Voltage
Logic "0" VOL 3 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc 2 - - - 12 4,5
Output Voltage
Logic "1" VOHA 3 -1.100 - -0.950 - - -0.845 - Vdc - - - 2 12 4,5
ThreshOld Voltage
Logic "0" VOLA 3 - -1.635 - - -1.600 - -1.525 Vdc - - 2 - 12 4,6
Threshold Voltage
SwitchinG Times +1.11 V 'ul.ln 'u,.Out -l.2V +2.0 V
110011 Leadl
Propagation Delay t'+3+ 3 - - 1.5 3.5 4.5 - - ns - - 1 3 12 4,5
'1-3- 3 - - 1.5 3.5 4.5 - - - - 1
t11+3_ 3 - - 2.0 5.0 6.0 - - 1 - 11
t11-3+ 3 - - 2.0 5.0 6.0 - - - 11
t2+3- 3 - - 1.0 2.0 2.9 - - - 2
'2-3+ 3 - - 1.0 2.0 2.9 - - -
Aiae Time
120%'0110%1
Fall Time
(20% '0 110%1
.+

.-
3

3
-

-
-

-
1.1

1.1
2.0

2.0
3.3

3.3
-

-
-

- j -

- j
MC 10574 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC

Vee,· Vee2 V out

+2.0 V.dc

''''f
r-------
it" .
------,
60

Input

TPout
Pul. Generator

Input Pulse
tT'" t- '"' 2.0 ±. 0.2 ns
(20 to 80%)

50..ohm termination to ground 10·

cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50·ohm
coaxial cable. Wire length should
be < 114 inch from TPin to input VEE = -3.2 Vdc
pin and TP out to output pin_
V out I, 2: 1 attenuated.

PROPAGATION DELAY

V out

V out

3-342
 '\ MECL 10,000 series
QUINT LATCH
~----------'
MC10575

ThrMC10575 is a high speed, low power quint .latch.
It features five 0 type latches with common reset and a
common ~o·!f1put clock. Data is tranSferred on the nega-
tive e4ge of the clock and latched on the positive edge.
1M t1f/o"1!lock inputs are "OR"ed together. Propagation
.Iays'are typically 2.1 nanO!l~n4s. from each data input
111 the :output.
. Any C;hal198. On the. data input will be reflected at the
ciltIlUfs while the clock is low. the outputs are latched
., tI1- po.sitiye transition of the clock. While the clock
i
is in the high state, a change in the information present
at the data inputs will not affect the output information.
The reset input is enabled only when the clock is in the
high state.
The MC10575 alldwsstorage of five bits of information,
and it is useful in temporary storage applications in high
speed central processOrs, accumulators, register files, digital
communication systems, instrumentation, and test equ ip·
ment.

POSITIVE LOGIC NEGATIVE LOGIC

00Io---------~--~ 1400 DOlO-------------~

I
!'
01 12-----------+-1~ 1501 15 01

0213-----------+-i~ 2 02 D21~--------_+_+~ 2 02

03 9------~--4_~~ 3 03 03 3 03

D. 5--~------4_~~ 4 04 o. 4 01
Co6 co
Ci 7
·A_t 11 ____________--4____-:'

TAUTHTA8LE
VCCI - Pin 1
0 C{) ~ R_t On+1 VCC2 - Pin 16
L L L ~ L VEE -PinS
H L L ~ H
~ H ~ L an
~ tP H L an PD - 400 mW typ/pkg (No Load)
~ H tP H L tpd - 2.6 netyp (Dllt. to Output)
~ ~ H H L
~ - don't car•

. . . . . . . . Infoml8ti!NIl8Cticin for packaging end "",ximum retingo.

~Gi

3-343
 ELECTRICAL CHARACTERISTICS DO
'0
,.
00 s:
Each full temperature range MECL 10,000 0
series circuit has been designed to meet the ...a
de spftcifications shown in the test table, e
CTI
after thermal equilibrium has been esut>- .....

-
os
fished. The circuit is in a test socket or
mounted on a printed circuit board and
0'
en
transverse air flow weater than 500 linear 8"
fpm is maintained. Outputs are terminated
through a l000hm resistor to -2.0 volts. Q,,
L SUFFIX
CERAMIC PACKAGE
CASE 820
...
::J
::J
Test Procedures are shown only for se- C
lected inputs and outputs. Other inputs to
and outputs are tested in the same manner. Cl.

.
DJ J
OJ

-~"
TEST VOLTAGE VALUES
(Vo""
OT. .
Tamperature V,H .... VIL min VIHA min ViLA ..... VEE
~: : C R -lisOc -0.880 -1.920 -t.2I5 -'.500 -5.2
R, •• " +25oC -0.7811 -1.850 -1.111i -1.475 -6.2
+125 oC -0.630 -1.820 -1.000 -1.400 -5.2
MCl11i75L T. . Limk,
Pin VOLTAGE APPLIED TO PINS LISTED BELOW:
-65"c +25o C +125Oc

,
Und_
Chltactetittic Sy_1 T. . Min Mo. Min Typ Mo. Min Mo. Unit V.H mix VIL min VillA min VILA .... VEE Gnd

i Power Supp4y Drain Current

Input Current
IE
linH
8
6
7
10
-
-
-
-
-
-
-
-
-
-
-
-
78
-
-
-
97
290
290
290
-
-
-
-
-
-
-
mAde
~Adc
-
6
7
10
-
-
-
-
-
-
-
-
-
8
8
1'6
1,16

~
-
•
11 645 l'
Input Leakage Current linL All 0.5 - 0.5 - - 0.3 - "Adc: - CD - - 8 1,18
LOgic: "1" VOH 14 -1.080 -0.880 -0.930 - -0.780 -0.825 -0.630 Vdc 10 6 - - 8 1,16
Output Voltage 15 -1.080 -0.880 -0.930 - -0,7811 -0.825 -0.630 Vdc 12 6 - - 8 1,16
Logic "0" VOL 14 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545. Vdc - 6,10 - - 8 1,16
Output Voltage 15 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vdc - 6,12 - - 8 1,18
Logic: "1" VOHA 14 -1.100 - -0.950 - - -0.845 - Vdc - 6 10 - 8 1,18
Threshold Voltage t5 -l.too - -0.950 - - -0.845 - Vdc - 6' 12 - 8 1,18

,
Logic "0" VOLA 14 - -1.635 - - -1.600 - -1.525 Vdc - 6 - 10 8 1,18
Threshold Voltage 15 - -1.635 - - -1.600 - -1.525 Vdc - 6 - 12 8 116
Switcltinl Timet +1.11 Vd. +0.31 Vd. 'ul.ln PU .. OU. -3.2Vdc +2.oVdc
Data Input '10>14+ 14 - - 1.0 2.1 3.5 - - ns 6,7 10 14 8 1,16
- - 2.1 - - -
'10-14-
t4 -
1.0 3.5 6,7, 10

I
Clock Input t6-14+ - 1.0 2.6 4.3 - - - 7 6,10

,
'&-14- - - 1.0 2.6 4.3 - - - 7 6,10
-- -
:414~
Reset Input t11+4- - 1.0 2.8 3.9 - 5 6 7,11
'11+14- 14 - 1.0 2.8 3.9 - - 10 6 7,11
Setup Time tsetup 14 - - 2.5 - - - - - 7 6,10
Hold Time 'hold 14 - - 1.5 - - - - - 7 6,10
Ri. Time (20 to 80%1 t+ 14 - - 1.1 2.0 3.5 - - - 6,7 10
Fon T,imo (20",_1 ,- 14 - - 1.1 2.0 3.5 - - - 8,7 '0
(i),1 'n~vidual'V ...t each input; apply Vel mm to pin unct.r telt.
a>~tpu~~~d ~o ~"'}~~~_~~or ta_tolt. _ ,"" .:..G ~. ~
; MC10575 (continued)

SWITCHING nME TEST CIRCUIT

Vee 1 =vCC2-
V out

DO
10
1
I
""ill""
r---- ---l
14
100

I
I 1 60
0,1 I

Data Input

TP out

PRF = 1.0 MHz

t+ = t- = 2.0 ns
(20% to 80%)
VOL ~ 0.31 V
VOH ~ 1.1, V

04 5'~1-------+-+~

~~ ~ I
R._t11~1~______~~__~

'----IF"~
VEEL~'VdC
50-ohm termination to ground lo-
cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin
and TP out to output pin.

Unused outputs connected to a 100

n resistor to ground.

3-345
MC10575 (continued)

VOLTAGE WAVEFORMS

RESET INPUT
\ /r-------+l.11 v
CLOCK~ L J________ +0.31

RESET
+0.31 V

r--.....,.+----- +1.11 V
OUTPUT
'------+0.31 V

DATA INPUT
r-----.'----- +1.11 V
DATA
+0.31 V

~---.....,.:+---- +1.11 V
OUTPUT
+0.31 V

CLDCKINPUT

DATA

~----+1.11 V
CLOCK
'--"------+0.31 V

t6-14+

------+1.11 V
OUTPUT
'-----''---------+0.31 v

~---.....,.-----+1.11 V
D

'----+0.31 V

tsetup'-'+---r---t--thold
r-------+1.11 v
NOTE: c
tsetup I, the minimum tima befbre the positive
tranlltlon of the clock pul .. (e) that information mUlt --------'·--------+0.31 V
ba pres.nt at the data Input (0),

_/
thold I, the minimum tim. aftar the pOsitive
transition of the clock pul .. (e) that information mUlt a
remain unchanged at the data input (0).

3-346
 MECL 10,000 series
LOOK-AHEAD CARRY
BLOCK

MC10579

The MCI 0579 device has 12 low power gates

internally connected to perform the look-ahead
carry function. This device has high Z input
Po : 300 mW typ/pkg (No Load) pulldown resistors and open emitter outputs.
1pd = 3.0 ns typ (Carry. Propagete) This device has applications in fast look-ahead
4.0 n. tv'P (Generate) adders such as with the MC10581. It can be
used also as a boolean function generator.

POSITIVE LOGIC

G3(9)5 -----------'~

P3(1) 1 3 - - -...._ _ _ _ _ _ _....,,~_.,

G2(13)9---+-------'~
~m=: 3(7) C n +4

P2116) 12 ---t:;:=======:4--" )c>---++.

C n (15)11

1513)PG

GlIll)7

P1114)10
6(10)C n +2
GO(S)4

L
P012)14

Pa - PO + P1 + P2 + P3 VCCI ~ Pin I (e)

GG ~ IGO + PI + P2 + P3) (Gl + P2 + P3) (G2 + P3) G3 VCC2 ~ Pin 16 (4)
C n +2 = (C n + PO + P1) (GO + P1) Gl VEE ~ Pin S 112)
C n +4 = (C n + PO + P1 + P2 + P3) (GO + P1 + P2 + P3) (Gl + P2 + P3) (02 + P3) G3

Numbers at end of terminals"ore pin numbers for L package (e ... 620).

Numbert In parenthesis denotes pin numbers for F package (CUll 660),

See General Information section for packaging.

3-347
 ELECTRICAL CHARACTERISTICS s:
Each MECL 10,000 series has t..n de-
signed to meet the de specifications shown 5 L: ...
n
o
::1, ~
in the test table, after thermal equilibrium
U1
has been established. The circuit is in a 3
.....
test socket or mounted on a printed circuit
board and transverse air flow greater than
c.c
500 linear fpm is maintained. Outputs are 2 n-
O
terminated through a 100-0hm resistor to ::J
-2.0 volts. Test procedures are shown only ~.
11 II I 1111"'"" -'

"""
for selected inputs and outputs. Other ::J
inputs and outputs are tested in a similar ! 4i::!:::!::J::: ') 15
L SUFFIX
c:
RI
manner. CERAMIC PACKAGE Co
CASE 620

1~ IIII:D ~ 6

t. ~

TEST VOLTAGE VALUES

(Voltsl
OT...
Temper.... ,. VIHmu VILmin VIHAmin VILAm .. VEE
-55"c -0.880 -1.920 -1.255 -1.510 -5.2
+25"1: -0.750 -1.850 -1.105 -1.475 -5.2
+126°0 -0.630 -1.820 -1.000 -1.400 -5.2
Col)
MCl0679L Test Limits
~ Pin TEST VOLTAGE APPLlEO TO PINS LISTEO BELOW:
Undor
~50C +2SoC +l25oC (Veel
Q) Ch .....ristic Symbol T... Min Max Min Ty. M ... Min Max Unit VIH max VIL min VIHAmin VILA max VEE Gnd
Power Supply Drain Current Ie 8 - - - 58 72 - - mAde - - - 8 1,16
Input Current linH 4.7.11 - - - - 270 - - ~Ade 4.7.11 - - - 8 1,16
- -
~ ~ ~
5.9 - - - 225 - - 5.9 - -
10.13 - - - - 440 - - 10.13 - - -
12 - - - - 395 - - 12 - - -
14 - - - - 355 - - 14 - - -
linL 4 - - 0.5 - - - - ~Ade - 4 - - 8 1.16
Logic "1" Output Voltage VOH 2 -1.080 -0.850 -0.930 - -0.750 -0.825 -0.630 Vde 4.5.7.9 - - - 8 1.16
Logic "0" Output Voltage VOL 3 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 Vde - - - - 8 1.16
Logic "1" VOHA 2 -1.100 - -0.950 - - -0.845 - Vde 13 - 5 - 8 1.16
- -
~ ~ ~ ~
- - - -
~ ~
Threshold Voltage 2 5.12 9
2 - - - - 5.9 - 12 -
2 - - - - 5 - 13 -
Logic "0" VOLA 2 - -1.635 - - -1.600 - -1.525 Vde 13 - - 5 8 1.16
- -
~
- - -
~
- 5

~
Threshold Voltage

~
2 13

Switching Tim.
2
2
-
- ~ -
-
-
-
-
- ~ 5
5,9
-
-
-
-
9
12

150n Lo..1 +1.11 V Pulse In Pul. Out -3.2 V +2.0 V

Propagation Delay t11+6+ 6 - - 1.0 - 4.5 - - ns 4,7 - 11 6 8 1.16
6 - - - 4.5 - - - 11

~
4.7 6

j j j
'11-6-
t5+2+ 2 - - - 5.5 - - 4.7,9 - 5 2
'5_2_ 2 - - - 5.5 - - 4.7.9 - 5 2
Ri.Time 120"10 80%1 '6+ 6 - - 1.1 - 3.5 - - 4.7 - 11 6
Flil Tim. (20"'0811%1 'I>- 6 - - 1.1 - 3.5 - - 4,7 - 11 6
 ELECTRICAL CHARACTERISTICS
Each MECL 10,000 .rie. hOI been de,
s::
C')
signed to meet the de specifications shown -0
in the test table, efter thermal equilibrium
9 -----I
o
has been established. The circuit is in a g]
::~
test socket or mounted on a printed circuit
(S)
board and transverse air flow greater than
500 linear fpm is maintained. Outputs are n-
O

~
terminated through a 10Q-0hm resistor to
-2.0 volts. Test procedures are shown only 6 ....::::l
for selected inputs and outputs. Other 3'
inputs and outputs are tested in a similar 15 II I FTff"" ./
c<D
manner. C.
3 F SUFFIX
CERAMIC PACKAGE

:;8
CASE 650

10

2
TEST VOLTAGE VALUES
(Vol'"
liT...
Temper.a.... VIHm_ VILmin VIHAmin VILAm. . VEE
-550 C -0.880 -1.920 -1.255 -1.510 -5.2
+25OC -0.780 -1.850 -1.105 -1.475 -5.2
(,J +1250 C -0.630 -1.820 -1.000 -1.400 -5.2

~
(l)
Pin
U_, -ss°C
MC10679F Toot Liml..
+25OC +126°C
TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
(Vee'
Ch.-.c.rtstic Symbol T... Min M_ Min Typ Max Min Max Unit VIHma VIL !'Ii" VIHAmi" VILAma VEE and
Power Supply Drain Curr.nt IE 12 58 72 mAde - - 12 4.5
Input Current linH 8,11,15 - - - - 270 - - ~Ade 8,11,15 - - - 12 4,5
9.13 - - - - - - - - -

! !
225

!
9.13
1.14 - - - - 440 - - 1,14 - - -
16
2
-
-
-- -
-
-
-
395
355
-
-
-
-
16
2
-
-
-
-
-
-
linL 8 - - 0.5 - - - - ~Ade - 8 - - 12 4,5
Logic "'" Output Voltage VOH 6 -1.080 -o.B80 -0.930 - -0.780 -0.825 -0.630 Vde 8,9.11,13 - - - 12 4,5
Logic: "0" Outpu, Vol'. VOl 7 -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vde - - 12 4,5
Logic ;",.
VOHA 6 -1.100 - -0.950 - - -0.845 - Vde 1 - 9 - 12 4,5
Threshold Vol_ 6 - - - - 9,16 - 13 -
6 - - - - 9.13 - 16 -

Logic "0" VOLA

6
6
+
-
-
-1.635
+
- - -1.600
+
- -1.525
+
Vde
9
1 -
17
- 9
+
12
+
4,5
Threthold V~tage 6 - - - - 9 - - 17
6 - - - - 9 - - 13

Switdli. . Tim.
6 -
+ - -
+ -
+ + 9,13 - - 16
+ +
150nL_' +1.11 V Pula In Pu. . Out -32V +2.0 V
Propegetion Oelay '15+10+ 10 - - 1.0 - 4.5 - - ns 8,11 - 15 10 12 4,5
- - - - - -

I II
'15-10- 10 4.5 8.11 15 10
t9+6+ 6 - - - 5.5 - - 8.11,13 - 9 6
- - - 5.5 - - -
Aile Time (20" to 80%)
'9~-
'10+
6
10 - - +
1.1 - 3.5 - -
1\11,13
8.11 -
9
15
6
10
Fall Time 120% to 80%) '10- 10 - - ~ ----=-- 3.5 - - 8,11 - 15 -
10
MC10579 (continued) ·... 1

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25"<:

vee1 = VCC2 = +2.0 Vdc

_":f±t~"
V out

r Coax

G31 I
P3 I IC n +4
G21 50
P21 GG
5Q.ohm termination to ground lo-
cated in each scop. channel input. Cn I
Pulse GIl PG
Generator Pll
Gal I C n +2
Input Pulse
t+ = t- '" 2.0 ±. 0.2 ns
(20 to 80%)

PROPAGATION DELAY

Vee = -3.2 Vdc

All input and output cable' to the
scope ar. equal lengths of 50-ohm
V out
c08xi.1 cabl •. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.
V out is 2: 1 attenuated.
Unused inputs and outputs con-
nected to a 100 ohm resistor to
ground.

When used with the MC10581 ,the MC10579periorms

APPLICATION INFORMATION
The MCl 0579 is a high speed, low power, standard
MECL complex function that is designed to perform the
look-ahead carry function_ This device can be used with
the MC10581 4-bit ALU directly, Of with the MC10580
dual arithmetic unit in any computer, instrumentation or
digital communication application requiring high speed
arithmetic operation on long words.
a second order or higher look-ahead. Figure 2 shows a 16-
bit look-ahead carry arithmetic unit. Second order carry
is valuable for longer binary words. As an example, addi-
tion of two 32-bit words is improved from 30 nanoseconds
with ripple-carry techniques, to 18 nanoseconds with carry
look·ahead techniques. A block diagram of a 32-bit ALU
is shown in Figure 1. The MC10579 may also be used in
many other applications. It can, for example, reduce sys-
tem package count when used to generate functions of
several variables.

FIGURE 1 - 32-BIT ALU WITH CARRY LOOK·AHEAD

3-350
 ,-" ," ~? -~
-~
....
o
g:
CD

A.
.. A' .. AS
A"
.,
A'O
A.3
."
A.'
...
c;-
O
::l
~.
.'0

yTI
• 2 .S A •• ::l
c:
9"f r~9' SiS ct>

Ii rli Q.

ii
AD 80 A 1 81 .4.2 82 ,A,3 83 AD 80 A1 81.4.282 A3 83
t'y LA~ .• O A' •• A2.2 A3 J3 AO 80 At 81 A2 82 P.3 83
I
Cin Cn en'" 4 en en +- 4 f-o C en t- .. en en +- 4 -0
~M ,---M -M

..
M

48IT:C~~~~~ETIC
,----50 MC10581 G_ -.0 MC105S1 -50 MClOSS1 G_

~
Gr-- r-- SO G
481TAAITHMETIC 4·BIT ARITHMETIC 4 BIT ARITHMETIC
~
r--" LOGIC UNIT LOGIC UNIT r-" LOGIC UNIT - 51 LOGIC UNIT
_52 p r-- 52 p - 52 p -52 P
53 .3 53 53
FO F. F2 F3 FO F. F2 F3 FO F. F2 F3 .. FO Fl F2 FJ

M
50
51
w 52
~ 53
en
-- FO F. F2 F3 F. F' FS F7 F. F" FlO Fll F.2 F1J Fl. F.,

PO GO P. G1 P2
I
G2 P3 G3

MC1OS79 G ---0
Cn
CARRY LOOKAHEAD
P---O
en +- 2 c" ....

I bets

FIGURE 2 - 16-BIT FULL LOOK·AHEAD CARRY ARITHMETIC LOGIC UNIT

 DUAl2·BIT
MEeL 10,000 series
ADDER/SUBTRACTOR

MC10580

The MCl0580 is a high speed, low power ganeral·pur·

pose adder/subtractor. It is designed to be used in spacial
purpose adderslsubtractors or in high speed multiplier'
arrays. The Mel 0580 eIIn be used in any piece of equip-
ment where these operations are necessary.
Inputs for each adder are Carry·in, operand A, and
Po - 380 mW typ/pkl (No Loodl
operand B; outputs are Sum, Sum, and Carry·out. The
tpd(typ): el n to C out - 2.2
AO 10 SO - 4.5 n.
n. common Select inputs serve as a control line to invert A
for subtract, and a control line to invert B. The speed
AO to Cout - 4.15 n. is very fast, with Carry·in to Carry·out propagation delay
of 2.2 ns and Operand in to Sum or Carry·out propagation'
delay of 4.5 ns.

POSITIVE LOGIC NEGATIVE LOGIC

(11)1 (11)7 1& 131

1131. (13) g :2 {e,
UU 15
(101 •
'9' 5
(1016
(8) .. (8) .. J (71

, . (2)

1 (5)
(115)11 (Hi! 11
(14)10 (14' 10
(16112 (18) 12 13 ell

Positive Logic Only Both Po,ltive end Negative Logic:

A' = A (!) SelA .. A 0 SetA S = Cjn (A'S' + A' 8') + Cin (A'S' + A'S')
Cout :: Cin A' + Cjn B' + A'S'
S'" S@S.IS" S0SoiS

Numb.,.. at Wid of termlnel' .re pin number. for L peeke,. (Case 620).
Numbe,.ln pe,.,th..11 denot.. pin number. for F package (C... 650).

POSTIVE LOGIC DIAGRAM - 1/2 Of Circuit Shown TRUTH TABLE

FUNCTION

.00
.... .... INPUTS
AO
L
80
L
Cin
L
so
L
OUTPUTS
so C~,

L
"" "" L
L
L
"L "" "
L
L
L
L
" "" L "" L
"L
....
eo """ "" """
L
L
"L

"L L" "

"
L

""
"" "" " "" "L
L

" "
L
"
C," o------++----t---l SUBTRACT
"" L
L
L
L
L
L "
L
L L

L L "L L " L"

"" L
L
L ""
L "L "
L
"
L L

"" L "" L
"L "
L ""
"" L
L " "" ""
L
L L

REVERse L L" L "L "

L "
L
SUeTA.4CT L
L """ L
L
L
"L
L
L
" "" ""
L
L "" L

" ""
L "L L" L

"L "
L

FUNCTION SELECT TABLE

L
L
L
"" "" L

"" "L ""

L
L
L
L

L L" L
" L
"L L " "
FunctIon
L
L
L
L
L
L
L
"L "" "
L
L
""
S - .4plul a
L L L " L
S·.4 Wllnul a
S· B,,"nuI.4
L
L
L
L " L
L
" "L
L

L" "
L "
L

S • 0 minUI A m,nul a L L
""" "" "
L L "" "
L
L L
" " L L

S. . Gen .. al Information ..ction for peck aging.

3·352
 ELECTRICAL CHARACTERISTICS
,. s:(")

-
Each full temperature range MECL 10,000
series circuit has been designed to meet the
....o
de specifications shown In the test table, U1
after thermal equilibrium has been estab· 00
lished. The circuit is in a test socket or L SUFFIX
CERAMIC PACKAGE
o
mounted on a printed circuit board and o
CASE 620
transverse air flow greater than 500 linear o
::J
'pm is maintained. Outputs are terminated
~.
mruug" a luu-onm reSistor fO -L U VOltS.
~,.
Test procedures are shown for only one L::: SelA 51
~,
TEST VOLT AOE VALUES
::J
r::

,.'2--- '"
Sels 51 Vol .. CD
input, or for one set of input conditions. a.
Other inputs are tested in the same manner.
':==== 8'
Cin Cout
~"
.Tat
TemptntuN
-aGe
VIHmu
-0.880
VILmin
-1.920
V'HAmin
-1.266
VILA.,."
-1.510
VEE
-52
~
+25"c -0.180 -1.850 -1.106 -1.415 -5.2
+1210 c -0.630 -1.820 -1.000 -1.400 -5.2
MC10680L Tell Limits
Pin TEST VOLTAOE APPLlEO TO PINS LISTED BELOW,
U-' -56"c +25"c +1211"e (Veel
CtwI'Kt_iRic $v_ TOIl Min Mo. Min Ty. Mo. Min Mo. Unit VIH m•• VILmin VIHAmin VILA.mp VEE and
Power Supply Dr.in Cur,..nt IE 8 96 10 86 - 95 mAde - - 8 16
Input Current 'inH 4 630 - 310 - 310 .Ade - - - 8 16
5 - 314 - - 220 - 220 - - - -
6 - 314 - - 220 - 220 - - - -
1 - 493 - - 290 - 290 - - - -
w
W
(11
9
10
11
12
-
-
-
-
483
314
314
-
-
-
-
-
-
-
-
290
220
220
310
-
-
-
-
290
220
220
j -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
j
w 630 310
linL All 0.6 - 0.5 - - 0.3 - .Ade - - - 8 18
Logic "I" VOH 2 -1.080 -0.880 -0.930 -0.180 -0.825 -0.830 Vdc 1~ - 8 16
OutPUt Volu.g. 3
15
-1.080
-1.080
-1.920
-0.880
-0.880
-1.665
-0.930
-0.930
-
-
-
-0.180
-0.180
-1.620
-0.825 -0.630
-0.826. -0.630
-1.820 -1.645
t 4.5.1.9
4.1.9
-
-
-
-
-
-
-
-
-
t
8
t
16

T
logic "0" VOL 2 -1.850 5.1.9
- -
OutPUt Vol . . . 3
15
-1.920
-1.920
-1.666
-1.666
-1.850
-1.650
-
-
-1.620
-1.620
-1.820 -1.645
-1.820 -1.645
1.9
1.9 -
-
- - t t

,
Logic "1" VOHA 2 -1.100 -0.950 -0.845 Vde 1.9 - 4 8 16
- - - I
Thrnhold Voltlgl

Logic "0" VOLA

3
15
2
-1.100
-1.100
-
-
-
-1.635
-0.950
-0.950
-
-
-
-
-
-
-1.600
-0.845
-0.845
-
-
-1.525
t
Vde
4.1.9
1.9
1.9
-
-
5
4
4
-
-
t
8 16
- - -
t ~
ThrW'told Voltlgl 3 -1.635 - -1.600 - -1.525 1.9 - 4
15 - -1.635 - - -1.600 - -1.625 4.1.9 - 5 -
Switching Times +1.11 V Pul_ln PuI_Out -3.2 V +Z.OV
PrOlMPtion 0tI1-V
Opwnlnput 15+15+ 15 - - 1.0 4.5 5.4 - - n. 1.9 - 6 15 8 16
tl+15+ 15 - - 4.5 5.4 - - 1.9 - 6 15
- - - - - 15

j
C_ry·in Input 1.4+15+ 15 2.2 3.3 1.9 4
l4+3+ 3 - - 2.2 3.3 - - 5.1.9 - 4 3
Select Input t'7+16+ 15 - - 4.5 5.4 - - 4.9 - 1 15
'9+15+ 15 - - 4.5 5.4 - - 1.4 - 9
Ri_Tim. t15+ 15 - - 1.1 2.0 3.1 - - 1.9 - 5
(20tollOlfol
F.,Time 'IS- IS - - 1.1
_L---
2.0 3.1 - - 1.9 - 5 1
·lndiYidu.lly ~Iy Vil min to pin under test.
 ELECTRICAL CHARACTERISTICS
II 3 s:
Each full temperature range MECL 10,000
....
(")

~
13 6
series circuit has been designed to meet the
de specifications shown In the test table, 9
F SUFFIX
o
(J'I
after thermal equilibrium has been estab- 10
8 --I--+---a.j CERAMIC PACKAGE 0)
lished. The circuit is in a test socket or
mounted on a printed circuit board and
CASE 650 o
transverse air flow greater than 500 Itnear C"l
'pm is maintained. Outputs are terminated
o
::J
~2
through a l00-ohm resistor to -2.0 volts
Test procedures are shown for only one L::: SelA
8ele
S1
51 ~5
TEST VOLTAGE VALUES
Vol ..
~,
::J
c:
input, or for one set of input conditions.
Other inputs are tested in the same manner.
1 5 - - AI
14-- ., .T. .
Temper.~,. VILAmu VEE
Cb
c.
1 6 - - C,n Cout ~1 VIHmu VILmin VIHAmin
-a"C -O.sao -1.920 -1.255 -1.510 -5.2
'---
+2Ii"C -0,780 -1.850 -1.106 -1.475 -5.2
+121i"c -{I,630 -1.820 -1.000 -1.400 -5.2
MC10610F T_ Limits
PI. TEST VOLTAGE APPLIED TO PINS LISTED ULOW,
U_ -W'c +2Ii"c +1211"C IVeel
Ctw. .illlic lo- T. . Min Mo. Min Typ Mo. Min , M ... Unit VIH mu: VILmin VIHAmin VILA m •• VEE Gnd
POW'er Supply Drein Current 'E 12 98 - 70 B6 - 95 mAde - - - - 12 4
I nput Current linH 8 - 830 - - 370 - 370 JlAdc - - - - 12 4
9 - 374 - - 220 - 220 - - - -

II
10 - 374 - - 220 - 220 - - - -
II - 483 - - 290 - 290 - - - -
13 - 483 - - 290 - 290 - - - -
w 14 - 374 - - 220 - 220 - - - -
W 15 - 374 - - 220 - 220 - - - -
CTI 16 - 630 - - 370 - 370 - - - -
~
linL All 0,5 0.5 - - 0.3 - JlAdc - - 12 4
Logic: "I" VOH 3 -LOBO -{I.880 -{I.930 - -0.780 -{I.825 -{I.630 Vdc 8,11,13 - - - 12 4
-
~ ~ ~
OulPUIVoIlIIIO 6 -LOBO -{I.sao -{I.930 -{I.780 -{I,825 -{I,630 11,13 - - -
7 -LOBO -{I,880 -{I.930 - -0.780 -{I,825 -{I.630 8,9,11,13 - - -
LOIIic:"O" VOL 3 -1.920 -1.855 -1.850 - -1.620 -1.820 -1.545 Vdc 11,13 - - - 12 4
- -
~ ~ ~
Output Voigg. 6 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 9,11,13 -
7 -1.920 -1.655 -1.850 - -1.620 -1.820 -1.545 11,13 - - -

,
Logic "1" VOHA 3 -1.100 -0.950 -{I.845 Vde 11,13 8 12 4
Thr.oId VolUge

Logic "0" VOLA

6
7
3
-1.100
-1.100
-
-
-1.635
-0,950
-{I,950
-
-
-
-
-
-
-1.600
-{I,845
-{I.845
-
-
-
-1.525
i
Vdc
11,13
8,11,13
8,11,13
-
-
-
-
9
9
8
-
-
i
12
I
4
Thf"llhold Vol~ 6
7
-
-
-1.635
-1.635
-- -
-
-1.600
-1,600
-
-
-1.525
-1.525 ~
11,13
11,13
-
-
8
-
-
8 ~
Switching Timll +1.11 V Pu"ln PuI_Out -3,2 V +2.0 V
Propegetion DeI~
ap.end I"Put t9+3+ 3 - - 1.0 4.5 5.4 - - ns 11,13 - 9 3 12 4
t10+3+ 3 - - 4.5 5.4 - - 11,13 - 10 3
C_ry·in Input ta+3+ 3 - - 2.2 3.3 - - 11,13 - 8 3

5eIect Input
ta+7+
111+3+
7
3
-
-
-
- j 2.2
4.5
3,3
5.4
-
-
-
-
-
9,11,13
6,13
-
-
8
II
7
3

J
113+3+ 3 - - 4.5 5.4 - 8,11 - 13
Ai_Time 13+ 3 - - 1.1 2.0 3.7 - - 11,13 - 9
12010_'
FoIIT_ 13- 3 - -
--
~~1__ ~.O -
3,7
- -
-
- -~ ~~ - 9

-Indhfiduelty IPP.'.¥ VIL min 10 pin under~.

:MC10580 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@l2SoC

Vee, : VCC2 -' +2.0 Vdc V out

Coax Coax

+-......--.I--t SelA ~--:"'15

9 + .....+--'~ SelB
5 AO
60
6 80

4 Cin C out -~-~ 3

TP in

14
Pulse Generator
11+------1-.
10+------1-.
12-i---aot 13

50-ohm termination to ground to

cated In each scope channel input.
L----fi-- -l
Unu_d outputl
connected to •
100~hm r ..i,tor

All input and output cables to the

scope .re equal lengths of 50-ohm
co . .:ial cable. Wire length should
be < 1/4 inch from TP in to input
1J 01 ~F
to ground.

pin end T~out to outPut pin. VEE'" -3.2 Vdc

V out I, 2:1 att.,uated.

PROPAGATION DELAY

r---~-------+1.11 v

'-------+0.31 V

TP out

TP out

3-355
 4-BIT ARITHMETIC lOGIC MECL 10,000 series
UNIT/FUNCTION GENERATOR

MC10581

The MC10681 is a high-speed arithmetic logic unit Group carry propagate (PGI and carry generate (GGI are
capable of performing 16 logic operations and 16 arith- provided to allow fast addition of very long words using a
metic operations on two four-bit words. Full internal carry second order look ahead. The internal carry is enabled by
is incorporated. for ripple through operation. applying a low level voltage to the mode control input (MI.
Arithmetic operations are selected by applying the When used with the MC10579, full-carry look-ahead, as
appropriate binary word to the select inputs (SO through a second order look ahead block, the MC10581 provides
S31 as indicated in the tables of arithmetic/logic functions. high speed arithmetic operations on very long words.

POSITIVE LOGIC NEGATIVE LOGIC

(19) 13 (19) 13
(21) 15 (21) 15
(23) 17 (23) 17
(20) 14 (20) 14

50 51 52 53
(3) 21 (8) (3) 21 2 (8)
(2) 20 (2) 20
F1 3 (9) 3 (9)
(24) 18 (24) 18
(11 19 F2 7 (13) (1) 19 7 (13)
(22) 16 (22) 16
F3 6 (12) 6 (12)
(17) 11 (17) 11
(16) 10 4 (10) (16) 10 4 (10)
(15) 9 (16) 9
PG 8 (14) 8 (14)
(4) 22 (4) 22
(6) 23 (11) (5) 23 5 (11)

Numben at end of terminals are pin numbers for L package (Case 620)
Numbers in parenthesis denotes pin numbers for F package (Case 650)

Po :: 600 mW typ/pkg (No Load)

Al to PG :=. 5.0 ns
tpd (typ): Al to F =6.5n5 A 1 to GG = 4.5 ns
en to C n +4 = 3.1 ns Al to C n +4 = 5.0 ns

POSITIVE LOGIC NEGATIVE LOGIC

Logic Fundion. Arithmetic Operation LogiC Functions Anthmetlc Operation

Function Select Mi, Htgh C .. D.C. Mi,low en
i,tow Function Select M is High M IS Lowen of LSB must be HIgh
53 52 51 50 F F S3 S2 S1 SO F F

F A F'" A plul 0 F'A, F - A minus 1

F ~ A .. ii F A plus (A. iiI F'~ F A plus (A • ih
H F " A+B F A plus (A. Bt F - A. B F . A plus (A ~ 81
H F ~ Logical "1" A tlme52 F A times 2
H L F .i.i (A" SI plutO H F - ,;:-;-s F fA. BI minus 1
H F Ii F ' (A .. II plus fA • 81 F • B (A • BI olus (A + Bl
H
H H
L
H
F" A
F =
It
A ..
•
B
F
F
A plus B
A plus (A .. 8)
F ~ AiDB
FA. B
A plus B
F - A plus (A. BI
H F-A".a F (A" BI plus 0 H F . A + B F ~ (A • SI mInus 1
H H F", A0 B F • A minus B minus 1 H F A@B F A mInus B mInus 1
H H
H F "A" 8
F
• F • (A .. HI plus (A • BJ
F A plul (A" Ell H
F ." B
F " A • B
F ' (A .51 plus (A + BI
F ~ (A .51 plus A
H L F - Logical "0" F ~ mmus 1 (twO's complement) H F < LogIcal "1'" F mInus 1 (two's complement'
F"'Aes F '. (A e SI mInus 1 H F " A + 8 F ~ (A + 51 plus 0
H H H F ." A e B F' (A e BI minUS 1 F ~ A + B F - (A + BI plus 0
F'" A F A mInus 1 F - A F . A plus 0

See General Information .. ction for peckaging.nd maximum ratingl.

3-356
MC10581 (continued)

,S3
S2
POSITIVE LOGIC DIAGRAM
SI
so

---D
~ ~ FO
f---J-L/
BO 0--
~ -L
~

AO

~ ,~/
~ Fl

Bl 0--
~ -L
~

~
AI

B2 0--
Vi
~ ~ " F2

A2
~ ~

- , .--" F3
,~
B3 0--
£>t
~§P
A3

,/
M

3-357
 ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10,000 3:
series circuit has been designed to meet (")
the de specifications shown in the test ~

~
table. after thennal equilibrium has been 0
mtablished. The circuit is in 8 test C11
socket or mounted on a printed circuit
CO
~
board and transverse air flow greater than
500 linear {pm is maintained. Outputs are
terminated through a 100-ohm resistor to
L SUFFIX
CERAMIC PACKAGE
8
:::l
-2.0 volts. Test procedures are shown for CASE 623 ~.
only one input, or for one set of input con- :::l
ditions. Other inputs tested in the same c:
CD
manner. a.

TEST VOLTAGE VALUES

IVai..,
OT...
T .... perMu ... VIH,.,.. Vil min VIHA min VILA....,. I VEE
-&15"1: -0.880 -1.920 -1.266 -1.510 I -5.2
+25o C ~.780 -1.850 -1.105 -1.476 I -5.2
. +126"1: ~.630 -1.820 -1.000 -1.400 I -5.2
MCl0511L T_ Limit. TEST VOLTAGE APPLIED TO PINS BELOW,
Pin
Undo< ~6"1: +25 o C +126"1: IVee'
a.eracteriltic Symbol TOOl Min Ma. Min TV. M.. Min Mao Unit VIH mill VILmin VIHA min VILA m •• VEE Gild

W
POMr Supply Drein Currant IE 12 180 145 - 160 mAde - I 12 1,24

W Iinpu. Cuneo. linH 9 420 245 - 245 /JAde 9 1 - 1 - 1 - T 12 I 1,24

U1 10 - 375 - - 220 - 220 10
(Xl 11 - 420 - - 245 - 245 11
13 - 340 - - 200 - 200 13
- 450 - - 265 - 265 14
"
15
16
-
-
450
375
-
-
-
-
265
220
-
-
265
220
15
16
17 -
-
460 - -
-
265 - 265 17
18 375 - 220 - 220 18
19 - 420 - - 245 - 2.5 19
20 - 420 - - 245 - 2.5 20
21 - 376 - - 220 - 220 21
22 - 496 - - 290 - 290 22
23 - 340 - - 200 - 200 23
Input Leakage Current I linL I 9 0.5 - 0.5 - - 0.3 - ",Adc - 9 I - I - I 12
I 1.24
10 - - - - - 10
11 - - - - 11
13 - - - - - 13
14 - - - - -
15
16
-
-
-
-
-
-
-
-
-
-
"
15
16
17
18
-
- -- -
-
-

-
-
-
17
18
19 - - - - - 19
20 - - - - - 20
21 - - - - - 21
22 - - - - - 22
23 - - - - - 23
High Output Voltage VOH -1.080 -0.8BO -0.930 - ~.780 ~.825 ~.630 Vdc
. - - 12 1,24
Low Output Voltage
High Threshold Voltage
VOL
VOHA
.
-1.920 -1.855
-1.100
-1.850
-0.950
- -1.620 -1B20 -1.545
~.845
Vdc
Vdc ....
-
.
-
..... 12
12
1,24
1,24
Low Thl'fthofd Volt. . VOLA -1.836 -1.8110 -1.625 'Vdc 12 1,24 ..
' .'~~
-.lrest ell iDpUt-GloltpUt.CGnIbift.8tioDl.-:coa:l". to.function T.Ibla.
·-For ttw'fthoklle¥iM _ . apply thrnhold input IIwI to only one input pin • • time.
 EL.ECTRICAL CHARACTERISTICS
E.th full temporeture r..... MECL 10.000
_ies circuit has been dlligned to mftt the
dc ~pecificetions shown in the t-'t toble.
~
....

~
efter thermol equilibrium he, been astat>- 0
U1
lished. The circuit is in 8 test .:Jeket or
mounted on 8 printed circuit board and
transverse air flow greater than 500 1inear ------ ~
....
00

fpm is maintained. Outputs are terminated

t"'ough a HIO·ohm resistor to -2.0 volts.
F SUFFIX
CERAMIC PACKAGE
8
::J
!:!.
CASE 652 ::J
c:
~

TEST VOLTAGE VALUES

IVaitsl
@Test
T.... per.tur. VIHma. VILmin VIHAmin VILA me. I Vee
_55°C -0.880 -1.920 -1.255 -1.510 I -5.2
+25 o C -0.780 -1.850 -1.IOS -1.475 I -5.2
+ 12SoC -0.630 -1.820 -1.000 -1.400
1 -5.2
MC10681F Test Limit. TEST VOLTAGE APPLIED TO PINS BELOW:
Pin
-5SoC +25"1: +125oC I Vee)
Ch.,.....istic Symbol
Under
T.,. Min MIX Min Typ MIX Min M •• Unit VIHm•• VILmin VIHA min VILA m.. I VeE I Gnd
Po.,..., Supply Drain Current IE 18 160 116 145 160 mAde I I 18 I 6.7
W
W
II nput Current linH 15
16
420
375
245
220
245
220
",Adc 15
16 I I I I 18
I 6.7

U1 17 420 245 245 17

CO 19 340 200 200 19
20 450 265 265 20
21 450 265 265 21
22 375 220 220 22
23 450 265 265 23
24 375 220 220 24
1 420 245 245
2 420 245 245
3 375 220 220
4 495 290 290
5 340 200 200
Input Leakage Current
I linL I 15
16
0.5 0.5 0.3 ",Adc 15
16
18 6.7

17 17
19 19
20 20
21 21
22 22
23 23
24 24
1 1
2 2
3 3
4 4
5 5
High Output Voltage VOH -1.080 -0.880 -0.930 -0.780 -0.825 -0.630 Vdc
I I 1 18 I 6.7
Low Output Voltage VOL -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc I 18 1 6.7
High Threshold Voltage VOHA -1.100 -0.950 -0.845 Vdc
1 18 1 6.7
Low Threshold Voltage VOLA -1.635 -1.600 -1.525 Vdc
-1 1 1 18
1 6.7
·Test aUlnput-output combinatIOns eccordtng to Function Table.
··For threshold level test, apply threshold input level to only one input pin at a time.
MC10581 (continued)

ELECTRICAL CHARACTERISTICS (CONT'I

AC Switching CharaCleriSlies
~s"C· +25o C +l25°C·
Characteristic Symbol Input Output Conditions t Min MIl. Min Typ M.. Min MIl. Unit
Propagation Delay t++. t-- Bl PG SO,S3 1.B 7.6 2.0 6.0 7.5 1.6 7.6 ns
Rise Time, Fall Time t+, t- Bl PG 50,53 1.0 3.5 1.1 2.0 3.5 0.9 3.5 ns
Propagation Delay tt+, t-- Bl GG 53, C n 1.9 B.l 2.0 6.0 B.O 2.0 B.l ns
AiseT.rne Fall Tmle tt t- Bl GG S3,C n 1.3 5.0 1.5 3.0 5.0 1.3 5.0 n.
Propagation Delay f+-, t-+ Bl Cn +4 S3, C n 1.9 B.l 2.0 6.0 B.O 1.9 B.l ns
Rise Time, Fall TIrr'le tt, t- Bl C n ?4 S3,C n 0.9 3.0 1.0 2.0 3.0 0.9 3.0 ns
Propagation Delay It+, t+- M Fl - 2.B 10.3 3.0 6.5 10 2.B 10.2 ns
Rise TIlTle, Fall Time t+, t- M FI - 1.3 5.2 1.5 4.0 5.0 1.3 5.2 ns
Propagation Delay t+-, t-+ 51 Fl AI, Bl 2.7 10.2 3.0 6.5 10 2.6 10.2 ns
Rise Time, Fall Time f+, l- SI FI AI, Bl 1.3 5.2 1.5 3.0 5.0 1.3 5.2 ns
Propagation Delay t-+,lt- 51 PG A3, B3 1.9 B.l 2.0 6.0 8.0 1.8 8.1 ns
Rise Tmle, Fall Time f+, l- SI P~ A3 B3 1.0 5.1 1.1 3.0 5.0 1.0 5.1 ns
Propagation Delay t+-, t-+ 51 C n +4 A3,83 1.9 9.1 2.0 6.0 9.0 1.8 9.1 ns
Rise Time, Fall Time t+,l- 51 Cn+4 A3,83 1.0 5.1 1.1 3.0 5.0 1.0 5.1 n.
Propagation Delay f+-, t-+ 51 GG A3, B3 1.7 9.2 2.0 6.0 9.0 1.7 9.1 ns
Rise Time, Fall Time '+, l- SI GG A3,B3 0.8 6.2 0.8 3.0 6.0 0.8 6.2 ns
Propagation Delay 1++, t-- Cn C n +4 AO,A I ,A2,A3 1.0 5.1 1.1 3.1 5.0 0.9 5.1 ns
Rise Time, Fall Time t+.t- Cn C n +4 AO,A I ,A2,A3 0.9 3.1 1.0 2.0 3.0 0.3 3.1 ns
Propagation Oelay t++. t+- Cn Fl AO 1.9 7.1 2.0 4.5 7.0 2.0 7.1 ns

Rise Time, FaU Time

Propagation Oelay
t-+, t--
t+, t-
t++, H-
I
Al
I I- 1.9
1.3
2.9
7. I
5.2
10.1
2.0
1.5
3.0
4.5
3.0
6.5
7.0
5.0
10
2.0
1.3
2.8
7. I
5.2
10.2
I
Rise Time, Fall Time
Propagation Oelay
t-+, t--
t+, t-
t++, t--
I
Al
F(
-
50,53
2.9
1.3
10.1
5.2
3.0
1.5
6.5
3.0
10
5.0
2.8
1.3
10.2
5.2
6.5
T
PG 1.8 6.6 2.0 5.0 6.5 1.8 n.
Rise Time, Fall Time t+, t- Al PG 50,53 0.9 3.5 1.1 2.0 3,5 1.0 3.6 ns
Propagation Delay t++, t-- Al GG AO,A2,A3,C n 1.9 7.1 2.0 4,5 7.0 2.0 7.1 ns
Rise Time, Fall Time t+, t- Al GG AO,A2,A3,C n 1.3 5.2 1.5 4.0 5.0 1,3 5.2 ns
Propagation Delay t+-, t-+ Al Cn+4 AO,A2,A3,C n 2.0 7. I 2.0. 5.0 7.0 1.9 7. I ns
Rise Time, Fall Time t+, t- Al C n+4 AO,A2,A3,C n 0.9 3.0 1.0 2.0 3.0 0.9 3.1 ns
Propagation Delay t++, t-+ Bl Fl 53, C n 2.9 11.1 3.0 8.0 11 2.7 11.2 ns
Rise Time, F311 Time t+, t- Bl FI 53,C n 1.3 5.2 1.5 3.5 5.0 1.3 5.2 ns

tLogic high level (+1.11 Vdd applied to pins listed. All other
input pins are left floating or tied to +0.31 Vdc. -For L Suffix only.
VCCI = VCC2 = +2.0 Vdc, VEE = -3,2 Vdc

3·360
'MC10581 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS., 25"<:

VCCl - ""CC2 +20 \,Ide V oul

PROPAGATION DELAY

50

'------+0.31 V

TP,ro
'roput

Input Pul,e
t+ = t- =2 ! 0.2 ns
(20 to 80%)

50-ohm termination 10 ground locat.cj TP out

in lI..:h IeOp. chenne' input.
All input a"d output cabl" 10 the scope
ar. ~u.ll.ngths at 50-ohm c08",ial clbla
Wire length should be < 1/4 inch "om UnuHd outpuuconn..:ted to II 100 ohm
TP in to input pin and TP out to output
pin. V out itl2:1 attenuated. retl.tor to grou ... d.

3-361
 MECL 10,000 series
HIGH SPEED TRIPLE
LINE RECEIVER

MC10616

The MC10616 is • high speed triple different..

amplifier designed for use in sensing differential IignM.
over long lines. The base bias supply (Vaal il ...-
available to make the device useful as a Schmitt
POSITIVE lOGIC NEGATIVE lOGIC trigger. or in other appl ications where a stable
reference voltage is necessary.
ActivB currant sources provide the MC10616 with
(S)4~2 (6) (S)4~2 (6) excellent common mode noise rejection. If any ampli·
(9) 5 3 (7) (9) 5 3 (7) fier in a package is not used, one input of that amplifier
must be connected to Vas to prevent upsetting the
(13)9~6 (10) (13)9~6 (10) current source bias network.
(14)10 7 (11) (14)107 (11) Complementary outputs are provided to allow driv·
(16)12~14(2) (16)12~14 (2) ing twisted pair lines, to enable cascading of several
amplifiers in a chain, or simply to provide complement
(1)13 15(3) (1) 13 15 (3)
outputs of the input logic function.
L - 11 (15) L - l 1 (15)
Vaa Vaa

Numbers at end of terminals are pin numbers for L package (Case 620),
Numbers in parenthesis denotes pin numbers for F package (Case 650),

I Case I VCC1 I VCC2 I VEE I

I 620 I Pin 1 I Pin 16 I Pin B I PO'" 100 mW typ/pkg (No LOad)
tpd '" 1.8 ns typ (Single ended)
I 650 I Pin 5 I Pin 4 I Pin 12 I '" 1.5 ns typ (Differential)

CIRCUIT SCHEMATIC

(6) 2 (7) 3 7 (111 (10)6 14 (21 vcel 15 (3) VCC2

1 (5) 16 (4)

8 (12)
(g) 5 (S) 4 (13) 9 (14) 10 (1) 13 (16112
VEE

See General I nformation section for packaging.

3-362
 ELECTRICAL CHARACTERISTICS
Each lull temperatura range MECL·l0,OOO
_i •.circuit has been designed to meet the ...3:o
de specifications shown in the test table.
...~
-
attar thermal equilibrium has baan estab-
lished. The circuit is in a test socket or 0)
mounted on a printed circuit board and
transverse air flow greater than 500 linear ::=:tt=~ L SUFFIX
8::J
fpm is maintained. Outputs ara terminated
through a 101k>hm resistor to -2.0 volts. 9:=:tt=6
10 1
CERAMIC PACKAGE
CASE 620
~.
::J
T.t procedures are shown only for selact- 12~14 C
ed inputs and outputs. Other inputs and 13~'5 en
outputs are tested in a similar manner a.
~"
VBB

TEST VOLT AGE VALUES

IV....I
.T...
Tem,.rature VtHm •• VILmin V'HAmin ViLA ..... V. . VEE
-5II"c -0.880 ."1.820 -1.2&1i -1.510 F..." -5.2
.2&"c ~.780 -1._ -1.106 -1.475 Pi" ~
w .1Z5"c ~.830 -1.820 -1.000 -1.400 11 ~
W
en Pi"
Mel.1IL T . . L1_
TEST VOLTAGE APPLIED TO PINS BELOW,
w U_, -&Ii"c +25o C .1Z5"c IVecl
Ch ___ ristic T...
5¥mbol Min M.. Min Ty. M •• Min M •• Unit VIHm. . VILmin VIHAmin VILA ..... V. . VEE Ond •
Power Supply Or.in Current 'E 8 28 20 25 28 mAde 4.9.12 5.10.13 8 1.16
Input Current linH 4 195 115 115 ~Ade 4 9,12 - 5.10.13 8 1.16
'CBO 4 1.5 1.0 1.0 ~Ade 9.12 5.10.13 1,4 1.16
9 - 1.5 - - 1.0 -
1.0 ,!lAde - 4.12 - - 5.10.13 B.8 1.16
Hith Output Volt. . VOH 2 -LOBO ~.880 ~.930 - ~.780 ~.825 ~.630 Vdc 4 9,12 - - 5.10.13 8 1.16
3 -LOBO -0.880 ~.930 - ~.780 ~.625 ~.630 Vdc 9.12 4 - -- 5.10.13 8 1.16
Low Output Voltege VOL 2 -1.820 -1.8&1i -1.850 -1.620 -1.820 -1.545 Vdc 9.12 4 - - 5.10.13 I 1.16
3 -1.920 -1.8&1i -1.850 - -1.620 -1.820 -1.545 Vdc 4 9,12 - - 5.10.13 8 1.16
High Threshold Volt. VOHA 2 -1.100 - ~.950 - - ~.845 Vdc - 9.12 4 - 5.10.13 8 1.16
3 -1.100 - ~.850 - ~.845 - Vdc 9.12 - - 4 5.10.13 8 1.16
Low Threshold Voll. VOLA 2 - -1.835 - - -1.BOO - -1.526 Vdc - 9.12 4 5.10.13 8 1,16
3 - -1.835 - - -1.BOO - -1.525 Vdc 9,12 - 4 - 5.10.13 B 1.16
R.ferenc::eVoltage VIB 11 -1.440 -1.320 -1350 - -1230 -1.240 -1.120 Vdc - - - - 5.10.13 8 1.16
Switching Til'Ml -3.2 +2.0
ISCHhmLoodl Pul.ln Pul.Out Vdc Vdc
Propaptlon Oeley 14+2+ 2 - .- 1.0 1.8' 2.5 - n. - - 4 2 5.10.13 8 1.16
.... 2- 2 - - - - - - 2
'4+3- 3 - - - - - - 3

j •~ j
.... 3+ 3 - - - - - - 3
Ri.Time
120% to 80%)
F.IITime
120%'080%1
'2+
'3.
'2_
'3-
2
3
2
3
-
-
-
-
-
-
-
-
1.5 -
-
-
-
-
-
-
j -
-

-
-

-
-
j 2
3
2
3
j j j
D• ..., i, 1.5 n. when inputs .... driven diff.rentillUy
Delay i, 1.8 n. when inpuh •• driven lingle ended
 ELECTRICAL CHARACTERISTICS
Each full temperature range MECL 10.000 3:
series circuit has been designed to meet the (')
de specifications shown in the test table, ...A
o0)
after thermal equilibrium has been estab-
...
~
lished. The circuit is in a test socket or
mounted on a printed circuit board and 8~6 0)
transverse air flow greater than 500 linear 9-~7

~FSUFFIX 8:::l
fpm is maintained. Outputs are terminated 13~10
through a 1OQ..ohm resistor to -2.0 volts. 14~11
Test procedures are shown only for select- 16~2 ~.
CERAMIC PACKAGE :::l
ed inputs and outputs. Other inputs and 1-~-3
L ___ 15
CASE 650 c:
outputs are tested in a similar manner (1)
VBe Co

TEST VOL TAOE VALUES

.T...
IV....'
I
T....per..u,. VIHIll. . V'lillin V'HAIR. VILA . . . V. VEE
-SS"c F,om
~
~.811) -1.820 -1.2M -1.110
.aoc -1._ Pin
~
~.180 -1.IOS -1.4111
eN
W Me,GS,., T. . limits
.laoc ~.630 -1.820 -',- -'.400 15 -5.2

~ Pin
u...., -SS"c "25Q C .,aoc
TEST VOL TIIOE .... LIEO TO PINS BELOW,
IVCCI
Characteristic So- T... Min Mo. Min Typ M.. Min M.. Unit VIHm•• Vil min VIHA min VILAma V. VEE 0"'"
Power SupplV Drlin Current 'E 12 -
28 - 20 25 - 28 mAde. - 8. '3.'6 - - '.8.'4 ,2 4.1
Input Current linH a 195 lIS 115 ~Adc 8 '3.16 1.8.'4 '2 4.&
Icao a 1.5 1.0 1.0 ",Adc 13.16 '.8.'4 8.'2 4.&
13 - 1.5 - - 10 '.0 ",Adc - 8.'3 - - '.8.'4 '2.'3 4.5
Htgh Output Volt. . VOH 6 -1.0B0 ~.880 ~.930 - ~.180 ~.825 ~.630 Vdc 8 13.16 - - '.8.'4 t2 4.11
1 -1.0B0 ~.880 ~.930 ~.180 ~.825 ~.630 Vdc 13.'6 8 - -. '.8.'4 '2 4.11
low Output Voltage VOL 6 -1.920 -1.855 -1.850 -1.620 -1.820 -1.545 Vdc 13.16 8 - - '.8.'4 ,2 4.&
1 -1.920 -1.655 -1.850 -1.620 -1.820 -1.545 Vdc 8 13.16 - - '.8.'4 ,2 4.11
High Thrnhold Volt. VOHA 6 -1.100 - ~.850 - ~.845 Vdc 13.16 8 - 1.8.'4 12 4.1
1 -1.100 ~.950 - ~.845 - Vdc 13.16 - - 8 1.8.'4 12 4.11
low Threshold Voltage VOLA
,
6
-
-1.635
-1.635
.-
-
-1.600
-1.600
- -1.525
-1.525
Vdc
Vdc
-
13.'6
13.16
-
-
8 -
8 '.8.'4
19.'4
,2
12
4.11
4.1
Reference Volt. . Va8 15 -'.440 -1.320 -1.350 - -1.230 -1.240 -1.120 Vdc - - - - 1.8.'4 8 4.11
Switching Times -3.2 +2.0
~5O-ohm LoMI) Pul.ln Pul_Out Vde Vdc
Pr~ion Oelav te+6+ 6 - - 10 1.8' 2.5 - n. - 8 6 1.8.'4 ,2 4.6
ta~- 6 - - - - 6
lfI+1- 1 - - - 7
- + - - -

j j j j j j j
lfI-1+ 1 1
Ri.Time '6+ 6 - - 1.5 - - 6
- - -

~
(20% to 80%1 '1+ 1 -
1
Fell Time '6- 6 - - - - - 6
(20% to 80%1 '1_ 1 - - - - - 7
D.-y i, 1.6 "' wtwn input, •• driven d;tferenttlilly
D...., i, 1.8 ,.. when inpuh •• driven lint" ended
,- MC10616 (continued)
I

.....

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@ 25°C

veel : VCC2
+2.0 Vdc Vout V out

Coa ..

Input

Pulse Generator

Input pulse
t+ = t- = 1.5 ±. 0.2 ns
(20 to 80%)

-n
I
I
I
I
I I
Unused outputs connected to
One input from each gate must L_- -:, ~F a 100-ohm resistor to ground.
be tied to Ves during testing. I
JO.' ~F
V:E '" -3.2 Vdc

PROPAGATION DELAY

50-ohm termination to ground lo-

cated in each scope channel input.

All input and output cables to the

scope are equal lengths of 50-ohm
coax ial cable. Wire length should
be < 1/4 inch from TPln to input
pin and TP out to output pin. V out
Is 2:1 attenuated.

3-365
 HIGH SPEED DUAL TYPE D
MECL 10,000 series
MASTER-SLAVE
FLIP-FLOP

MC10631

The MC 10631 is a dual master-slave type D

flip-flop. Asynchronous inputs Set (S) and Aeset
R.s TRUTH TABLE
(A) override the Clock (CC) and Clock Enable
A
(eE) inputs. Each flip-flop may be clocked sep-
S On+1
L L arately by hold ing the common clock in the low
an
L H H state and using the enable inputs for the clack.ing
H L L function. If the common clock is to be u~ to
H H N.D. clock the flip-flop, the Clock Enable inputs must
N.D. '" Not Defined be in the low state. I n this case, the enai>le
inputs perform the function of controlling the
common clock.
CLOCKEO TRUTH TABLE The output states of the flip-flop change on
C 0 °n+1 the positive transition of the clock. A chailge
L <P an in the information present at the data (0) input
H L L will not affect the output information at any
H H H
other time due to master slave construction ..
4l :::: Don't Care Input pulldown resistors eliminate the nl!ed
C = CE + CC' to tie unused inputs to VEE. Output rise and fall
A clock H is a clock transition
times have been optimized to provide relaxatjon
from a low to a high state.
of system design and layout criteria.

CASE VCC1 VCC2 VEE

620 Pin 1 Pin 16 Pin 8
Po:::: 270 mW typ/pkg (No Load)
650 Pin 5 Pin 4 Pin 12 fTog = 225 MHz typ

POSITIVE LOGIC NEGATIVE LOGIC

SI (91 5 Al (91 5---------------,

01 (111 7 2 (61 01 (111 7 ---------"'''1 2 (6)

GEl (1016 CEI (101 6

3 (71 3 (71

Rl (814 51 (81 4
Cc (131 9 GC (131 9
R2 (1113 52 (1113

14(21 14 (21

GE2 (15111 CE2 (15111

02 (14110 15 (31 02 (14110 15 (31

S2 (16112 A2 (16112

Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650).

3-366
 51 ~

~
EL:t!CTRtCAl etfMlACTERISITCS
.. '",'

- ....
01 7 L SUFFIX
E·ach 10.11 temperature range MECL· m~ooo
2
CEAAMIC PACKAGE
eEl 6
"ierielcircuit has been designed .to meet the
de specifications shown in the ·test table, 3
CASE 620 o
after thermal equilibrium has been estab-
AI
~
....
lished. The circuit is in a test sock.et or Cc

"'''~-~
mounted on a printed cIrcuit board and (")
tr~nsverse air flow greater than 500 Imear
TEST VOLTAGE VALUES o
::J
'pm is maintained. Outputs are terminated 02 14 VdU.ll1 .-+
eT_
through a 100-ohm resistor to -2.0 volts. CE2 '1 ::J
I T.........-ure VIH mu: VILmin VIHAmin ViLA ..... VEE c:
Test procedures are shown for only one 0210- Q2 15 T" CD
-a"C -0.880 -1.920 -1.2&& -1.&10 -5.2
input, or for one set of input condition$.
S212 +25"C -0.780 -1.850 -1.105 -1.475 -5.2 ~
Other inputs are tested in the same manner.
+126"C -0.830 -1.820 -1.000 -1._ -5.2
" MC10831L T_ Limit.
Pin VOLTAGE APPLIED TO PINS LISTED BELOW,
U_ -61i"C +25"C +125"C tVee'
Chare;teristic 111'- T_ Min Mo. MI. T,p Mo. Min Max Unit VIH max VILmin VIHAmill VILA max VEE Ond
Power Supply Drlin Currlnt Ie 8 72 S2 65 - 72 mAdc - - - - 8 1.16
Inpul Current linH 4 - 100 - - 410 - 410 .Adc 4 - - - 8 1.16
5 - - - 410 - 410 5 - - -

! !
100

Input Leak. . Current linL

6
7
9
4,5,·
-
-
-
0.5
375
375
495
- 0.5
-
-
-
-
-
-
-
220
220
290
-
-
-
-
0.3
220
220
290
-
!
"Adc
6
7
9
-
-
-
-
-
-
-
-
-
-
-
- 8 1.16
6.7.9' 0.5 - 0.5 - - 0.3 - ",Adc - - - 8 1.16
Lottc .. , .. VOH 2 -1.(110 -0.880 -0.930 -0." -0.825 -OAl3O Vdc 5 - 8 1.16
eN Output Volt. . 21 -1.(110 -0.880 -0.930 - -0.780 -0.825 -0.830 Vii< 7 - - - 8 1.16
W Logte: "0" VOL 3 -1.920 -1.865 -1.850 - -1.620 -1.920 -1.545 Vii< 5 - 8 1.16
Cl
-..J
Output Volt. . 31 -1.920 -1.665 -1.850 - -1.620 -1.820 -1.545 Vdc 7 - - - 8 1.16
Logic .. , .. VOHA 2 -1.100 - -0.950 - - -0.845 - Vdc - - 5 8 1.16
Threshold Vol" 2t -1.100 - -0.950 - - -0.845 - Vdc - - 7 9 8 1.16
Logic "0"
Threshold Vol"
VOLA 3
31
-
-
-1.636
-1.635 -
- -
-
-1.600
-1.600
-
-
-1.525
-1.525
Vii<
Vii<
-
-
-
-
S
7
-9 8
8
1.16
1.16
Pul. Pu'.
Switching TimesC'OO-ohm lo.dl +1.11 Vde +O.31Vde I. Out -3.2Vde +2.0Vde
Clock '''put
PrCJp9tton DeIlY t9+2- 2 - - 1.5 2.0 3.3 - - ns - - 9 2 8 1.16

~
- - - - -

~
1.5 3.3

! ~ !
'&+2+ 2.0 7 6
Ri. Time (20 to 80%) '2+ - - 1.0 1.3 3.1 - - 7 - 9
F.. , Time (20 to ..... '2_ - - 1.0 1.3 3.1 - - - - 9
Set Input
PrOpegition Delay t5+2+ 2 - - 1.1 2.0 3.3 - - ns - - 5 2 8 1.16
t12+15+ 15
3
-
-
-
-
-
-
-
-
-- -
-
12
6
15
3
t5+3-
- -
•
-
14 -
+ - 12 14
+
• •
-

•
112+14-
R. . . lnput
Prop-e.tion DeIlY 14+2- 2 - - 1.1 2.0 3.3 - - ns - - 4 2 8 1.16
'13+15- 16
3
-
-
-
-
-
-
-
-
-- -
-
13
4
15
3
'4+3+
- +- - -
+ - + +
• +
t13+14+ 14 - - 13 14
!ietupTime "'NO 7 1.0 0.75 ns 6.7 2 8 1.16
Ho'dTime

.
T~ FreQUency (MII_,
"'old
'Tog 2
7
200 -
0.76
200
-0.5
225
-
- 200 -
ns
MHz .. 6.7
6
2
2
8
8
1,16
1.16
Individu8lly t . . -=h input; ~y VIL min to pin under t ....
"Pin 3 il tied to pin 7 for theII l.-.s.
, - : 1
f Output ,..... to be ~RId after I clock pul_ has bean ~Iied to lhe CE input (pin 6!....J
n-
L
VIH mix
VILmin
 51 9----~
ELECTRICAL CHARACTERISITCS 3:

~
0111 8 (")
Each full temperature range MECL tO,ooo ~
eEl 10
.i.circuit h. been designed to meet the
de: specifications shown in the test table,
FSUFFIX
CERAMIC PACKAGE
o
atter thermal kluilibrium hal been estab·
Rl 8~
CASE 6&0 fl
~
lished. The circuit il in a test socket or Cc 13
mountea on a pnntea Circuit ooarCl and
tranlYene air' flow greater than 500 I inesr
fpm is maintained. Outputs are terminated "'.~ Q2 2
YESI' VOLTAGE V"'LUES

Vdc:tft
I
8::J
!:!.
through a tOO-ohm resistor to -2.0 volts. CE21& .T. . ::J
Test procedures are shown for only one 0214 Q2 3 T_. yIH ...• VIL- VlltA- VILA- V.E c:
<D
-1iI"I: -1.9:20 -1.255 -1.1110 -1.2
input, or for one set of input conditions.
5216 ~.- S:
Other in puts are tested in the same manner. +21o C ~.780 -1._ -1.105 -1.476 -5.2
+126"1: ~.930 -1.820 -1.000 -1.400 -1.2

-
Mel0931F T. . Limit.
PIn VOLTAGE· ...PPLIED TD _ LIITID BILOW
lind.- -SoC +2I"c +126"1: CVCCI
C.........ic !Iv_I T. . Min Mox Min Typ Mox Min Unit ViM .... VIL min VIHA- VILA_ Vu O.
Po.,. Suppty Orem Current IE 12 - 82 - 45 86 -82 mAd. - - - - 12 4.&
Input Current IlnH 8
9 -
700
700 - -
410
410 -
410
410
.... de 8
9 -
-- -- 12 4.&
10
II
13
-
-
-
375
375
49&
-
-
-
-
-
-
2:20
2:20
290 -
-
2:20
-
2:20
290
l 10
11
13
-
-
-
-
-
-
-
-
- 1 l
Input LMUga Current linL 8.9"
10,11,13-
0.5
0.5
-
-
0.5
0.6
-
-
-
-
0.3
0.3
-
-
pAd.
lOAd.
-
-
"
"
-
-
-- 12
12 :~
w Logic "I"
Output Voltege
VOH 8 -1.080
~.- -0.930 - ~.780
-
-0.825 ~.930 Vde 9 -
-
-
-
-- 12 4.&
W 81 -1.080
~.- -0.930 ~.780 -0.826 ~.83O Vde 11 12 4.1i
en Logic ''0'' VOL 7 -1.920 -1.86& -1._ -
-1.820 -1.820 -1.646 Vde 9 - - - 12 4.&
(XI Outpu,Vo_ 71 -1.9:20 -1.856 -1._ -
-1.620 -1.820 -1.646 Vde 11 - - - 12 4.&
Logic "I" VOHA 8 -1.100 - -0.950 - - -0.845 - Vde - - 9 - 12 4.&
ThrOllloIdVol_ 6t -1.100 - -O.9liO - -
-0.846 - Vde - - 11 13 12 ~
Logic ''0'' VOLA 7 - -1.935 - -
-1.600 - -1.525 Vd. - - 9 - 12 4.&
Throthold Vo_ 71 - -1.935 - - -1.600 -
-1.526 Vd. - - 11 13 12 4:a
Pu_ Pul.
+1.11 Vdc +0.31 Vd. In In -3.2 VIII +2.DVde
Switching TirNt UOO-Ohm Ioed) 6 - - 1.5 2.0 3.3 - - n. 13 a

rr
'13+8-
Clock Input 6 - - - - 11 -

l l l
'13_ 13
Pro.-gltion DeIly '10+8+ 8 - - - - 11 - 10
'10+6- 6 - - - - - - 10
- - - - - -
Ri. Time (28 .. 111*)
Fell Timl (20 10 ~J
'8+
'6-
6
6 - -
1.0
1.0
1.3
1.3
3.1
3.1 - - J - -
13
13 J
Sot Input
Pro ....tion Delay '9_ 8 - -
-
1.1 2.0 3.0 - - n. - - 9 8 12 4.&
- - - - -
~
3

l l
t18+3+ 16

~
3
'9+7_
'18+2-
7
2
-
-
-
-
-
-
-
-
-
-
-
-
9
16
7
2 ~ ~
R_lnput
Pro~ion O-.y '9+6- 8 - - 1.1 2.0 3.3 - - n. - - 8 8 12 4.&
- - - - - -
~ l i-
t1+3- 3 1 3

htupTime
tB+7+
t1+2+
,,,uP
7
2
11
-
-
-
-
-
- 1.0 0.75
-
-
-
-
-
-
~
n.
-
-
-
-
-
-
8
1
10,11
7
2
8
!
12
~
4.&
HoldTlmo 'hold 11 0.76 ~.5 n. 10,11 8 12 4.&
T.... Freq--V IMoxI 'T",
"Ind_1y , . _Input; ....... VIL minto pin u~_.
• - - 200 250 - - - MH. "" - 10
• 12 4.& i

··Plft7 IItWto PIn 11 forte-t... .. n-yIH ....

1 0 _ . _ to ... _ a d _ . _ puI. . . . _ oppIled to ,ho CE Input !pin 10l...J L
VILmin
MC10631 (continued)

FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT

V out

Co.x

t+ = t-= ~1.0ns
(20% to 80%) 50

Clock Input (O+--~I-------ll!E 01------'

o----ic
SQ...ohm termination to ground lo-
cated in each lCope channel input.
All input and outPut cable. to the
lCope .re equal length, of 50-ohm
co •• ial cable. Wire length should 100
be <1/4 inch from TPin to input
pin and TP out to output pin. V out
is 2: 1 attenuated.

FIGURE 2 - SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC

veCl = VCC2 =
+2.0 Vdc V out

Coax

PW - ~2 0 n.
PRF=I,OMH. 50
iTPout
Clock Input IOt---j~-o
Input Pulse
t+ = t- = 1.5 ± 0.2 ns
(20 '0 80%)
50-ohm termination to ground lo-
cated in each scope channel input. l: O.II'F
All input and output cilbles to the
scope ar. equal lengths of 50-ohm
coaxial cable. Wire length should VEE = -3.2 Vdc
be <1/4 inch from TP in to input
pin and TP out to outJ)ut pin. V out
is 2: 1 attenuated.
e ,r5-0 -""---,.------+1.11 V

A Input
_ _ _ _"1 '-----+0,31 V
thold
+0.31 V
+1.11 V o
Sinput - - - . . J ]

Q __ ----.J/
a Output - - - - / - "

a Output '5-3-
50""
i NOTE,
tsetup is the minimum time before the positive
transition of the clock pulse (e) that information mu.t
be pre..nt at the data input (D).

'3_ thold is the minimum time after the positive tran-

sition of the clock pul .. (e) that information mUlt
remain unchanged at the data input (0).

3-369
 64-BIT RANDOM MECL 10,000 series
ACCESS MEMORY

MCM10140
MCM10142
MCM10148

64-BIT RANDOM ACCESS MEMORY

The MCM10140, MCM10142 and MCM10148 are 64·Bit
Random Access Memories (RAMs)·. They offer very high speed,
full binary decoding, two chip enable inputs for easy memory
expansion, and separate data input and data output pins.
Organization of these memories is 64 one· bit words and
they are packaged in standard l6-pin herm8tic dual in·line
packages.
MCM10142and MCM1014810gic levels are fully compatible
with the MECL 10,000 logic family and are specified for L SUFFIX
driving a 50 ohm load. The MCM10140 logic levels are com· CERAMIC PACKAGE
CASE 620
patible with the MECL 10,000 logic family except they are
specified for driving a 90 ohm load.

BLOCK DIAGRAM PIN ASSIGNMENT

Addr••• lnputl

AO A1 A2 A3 A4 A5

VCC1 16
2 AO 15
3 A1 14
4 13

5 iN 12

6 A2 11
The Chip is enabled
when CE 1 and CE2 A3 A4 10
inputs are at positive
Column 8 A5 9
logic "0". VEE
Select
Gates
16)( 4
Array

CE1 Chip
Enable
CE2 Buffer
TRUTH TABLE
MODE INPUT OUTPUT
CE WE Din °out
Data Out
Write "0" L L L L
Write "1" L L H L
Read L H 'I> Q

Data In C > - - - - - - - - - - j Disabled H 'I> 'I> L

and
Writ. C > - - - - - - - - - - j Data I nput Buffer ~ = Don't Care.

3-370
 ELECTRICAL CHARACTERISTics 3:
n
Each MECL 10,000 series circuit has been
designed to meet the de specifications ...
3:
shown in the test table, after thermal
equilibrium has been established. The cir·
cuit is in a test socket or mounted on a CE1
~CE2 ...
o
.;..
printed circui.t board and transverse air flow 3 AO o
-..
greater than 500 linear 'pm is maintained. ~A1
Outputs are tenn inated through. So-ohm A2 3:
resistor to -2.0 volts. Test procedures are
115 n
~A3 ...s:
D out
shown for only selected inputs and outputs.
10 A4
Other inputs and outputs tested in the
same manner. 13
A5
Din ...
o
WE
12
TEST VOL TAGE VALUES it
@Test
(Volts)
n-O
Tamperature VIHmax VILmin VIHAmin VILAmax VEE ::J
~,
_30 oe -0.890 -1.890 -1.205 -1.500 -5.2 ::J
+2S"c -0.810 -1.850 -1.105 -1.475 -5.2 ~
+SSoC -0.700 -1.825 -1.035 -1.440 -5.2 Q.
MCM10140, MCM10142, MCM10148 Test Limi"
Pin.J
Characteristtc
Und.r
Test Min
-30G C
,- Ma.
1
Min I
+2SOC
Typ Max Min
+8S0C
Max Unit
I
VOLTAGE APPLIEO TO PINS LISTED BELOW,

VIHm•• ! VILmin !VIHAmin!V,LAmu ! VEE

IIVCCI
Gnd
r 1 - ..1
W
W r Power Supply Drain Current 'E 8
6
-
1 - ..1 80 100
265
mAdc 8 16

•
",Adc
..... Inpu. Cunen' linH

linL
4
6 - - 0.5
50
6

6
t 16
..1
Logic "1" Output Voltage VOH 15 -1.060 . -0.890 -0.960 -0.810 -0.890 -0.700 Vdc 14 I - I - - 8 1,16
Logic "0" Output Voltage VOL 15 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 14
.1 - .1 - - 8 1,16
Logic "'" Threshold Voltage VOHA 15 -1.090 - -1.980 -0.910 Vdc 3,14 - 8 1,16
Logic "0" Threshold Voltage VOLA 15 - -1.655 -1.630 -1.595 Vdc 3,14 8 1,16
SWitching Times Pul. In Pulse Out -3,2 V +2,0 V
Access Times tCE-D+ 15 12 4 15 8 1,16
Chip Enable tCe+D- 15 12 4 '5
Address Inputs tA+D+ 15 10",15"" 2 15
tA+D- 15 10",15"" 15
tA_D+ 15 10" ,15"" 15
tA-D- 15 10" ,15"" 15
Write Pulse Width 'WWE 12 10 13 12
Chip Enable Pulse Width 'WICEI 13 13
Write Strobe Mode Times Setup
Data tsetup(OtW-) 12 0 12
Chip Enable tsetup(CE-W-) 12 4 12
Address tsetup(AtW-) 12 4 12
Hold
Data thold(W+D±1 15 12 15
Chip Enable tholdIW+CE+) 4 o 12
Address tholdIW+A:t) 12

"MCM10142
""MCM10140, MCM10148
MCM10140/MCM10148 (continued)

CHIP ENABLE ACCESS TIME

Dout

ADDRESS ACCESS TIME

Address

D out

WRITE STROBE MODE

Address

th01d(W+O±1

14---. . thold(W+CE+)
thold(W+A±)~

°aut

3-372
 SWITCHING TIME TEST CIRCUIT., 25°C

r"
:

VCCI = VCC2= +2.0Vdc V out

,- d!
Coax 25 "F 01 "F Coe",

r...
- -- -- "I
I I
I I
I
I
I
41 51 I
I 2 CEI CE2

Input I 3
AO
AI
I
6
7
A2
15
I
A3 D out
Pu I. Generator 9 A4
I 10
A5
I
I 13
Input Pulse
Din
WE
I
t+ = t- ., 2.0 ± 0.2 I 112 I
120% to 80%)
I
I
I I
I I
L
-Q~
I 01"F

- 3 :Vdc

50-ohm termination to ground lo-

cated in each scope channel input.
All input and output cables to the
scope ar. equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.

3-373
 MECL 10,000 series
8 x 2 MULTIPORT REGISTER
FILE (RAM)

MCM10143

8 x 2 MULTlPORT REGISTER FILE

(RAM)
The MC10143 isan 8 word by 2 bit multi port register file (RAM)
capable of reading two locations and writing one location simulta-
neously. Two sets of eight latches are used for data storage in this L SUFFIX
CERAMIC PACKAGE
LSI circuit.
CASE 623

WRITE
The word to be written is selected by addresses AO-A2. Each bit
of the word has a separate write enable to allow more flexibility in
system design. A write occurs on the positive transition of the clock.
Data is enabled by having the write enables at a low level when the
clock makes the transition. To inhibit a bit from being written, the
bit enable must be at a high level when the clock goes low and not
change until the clock goes high. Operation of the clock and the bit
enables can be reversed. While the clock is Iowa positive transition of
the bit enable will write that bit into the address selected by AO-A2.

PIN ASSIGNMENT
READ
When the clock is high any two words may be read out simulta·
neously, as selected by addresses BO-B2 and Co-C2, including the
word written during the preceding half clock cycle. When the clock
goes low the addressed data is stored in the slaves. Level changes on
the read address lines have no effect on the output until the clock
3
again goes high. Read out is accomplished at any time by enabling
output gates (Bo-B,), (CO-C,). 4 21

5 20

6 19

18
tpd: 8 17
Clock to Data out = 5 ns (typ) 9 16
(Read Selected)
10 15
Address to Data out = 10 ns (typ)
(Clock High) 11 1.
Read Enable to Data out = 2.8 ns (typ) 12 13
(Clock high, Addresses present)
Po = 610 mW/pkg (typ no load)
Vcco" Pin 1
Vee1 = Pin 23
Vee - Pin 24
VEE = Pin 12

See General Information taetion for packaging.

3-374
MCM 10143 (conti nued)

BLOCK DIAGRAM

4
REB

6
OB1
BO
B1
5
B2

aBo

9
WEo
DO 10
19
Clock
AO 14
A1 15
A2 13

WE1 8
11
01

OC1

Co 17
C1 16
18
C2
OCo

20
REC

3-375
 MCM1 0143 (continued)

ELECTRICAL CHARACTERISTICS 80 REB

Each MECL 10,000 series circuit has been B,
OB,
designed to meet the de specifications B2
shown in the test table. after thermal WEo
equilibrium has been established. The cir- '0 DO 080
3
cuit board and transverse air flow greater Address AO Data
Line, '5 Output
than 500 linear fpm is maintained. Out- 13
A,
Lines
puts are terminated through a 5O-ohm A2 22
OC,
resistor to -2.0 volts. Test procedures are
shown only for selected inputs and out-
puts. Other inputs and outputs are tested TEST VOLTAGE VALUES
!Vohsl
in a similar manner.
Test
@I f-----.-,
Temperllur. VIHmu VILmin VIHArmn VILA",.. VEE'
_lOGe -0890 -1.890 -1.205 -1.500 -5.2
+25o c -0810 -1.850 -1105 -1.475 -5.2
+85o C ...(l700 -1.825 -1035 -1.440 -5.2
MCM10143L Test Limits TEST VOLTAGE APPLIED TO
Pin

(:=
PINS LISTED BELOW:

Symbol
I,
Undo<
T.., M~
-lOoe
.... M"
+25°e
Ty. M. . Min
+85oe
M.. Unit '"'V""I-H-_-.""""'Vo-"'L-m-'n""""'Vo-",H-""'-'n"V'""'L......
--.-.-V"".-.--f
Power Supply Dram Currenl 12
". '47 mAdc 4.5,6,7,8,
9,13,14,
15,16,17,
12 1,23,=

18.19,20
Input Current 200 /lAde: 12 1.21;

,.'..,.
13 13
14
'5 ,...,,.
'4
15

20 20

lin L
,."
10

0.5
245
245
245
/-lAde
,."
10

12 1.:n:':
LogiC .. ,., Outpul Vollage VOH -1.060 -0890 -0960 -0.Bl0 -0.890 -0.700 Vd, 10,11 CD 12 1.»;

t• t t
• ++ •+
21
22 + + + +
•.:
Log'c "0" Output Voltage VOL -1890 -1675 -1850 -1.650 -1815 -1.615 Vd, 4,20G) 12 ,,no

t
J

+ + +
• •+ +
21
22
LogiC .. ,,, Threst10ld Voltage VOHA -1080 -0.980 -0.910 Vd, llG) 4 12 '.23.:

t + 4

t
• + 10

• +
21 10 20
22
Log'c "0" Tl'1reshold Voltage VOLA -1.655 -1.630 -, 595 Vd, "llG) 20
'2 '.m
t +
t + ..,1
4.

SWltch.ng Tun., @
AccessT'me
Address Input tB-OS_
21
22

'0
• •
10

" Fiture
20
20
Put. In Pul.Out

5
-3.2 V

'2
.
'.23.1
tS+08+ 10 5
Read Enable t/rE_Q8+ i. 4
Data
Selup
Address
Hold
tClock+QB_

'setup(B-Clock-1
,. 5.0

5.5
19

,.
Address 'l'1old(Clock-B+1 -4.5 19
WriteTirne@
Setup
,.,. ,.
,.,.
Wnte Enable Iselup(WE-Clock~) 20 '9
'setup(WE+C10Ck-1 20
Address 'setup(A-Clock+) 30 14 19
Da~a tsetupID-Clock+) 2.0 10 19
Hold
Wrote Enable thotd(Clock+~+1
IholdICtock+M-1
-2.0
-20
,.
19
19
,.
,.
Address tl'1old(Clock+A+) -3.0
Data tholdtClock+O+1 10 ~2.6 '9 '0
Write Pul. Width
RIM Tune
""'WE
2
5.0
2.0
• '9
2
(20% to 80%1
fill T"", 20
120% 10 80"'{')

• Lim" appl'es for all 'nputs, indiVidually apply VI Lmm 10 pin under les!
CD Datil has to be clocked In. ---, r- -0810 V
@ AC liming f'9Ure$ do nOt show all tl'1e necessary pre· seiling cond,tlons L-....J -1.85 V

3-376
MCM10143(continued)

SWITCHING TIME TEST CIRCUIT. 25°C

Vcc ~ VCCO = VCCI = +2.0 Vdc

Coax ±O.I~F Coax

,----- -----,
I
I ,

: BO REB
{
O-----;Ic--i Bl DB 1
0---'---1 B2
0----'-1--1 WEO
1
• 0-----;1,----1 00
1------;---<>

'®-~ H~====~:===~ ::
OBO

0---
Pulse Generator « o--~Ic--i WE 1
OCI 1----;---<>
0---71I -...,0 1

~~ _ c~~c: 1-----;---<>
Input Pulse
t+ "" t- : 2.0 ± 0.2 ".
(20% to BO%) {o----+: 1
--I
C 2 REC
PRR "" 1 MHz
PW ;:;:'20 n. 0-----+,_---'I I

50-ohm termination to ground lo-

cated in each scope channel input.
All input and output cables to the
scope ar. aqual lengths of 50-ohm
Unused output. connected to a 50-ohm resistor
to ground.
coaxial cable_ Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.

3·377
MCM10143(continued)

READ TIMING DIAGRAMS

FIGURE 1

Enable
RE

t~'''.Q'-
FIGURE 2

a ·,,~·t ~
FIGURE 3

Setup .nd Hold

t/~-----------d~'
FIGURE 4
_________1 _ _ ,_. _ _ _ _ _ _ _
B
Clock ~
'.,up . ~-'-ho-l-d---r-----------

WRITE TIMING DIAGRAMS

Enable
WE FIGURE 5

Clock r~·"'=r·M·1
F~·'l F'""4==
Diloble FIGURE 6
WE

Clock

PuiloWidth
WE FIGURE 7

Clock
'»'hOld

Ad....
A FIGURES

Clock _____________________'1

3-378
 MECL 10,000 series
256 BIT RANDOM
ACCESS MEMORY

MCM10144

256 X 1 BIT RANDOM ACCESS MEMOR Y

The MCM10144 is a fully decoded 256-bit Random Access
Read/Write Memory organized as 256 one bit words. Stored data is
.Iected by means of an eight bit address, consisting of inputs AO
through A7.
The MCM10144 has three active· low chip enable inputs for CERAMIC PACKAGE
increased logic flexibility permitting memory expansion up to 2048 CASE 620

words without additional decoding. For larger memories, the upper

address words are selected by using one of the cr inputs for
enabling 1024 word segments.
The MCM10144 operating mode (all ~ inputs low) is con-
trolled by the W£ input. With W£ low, the chip is in the WRITE
mode, the output, Dout, is tow and the data state present at the data
input (pin 13) is stored at the selected address. With the ~ high
the chip is in the READ mode and the data state at the selected
memory location will be presented, noninverted at the data output
(pin 15).
Open emitter outputs permit full wire-ORing to data buses, with
1-· .Q low when the chip is disabled.
The device is fully compatible with the MECL 10,000 logic MCM10144AL
CERAMIC PACKAGE
family. It is designed for use in high speed scratch pad, control, CASE 690
cache, and buffer storage applications.

BLOCK DIAGRAM
PIN ASSIGNMENT

AO VCC 16

2 Al Dout 15

3 A2 WE 14

4 A3 Din 13

5 CEI A7 12

6 CE2 11
AO -;:
: CE3 A5 10
2 ';. i
A1 III", "':::,
~
14
WE 8 VEE A4 9
n" 0 «III
.
3
A2
-DO 8=
A3
4
"'N
«l:! "~';; Din
9
"'-
is
0 13

A4 ~
TRUTH TABLE

MODE INPUT OUTPUT

CE WE Din Dout
Writ. "0" L L L L
A5 A6 A7
Write "1" L L H L
R..d L H t/J Q

Disabled H t/J t/J L

tP - Don't Car•.

3-379
 ElECTR ICAl CHARACTER ISTICS
Each MECL 10,000 series circuit has been
3i:
(")
designed to meet the de specifications
shown in the test table, after thermal eQui-
...c3i:
librium has been established. The circuit
is in a test Socket or mounted on a printed
circuit board and transverse air flow great-
...
t
A,
er than 500 linear fpm is maintained. A,
Outputs are terminated through a 5O~hm
resistor to -2.0 volts. Test procedures are
AJ
A4
n-
O

~T
shown for selected inputs; other inputs
11 A6 Dout
I,. ....
::J
are tested in the same manner. 12 A7 :;'
c:
CI>
~

13 Din TEST VOLTAGE VALUES

We IVott.,
1'4 l'T ...
remp ••tur. VIHINJI: VILmin VIHAmin I VILAmiX 1 VEE
_lOGe -0.890 -1.890 -1205 -1.500 I -5.2
+2SoC -0.810 -1.850 -1.105 -1.475 ·1 -5.2
+8SoC -0.700 -1.825 -1.035 1 -1.440 I -5.2
MCM10144 Test Limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW:
Under
_lODe +25o c +8SoC Vee
Charecteristic Symbol T... Min M.. Min TV. M.. Min M•• Unit V1H""x VILMin VIHAmin VILA ... x VEE Gnd

W I Power SupplV Drain Current Ie 80 100 mAde 16

W I,npu, Cunen' 'in H 5 265 IJAde 5 16
00
I I
1 50 1
0 12 50 12
14 50 14
IlnL 05 IJAde 16
Logic "1" VOH 15 -1.060 -0.890 -0.960 -0.810 -~.890 -0.700 Vdc 13,14 1,2,3,4,5,6, 16
Output Voltage 7,9,10,11,1"2
Logic "0" VOL 15 -1.890 -1.675 -1.850 -1.650 -1.825 -1.615 Vdc 1,2,3.4.5,6,7, 16
Output Voltage " 9.10,l1,1:l,13
Logic "1" VOHA 15 -1.0BO -0.980 -0.910 Vdc 13,14 1,2,3,4,5,6, 5,6,7 16
Threshold Voltage 7,9,10,11,12
Logic "0" VqLA 15 -1.655 -1.630 -1.595 Vdc· 13·,14 1,2,3,4,5,6, 5,6,7 16
Threshold Voltage 7,9,10,",12
Switching Times Pulse In Pul .. Out
Access Times
Chip Enable tCE_D out + 15 10 ns 6,7 15 16
t~+Dout- 10 I 5
Address Inputs tA±Dout + 18 30
tA±Dout - 18 30
Write Strobe Mode Times
Setup
Data tsetuplO±W- 15 2.0 13,14
Chip Enable tsetup(~-W-) 2.0 5,14
Address tsetup(A!VJ:) 10 1,14
Hold
Data thold(W+D±) 2.0 13,14
Chip Enable thold(W+~+1 2.0 7,14
Address tholdlW+A±1 0 1,14
Recovery Aher Writ" Time tW+Dout + 17 14
tW-Do ... t- 17 14
Wri~ Ptli. Width tw(WE) 12 30 14
MCM10144 (continued)

SWITCHING TIME TEST CIRCUIT. 250 C

Vee"" +2.0 Vdc

V out

Coax
,,~rtt"~
,- - - ---.----,
..-
eoa.

I I
I I
I 51 sl 7
I
I
I 1 CEI CE2 CE3
I 2
AO
Al
I
I 3 I
A2
Input
I
4
A3 I
9 I
A4
I 10

Pulse Generator I 11
A5
15 I
AS Dout
I 12
A7
I
I I
Input pulse
I
t+ = t - '" 2.0 ±. 0.2 ns I I
(20 to 80%)
J I
I 13
Din WE
I
I I
IL _ _ _ _ 114
I

-fl ~,~,
1-3~vdc

50-ohm tarmin,tion to ground lo-

cated in e.ch scope channel input.

ICOpe .r.
All input end output cables to the
equel lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin end TP out to output pin.

3-381
MCM 10144 (continued)

CHIP ENABLE ACCESS TIME

Dout

ADDRESS ACCESS TIME

Addrell

Dout

WRITE STROBE MOOE

Addr....

'hold(W+O±l1

\4---.....+'hold(W+CE+)
'hOld(W+A±)-..l

Oaut

3-382
 64-BIT REGISTER FILE MECL 10,000 series
(RAMI

MCM10145

64-BIT REGISTER FILE

(RAMI

The MC10145 is a 64-Bit RAM organized as a 16x4 array. This

organization and the high speed make the MC10145 particularly use-
ful in register file or small scratch pad applications. Fully decoded
inputs, together with a chip enable, provide expansion of memory
capacity. The Write Enable input, when low, allows data to be
entered; when high, disables the data inputs. The Chip Enable input
when low, allows full functional operation of the device; when high,
all outputs go to a low logic state. The Chip Enable, together with
open emitter outputs allow full wire-OR ing and data bussing capa-
bility. On-chip input pulldown resistors allow unused inputs to
remain open. L SUFFIX
CERAMIC PACKAGE
CASE 620

BLOCK DIAGRAM PIN ASSIGNMENT

Chip Enable

CE
AO_{
Lines
AO
AI
A2
00

01
2
16
15

A3 Data 3 14
Output
4 13

"_,",o.{
DO Lines
02 5 12
Dl
Lines D2 6 11
D3 _ 0 3 10
WE
8 9

Write Enable

TRUTH TABLE
VCC = Gnd
VEE - -5.2 Vdc MODE INPUT OUTPUT
CE WE D a
Writ. "0" L L L L
Writ. "1" L L H L
Po"" 625 mW tvp!pkg (No Load)
tAeces. = 10 ns tvp (Addre. Inputs) R.ed L H o
Disabled H L
4J - Don't Care.

See General Information section for packaging.

3-383
 MCM10145 (continued)

ElECTRICAL CHARACTERISTICS Chip Enable - - - - - ,

3
Each MECL 10,000 series circuit has been
designed to meet the de specifications shown
10 Ce QO
AO
in the test table, after thermal equilibrium 9
A1
has been established. The circuit is in a Addre .. {
Lines A2
test socket or mounted on a printed cirCUit
6 Q1
board and transverse air flow greater than A3 Data
5 Output
500 linear fpm is maintained. Outputs are
DO 15 Lines
terminated through a 50-ohm resistor to 4 Q2
-2.0 volts. 08t8ln ut'{
Lines
p 11
01
02
12 14
03 _ Q 3
WE
13
Write Enable - - - -..... nST VOLTAGE VALUES
(Yohs)
"Tao
T.n""'I1'" VIHmK VILmin YIHAnlln VILA"". V ••
-lOoe -<1.8'0 -, 890 -1.205 -1.500 -52
+25o C -0.810 -1850 -1.105 -5.2
...·c -0.700 -1.825 -1.035 -1440 -52

--- ... -..

MCM10146l T . . Llml..

a..-.... ..m...
~n
...-
T_
-"'C +25o C
Tv. .... Mn ....
TEST VOLTAGE APftLIEO TO PINS USTED BELOW

Power Supptv O,.,n Current

InputCurrllOt '.
I,n H
• 'SO
200
220
220
~Adc 3
4
5
200 6
200 7

'0
200
200 •
'0
"
12
'3
220
220
.70
"'3
12

lin l 0_5 .Ad,

-1.060 -0.890 -0.....
,~,
LogIC "," VOH -0.810 -0.890 -0.700 Vdo

I I
OutputVoltaga

logic "0"
I
-U90
I I
-1.825
I
-1,615 "
I
VOL ~1.675 ~1.850 ~1.650 IIde

I I
Output Vollage

,
'5 I I I I I
LogIe "',. -1.080 -0_ -0.910 Vd, a>
Thrll'Shold Voltage
VOHA
,.
2
~ I I I I
5
12

Logie "0" ,
'5
~1.655 ~1.630 -1.595 Vd, <2l "
VOLA
,.
2

'5 I I I "
5

SlJritchi",n. . . ~ +1.11.11 PUI.ln PUI.Out ~3.2V

Atasl Times
Ch,pEnlble ICE...Q+
r--- ())
7.0
tCE+Q- 7.0
Addr. . ,nP\lIl

WrIte Strobe Mode T,,""

Setup
lA+Q+
lA...Q+
lA+Q+
lA-Q_
1,2,14.15

l
10,0

! ! 6,1,9.10 1,2,14,15

l
,
Do,.
ChIP Eneble
t~tuplO'WI
tMtupIC""!·W 2
0
3.5
5,13
3.13 ,
Add,.., lyluPIA.W 1,2,14.15 3.5 8,1,9,10,13 1,2.14,15
Hold
0 ... tholdlW·OI 2 3.0 5,13 ,
Reeo_y Ah., Wnt. Time
....,"'
ChIP EnMJI. 'hold IW.e-E1
tholdlW'·AI
tW+Q+
2
1,2.14,15
2
3.0
3.'
7.5
3,13
6,1.9,10,13
'3
2
1,2.14,15

tW+Q_ 7.5 '3

Wnte Pulse Width PWw 7_5 '3
Chip Enable

--
Strobe Mode Timll'l;
setup 0010
Write Enlble
.1.tupIO-CE1
t.tup(W..c"l1
'lHupIA-C"!")
1
1.2,14.15
7.5
11.0
3.0
3.5
3.13
3,6,1.9,10
,
2

1,2,14.15

o.t' 'hold let.OI 2 3.0 3_5

Hold Wrote Enabl' 2 3.0 3.13 2
lholdle1:;·WI
....no lhotdler·AI 1,2.14.15 3.0 3.6.1.9.10 1,2,14,15
Chip Enable Pulse Wldlh PWce 2 7.5

!
RIM TIme 3.0 ())
120%10110%1
FilII Til"" 3.0 ())
t20%fO 10%1

·Llmlt IIPPhM for.1I inputs, ind''lldUlilly apply V'L mIn to pm un_ IHI.
·-For definItIon of tlml,.. per,met.rs, _ F,g .....,·
<D Prope, hiah/low logic lewl, ,re wrot1otn InlO ;Jddrftsed Ioc:.llon pnor to I..t
~Pul" IS "PPfied to pIn 13 (Write EOIbIe) WIth onput conditIon. M shown before menu"n" outpUt condltoons
Q) For defInition of .yrnbol • •, limong di .... ~.

3-384
MCM1 0145 (continued)

SWITCHING TIME TEST CIRCUT

Vcc V out
+2.0 Vdc

C08K Coax

,----1
16t I I
Pulse

Input Pulse
t+ = t- =
~erator

2.0± 0.2 os
{ I
I

I
AO CE 00
A1
A2
A3
01
I
I

I 0--
DO
(20 to 80%) 02
01 I

J {
I
02
I I
+1.11 VdcO

0.11'F 1° I
03 _ 0 3
WE
I I
L __ Q~
Unused outputs eonnected to 8 50-ohm raslstor 1011'F
to ground.

-3.2 Vdc
VEE

50-ohm termination to ground 10·

cated in each scope channel input.
All Input and output cable. to the Unu.d outputl connected to • 60-ohm r •• lator
scope are equal lengths of 50-ohm to ground.
coaxial cable. Wire length should
ba < 1/4 Inch from TPin to Input
pin and TPout to-output pin.

3·385
MCM10145 (continued)

WRITE TIMING DIAGRAMS-WRITE STROBE MODE

A _ _ _J

D;n _ _ _ _ -+..... 1

t ..tup (CE-WI -+---1 t - - - i - thold (D-WI

C l - - - - 1 - -..... 1

t ..tup (A-Wl-t-------t-Pww-ll-----I--thold (CE-WI

w--------""""
°out----------------------------'

CHIP ENABLE STROBE MODE

---"""".~----------~.
A ----II~ -- _ -- _ -- -- -- -- -- -"1'-_ __
t_up (D-CEI----t----+-- thold (A-CEI.

D;n ---------1-'"

t_up (A-CEI-il----+....-
CE--------~I

READ TIMING DIAGRAM

CE-----~ ~--------

--
~~.1
---
f 1I--f-l~ta+0-
- - - -- """" ,.-----------------

00: ------------3~t:~--------~~= tA+Q+

tA+Q_
tA-Q+
tA-Q_

3-386
 MECL 10,000 series
128-1 BIT RANDOM
ACCESS MEMORY

MCM10147

128 x 1 BIT RANDOM ACCESS MEMORY

The MCM10147 is a l28-bit RAM organized as a l28-word by
;T-bit array. This organization and the high speed of this MECL
10,000 device make the MCM10147 particularly useful in fast
$Cratch pad, register file, and buffer memory applications. Full
..odress decoding, and two Chip Enables (C E) are included in this
!levice to permit simple memory expansion.
, For writ,n!! Data (D) into this memory. both Chip Enables eEl
lind ~are brought low, the address is presented at AD-A6, and the
"eaa/Wiite Enable (WE) is taken low while Data is valid. To read a
Particular address, both Chip Enable inputs must again be low. but
the ReadlWrite input is high (Data input disabled) while the location
Is addressed.
. The two aup Enables are provided for row or column selection
of device packages in an expanded rnemory system. Either input can
be used to select a particular row or column of stored data bits.
Open emitter outputs permit full wire-OR ing to data buses. with
the output being held low when either Chip Enable is high. LSUFFIX
CERAMIC PACKAGE
Internal input pulldown resistors are not used on this device. CASE 820
Unused inputs should be tied to VEE.

BLOCK DIAGRAM PIN ASSIGNMENT

Chip Enable

Chip Enable
I J
CE2
2
16

15
Ao CE1
3 Al CEI 14
Al
A2 4 Ao CE2 13
A3
A4 6 A3 WE 12

A5 6 0 11
A4
A6 a - Oete Out
7 A5 A6 10

B 9

Oat. Input D
WE

Reed/Write I TRUTH TABLE

Eii"ibii
MODE INPUT OUTPUT
CEI CE2 WE Din D out

Writ. "0" L L L L L
VCCI m VCC2 D Gnd
VEE s -5.2 V Writ.", .. L L L H L
R.ad L .L
• H a
• •
Po D 415 mW ,yp/pkg (No Load)
DI,.bled H L L
IAcee.1 E 10"1 tvp (Addr... Inputs)

This I, edvance information and specification •• re subject to change without notice. tP - don t car.
L H
• • L

3·387
 ELECTRICAL CHARACTERISTICS
Each MECL 10,000 series circuit has been
desiWled to meet the de specifications
shown in the test table, after thermal equi-
librium has been established. The circuit
is in a test socket or mounted pn a printed
circuit board and transverse air flow great-
er than 500 linear fpm is maintained.
"-
,
10_A.
"
"A,
...
"
Q~'B
-
TEST VOLTAGE VALUES
3:
n
3:
Outputs are terminated through a 5O-ohm (Volts) ~
@Tnt
resistor to -2.0 volts. Test procedures are Temperature VIHmaIC Vilmin VIHAmin VILAm •• VEE 0
~
shown for selected inputs; other inputs WI: _JODe
....
11_0
-0.890 -1.890 -1.205 -1.500 -5.2 ~
~
are tested in the same manner. +2SoC -0.810 -1.850 -1.105 -1.475 -5.2
"
MCl0141AL Test Limits
+ISoC -0.700 -1.825 -1.035 -1.440 -5.2
8
Pin _30 D e +25 oC +8SoC TEST VOLTAGE APPL1EO TO PINS L1STED BELOW,
....
:::l

I u,.':t er 5"
Chllract.,istic I Symbol Min M.. Min Typ M.. Min MIX Unit VIHm... VILmin VIHAmin VI LAm .. VEE Gnd c:
Power Supply Drain Current I IE 80 100 mAde 8 16 ~
Input Current
I lin H
I 35 ~Adc 8 1,16

~ ~ ~
11 11
13 13
12 75 12
lin L
I ~.O +6.0 ~Adc 8 1.16

~ ~ ~
11 11
13 13

Logic "'" VOH

12
15 -1.060 -0.890
~.O

-0.960
+
-0.810 -0.890 -0.700 Vdc
12
2.3.4.5. 12 13.14 1.16
Output Voltage 6.7,10,11
Logic "0" VOL 15 -1.920 -1.675 -1.880 -1.650 -1.855 -1.615 Vd, 2.3.4.5 12 13,14 1,16
Output Vol tage 6,7,10.11

W I Logic "'" VOHA 15 -1.080 -0.980 -0.910 Vd, 2.3.4.5. 12 13,14 1,16
W
CO
CO
I Threshold Vol tage
Logic. "0" VOLA 15
15
-1.655
-1.655
-1.630
-1.630
-1.595
-1.595
Vd,
Vd,
6,7,10,11
2.3.4.5.
6,7,10,11
13
14
1.16
1,16
SWitching Tim. Pulse In Pulse Out
Access Times
Chip Enable t~_Q+ 15 80 ns 13 15 a I 1.16
tCE+O- 8.0 I'
Address Inpu IS tA+O+ 10 12 7
tA_O+ 10 12 7
tA+O+
tA_Q_ J 9
9
10
10 I
4
4

Write Strobe Mode Times

Setup
Data tsetup(D-WI 15 10 11,12
Chip Enable lsetup(CE"-WI 1.0 12.13
Address tsetupIA-W) 3.0 2,12
t.tup(A-W) 4.0 7.12
Hold
Data
"'oldID-WI 1.0 11.12
Chip Enable "'oldICE-WI 1.0 12,13
Address tholdlA-WI 3.0 2,12
Recovery After Write Time tW+O+ 8.0 12
tW+Q_ 8.0 12
Write Pulse Width twl\W£) 12 8.0 12
Rite Time t+ 11 20 11 1,16
120% to 80%1
Fall Time t- Il 1.0 11 1,16
,<:20% to 80%1
MCM10147 (continued)

SWITCHING TIME TEST CIRCUIT @ 25°C

Vee::: Vee, = VCC2 = +2.0 Vdc

Coax
251'F

,- --
I
m --
OlllF

I
I
~
Coax

I I
I AO
CEl CE2 I
I
Al
A2 I
Input
I
A3
A4
I
A5 I
Pu lse Generator I AS D out I
A7
Input Pulse
I I
t+ = t-::::
2.0 ± 0.2
(20% to 80%)
n. I I
I I
Din WE
I I
I
I
~
-- J
-nOlilF

1_37VdC

50-ohm termination to ground lo-

cated in each scope channel input.
All input and output cables to the
scope ar. equal lengths of 50-ohm
coaxial cable. Wire length should
be <1/4 inch from TPin to input
pin and TP out to o~tput pin.

3-389
MCM10147 (continued)

CHIP ENABLE ACCESS TIME

Dout
-DOU'+~~
'_CE G,,--'CE_+
D ou
,-

ADDRESS ACCESS TIME

Addr...

Dout

WRITE STROBE MODE

Addr...

'hold(W+Oj

~---IIo! 'hold(W+C'E+)
'hold(W+A±)-.j

Oout

3-390
rnr-------------------------------------------------------------~----------------~

1024 BIT PROGRAMMABLE MECL 10,000 series

READ ONLY MEMORY

MCM10150

Advance InforIDation

256 x 4 BIT PROGRAMMABLE READ ONLY MEMORY

The MCM10150AL is a monolithic 1024-bit programmable read

only memory (ROM) that can be factory programmed for custom
requirements. The basic organization of the memory is 256 four· bit
words. This organization and the high speed of this MECL 10,000
device make the MCM10150AL particularly useful in fast micro
programs, look up tables, decode functions, code conversion, number
conversion, and ran"dom logic.
Metal interconnections establish each bit initially in the logic "1"
state. By "blowing" appropriate nichrome resistors and thus breaking
metallization links these bits can be changad to the logic "0" state
to meet specific custom program requirements.
The MCM10150AL has eight address inputs to select the proper
word and one chip enable input as well as outputs for each of the
four bits. The MCM1 0150AL is specified over an operating temper· MCM10150AL
CERAMIC PACKAGE
ature range of -300C to +850 C.
CASE 690

VCCI - Pin 1
VCC2 - Pin 16
VEE-Pin8

BLOCK OIAGRAM

Input 32.32
Decoder Arrey end
AlIOciated Orl..,.1

A7 7

Output
A3 9 Decoder

A"10

EE 13-----------------------------------t~--------~_t--------t_t_------_,

11
C ou t3
12
D out2
I" Ui
CoutO
Dout '

Thl. I, .dv.n~ Information and tpeelf'cetlon ..... aubject to change without notice.

3-391
 ELECTRICAL CHARACTERISTICS
s:(')
Each MECL 10,000 series circuit has been
4 AO
2 Al °O\.ltO
15
s:
...
designed to meet the de specifications
shown in the test table. after thermal equi-
librium has. been established. The. circuit
is in a test socket or mounted on a printed
3 A2
9 A3
10
Doutl
14 ...
0
C11
A4 0
circuit board and transverse air flow great-
er than 500 linear fpm is maintained.
6 A5
D out2
12 n-
0
Outputs are terminated through a 50-ohm 5 A6 ::J
~,
resistor to -2.0 volts. Test procedures are A7 11 ::J
shown for onlv one input and one output. 13 °out3 C
CE It>
The other inputs and outputs are tested in
the same manner.
a.

TEST VOLTAGE VALUES

tVoltol
@II Test
Temperature V,Hm.x V,Lmin VIHAmin VI LAm. . VEE
w -lOoe ~.890 -1.890 -1.205 -1.!!QO .5.2

~
I'J
+25"<:
+85oC
~.810

-0.700
-1.850
-1.825
-1.105
-1.035
-1.475
-1.440
-5.2
-5.2
MCM10150AL Test Limits TEST VOLTAGE APPLIED TO PINS
Pin
-3d'e +2SoC +8SoC LISTED BELOW, Vee
Under
Characteristic Symbol Te.. Min Ma. Min TVp Max Min Ma. Unit V,Hmax V,Lmin V,HAmin V,LAmax VEE Gnd
Power S~pply Drain Current IE 8 110 150 mAdc 8 1,16
I nput Current ImH 2 - - - - 265 - - ~Adc 2 - - - 8 1,16
- -
Logic" 1" Output Voltage
linL
VOH"
2
15
-
-1.060
-
-0.890
0.5
-0.960
- -
-0.810
-
~.890 ~.7oo
- ~Adc

Vdc .
2 - 8
8
1,16
1,16
Logic "0" Output Voltage VOL 15 -1.890 -1.675 -1.850 - -1.650 -1.825 -1.615 Vdc 13 - - - 8 1,16
Logic" 1" Threshold Voltage VOHA' 15 -0.080 -0.980 0.910 Vdc 8 1,16
Logic "0" Threshold Voltage VOLA 15 - -1.655 - - -1.630 - -1.595 Vdc - - 13 - 8 1,16
Switching Times (SO n Load) Pula In Pula Out -32 V +2.0 V
Access Time
Chip Enable tC'E-D ou.t + 15 - - - 7.0 - - - ns - - 13 15 8 1,16
- - - 7.0 - - - - - 13

I
tCE.+D out -
Address Inputs" tA+D out + - - - 20 - - - - - 7

Rise Time
/20% to 80%)
Fall Time
(20% to 80%1
tA-O out +
t15+

t15-
j
-
-

-
-
-

-
-
-

-
20
4.0

4.0
-
-

-
-
-

-
-
-
-
j
-
-

-
-
-

- 7
7
7
j j
·VOH measurement pattern dependent .
•• AC tests shown for only one address line and one output /times are pattern dependent).
MCMl 0150 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 2SoC

Veel "" v CC2 .. +2.0 Vdc

V out

Coax Co ••
0.1 IlF

AD
AI °outO
A2
A3 °out1
A4
A5
°out2
A6 ' T P out
Pulse Generator
A7
CE °out3
Input Pulse
t+ = t-'" 2.0 ± 0.2 ns
(20 to 80%)
0.1 IlF

50-ohm termination to ground 10

cated in each scope channel input. VEE· -3.2 Vdc

Unused output• • r. tied to a 50-

All input and output cables to the
ohm r.,iltor to ground.
scope are equal lengths of 50-ohm
coaxial cable. Wire length should
be < 1/4 inch from TPin to input
pin and TP out to output pin.

ADDRESS PROPAGATION DELAY CHIP ENABLE PROPAGATION DELAY

NOTE: Addr • • mult be.t up

_ to produce a high state
on the output being
examined.

3-393
MCM 10150 (continued)

MASTER PART NUMBER

MOT'CHIOLA 'NO. ~
'V Sentlconduc<o, P,oducu DI"I.'on

--- 101_11111,1.1111,111'111111,2
_"11111111_11111111'111,1113
22QOWEST 8P10AOWA't'. MES .... ","'IZONA '!S202

MCM10150 ORDER FORM

-- 111_111111111,11'111'1'111114

1011'111111111'_'111'1'1'11'
________ '0 __
_r'llllllllll'I'II'I'I,I'II'

DASH NUMBER P'URCH. ORDER NO. _ _ _ _ _ __

101111121121 rl' lSI II, I" "~I ,1'1

~--
11'1" 121 III 'I' '11(1' ,., ,I, 'I'
'0' I" 121 III ra, '1111r I I I I I I 1'1

-- '0'
'I'
,.,
I')
III
III
III
lilli'
'I' lilli'
1.111'
III
"~I
'I'
'I'
'I'
'II
I 0 I 1'1 I J 1 121 I' I 1'1 ( . I I • I 1'1 I' I •

ORDER DATE·

Mlk, All M...b .~.

With,Soft#2llld
Pencil Whon Comp1tlinl
CUSTOMER NAME CODE Form.
-j lUI "'I 101 1'1121121 'I' 'I' '1'1'1'1' ,.1 1
EI1I.COmpl,"ly
~:::: :::: ::: ::: ::: ::: ::: :::',: I,',', 'I:' :.: ~ Any MI,b You
DASH NO _ _ _ __
WiItI to Chi""
....,:::: :::: ::: ::: ::: ::::::::: 'I' ,,, •

YOUR PART NUMBER" Numbers ar' ma,ked normally on e.:h line. For any other characters, standilrd Holle,ith coding IS used.
For elUlmple, I d.sh Ciln be coded by marking the ll·block in one line. The tlble ilt the lelt shoW! how to

"1< I" I' '1° I" I'

KLMNOl'OR
ITUVWXYZ
cod"etters Inote thilt .... ,ener requlru two marks - a "lone" milrk and iI "select" mark. I
As an ellample. you would code the lO-character Plrt number: 'MYPART -123' as folloW5 - For the 'M'

=
- '. " , on Ime 1, milrk the ~ column Il1·blockl and the ~ column 14·blockllike 11""115:

- '''' ... ".''''''

112'1"'10'1"1.,,1,,'1,1,11,1'11.11.1

"".'""."",. ,.'
3
IMPORTANT FDA THE 'V' ON LINE 2. MARl( THE [[!Q]] AND THElli9!lCOLUMNS

-- "",:::::::::::,::,,:,:::::,::::::,.,. P"nl Ptrl Numblr

3. ~
1hlQJ]" ~
.• ~

.
Hlr.- 'A' of.
I I ! § ] ] " (!ill
- 'R'
[ i } Q I ) " (ill]
- 8"oreM,rklne
6.

- I 121 1" I I 0 I 1'1 131 131 1'1 I I I I·' I 1" 1'1

"
I' I 10
Grid II Llf,. "·8LOCK
8.9. 10, MARK THE 1 2,. BlOCKS, REsPECTIVELY.

QUANTITY ORDERED IWOIitTANT

1,11111111" 11,1,1 ,'llllltl 1 Code your order qu.ntity in thl5 field. For eJI.mple, if you require 46 J»I"1i of
lal 11"1 121 III 1'1 Itlill 1'1 III III thiS type. milrk the 4'block in line 2 end the 6·bI~k in linl 3.
UI'I'Talal 1'1 121 12_1 1'1 1'1 1111'1 III 1'1

MARKING OPTION °If you desire your p.,-t number to be marked on each device, it must be coded In the proper field .bove;

-
MOTOROlA DAIH H .... I I YOUR "A T HaR. I I otherwi_. the .bove p.,-t number filid is optional.

.... PACKAGE TYPE

ORDERIPERSONALITY TYPES
,. I I ,. ,
If this is a new order (not a reorder of a pettern), the personality mun be coded. Note that Nlative
!ORD!R I I HEQATtYI LOGIC! I logic can be used if mor. th.n h.1I of your plttern IS 'ones'"

ADD"I.
. N+I ...
ROM PERSONALITY
ADORI. ....... YOUAAEMAAKS ________________________ ~--~~---------- __

1'1 [ ' I I , I 101 l:i I 131 ( " 101 1'1 I I I I • I 101 0

fI I I I I 1.1 I fTl 1.1 I I I I 1" I a 11\3 I " I ( ' J 101
III III III lal III 131 ' " 101111 11'1111101
121 (II 1'1 1'1 III III 1'1 1'1111 121 1" 1019
III III 1'1 101111 III (11 '01111 III 1'1 10112
III (21 1'1 10J 1 1 1 2 1 1 ' 1 1 0 1 1 1 1 t21111 lOt 16
101 [I I I I I 1'1 (I I I I i 131 ( , I 101 18

1" III 1311'1 10111', III t'r'IOl 21

.01 I J I I' I " 1 I a I " I 121 111 101 24
III III III 111101111 l:il [" (0 21
f 0 I (I I I I I I 1 I 101 I 3 I I I I I , I 101 30

Request your order forms from your Motorola representative.

3·394
 MEel III
INTEGRATED CIRCUITS
Mel600 SERIES

4-1
 VOL TAGE-CONTROLLED MECL III MC1600 series
OSCILLATOR

MC1648

The MCl648 is an emitter-coupled oscillator, construc-

ted on a single monolithic silicon chip. Output levels are
compatible with MECL III logic levels. The oscillator reo
quires an external parallel tank circuit consisting of the
inductor (L) and capacitor (C).
1101 A varactor diode may be incorporated into the tank
1121 circuit to provide a voltage variable input for the oscillator
(VCO). The MC1648 was designed for use in the Motorola
Phase· Locked Loop shown in Figure 9. This device may
151 also be used in many other applications requiring a fixed
Numbers in parenthesis denote pin number for or variable frequency clock source of high spectral purity
F package (Ce. 607) L package (Case 632), and (See Figure 2).
P package (Cas. 646).
The MC 1648 may be operated from a +5.0 Vdc supply
Input Capacitance '= 6 pF typ or a -5.2 Vdc supply, depending upon system requirements.
Maximum Series Resistance for L (External Inductance) = son typ
Power Dissipation = 150 mW typ/pkg (+5.0 Vdc Supply) SUPPLY VOLTAGE GNO PINS SUPPLY PINS
Maximum Output Frequency = 225 MHz typ +5.0 Vdc 7.8 1.14
-5.2 Vdc 1,14 7,8

FIGURE 1 - CIRCUIT SCHEMATIC

VCC2 veel
(14) (11

+----+----+----{ on
012

014 Q13 f;-+--.-+--++-1

02

(7) (10) (12) (81 (5)

Vee 1 B,al Pt. Tank Vee 2 AGe
Numbers in parenthesis denote pin number for F packev. (Case 607), L package (Case 6321, and P pacl<age (CaM 6461.

FIGURE 2 - SPECTRAL PURITY OF SIGNAL AT OUTPUT

L: Micro Metal tarraid #T20-22, 8 turns

#30 Enamled Copper wire.
C ~ 3.0 - 35 pF r - - -....~~-._ +5.0 Vdc

1101 1141

1200·

13)
Signal
Under
112) Test
15)
1:: 0.1 jlF
B.W. '" 10 kHz Scan Width =' 50 kHz/div -The 1200 ohm resistor and the scope termina-
tion impedance constitute a 25: 1 attenuator
Center Frequency = 100 MHz Vertical Scale"" 1 0 dB/div
probe. Coax shall be CT ·070·50 0 r equ ivalent.

4-3
MC1648 (continued)

ELECTRICAL CHARACTERISTICS

(10) (3)
Supply Voltage. +5.0 .olts Output
TEST VOLTAGE/CURRENT VALUES
(12)

VIM ..,... 'L

T'~::; 1--"'::::;:'+-'-":"::::"-1--''7-+-77-1
"IL "'in Vee
., 960 +1.410 50 ·50
(51 '25"< ., 300 50 ·50
+lSoC +1.680 +1.180 50 ·50
MCl141 Tt'It Lom, .. TEST VOL TAGlE/CURRENT APPLIED TO
p," PINS LISTED BELOW
..,-
_lODe '25"<
o.IICtwtRIC ,..,
u .....
Min Vee 'L
VEl
COndl
P_SupplyDr,onCurr,nt
Log.c"'"
Output Volt....
"
VO~-i 3.94
.'. .04
'0
"5
1.14
1.14
7.'
7.'

LotIc "0"
Output Vol,.
8,~ Volt.
VOL

I/a.n '0
3.16

",
340

' ..
3.20
'" 3.23 '46
, . " 1.14

, ..
7.'

'" '"
Min 'yp
P..k 10·P.... T.nk Vol' .... "g.p
" 500 Se.F.gu.eJ 1.14
'.'
Output Quly Cycl.
OIC,U,lIlOnF'''Iuency ,_.
VDC

I '00 '"
50 SeIF/gut.J
.see F'gu'eJ
1.14 7.'
7.'

ELECTRICAL CHARACTERISTICS

,--------,
I I
(101
Supply Voltage = -5.2 .olts ; : (3)Output
TEST VOL TAGE/CUFILRENT VALUn
(121
I (VWII) mAd<
L _______ J T."'....Ilu •• VIH ..,... "IL ",in VEE 'L
• ... e
'25OC
-3300
-3400
-3.800
-3.900
."
-5.2
-5.0
·50
151
Me 1&48 T .., limttl
+86 o C -3500 ·-4000
."
TEST VOLTAGE/CURRENT APPLIED TO
·50

·...e PINS LISTED BELOW.

Vee
Min M.. "IHmo. "ILmin VEl 'L 10ndi
7.' 1.14
., 0.5 -0815 ·0960 -0150 .0.90 -0650
" 7.' 1,14

-1.890 -1650 -1850 -1620 -1830 -1515 Vdo

" 7.' 1.14

. 7.'
-3.690 -3.340 -3800 -3.500 -3.910 -3.620 Vol< r,14

.... " Mo. .... ". 500

Mo • Min Typ .... S.. Fi,urt3 7.' 1.14
50 % SnFi.,..rt3 7.' t,14

-1 -1 - 200.1 "'L MH, Site Figure3 7.' 1,14

FIGURE 3 - TEST CIRCUIT AND WAVEFORMS

• Use high impedance probe ( > 1.0 Megohm must

be used).
•• The 1200 -ohm resistor and the scope termination
impedance constitute a 25: 1 attenuator probe.
Coax shall be CT 070-50 or equivalent .
••• Bvpass only that supply opposite ground.

Duty Cycle (VOC) '" _. '.

'b

4-4
MC1648 (continued)

OPERATING CHARACTERISTICS

Figure 1 illustrates the circuit schematic forthe MC1648. FIGURE 4 - THE MC1648 OPERATING IN THE VOLTAGE
The oscillator incorporates positive feedback by coupling CONTROLLED MODE
the base of transistor 07 to the collector of 08. An auto·
matic gain control (AGC) is incorporated to limit the cur·
rent through the emitter·coupled pair of transistors (07
and 08) and allow optimum frequency response of the
oscillator.
In order to maintain the high 0 of the oscillator, and pro·
vide high spectral purity at the output, a cascode transistor
(04) is used to translate from the emitter follower (05) to
the output differential pair 02 and 03. 02 and 03, in
conjunction with output transistor 01, provide a highly
buffered output which produces a square wave. Transistors
010 thru 014 provide the bias drive for the oscillator and
output buffer. Figure 2 indicates the high spectral purity
of the oscillator output (pin 3).
When operating the oscillator in the voltage controlled When the MC1648 is used with a constant dc voltage
mode (Figure 4). it should be noted that the cathode of to the varactor diode, the output frequency will vary
the varactor diode (0) should be biased at least 2 VSE slightly because of internal noise. This variation is plotted
above VEE ('" 1.4 V for positive supply operation). versus operating frequency in Figure 5.

FIGURE 5 - NOISE DEVIATION TEST CIRCUIT AND WAVEFORM

I
.,::;

-
100
vcc 5.0 Vdc Oscillator Tank Components
a: {Circuit of Figure 4J
z· f L
Q ~ MHz 0 jlH
I-
:5 1.0·10 MV2115 100
>
w 10
V 10-60 MV2115 2.3
0 60·100 MV2106 0.15
>-
u
z
W
::J
0
W
a:
u.
1.0
<i 1.0 10 100
f, OPERATING FREQUENCY, (MHz)
I S'9nal Generator

20 kHz above MC1648 F'equencV ~ I

HP 608
or Equiv
I
300 mV
IB.w. ""
MC1648 I 10mV Product I 20 kHz
1.0 kHz
Frequency Voltmeter

II I
Attenuatar Meter AMS
Under Test
I MC1648
Frequency (f)
Detector
I I HP5210A
or Equiv
HP34QOA or Equiv

(HP5210A output voltage) (Full Scale Frequency)

Frequency Deviation =
1.0 Volt

NOTE: Any frequency deviation cauted by the lignal gen.rator and MC1648 power
supply should be determined end minlmzed prior to telt'ne.

4-5
MC1648 (continued)

TRANSFER CHARACTERISTICS IN THE VOLTAGE CONTROLLED MODE

USING EXTERNAL VARACTOR DIODE AND COIL. TA = 25°C
FIGURE 6

64
L, Micro Metal Toroidal Core #T44-1D,
60 4 turns of No. 22 copper wire.
i 56 Vin
~ 52
>
U
z
w
48
44 ./ (10)
[J
:J
d
w
...a:
40
36 /' "" 1 k
"'~'~'
~
I'FI I
32 L: I
..
f out
I-
:J 28 L -= , I (31
I- 24
II..... I L_______ J
:J /'
0 20 M~1401 (121
(51
; 16
Veel '-' VCC2 = +5 Vdc
_0
12 /' 51'FJ X O. 1 1'F
VEE 1 ," VEE2 '" Gnd
8.0 1--
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 -The 1200 ohm resistor and the scope termina-
tion impedance constitute a 25: 1 attenuatar
probe. Coax shall be CT -070-50 or equivalent.
Vin. INPUT VOLTAGE (VOLTS)

FIGURE 7

18
L' Micro Metal Toroidal Core 6T44 10,
N 17 4 turns of No. 22 copper wire.
I Von
~ 16
> C '" 500 pF
U
zw
15
f.-- (10) J
~
14 ._- -- - r---- t-- -- ----- ---- - - -
:J

,r,~
0
w 13 / 1 k 0.1 (: : 1200'
...a: V I'FI ~
L C:
I
I
.
I- 12
/ =, I (~
f out
:J
I- 11 U...1 L_______ J
:J
0 10
/ ,,~

MV1401 (121
(51
; 9.0 / 51'FJ Veel '" VCC2 '" +5 Vdc
XO"1'F
_0
8.0
1/ VEEl = VEE2::::' Gnd

0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 -The 1200 ohm resistor and the scope termina-
tion impedance constitute a 25; 1 attenuatar
probe. Coax shall be CT-070-50 or equivalent.
Vin. INPUT VOLTAGE (VOLTS)

FIGURE 8

190

£U
L, Micro Metal Torodial Core #T30·22.
180
5 turns of No. 20 copper wire.
i 170
~ 160 /' <j>V tn £ VCC1=-VCC2-+ 5Vdc
> ./
u 150
51'F I'FX "ceo "m
Z
w 140
V I= 51k - (10)
0 ""'

:J
0
w
130
120 /
-
~
,r--------, I 1200'
...a: 1/ I I
110 :! L I
, (3)
I
f out

..
I-
:J
I-
100
90 /. f:.)
> I
I
IL _ _ _ _ _ _
_J
I

:J
0 80 ./ 1121
; 70 L' (51

_0 60 ./ ::r:: 0.1 I'F

50 ......-
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8_0 9.0 10 ·The 1200 ohm resistor and the scope termina-
tion impedance constitute a 25: 1 attenuator
probe. Coax shall be CT -070·50 or equivalent.
Vin. INPUT VOLTAGE (VOLTS)

4-6
MC1648 (continued)
Typical transfer characteristics for the oscillator in the
voltage controlled mode are shown in Figures 6, 7 and 8.
Figures 6 and 8 show transfer characteristics employing
onl~ the capacitance of the varactor diode (pluse the input
capdcitance of the oscillator, 6 pF typical). Figure 7 illus·
trates the oscillator operating in a voltage controlled mode
with the output frequency range Ii mited. This is achieved
by adding a capacitor in parallel with the tank circuit as
shown. The 1 kn resistor in Figures 6 and 7 is used to pro·
tect the varactor diode during testing. It is not necessary
as long as the dc input voltage does not cause the diode to
become forward biased. The larger·valued resistor (51 kn)
in Figure 8 is required to provide isolation for the high·
impedance junctions of the two varactor diodes.
The tuning range of the oscillator in the voltage con·
trolled mode may be calculated as:
f max yco (max) + Cs
fmin yCo (min) + Cs
1
where fmin = --:--r=:=======
2tr y L (CO (max) + CS)
Cs = shunt capacitance (input plus external
capacitance) .
CD = varactor capacitance as a function of
bias voltage.
APPLICATIONS INFORMATION
The phase locked loop shown in Figure 9 illustrates the
use of the MC 1648 as a voltage controlled oscillator. The
figure illustrates a frequency synthesizer useful in tuners
for FM broadcast, general aviation, maritime and land-
mobile communications, amateur and CB receivers. The
system operates from a single +5.0 Vdc supply, and requires
no internal translation, since all components are com·
patible.
Frequency generation of this type offers the advantages
of single crystal operation, simple channel selection, and
elimination of special circuitry to prevent harmonic lock·
up. Additional features include de digital switching (pref-
4·7
Good R F and low-frequency bypassing is necessary on
the power supply pins (see Figure 2).
Capacitors (Cl and C2 of Figure 4) should be used to
bypass the AGC point and the VCO input (varactor
diode), guaranteeing only dc levels at these points.
For output frequency operation between 1 MHz and 50
MHz a 0.1 /IF capacitor is sufficient for Cl and C2. At
higher frequencies, smaller values of capacitance should be
used; at lower frequencies, larger values of capacitance. At
higher frequencies the value of bypass capacitors depends
directly upon the physical layout of the system. All by-
passing should be as close to the package pins as possible
to minimize unwanted lead inductance.
The peak-to·peak swing of the tank circuit is set inter-
nally by the AGC circuitry. Since voltage swing of the
tank circuit provides the drive for the output buffer, the
AGC potential directly affects the output waveform. If it
is desired to have a sine wave at the output of the IViC1648,
a series resistor is tied from the AGC point to the most
negative power potential (ground if +5.0 volt supply is
used, -5.2 volts if a negative supply is used) as shown in
Figure 10.
At frequencies above 100 MHz typ, it may be necessary
to increase the tank circuit peak-to· peak voltage in order to
maintain a square wave at the output of the MC1648. This
is accomplished by tying a series resistor (1 kn minimum)
from the AGC to the most positive power potential (+5.0
volts if a +5.0 volt supply is used, ground if a -5.2 volt
supply is used). Figure 11 illustrates this principle.
erable over RF switching with a multiple crystal system),
and a broad range of tuning (up to 150 MHz, the range
being set by the varactor diode).
The output frequency of the synthesizer loop is deter-
mined by the reference frequency and the number program-
med at the programmable counter; fout = Nfref. The
channel spacing is equal to frequency (fref).
For additional information on applications and designs
for phase locked·loops and digital frequency synthesizers,
see Motorola Application Notes AN-532A, AN-535, AN-553,
AN-564, AN-594, or Phase-Locked Loop Systems Data
Book.
MC1648 (continued)

FIGURE 9 - TYPICAL FREQUENCY SYNTHESIZER APPLICATION

Voltage-
Controlled
Oscillator
f - -....~_fout
MC1648
fout = Nfref
where
N = Np • P +A

N = Np. P + A

Figure 10 shows the MC1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To obtain a sine
wave at the output, a resistor is added from the AGC
circuit (pin 5) to VEE.
Figure 11 shows the MC 1648 in the variable frequency
mode operating from a +5.0 Vdc supply. To extend the
useful range of the device (maintain a square wave output
above 175 MHz), a resistor is added to the AGC circuit at
pin 5 (1 k·ohm minimum).
Figure 12 shows the MC1648 operating from +5.0 Vdc
and +9.0 Vdc power supplies. This permits a higher voltage
swing and higher output power than is possible from the
MECL output (pin 3). Plots of output power versus total
collector load resistance at pin 1 are given in Figures 13
and 14 for 100 MHz and 10 MHz operation. The total
collector load includes R in parallel with Rp of L 1 and
Cl at resonance. The optimum value for R at 100 MHz is
approximately 850 ohms.

FIGURE 11 - METHOD OF EXTENDING THE USEFUL RANGE

FIGURE 10-METHODOF OBTAINING ASINE·WAVE OUTPUT OF THE MC1648 (SQUARE WAVE OUTPUT)

+5.0Vdc
+5.0 Vdc

1--+---0 Output
1 k min

I
4-8
MC1648 (continued)

FIGURE 12 - CIRCUIT SCHEMATIC USED FOR COLLECTOR OUTPUT OPERATION

+9.0 V

~.01 jJF

R
VCC2
(14)
Output
+5.0 v

~----~--_1----_+--_1Ql0

t-----+-----+---~ all

Q12

02

(10) L2 '.2 k
(7)
Bias Pt. +--__::#~::::C=o2_' (8) (5) ILl. I , 0 "f .. +5.0 V

VEEl V EE 2 AGC~
'T'''-
_ 'T' . ~
~
('2)
Tank
ci

FIGURE 13 - POWER OUTPUT varsus COLLECTOR LOAD FIGURE 14 - POWER OUTPUT varsus COLLECTOR LOAD

$eetestcircuit, Figure 12,f= 100MHz S.etestcircuit, Figur.12,f:::: 10MHz

C3 = 3.0 - 35 pF C3 = 470 pF
Collector Tank Collector Tank
Ll=0.22jJH Cl=1.0-7.0pF L1 = 2.7 jJH C' = 24 - 200 pF
R=50n-l0kn R = 50 n - 10kn
Rpof Ll andCl:::: 11 k{l@100MHzResonance Rp of L 1 and Cl = 6.8 kn@ 10 MHz Resonance
Oscillator Tank Oscillator Tank
L2 = 4 turns #20 AWG 3/16" 10 L2 = 2.7 jJH
C2 = 1.0 - 7.0 pF C2 = 16 - 150 pF

14

_ 6
_'2 '\
!II
~
a: 5
!II
~
a:,O \
~
-4
I \ ~
S 8
ioo'" ~
I-
:;) / \ ..
l-
:;)
V ~
~ 3 I- 6
:;)
o
a: 2
w
/ \ :;)
0
a: 4
w

.
~
01
..
~
0 2

0
100 1000 '0,000 10 100 1000 10,000

TOTAL COLLECTOR LOAD (ohms) TOTAL COLLECTOR LOAD (ohm,)

 MC1650. MC1651

Positive Logic The MC1650 and the MC1651 are very high speed
comparators utilizing differential amplifier inputs to sense

V1a(10)
V2a(9) 56 3 :
- 1+ 0 _O~ 2(6)_00
analog signals above or below a reference level. An output
latch provides a unique sample-hold feature. The MC1650
provides high impedance Darlington inputs, while the MC·
C. (8) 4· C a 3 (7) 00 1651 is a lower impedance option, with higher input slew
'----' rate and higher speed capability.
Complementary outputs permit maximum utility for
V1b(16) 1 2 3- : 1 +0
V2b(15)11 0_~14(2)_01 applications in high speed test equipment, frequency meas·
urement, sample and hold, peak voltage detection, trans-
mitters, receivers, memory translation, sense amplifiers
Cb(1) 13 C a 15(3)01 and more.
L.......-_...J The clock inputs (Ca and Cb) operate from MECL III
v CC • +5.0 V - P;n 7,10 - (11). (14) or MECL 10,000 digital levels. When Ca is at a logic high
VEE - -5.2 V D P;n 8 (12) level, ao will be at a logic high level provided that V 1 >
Gnd"" Pin 1,16 (4) (5)
Po = 330 mW tvp/pkg (No Load)
V2 (Vl is more positive than V2). ao
is the logic com·
•
plement of ao. When the clock input goes to a low logic
• tpd "" 3.5 ns typ (MC1650)
level, the outputs are latched in their present state.
= 3.0 ns typ (MC1651)
• Input Slew Rate = 350 V/",s (MC16501
Assessment of the performance differences between the
- 500 VII" (MC1651) MC1650 and the MC1651 may be based upon the relative
• Differential Input Voltage: behaviors shown in Figures 3 and 6.
-5.0 V to +5.0 V (-30o e to +8SoC)
• Common Mode Range: TRUTH TABLE
-3.0 V to +2.5 V (-30o e to +SSoCI (MC1651)
-2.5 V to +3.0 V (-30o C to +8SoC) (MC1650) C V1, V2 00n+1 00n+1

• Resolution: ~20 mV (_30o e to +8SoC) H V1>V2 H L

H V1 <v2 L H
• Drive. 50 n lines
Number at end of tarminal danotes pin number for L package (Case 6201, L q, q, oOn oOn
Number in parenthesis denotes pin number for F package (Case 650). t/J "" Don't Care

CIRCUIT SCHEMATIC·
MC1650 Input. 1/2 of Device Shown (Both Davices)
'--~-"-----<l------ A

t---+---- -- B
t--+--f---- - - C
B---
V1 (10)6
C----+--~----+---~
2 a
'--+----+------<> 3 a:
(7)

} - - - - - - - --0
' - - - -_______- - -- -E

MC16S1 Inputs
,---_------ A

+--------8
t---+-------- C O-------r--+-+-~~-+~
V1 (10) 6

E-------~----~~--~----_+~--~----+---~
Rp
}--------o 4
--- E Clock

S. Gen.,.' Inform.tion Metion for p.::k . . ing Informetion.

4-10
 -
ELECTRICAL CHARACTERISTICS POSITIVE LOGIC
3:
This MECL III circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
V1a6~
V~. 5 _ 0: 2:0 ....
(")

O'l
been established. The package should be Ca 4 C Q 3 00
CJ'I
housed in a suitable heat sink (lERC-LlC- L SUFFIX o
214A2WCB or equivalent) or a transverse
airflow greater than 500 linear fpm should
be maintained while the circuit is either in a
V1b12~
V2bl1 - 0 Q 14Ql
CERAMIC PACKAGE
CASE 620 •
3:
a
test socket or is mounted on a printed
circuit board. Test procedures are shown
for selected inputs and selected outputs.
(;b13 C 1501
....
(")

O'l
The other inputs and outputs are tested in
a similar manner. Outputs are tested with
TEST VOLTAGE VALUES
(Valt,) ....
CJ'I

vcc~lv •• ~
<OT ...
a 50-ohm resistor to -2.0 Vdc. See general VIHm. . VILmln VIHA.min VILAm. . VA1 VA2] VA3 VA4 I VAS VA6 n
information section for complete thermal
Temper.tur.
_30°C +5.0 -5.2
o
-0.875 -1.890 -"80 -1.515 +0.020 -0.020 :J
data. ~
+25 oC -0.810 -1.850 -1.095 -1.485 +0.020 -0.020 See Note@ +5.0 -5.2
+5.0 -5.2 :J
+8So C -0.700 -1.830 -1.025 -1.440 '+0.020 -0.020
C
MCl6S0Ll1651L Tnt Limits <D (I)
Pin
-~c +25 o C I +8S o C
TEST VOLTAGE APPLIED TO PINS LISTED BELOW a.
ChI,.I:t ... st,c Symbol
Und ..
T", M." I MIX I Min I MIX I Min I MIX I Unit I VIHmlX I VILmint VIHAminIVILArnI.1 VAl VA2 VA3 VA. VAS VA. I a
Vcc(j) V•• 0'"
Power SupplV Dram Current
POSitive 'CC 7,10 25" - mAde 4,13 6,12 7,10 1,5,11,16
Negative 'E S 55" - mAde 4,13 6,12 7,10 1,5,11,16
Input Current
MC1650
'," 10 - 13 7,10 1.5,11,16
MC16S1 40 -
,uAdc
j.l.Adc 13 "" 7,10 1,5,11,16
f" pnpU1 Leakage Current 'R
1,5,11,16
~
- 7,10 S
MC1650
MC1651 10 -
.'lAde
/-lAde
13
13 "" 7,10 8 1,5,11,16
Input Clock Current lon H 350 - ,uAdc 13 6,12 7,10 8 1,5,11,16
linL 0.5 - ,uAdc 13 6,12 7,10 4.B 1,5,11,16
LogiC "1" Output Voltage VOH 1.04SI.Q87SI.a960 .QB 10 -OB90 -0700 Vde 4,13 6,12 7,10 B 1,5,11,16
5,11 1,6,12,16

I
6,12 5,11 1,16
5,11 6,12 1,16

5,11 [
6,12

5,11 6,12
6,12 5,11
j 1,5,11,16
1,6,12.16
1,16
1,16
LogIC "0" Output Voltage VOL 1.8901·1.6501·1.850 1-1.6201-1.8301·15751 Vdc r 4.13 6,12 7,10 B 1,5,11,16
5,11 1.6,12,16

II
5,11 6,12 1,16
6,12 5,11 1,16
6,12 1,5,11,16
5,11 1.6,12,16
6,12 5,11 1,16
5,11 6,12 1,16

LogIC "I . Ttueshold VOltage~~ I VOHA -1.065[ - [-0980 - ,.(19101 - I Vdc 13 7,10 S 1,5,16

~I~ ~ ~ ~ ~
LogiC "0" r"reshold VOltageJ;

NOTES CD
~ I~
I VOLA - '-1.630

-rl = rnr
All data IS for Y. MC1650 or MC16S1, e)(cept data marked (-I which refers to the entire package.
13

+
@
7,10

~
I All T.....,,'u,•• I VA3 I VA4 1 VAS 1 VAB
B

~
I 1.5,16

@
(j)
Them tests done in order Indica.d. See Figure 4.
I MCI650 I +3.000 I +2.980 -2.500 1-2.480 J
Ma)(lmum Power Supply Voltages (beyond wl'lIch deviCl! life may be Impaired):
IVee!'" IVccl:(;12 Vdc. r MC1651 T+2.500 T+2480 1-3 .000 -2.980
 SWITCHING TIMES s:
n
....

- ~
o
POSITIVE LOGIC •
s:
V1a6~O n
v2.5 - 0 200 L SUFFIX
CERAMIC PACKAGE ....
~
C. 4 C 0 300 CASE 620
....
Vlbl2~
v2bll - 0 0 1401 8::J
....
Cb13 C 0 1501 :;'
c:
Cl)
TEST VOLTAGE VALUES a.
IVolt.1
• Toot
Tempeqture VRI VR2 VR3 Vx VlO( Vee a> VEE a>
-:JIIOe +1.040 +2.00 +7.00
~ -3.20
+ZSoC @ +1.110
~
Sell No •• +2.00 +7.00 -3.20
_OC +2.000 +1.190 +2.00 +7.00 -3.20 See Figure 2

-
~
~
Ct.r.ct.ilCic
Switchina Times
Symbol
t6+2+
Pin
Und.
T...
2
Min
2.0
Mel11iOU11161 L T... Limits
-:JIIOe
Mo.
5.0
+25o C
Min
2.0
Mo.
5.0
_oe
Min
2.0
Mo.
5.7
Unit
ns
VR'
5
TEST VOLTAGE APPLIED TO PINS LISTED BELOW

VR2
-
VR3
-
Vx
4
Vxx
1,11,16
Vee a>
7,10
VE~a>
8
PI
6
P2
-
'3
-
'4
--
Propegltion Delay t6+2+ 2 - 5 - - 6 -
150% '0 50%1
V-Input to Output
t6+2+ 2
3
-
5
-
-
5
-
-
6
-
-
6
-
--
'6+~
t6+3- 3 - 5 - - 6 - ~

'6+~ 3 - - 5 - - 6 -
'&-2- 2 5 - - 6 - - -
'6-2- 2 - 5 - - 6 - -
'&-2- 2 - - 5 - - B -
t6-3+ 3 5 - - 6 - - -
'&-3+ 3 - 5 - - 6 - -
'6-3+ 3 - - 5 - - 6 -
Clod< '0 Ou'PU' <2> t4+2+ 2 2.0 4.7 2.0 4.7 2.0 5.2 n. 5 - - - 1,11,16 7,10 8 6 - - 4
- - - - -
~ ~ ~ ~ ~ ~ ~
2 6 5

!- !
t4+2-

Clock Enable Time C3>

t4+3+
t4+3-
t.tUD
3
3
6 - 2.5 - - - n.
6
5
5
-
-
-
-
-
-
-
-
-
l
1,11,16
~
7,10 8
5
6
6
-
-
-
-
-
- 4
Clock Aperture Time_Q}_ .~ 6 - - 1.5 - - - n. 5 - - - 1,11,16 7,10 8 6 - - 4
RiltTi .... '2+ 2 1.0 3.5 1.0 3.5 1.0 3.8 n. 5 - - 4 1,11,16 7,10 8 6 - - -
110%'0 _ I 13+ 3 1.0 3.5 1.0 3.5 1.0 3.8 n. 5 - - 4 1,11,16 7,10 8 6 - - -
FellTi ... '2_ 2 1.0 3.0 1.0 3.0 1.0 3.3 n. 5 - - 4 1,11,16 7,10 8 6 - - -
110%'090%1 .~ 3 1.0 3.0 1.0 3.0 1.0 3.3 n. 5 - - 4 1,11,16 7,10 8 6 - - -
NOTES: CD Mlximum Power Supply VoltllQII (bayond which device life may be iq)8ired: @) I All T. .pero.u... VR2 I VR3
IVccl+ IVEEI"12Vdc.
® Unu.d clock input. may be tied to ground. I MC16&O I +4.900 I ~.4OO
(3) Sell F iou'. 8. I MC1861 I +4.400 I ~.9OO
 ELECTRICAL CHARACTERISTICS POSITIVE LOGIC
Thil MECL III circuit has bHn deligned to
milt the de ip8cificationl Iho'M'1 in the
tl.t table, after thermal equilibrium hal
t:.en estabtished. Air flow greater than
"'."~
V2.

Ca
9

8
- 0

C
0

Q
6

7
00

00 ~
....,..,; -. ...3:
(")

~
.
500 linear fpm thould be maintained while
the circuit il either in a test lOCket or is
mounted on a printed circuit board. Telt
procedures are shown for selected inputs
" "~
'V2b 15 - 0 0 2 01
FSUFFIX •
3:
...
CERAMIC PACKAGE
and selected outputs. The other inputs Cb 1 C 0 3 01 CASE 650 (")
and outputl are tested in 8 simitar manner.
Jutputs are tested with 8 50-ohm resistor
to -2.0 Vdc. See genera' information
.ction for complete thermal data.
TEST VOL TAGE VALUES
(Vah.)
m
...
g
v".
OT ...
Temperatur. vlHm.. vlLmin VIHAmin VILA.,.... YAI YA2 YA3 YA< VAl Ycc<3l YEE<3
-3D"c -0.875 -1.890 -1.180 -1.515 +0.020 -<1.020 +5.0 -5.2 ...
::l

MC161OF/1651F T... Limits (j)

_·c
+26 oC -0.810
-0.700
-1.850
-1.830
-1.095
-1.025
-1.485
-1.440
+0.020
-+(1.020
-0.020
-0.020
See NotefD +5.0
+5.0
-5.2
-5.2
:;'
t:
C1)
C.
Pin TEST WL T AGE APPLIED TO PINS LISTED BELOW

C....ct• •ic
Power SupPIv Or.,n Current
Sy_'
U .... -3O"c
Tost M" Min....
+25 o C _"c
Min .... .... Unit VIHm.. VILmin VIHAmin VILAmlix VAl YA2 VA3 YA< V"S YA6 Yc~ y.;<J O.d

Positive ICC 11,14 - - - 25' - - imAdC - 1.8 - - 10,1. - - -- -- - 11,14 12 4,5,9,15

Neptive 'e 12 - - - 55' - - mAde 1.8 - - - 10,18 - - - tt,14 '2 4,5,9,15
Input Current lin
MCl650 10 - - - 10 - - .wAdc 8 1 - -- 16 - 10 - - - 11,14 12 4,6,9,15
MC165! 10 - - - 40 - - .wAdc 8 1 - 16 - 10 - - - 11,14 12 4,5,9,15
Input Le.k. Cur...nt
~
..... MC1650
'R
10 - - -- 7 - - J,lAdc 8 1 -- - 16 - - -- 10 - 11,14 12 4,5,9,15

w
MC1651 10 - - 10 - - J,lAdc 8 1 - 16 - 10 - 11,14 12 4,5,9,15
Input Clock Current lin H
lin L
6
6
-
0.5
350
-
- .wAdc
.wAdc
• 1
1
10,16
10,16
- 11,14
11,14
12
8,12
4,6,9,16
4,5,9,16
L09IC "1" Output Voigge VOH 6 1045 -0875 1-0960 .QB90 -<1700 Vdc 1.6 10,18 - - 11,14 12 4,5,9,15
6 - - - -- 9,16 - - -- - 4,6,10,16
6 - - - - 10,16 9,15 - <.S

T I
- - - - - - - 9,15 10,16

j j
6 <.S
7
7
7
7
,_ j --
-
-
-
-
--
-
-
-
-
-
9,15
-
-
10,16
--
-
9,15
-
-
-
-
-
10,16
-
-
--
10,16
-
-
-
9,15
4,5,9,15
4,5,10,16
4.5
<.'
LogiC "0" Output VOltaige VOL 6 -1.650 -USO -11120 ·lB30 ·1575 Vdc 1.8 -- -
10,16
-
-- -
-- -
11,14 12 4,5,9,15
6 - 9,15 4,5,10,18

I II
6 -
-
- -
-
-- -
-
9,15
-
10,16
-
- - <.6
6 - 10,16 9.16 <.'
7
7
j j j j j j -
-
-
-
-
-
-
-
-
10,16
-
-
-
9,15
-
-
-
-
-
-
-
-
--
-
1,5,11,16
1,6,12,16

f
7 10,16 9,15 1,16
7 - - - - - - - 9,11 10,16 1,16

L.g;c "I" n ... ho'd V.'~ VOHA 6 -1.065 -0980 .Q910 Vdc 1 8 - 10 11,14 12 4,5,9
- - - - - - -
~
a> - - - 8

,
10

~
6
2
3 7
~ -
~ -
- ! - - 8 - - 10 - -- - -
- ~ ! ~
v.'-r 4 7 8 10 -
Log;c "0" T",.. hold VOLA 7 - -1.630 - -1.600 - -1555 Vdc - 1 8 10 - - - - 11.14 12 4,5,9
- -- - - - - 10 - - - -
~ ~ ~
8

~ !
7
a> ' 3
<
6
6
-
- -
-
-
-
- +
8
-
-
8
-
10
10
-
-
-
-
-
-- -
- ~
~
All TefY1Mlr.tur•• VA3 VA< VAS -.l VA6
I MC1150 I +3.000 I +2.980 -2.500 I -2._
r Me1161 T +2.500 T+2.480 -3.000 -2.980
 SWITCHING TIMES (continued)
s:
....
~
(")

en
0'1
,0
F SUFFIX
POSITIVE LOGIC CERAMIC PACKAGE s:
CASE 650 n
....
V'a
V28 9 _ 0: 6
10~ ao
en
Ca 8 C a 7 00 ....
0'1

n
o
16~
V,b :J
'V2b 15 - 0 a 2 al !:!.
:J
C a 3 01
c:
(I)
TEST VOLTAGE VALUES a.
(Volt,)
@T ...
TlmJ*".tur. VRl VR2 VR3 Vx Vxx VCC(J) VEE(J)
_lODe t +2.000 +1.040 +2.00 +7.00 -3.20
+25o C 1 +2.000 S.. Note@) +1.110 +2.00 +7,00 -3.20
+8SoC +2.000 +1.190 +2.00 +7.00 -3.20 See Figure 2
MCl650F/1651F THt Limits
Pin TEST VOLTAGE APPLlEO TO PINS LISTEO BELOW
_30D e +25 oC
~ Under +85°C
~
Chlr.cterittic Symbol T. . Min M.. Min Ma. Min Ma. Unit VRI VR2 VR3 Vx VXX VCC(J) VEE(J) Pl P2 P3 P4
.".
Switching Times 110+6+ 6 2.0 5.0 2.0 5.0 2.0 5.7 ns 9 - - 8 4.5.16 11.14 12 10 - - -
Propagation Delay 110+6+ 6 - 9 - - 10 - -
(50%'050%1 110+6+ 6 - - 9 - - 10 -
V-Input to Output 110+7_ 7 9 - - 10 - - -
110+1- 7 - 9 - - 10 - -
110+7- 7 - - 9 - - 10 -
tl0~_ 6 9 - - 10 - - -
110-6_ 6 - 9 - - 10 - -
'10-<>- 6 - - 9 - - 10 -
110-7+ 7 9 - -- 10 - - -
110-7+ 7 - 9 - 10 - -
110-7+ 7 - - 9 - - 10 -
Clock to Output (l) 18+6+ 6 2.0 4.7 2.0 4.7 2.0 5.2 ns 9 - - - 4.5.16 11.14 12 10 - - 8
- - - - -
~ ~ ~ ~ ~ ~
18+6_

~ ~
6 10 9

Clock Enable Time G>

18+1+
18+7-
tsetup 10
7
7
- - 2.5 - -
!- ns
10
9
9
-
-
-
-
-
-
-
-
-
!
4.5.16
~
11,14 12
9
10
10
-
-
-
-
-
- 8
Clock Aperture Time G> teo 10 1.5 - - - ns 9 - - - 4,5,16 11,14 12 10 - - 8
R_Time '6+ 6 1.0 3.5 1.0 3.5 1.0 3.8 ns 9 - - 8 4,5,16 11.14 12 10 - - -
(10%'090%1 '7+ 7 1.0 3.5 1.0 3.5 1.0 3.8 ns 9 - - 8 4,5,16 11,14 12 10 - - -
Fill Time '6- 6 1.0 3.0 1.0 3.0 1.0 3.3 ns 9 - - 8 4,5,16 11,14 1.· 10 - - -
(10%'090%1 t7_ 7 1.0 3.0 1.0 3.0 1.0 3.3 ns 9 - - 8 4,5,16 11,14 12 10 - - -
NOTES: <D Ma)(imum Power Supply Voltages (beyond which device life may be ilT1>aired:
@) r All Tempor ••ur•• I VR2 I VR3
tvccI + tVEEI'; 12 Vdc.
(2) Unu.d clock inputs may be tied to ground. I Me1650 I +4.900 I -0.400
@ See F igur. 8. I MC1651 I +4.400 I -0.900
MC1650, MC1651 (continued)

FIGURE 1 - SWITCHING TIME TEST CIRCUIT @ 25°C

·V out to
V In to Channel A Channe' B

'~"p-+----+---+-----+-11':~:f1 fr'~
PI I
~~ I
~ ~J I
Gnd - - ,

Q~-+--"'"

Q~-~-----'

VEE·
-3.2 Vdc

50-ohm termination to ground located

in each scope channel input
All input and output cables to the scope
are equal lengths of 50-ohm coaxial cable.

·Complement of output under te.t should

always be loaded with 50-ohms to ground.

4-15
MC1650. MC1651(continued)

FIGURE 2 - SWITCHING AND PROPAGATION WAVEFORMS @2s"C

The pulse levels shown are used to check Be parameters

over the full common-mode range.

V - I nput to Output

~V'H
50%---VA 7
.._ _ _ _ _ v, L
_ _ _ _oJ

t+

Test pulses: t+. t_ =" 1.5 ±O.2 n$ (10% to 90%)

f= 5.0 MHz
50% Duty Cycle
VIH is applied to C during tests.

TEST PULSE lEVELS

Pulse 1 Pulse 2 Pulse 3
MCI650 MC1651 MCI650 MC1651 MCI650 MC1651
VIH +2.100V +2.100 V +5.000 V +4.500 V -0.300 V -0.800 V
VR +2.000 V +2.000 V +4.900 V +4.400 V -0.400 V -0.900 V
VIL +1.900V +1.900 V +4.800 V +4.300 V -0.500 V -1.000V

Clock to Output
V'H +2.100 V
PI VA +2.000 V
Vin VIL + 1.900 V

+1.'10 V
P4

C +0.310 V

a
P4, t+. C "" 1.5 ± 0.2 ns.

4-16
MC1650. MC1651 (continued)

FIGURE 3 - PROPAGATION OELAY Itpdl versus INPUT PULSE AMPLlTUOE ANO CONSTANT OVERDRIVE

Test Circuit

,-------1
Vin

Vref
t>-D
-
% Device
a II
I 50
a

I 50
V ,H C -2.0 v
C a
I I
50 L ______ ~

Vref = Gnd
'= 1
Positive Pulse Diagram Negative Pulse Diagram
Positive

j
Overdrive

"
Vm .. ~
,pr- PA
V t
V::f Pe
Negative
Ove,d,;v.
t

a 50% o
~
Input switching time is constant
at 1.5 ns (10% to 90%),

Propagation Delay versus Pulse Amplituda

5
11TT
- 4~ 1
w
T T T;]IIII
OverdrIVe Constant@100mV
I
~
- - - Positive Going Pulse
I--- - - - Negative Going Pulse
~
MC1650"
3
>
~ III tll,~
'"z MC1651,V )<
'">=
2
11:') f;(V
'"'" l-
i I

f----t- tPC! referenced to PA, Ps '" 20 mV ........ 1'

o i'-..
0.01 0.02 0.05 0.10 0.20 0.50 1.0 2.5 10
PULSE AMPLITUDE PA. PB (VOL TSI

4-17
MC1650. MC1651 (continued)

FIGURE 3 (continued)

Propagation Delay versus Overdrive

P~. p~ C;n~ta~tl~ 100 ~v I I I

2 1\ - - - Positive Overdrive (PAl

- - - Negative Overdrive (PSI
1\ tpd is measured from Vrel on the input
to 50% on the output.
\.\1 -/ MC1650

r~
1
MC1S51 ~:\
\:
~
~ tpd Isreterenced to 2.5 V overdrIve.

0 ~ II'f II I
0.01 0.02 0.04 0.07 0.10 0.2 0.3 05 0.7 1.0 2.5 10

OVERDRIVE (VOLTS)

FIGURE 4 - LOGIC THRESHOLO TESTS (WAVEFORM SEQUENCE DIAGRAM)

I
+0.020 V
Vin
-0.020 V
\ (I i
I
V 1HA
I
C I
I

Q
"'"
"0"
"1"
i\
5
"0" I
Sequential
3 4
Test Number
(See Test Table)

4-18
MC1650. MC1651 (continued)

FIGURE 5 - TRANSFER CHARACTERISTICS (0 venusVini

Test Configuration

Dif,f:~:~tia' ~ I 4>--- - - -1
Vin { o-----4~-t__"..J1: D Q~-;'-I-'----O Q
I % DeVice I
V IH o-c----1----<t------,c Q~: 50

L _____ ~

Vref ~2.0 Vdc

-2.5 Vdc ~ Vref:S;;;; +2.5 Vdc

Typical Transfer Curves

O,----r-
I---t-----t--
-----r~-~- ~-_~_ ----1--+-----1
~
G --- A,solutioo_ -- - --f-;.------+---
~
o
2': t-- --- - - - - t - - t-
w
'"
; -1j-------- [ - -
,...+--.....
- -
...--+-+-+ .........+t--...., logic "I"
-1-- - - - t - -
o
>
~
t----- t---- f--1r- - --- - ~-t--- ---
=>
~
~
=>
o
I- -- -t---t-
ci ---t------j logic "0"

-:2~O-~-175-~-1~O---5~-.r-~~-~lO~-~,~5-~20
Vrel
V m, DIFFEAENTIAllNPUT VOLTAGE (m VOLTS)

4-19
MC1650. MC1651 (continued)

FIGURE 6 - OUTPUT VOLTAGE SWING vorsus FREQUENCY

(AI Test Circuit

r-------,
""
V,
v2
t>-o Q
I
I

f
Q

V,H
C
* I

I
L ______
Y:. Device

C Q

~
I
I
I
50 50
-2.0 Vdc

(BI Tvpical Output Logic Swing versus Frequencv

v;
0.850
MC,651
....... , r---..:' ~
~ 0.650
~ l"'-~
~
l-
~
g 0.450
I\. 1\'"
\ \ f'\..'"~
.:
~
\ 1\ \\
~ 0.250 \ \ \ ~
"
~
50 75\ '00\ 200
\~O
0.050
Input Voltage
mV leak to pear- -

10 20 30 50 70 100 200 300

FREQUENCY (MHz)

v;
:;
0.850
MC,650

-r-... -....... ....... r-.... ...;;~

~ 0.650
I-
=>
.......
........
t'--,.
.........
"-
""'" "",-
" '" '"
~
I-
~ 0.450 "- \ ,\
"'"
~
~ 0.250

"
~
~
f',
50 '"'" ('-----r==-
75' 100'
\
Input Voltage
mV Peak to Peak
\
100\ lboo
0.050

10 20 30 50 70 100 200 300

FREQUENCY (MHz)

4·20
MC1650. MC1651 (continued)

FIGURE 7 - INPUT CURRENT versus INPUT VOLTAGE

TEST CIRCUIT

O.l/JFI
lr--rTo+50 Vee
Vdc

r - Vee- -Vee ---,I

'I
r---~-~~,l--it>-- °50 I
_ : 50
Q

J- i c
-2.0 Vdc

b I e Q I

lin f+ VIH:~:
I - 0 Q ,
, ,
I e Q I
I
L VEE Gnd Gnd J
0'~1--9
r'lVEE -5.2 Vdc
=

Typical MCI650 (Complementary Input Grourdedl Typical MC1SSl (Complementary Input Grourdodl

1---+--+--= ~-:---=~-+-
5I----jl--l---I---- - - -30'e +25'e
- )--
.. ' .... .'
30,--,-,--,--,-,--,-,-,--,-,--,

...+.-..~···~·
151----j--l--+--+-~-_~30~07e-+--+--

4' I---t----t--f ---+----t-+:'

.......• .~k:....."....
:;;--- -,...- - 1 10r-~r--j-_+--+--+--~-'~~~'~"'~"~'~"'-+-~
3 -
~ .... ...•.... +250C~ __

~
a.... 0
. Y:;; +85 0e ~ 15r----jI--j--+--+--Hi-~ -~~+-~+-~
___

~ 10r----j1--j-_+--+--H~~~~~--~·~~-------+--~
~ ..- -- - ---f--+---II---+--t---j ~
~
5r----jI--j--+--+-~-~-+_-+_-+~85~O~e~
j """
0b;t;_~~=+=+=+=~
-5
-5 .,.,...••...
-1.5 -1 -1 +1 +2 +2.5 -1.5 -1 -1 2 1.5
Vin.INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)

4-21
MC1650. MC1651 (continued)

FIGURE 8 - CLOCK ENABLE AND APERTURE TIME TEST CIRCUIT AND WAVEFORMS@250C

Vin to Channel A Vee = +7.0 VXX = +2.0 V out to Channel B

0:;1 hCo,
I'F:Jri_~I'F
r- Vee Gnd--'
V;no---f---<~-+-"'l+ 1
VR 0 _+-__
0 ..... ..J

-
CO--------I---""ole _ _-+1_--,
1 Or 1

1
i
1
1
1
U
L ___VEE _ _ ~
DO

e Q
1
I
1
1
1
50

r---11 T
-=- 0.' I'F 0 VEE = -3.2 Vdc

50-ohm termination to ground located

in each scope channel input.
All input and output cables to the scope
are equal lengths of 50-ohm coaxial cable.

Analog Signal Positive and Negative Slew case

Vin Negative - - - --,,\ ~----------VR + 100 mV = +2.100 V

" VA = 2.000 V
Vin Positive ---~ '- - - - -CIOCkE~abl;-VR -100 mV "" +1.900V

c ---+--.---,. VtH=+1.'10V

X-------V'L = +0.3'0 V

~V:-:--- .. , ..
-L 50%
Q Positi...,e ----+-----...r.... '--l--\j'----"O"

o Nega,;ve -----ic=---,-Pd-3-_F u! __ u': ', -%

50 .....

Clock enable time = minimum time between analog and clock

signal such that output switches, and tpd (analog to 0) is not
degraded by more than 200 ps.
- - - - - - Clock aperture time = time difference between clock enable time
and time that output does not switch and V is less than 150 mV.

4-22
 BINARY COUNTER 'l~ ________~____ __E_C_L_I_II_M_C__16_0_0_~
M __ri_es~

MC1654

The MC1654 is a four-bit counter capable of divide-

by-two, divide-by-four, divide-by-eight, or a divide-by-16
functions_ When used independently, the divide-by-16
TRUTH TABLE section will toggle at 325 MHz typically. Clock inputs
INPUTS OUTPUTS trigger on the positive going edge of the Clock pulse.
R SO Sl S2 S3 Cl C2 00 011 0 2103
Set and Reset inputs override the Clock, allowing asyn-
chronous "set" or "clear". Individual Set and common
1 a a a a <P <P
a 1 1 1 1 <P <P
a1 101°.1
1 1 a1 Reset inputs are provided, as well as complementary out-
0 a a a a 1 <I> No Count puts for the first and fourth bits. True outputs are available
a a a a a <P
.. 1 No Count
at all bits.

......
a 0 a a a a a a a
a a a a a 1 0 a a
a 0 a 0 a a 1 a a
a
a
a
a
a
a
a
a
a
a ..,. 1
a
1
a
a
1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
.... 1
a
a
1
1
1
a
a
a
a a a a a .... 1
a
1
a a
1
1
a a a a a
.. 1 a a 1

......
a a a a a a 1 a 1
a a a a a 1 1 a 1
0 a a a a a a 1 1
a
a
a
a
a
a
a
a
a
a
0
a
a
a
a
.... 1
a
1
a
1
1
1
1
1
1
1
1
Power Dissipation = 750 mW typ
f Tog = 325 MHz typ

(/J = Don t Care

Clock transition from V 1L to VIH
"VIL J V I H may be appl ied to C 1 or C2 or both
for same effect.

SO 3 00 5 S1 7 01 6 S2 9 02 11 S3 14 03 12

Q'
RT
Clock. 1 15 C1
Clock 2 C2 a C a
R

Reset 10

00 4 03 13

VCC: 1,16
VeE:: 8

See General I nformation section for packaging.

4-23
MCl654 (continued)

CIRCUIT SCHEMATIC
1/4 OF CIRCUIT SHOWN

~ >-
100 100 300 100 1 100

.J ....
~
~
>- -----t ....

<»
~
125
125

~>-
:>c x
D
...f ~~
Q 0

Cl 0 - ' - -
~~~~
60
1235
C2 f- f-
5

R
r----rt: 1- ~ ~
~ ~~ )
50 k 50 k 50 k
50
50 k k 560 1.3 k 1.3 k (05

.Iv EE
675 325 675
~ 1.5 k 1 k 1.5 k

FIGURE 1 - TOGGLE FREQUENCY TEST CIRCUIT

VCC VEE
+2.0 Vdc -3.2 Vdc

Coax Coax Coax

50 50 50

Cl 00
Clock 1nput {ot----1~--O--- 2 12
C2 03

I
3
100 50
51
9 100
52
0". 14
53 00
4
10 13
R 03
01 02
All input and output cables to 100
6 11
the scope are equal lengths of
50,ohm coaxial cable.
Open -=-

4·24
 ELECTRICAL CHARACTERISTICS
This MEeL III circuit has been designed to
me,

s
o
Clock 1 15
Clock 2

R_., 10
2
-
S03005

Cl
C2 R
11'
AT

oo! ..
51

-
c A
7

11'
AT
Qt •

c
52902'"

"

A
-
11'
AT
u

c
u

11'
AT

a
12

@Test
Temperatur V'Hmu
-JOoc
- TEST VOLTAGE VALUES
(Volts I

VILmin VIHAmi
LSUFFIX
CERAMIC PACKAGE
CASE 620

VILAmax VEE
3:
(")
....
m
~

8'
::J
~.
o 53 13 -0.875 -1.890 -1.180 -1.515 -5.2
::J
t +2SoC -0.810 -1.850 -1.095 -1.485 -5.2 C
m
+8SoC -0.700 -1.830 -1.025 -1.440 -5.2 Co
MC1654 Test limits TEST VOLTAGE APPLIED TO
Pin
Under -JOoC +25 oC +8SoC PINS LISTED BELOW:
Characteristic Symbol Test Min Max Min Max Min Ma. Unit VIHmax Vilmin VJHAmin VILAmax VEE Gnd
Power Supply Drain Current IE 8 - - - 200 - - mAde 10 - - - 8 1.16
Input Current 'in H 10 - 1.00 - - mAde 10 - - - 8 1.16
2.3.7.9.14.15 - - - 0.60 - - mAde - - - 8 1.16
1m L 10 - - 0.5 - - - j.JAdc - 10 - - 8 1.16
2.3.7.9.14.15 - - 0.5 - - - /JAde - - - 8 1.16
LogiC "1" VOH 4.13 G) -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc - 3.7.9.14 - - 8 1.16
Output Voltage 5.6.11.12 ~ -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc - 10 - - 8 1.16
LogiC "0" VOL 4.13 ~ -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc - 10 - - 8 1.16
Output Voltage 5.6.11.12 1 -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc - 3.7.9.14 - - 8 1.16
LogiC "1" VOHA 4.13 ,~ -1.065 - -0.980 - -0.910 - Vdc - - - 3.7.9.14 8 1.16
",. Threshold Voltage 5.6.11.12 4 -1.065 - -0.980 - -0.910 - Vdc - - - 10 8 1~
~ Logic "0" VOLA 4.13 ~ - -1.630 - -1.600 - -1.555 Vdc - - - 10 8 1.16
c.n Threshold Voltage 5.6.11.12 - -1.630 - -1.600 - -1.555 Vdc - - - 3.7.9.14 8 1.16
AC Characteristics PutSBln Put. Out -3.2Vdc +2.0Vdc
Clock Delays '15+4+ 4 1.0 2.9 1.0 2.7 1.0 3.1 ns - - 15 4 8 1.16

~ ~ ~
150 n Load)

~
- -

~ ~ ~
5 IS 5

~ ~
'15+5+
'2+4+ 4 - - 2 4
'2+5+ 5 - - 2 5
'15+4- 4 1.0 2.9 1.0 2.7 1.0 3.1 ns - - 15 4 8 1.16
- -

~ ~ ~
15

~ ~
5 5

~
'15+5-
'2+4- 4 - - 2 4
+ + - -

•
'2+5- 5 2 5
Set Delay t3+4+ 4 2.0 39 2.0 3.1 2.0 4.1 ns 3 4 8 1.16
t3+5_ 5 2.0 39 2.0 3.7 2.0 4.1 ns - - 3 5 8 1.16
Reset Delay '10+4+ 4 2.0 3.9 2.0 3.1 2.0 4.1 ns 10 4 8 1.16
tl0+5- 5 2.0 3.9 2.0 3.7 2.0 4.1 ns - - 10 5 8 1.16
Rise Time 14+ 4 1.0 2.9 1.0 2.7 1.0 3.1 ns 15 4 8 1.16
15+ 5 1.0 2.9 1.0 2.7 1.0 3.1 ns - - IS 5 8 1.16
Fall TIme 14_ 4 1.0 2.8 1.0 2.6 1.0 3.0 ns - - 15 4 8 1.16
IS_ S 1.0 2.8 1.0 2.6 1.0 3.0 ns - - 15 5 8 1.16
MaXimum Toggle Frequency II 3 ® 260 - 300 - 260 - MHz - - - - 8 1.16
~
--- - - -- -

-Individually apply VIH or VIL to tnput under test <D Reset all four flip-flops by applYing PAl to pm 10 @)Set all f~ur flip-flops by applYing PA2 to pins 3, 7,9,
and 14 Simultaneously.
a.> Set all four flip-flops by applYing PAt to pins 3,7,9,
and t4 Simultaneously
PA2~VIHA
Q) Reset all four fltp-flaps by applYl!lg PA 2 to pin 10 VILA

---,-VIH
PAl L..-VIL
® See Figure 1 for toggle test circuit
 MECL III MC1600 series
VOLTAGE-CONTROLLED
MUL TIVIBRATOR

MC1658

Th, MC 1658 is a voltage-controlled multivibrator which

provides appropriate level sh ifting to produce an output
compatible with MECL III and MECL 10,000 logic levels.
1~X1 ~~ CX~4 Frequency control is accomplished through the use of
voltage·variable current sources which control the slew.
" rate of a single external capacitor.
The bias filter may be used to help eliminate ripple on
vcx a 6 the output voltage levels at high frequencies and the input
filter may be used to decouple noise from the analog input
Bias Filter 12 signal.
The MC1658 is useful in phase-locked loops, frequency
Input Filter 13 Q 4
synthesizer and clock signal generation applications for
instrumentation, communication, and computer systems.

Vee1 = P n 1
VCC2 ~ P n 5
VEE = P n8

FIGURE 1 - CIRCUIT SCHEMATIC

a 4 6 a
1000
Vcx 2
12 Bias Filter

1 k

Cx 1 1 0 - - - - + - - -...... ---+ +----......- - - + - 0 1 4 Cx

250
Input Filter 1 3 0 - - - - + - - - - +......- + - + - - - - 1 - - - - - + - i

125

500 600 62 500 250

8
VEE

S•• General I nformation Section for packaglno.

4-26
 -
ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
s:n
meet the de specifications shown in the ~

test table, after thermal equilibrium has

been established. The circuit is in a test
L SUFFIX
8l
CO
socket or mounted on a printed circuit
CERAMIC PACKAGE

~
board and transverse air flow greater than ex 1 C X2 n
500 linear fpm is maintained. Outputs are 11 <>1t-Q 14
CASE 620 o
::l
terminated through a 50-ohm resistor to ~,

-
-2.0 volts. ::l
C
ct>
Vcx Q 6 F SUFFIX Q.
CERAMIC PACKAGE
CASE 6S0
Bias Filter 12

P SUFFIX
Input Filter 13 Q 4 PLASTIC PACKAGE
CASE 648

TEST VOLTAGE VALUES

Vdc±'%
Test
(@I
Temperature V,H V,L V3 VIHA I VEE
-3O"c 0.0 -2.0 -1.0 +2.0 -S.2
~ +25o C 0.0 -2.0 -1.0 +2.0 -S.2

'" +85o C 0.0 -2.0 -1.0 +2.0 I -5.2

'" Pin
Under -3O"c
MC1658 T.t Limits
+2SoC +8SoC
VOL T AGE APPLIED TO PINS LISTED BELOW:
1Vcel
Ch.racteristic Symbol Test Min M.. Min Ty. Mo. Min Mo. Unit V,H V,L V3 VIHA VEE Gnd
Power Supply Orain Current 'E 8· 32 mAde 2 1,5
8·· 32 mAde 1,5
Input Current linH 2· 350 .uAdc 1,5
I nput Leakage Current linL 2· 0.5 .uAdc 1,5
"0" High VOH 4· -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 8 1,5
Output Voltage S·· -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 VOC 8 1,5
"0" Low VOL 4· -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc 1,5
OutPUt VOltage S·· -1.890 -1.650 -1.850 -1.S20 -1.830 -1.575 Vdc 1,5
AC Charecteristics (Figure 2) VEE VCC
(Tests shown for one output, but CXl CX2 Gnd -3.2 V +2.0 V
checked on both)

Rise Time (10% to 90%) t+ 2.7 1.S 2.7 3.0 11,14 1,15
Fall Time (10% to 90%) t- 2.7 1.' 2.7 3.0 11.14 1.15

Oscillator Frequency foscl 130 130 155 175 110 MHz 11.14 1,5
fosc2 78 90 100 MHz 11.14 1,5
Tuning Ratio Test t TR 3.1 4.5 11,14 1,5
·Germaruum dIode (0.4 drop) forward bIased from 11 to 14 (11 ~ 14). C1 = O.OlI-6F connected from pin 12 to Gnd.
• -Germanium diode (0.4 drop) forward bUlSed from 14 to 11 (11 ---+t---- 141. C2 = 0.1)01 "F connected from pin 13 to Gnd.
tTR '" Output frequency at V!;;X '" Gnd CX1'" 10pF connected from pin 11 to pin 14.
OutPut frequency at VCX -2.0 V CX2 '" 5 pF connected from pin 11 to pin 14.
MC1658 (continued)

FIGURE 2 - AC TEST CIRCUIT AND WAVEFORMS

Vee
+2.0 Vdc

Input
Filter

Coax iei Cables

'---"t----o---! vex (Equal lengths, typ 2 places)
To Scope

ex

50-ohm termination to ground lo-

cated in each scope channel input.

*O.I"F All input and output cables to the

scope are equal lengths of 50-ohm
-3.2 Vdc coaxial cable. Wire length should
VEE be < 1/4 inch from TPin to input
pin and TP out to output pin.

4-28
MC1658 (continued)

FIGURE 3 - OUTPUT FREQUENCY varsus CAPACITANCE FOR FIGURE 4 - RMS NOISE O.EVIATION
VARIOUS VALUES OF INPUT VOLTAGE versus OPERATING FREQUENCY

1000

150 MHz @ 5.0 pF 10,000

1111111 1 Z
100 75 MHz @ 5.0 pF 0 Vee'" +5.2 Vdc
i= VEE' 0,0 Vde
N <
I: 35 MHz @ 5.0 pF :;; 1000
w_
~ o N
>- >-!
~ 10 u'"
w z::;
::> ~a: 100
Cl
w - Vcx o Vdc Cl
w
II: a:
U~lx
IL IL
1.0 .lllJv de /i\ 'Z. DC CONTROL INPUT' 4.0 Vde
=== 10 L III I I 11111~_LLUl
0.1 1.0 10 100
VIC~ "Ifi~ Vdt 1""- f. OPERATING FREQUENCY (MHz)

o. 1
1.0 10
11111111

CX(PICOFARODS)
100 1000
" 10,000

FIGURE 5 - FREQUENCY·CAPACITANCE PROOUCT varsus

CONTROL VOLTAGE (VCXI

...U
:;:J 1500
o CX(pf) = Frequency-Capacitance Product at Desired Vex _
o 1400
Desired Frequency (MHz)
..,.L.
a: 1300
Q.

w
U
Z
1200
--/ /'
1100
<
... /
U
<
Q.
1000
900
7' - . - --- _ . -

< 800 ./
~ /'
>- 700
U
Z 600 L
w ./
:;:J 500
aw 400
f-"'"
a:
IL 300
x
u
• -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 o

Vcx, INPUT VOLTAGE (Vde)

4-29
 MECL III MC1600 series
DUAL 4-INPUT GATE

MC1660

MC1660 provides simultaneous OR-NOR or AND-

POSITIVE LOGIC
::: : § = t i =X : 3
C y
(10) 6 2
NAN D output functions with the capability of driving
50-ohm lines_ These devices contain an internal bias
reference voltage insuring that the threshold point is
(7) always in the center of the transition region over the
(6) temperature range (-300 to +850 C)_ The input pulldown

§=x=
(11) 7
o resistors eliminate the need to tie unused inputs to VEE.
X=A+B+C+D
Y =A + B + C + D
(14) 10
(1S) " 14 (2)

(16) 12 1S (3)
(1) 13

NEGATIVE LOGIC

(8)4~A
B X
(9) S 3 (7)
(10) 6 c y 2 (6)
tpd'" 0.9 ns typ 15l0-ohm load)
== 1.1 ns typ ( 50-ohm load)
(11)

(14) 10
(1S) 11
(16) 12
7

§=x=0

14 (2)
1S (3)
X=A_S_C_O
Y=A-S-C_O
Po = 120 mW typ/pkg (No load)
Full Load Current, I L -= -25 mAde ma)(

(1) 13

Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650).

CIRCUIT SCHEMATIC

(4) (S)
16
VCC2

(6) (3)
OR 2 o---I--~~ ----+-----<D 1S OR

NOR NOR

so so so
k

4 5 6 7 8 10 11 12 13
(8) (9) (10) (11) (12) (14) (1S) (16) (1)

Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650).

See General I nformation section for packaging.

4-30
MC1660 (continued)

ELECTRICAL CHARACTERISTICS
This MECL I" circuit has been designed to
meet the de specifications shown in the
test table, after thermal equilibrium has
been established. Air flow greater than 500
linear fpm should be maintained while the
9 7
circuit is either in a test socket or is '§=t=
mounted on a printed circuit board. Test 10 6
procedures are shown for only one input 11
and one output. The other inputs and
outputs are tested in a similar manner.
Outputs are tested with a 50-ohm resistor 1
15 4 § = t = 2 F SUFFIX
to -2.0 Vdc. See general information sec- 16 3 CERAMIC PACKAGE
tion for complete thermal data. CASE 650
1

TEST VOLTAGE VALUES

(Volts)
@T ...
Temperature VIHm.x VILmin VIHAmin VILAmex VEE
_30 oe -0.875 -1.890 -1.180 -1.515 -5.2
+25 o C -0.810 -1.850 -1.095 -1.485 -5.2
+8SoC -0.700 -1.830 -1.025 -1.440 -5.2
MC1660F Test limits TEST VOLTAGE APPLIED TO
Pm PINS liSTED BELOW:
Un..... _30°C +25 o C +ssoC fVccl
Chliracteristic Svmbol Toot Min Max Min Mox Min Mox Unit VIHm.. Vilmin VIHAmin VIlAm8x VEE Gnd
Power SupplV Drain Current 'E 12 28 mAde 12 4 ••
Input Current linH 3SO /.lAde 12 4,.
linL 0 .• JlAde 12 4 .•
NOR logic "1 . Output VohaQe VOH -1.045 -0.875 -0.960 -0810 -0.890 -0.700 Vd, 8 12 4 .•

j j j j j j j •
10 j j
11
NOR Logic "0" Output Voltage VOL -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vd, 8 12 4 .•

j I j j j j • j j
~ 10
11
OR logic "'" Output Voltage VOH 6 -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vd, 8 12 4,.
•
OR logic "0" Output Voltage VOL 6
j j
-1.890 -1.650
I j
-1.850
l
-1.620
j
-1.830 -1.575
j j
Vd,
10
11
j
12
I
4 ••

NOR Logic ''1'' VOHA

j
7
j
-1.065
! j
-0.980
I j
-0.910
j j
Vd,
10
11
j
12
j
4.5

I ! j j
Threshold Voltage

NOR Logic "0" VOLA 7 -1.630

j
-1.600 -1.555
I
Vd,
10
11
12
I
4.5
•
j l j j
Threshold Voltage

OR logic "'" Threshold VOltage VOHA

I
6 -1.065 ·-0.980 -0.910
j
Vd,
10
11
8 12
j
4.5

j j j j j •
10 j j
11
OR logic "0" Threshold Voltage VOLA 6 -1.630 -1.6OQ -1.555 Vd, 8 12 4.5

j j j •
! 10
11
j I
Switching Times ISO n Load)
Propagation Delav t8+7_ 1.8 1.7 I..I.. Pul.ln Pul.Out
8 7
-3.2 V
12
+2.0 V
4.5
'8-&-
t8+6+
t8-7+
1.8
1.6
16
1.7
1.5
1.5
1.7
17
j 6
6
7
j j
Fti_Time '7+ 2.2 2.1 2.3 12 4.5
'6+ 2.2 2.1 2.3 12 4.5
Fall Time '7_ 2.2 2.1 2.3 12 4.5
'6- 2.2 2.1 2.3 12 4 ••
-'ndlvlduallv test each Input applVlng VIH or Vil to the Input under test.

4-31
MC1660 (continued)

ELECTRICAL CHARACTERISTICS
This MECL III circuit has been deligl18d to
meet the de specifications shown in the
test table. after thermal equilibrium hal
been established. The package should be

:~3
-
housed in •
suitable heat sink IIERC-
14A2CB or equivalent) or a transverse air
flow greater than SOO linear fpm should 6 2
be maintained while the circuit is either in 7
a test socket or is mounted on a printed

10~ 14
circuit board. Test procedures are shown
for only one input and one output. The 11 L SUFFIX
other inputs and outputs are tested in a CERAMIC PACKAGE
12 15
similar manner. Output$ are tested with a CASE 620
5O-ohm resistor to -20 Vdc. See general 13
information section for complete thermal TEST VOLTAGE VALUES
dete. (Voh.1
OT...
Temper_tur. VIHmu VILmin VIHAmk'l VILAm •• VEE
_30 oe -0.815 -1,890 -1.180 -1.515 -5.2
.>sOC -0.810 -1.850 -1.095 -1.485 -5.2
+86°C -0.700 -1.830 -1.025 -1.440 -5.2
MC1116DL Test LimiU TEST VOLTAGE APPLI ED TO
P ..
-3O"c .>sOC _DC PINS LISTED BELOW:
u_ IVCCI
Cher.n.inic Svmbol Tat M.. M.. M.. M.. Min M.. Unit VIHmo VILmin VIHAmin VILAmax VEE Ond
~UPPIY Drain Cur,..nt IE 28 mAde 1,18
Input Current linH 350 ~Adc 1,18
linL 0.5 /o'Adc 1,18
NOR Logic "1" Output Voltaglt VOHtP -1.045 -0.875 -0.960 -0.810 -<).890 -0.700 Vd, 1,16

j I 1 1 1 1 w,1 1
NOR LogiC "0" Output Voltage VOl. tP -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 1,18

j ! 1 1 l 1 1 1
OR Logic "1" Output Voltage VOHtP -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vd, 1,16

j ! 1 1 l I 1 1
OR Logic "0" Output Volta. VOL41 2 -1.890 -1.650 -1.850 -1.620 -1.830 -'.575 Vd, 1,'6

I j j 1 1 1 1 1 1
NOR Logic "'" VOHAtP 3 -'.065 -0.980 -0.910 Vdo 1,16
Threshold Voltage

I j 1 1 1 1
NOR Logic "0" VOLAtI> 3 -1.630 -1.600 -1.555 Vd, ',18
Threshold Voltage

I j 1 j 1 1
OR Logic "'" Threshold Voltage VOHA41 -'.065 -0.980 -0.910 Vdo 1,16

OR Logic "0" Threshold Voltage VOLAtP

I -1.630
1 1 I -1.600 -1.555 Vd,
1
1,16

j 1 1 1
Switcl'ling Times (50 n load) Pul.ln Pul.Out -3.2 V +2,0 V
Propagation Delay 14+3- 18 1.7 1.9 4 3 8 1,18
1.7 "'
I 1
18 1.9

I 1
t4_2_ 2
t4+2+ 16 1.5 1.7
t4-3+ 1.6 15 1.7
Ri. Time '3· 2.2 2.1 2.3 ',16
'2. 2.2 2.1 2.3 4 1,16
Fall Time '3-
'2-
2.2
2.2
2.1
2.1
2.3
2.3 •
4
1,16
1,16
-IndiVidually test each Input applying VIH or VIL to the Input under test. tP NOTES
The electrical spacifiClltions shown abow apply to the MCl880
under the following conditions:
1. The packagl is hou.d in a suitable "'at sink. t
D'
2. Air is blown transwr.ly ovar the PICkage. See 91ne,..1
information section for mora details.

tA suitable heat sink is an IERC UC14A2U or equivalent.

4-32
MC1660 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS. 25°C

Vin to Channel "A" V out OR V out NOR

To
Channel
"8"
Coax Coax

Input 50 , - - - - --., 50 50
~____~~__;'__~ I
I
Pulse Generator

§xt:
I
All input and output cables to
the scope are equal lengths of
50-ohm coaxial cable.
I I
I I
100 L ______ ...JI 100 100

Input Pulse t+ =:: t- = 1.5 i.O.2 ns

Unused outputs connected to 8 50-ohm resistor to ground

PROPAGATION DELAY

,-----+1.11 V

+0.31 V
V out OR

t+
t-

V out NOR

4-33
 MECL III MC1600 series
QUAD 2-INPUT "NOR" GATE

MC1662

Four 2-input NOR or NAND gating functions

in a single package. An internal bias reference
POSITIVE LOGIC NEGATIVE LOGIC voltage insures that the threshold point remains
in the center of the transition region over the
(8)

(9)
4~
S
B 2 (6)
(8)

(9) S
4~ B 2 (6)
temperature range (-30 to +850 C).
Input pulldown resistors eliminate the need

~==Lr--3 (10)6~3
(10) to tie unused inputs to VEE.
(7) (7)
(11 ) (11) 7

(14)10~ (14)10~
14 (2) 14 (2)
(lS) 11 (lS) 11

(16)12~ (16)12~
15 (3) lS (3)
(1) 13 (1) 13

X= A+B x = .A""iB
tpd "" 0.9 ns typ (510-ohm load)
=
1.1 ns typ (50-ohm load)

Po == 240 mW typ/pkg (No load)

Full Load Current. I L = -25 mAde max

Number at end of terminals denotes pin number of L package (Case 620).

Number in parenthesis denotes pin number for F package (Case 650).

CIRCUIT SCHEMATIC

(11 ) (10) (4) (S) (8) (9)

6 4 5

(7) 3 --++--<J 2 (6)

so k 50 k 50 k so k

14 - - - + - . 0 1 5 (3)
(2)

50 k 50 k so k 50 k

VEE
10 11 8 12 13
(14) (15) (1)
(12) (16)

See General I nformation section for packaging.

4-34
 s:
....
(")
0)
0)
N
(')
ELECTRICAL CHARACTERISTICS o
This MECL III circuit has been designed to
....
::J
::J
meet the dc specifications shown in the c:

~
(1)
test table, after thermal equilibrium has CL
been established. Air flow greater than SOO
linear fpm should be maintained while the
circuit is either in a test socket or is ~ CERAMIC
~~ FSUFFIX
PACKAGE
mounted on a printed circuit board. Test
procedures are shown for only one input :~6 CASE 650
and one output. The other inputs and 10~7
outputs are tested in a similar manner 11~
Outputs are tested with a 5!klhm resistor
to -2.0 Vdc. See general information sec· 14~2 TEST VOLTAGE VALUES
15 (Volts)
tion for complete thermal data.
1~~3
@Test
Temperature VIHma)( Vil min VIHAmin VILAm . . VEE
-ao"C -0.875 -1.890 -1.180 -1.515 -5.2
+2SoC -0.810 -1.850 -1.095 -1.485 -5.2
~ +850 C -0.700 -1.830 -1.025 -1.440 -5.2
W
(J1 Pin
MCl662F Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW,
Und .. -ao"C +25o C "-SSoC
Characteristic Symbol Test Min Ma. Min Ma. VIH max Vil min VILA max VEE Gnd
Min Ma. Unit VIHA min
Power SupplV Drain Current 'E 12 - - - 56 mAde - 12 4.5
Input Current lin H - 350 - - /-lAde 12 4.5
lin L 0.5 ~Adc 12 4,5
Logic "'"
Output Voltage
VOH 6 -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 8 - 12 4.5
6 -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc - 9 - - 12 4,5
Logic "0" VOL -1.890 -1.650 1.620 12 4,5
6 -1.850 -1.830 ·1.575 Vdc 8
Output Voltage -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 9 - - - 12 4.5
6 Vdc
Logic "1" VOHA -1.065 - -0.980 - -0.910 - Vdc - 8 12 4.5
6
Threshold Voltage -1.065 -0.980 -0.910 Vdc - - - 9 12 4.5
6
Logic "0" VOLA 6 - ·1.630 - -1.600 - -1.555 Vdc 8 12 4.5
Threshold Voltage 6 -1.630 -1,600 - -1.555 Vdc - - 9 - 12 4.5
Switching Times (50 n Load) Pulse In Pulse Out -3.2 V +2.0V
Propagation Delav t8-6+ 6 - 1.6 - 1.5 - 1.7 ns 8 6 - - 12 4.5
t8+6_ 6 1.8 - 1.7 - 1.9 ns 8 6 - - 12 4.5
Rise Time '6+ 2.2 2.1 2.3 ns 8 6 12 4,5
6
Fall Time '6 2.2 2.1 2.3 ns 6 12 4,5
6 8
Individually test each input applying VIH or VIL to input under test.
 S
n
....
0)
0)
ELECTRICAL CHARACTERISTICS N
(")
This MECL III circuit has been designed to o
::J
meet the dc specifications shown in the ::!.
test teble, after thermal equilibrium has ::J
been established. The package should be c:
CII
housed in a suitable heat sink (I ERC· CL

-
14A2CB or equivalent) or a transverse air
L SUFFIX
flow greater than 500 linear fpm should
CERAMIC PACKAGE
be maintained while the circuit is either in
CASE 620
a test socket or is mounted on a printed
circuit board. Test procedures are shown
for only one input and one output. The :~2
other inputs and outputs are tested in a
similar manner. Outputs are tested with a ~~3
5O-ohm resistor to -2.0 Vdc. See general 10~ TEST VOLTAGE VALUES
information section for complete thermal 11~i4 (Volts)
deta. @IT ...
12~ Temperature VIH rna. VILmin VIHAmin V,LA me. VEE
13~15
-3O"c -0.875 -1.890 -1.180 -1.515 -5.2
~ +2SoC -0.810 -1.850 -1.095 -1.485 -5.2
W
C)
+85"C -0.700 -1.830 -1.025 1.440 5.2
MC1662L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BelOW,
Uncle. -3O"c +25o C +8S0C
Characteristic SVmbol Test Min Max Min Max Min Max Unit VIHmax VILmin VIHAmin VILA mal( VEE Gnd
Power Supply Drain Current IE 56 mAde 1.16

~
Input Current 350 .uAdc 1.16

Logic "1"
Output Voltage
lin L
VOH -1.045
-1.045
-0.875
-0.875
05
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
1 -0.700
-0.700
,uAde
Vdc
Vdc
1,16
1.16
1.16
Logic "0" VOL -1.890 -1.650 -1.850 -1.620 -1.830] -1.575 Vdc 4 1.16
Output Voltage -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc 1.16
Logic "1" VOHA -1.065 - -0.980 - -0.910 Vdc 4 1.16
- -
Threshold Voltage
Logic "0"
Threshold Voltage
VOLA
-1.065
1.630
-1.630
-0.980
-
-
-1.600
-1.600
-0.910
-
-
J -1.555
-1.555
Vdc
Vdc
Vdc
4
5
5 1.16
1.16
1,16
Switching Times (50 n Load) Pulse In Pulse Out -3.2V +2.0V
Propagation Delay t4+2+ 1.6 1.0 1.5 - 1.7 1,16
t4_2_ 1.8 1.1 1.7 I - I 1.9 1.16
Rise Time '2+ 2.2 1.4 2.1 - I 2.3 1,16
Fall Time '2_ 2.2 1.2 2.1 I - I 2.3 1,16
-Individually test each Input applying VIH or VIL to input under test.
MC1662 (continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS@2S0C

V out

Coaxial Cables
(Equal lengths, typ 2 places)
To Scope

Input
50
r - - - ---,
50
~5~0%_-r---
~-{--~r-+---~~ ~~I____~
I ~:-+
i:Lr+
Pulse Generator

100 100

I I

~
~.J
L ______
Input Pulse t+ "" L = '.5 (±O.2) ns
Unused outputs connected to a 50-ohm resistor to ground.

4-37
 MECL III MC1600 series
QUAD 2·INPUT "OR" GATE

MC1664

Four 2·input OR or AND gating functions

in a single package. An internal bias reference
POSITIVE LOGIC NEGATIVE LOGIC voltage insures that the threshold point remains
in the center of the transition region over the
181
191
:~2161 181
191
4~
B
5
2 161
temperature range -30 to +850 C.
Input pulldown resistors eliminate the need
to tie unused inputs to VEE.
~~3
11016~ __ 1101
171
11117~3171 1111
114110~ 114110~ 14 (
115111~14121
2)
115111
116112~ 116112~15131
11113~15(31 111 13---""L.....J

tpd = 0.9 ns typ (Sl()..ohm load)

veel = Pin 1 (5)
.., 1.1 "I typ (50-ohm load)
VCC2 = Pin 16141
VEE = Pin 8 (12) Po = 240 mW tvp/pkg (No load)
Full Load Current, I L ::: -25 mAde max
Number at end of terminals denotes pin number of L packaga (Case 6201-
Number in parenthesis denotes pin number for F package (Case 650).

CIRCUIT SCHEMATIC

1111 1101 141 151 181 191

7 6 16
VCC2

"""---+-+--<> 2 161
171 3

50k 50 k 365 2. 1958 2 k 365 50 k 50k

--..1--"15
(2114 131

50k 50k 365 2 k 1958 2 k 365 50 k 50k

VEE
10 11 8 12 13
(14) (15) 1121 1161 111

S_ General I "formation Mctio" for packaging.

4·38
 ELECTRICAL CHARACTERISTICS 3:
This MECL III circuit has been designed to ....
C')

~
meet the dc specifications shown in the
test table, after thermal equilibrium has ~
been established. Air flow greater than 500 n
linear fpm should be maintained while the o
::J
circuit is either in a test socket or is ~.
mounted on a printed circuit board. Test ::J
procedures are shown for on IV one input
c:
~

~
and one output. The other inputs and CL
outputs are tested in a similar manner.
Outputs are tested with a 50-ohm resistor
to -2.0 Vdc. See general information sec·
tion for complete thermal data. F SUFFIX

:~6
CERAMIC PACKAGE
CASE 650

10~
11 ~ 7

14~
15 ~ 2

16~ TEST Val TAGE VALUES

1 ~3
.j:o
W
CO @T ...
(Volts)

Temp8fature VIH max V'l min V'HA min V'LAmax VEE

_lODe -0.875 -1.890 -1.180 -1.515 -5.2
+2SoC -0.810 -1.850 -1.095 -1.485 -5.2
+8SoC -0.700 -1.830 -1.025 -1.440 -5.2
MC1664F Test Limits
Pin TEST VOLTAGE APPLIED TO PINS lISTEO BELOW:
_lODe +250 C +8S0C
Und .. 1Vee l
Characteristic Symbol Test Min Max Min Max Min Max Unit V'H max Vll min VIHA min VILA max VEE Gnd
Power SupplV Drain Current 'E 12 56 mAde 12 4.5
Input Current lin H 350 .'lAde 12 4.5
~ 05 /JAde 12 4.5
LogiC "1" VOH -1.045 -0.875 -0960 -0.810 -0.890 -[ -0.700 Vdc 8 12 4.5
Output Voltage
logic "0"
Output Voltage
Val
-1.045
-1.890
-1.890
-0.875
-1.650
-1.650
-0.960
-1.850
-1.850
-0.810
-1.620
-1.620
-0.890'
-1.830
-1.830
J-0.700
-1.575
-1.575
Vdc
Vdc
Vdc
9 12
12
12
4.5
4.5
4.5
LogiC "1" VOHA -1.065 -0.980 -0.910 Vdc 8 12 4.5
12
J
Threshold Voltage -1.065 -0.9S0 -0.910 Vdc 9 4.5
Logic "0" VOLA -1.630 -1.600 -1.555 Vdc 12 4,5
Threshold Voltage -1.630 -1.600 -1.555 Vdc 12 4.5
Switching Times (50 H Load) Pulse In Pulse Out -3.2V +2.0V
Propagation Delay 1.6 1.5 6 12 4.5
18+6+
t8_6_ 1.8 1.7 I 1
17
19 6 12 4.5
Rise Time '6+ 2.2 2.1 I 2.3 6 12 4.5
Fall Time '6_ 2.2 2.1 I I 2.3 6 12 4.5
·Indivldually test ea~h Input applYing VIH or VIL to Input under test.
 s:
ELECTRICAL CHARACTERISTICS ...
(")

m
This MECL III circuit has been designed to
IIIMt the de specifications shown in the ~
test table, after thermal equilibrium has n
o
been established. The package should be :l
houled in a suitable heat sink OERC· ~.
:l
14A2CB or equivalent) or a transverse air

-
C
flow greater than 500 linear fpm should ct>
CL
be maintained while the circuit is either in
a test lOcket or is mounted on a printad
circuit board. Test procedures are shown
for only ona input and one output. The :~2
other inputs and outputs are tested in a LSUFFIX
similar manner. Outputs are tested with a
5().ohm resistor to -2.0 Vde. See general
~~3 CERAMIC PACKAGE
CASE 620
information section for complete thermal tO~ 14
data. 11~
12~
13~15 TEST VOLTAGE VALUES
IVoIts)
,I::> @Test

~ Temperature VIH max V'lmin V'HA min V,LA max VEE

o _30 De -0.875 -1.890 -1.180 -1.515 -5.2
+2S o C -0.810 -'.850 -1.095 -1.485 -5.2
+8SoC -1).700 ·1.830 -1.025 -1.440 -5.2
MCl664L Test Limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BelOW,
Under -JO"c +250 C +8S0C
Characteristic Sy ... bol Tost Min Max Min Max Min Max Unit V'H max VILmin VIHAmin VILA max VEE Gnd
Power Supply Drain Current IE 56 mAde 8 1.16

~
Input Current 350 ~Adc 1,16
'in L 05 .uAdc 8 1,16
Logic ''1'' VOH -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 1,16
Output Voltage -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 1,16
Logic "0" VOL -1.890 -1.650 -1.850 -1.620 -1.830 -1.515 Vdc 1.16
Output Voltage -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc 1,16
Logic "1" VOHA -1.065 -0.980 -0.910 Vdc 1,16
Threshold Voltage -1.065 -0.980 -0.910 Vdc 1,16
Logic "0" VOLA -1.630 -1.600 -1.555 Vdc 1,16
Threshold Voltage -1.630 -1.600 -1.555 Vdc 1,16
Switching Times (50 n Load) Pulse In Pulse Out -3.2 V +2.0V
Propagation Delay 14+2+ 1.6 1.5 1.7 8 1,16
'4-2- 1.8 1.7 1.9 8 1,16
Rise Time '2+ 2.2 2.1 2.3 1,16
Fall Time '2_ 2.2 2.1 2.3 8 1,16
·lndividually test each input applying VIH or VIL to input under test.
MC1664(continued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS 0 2SD C

V In to Chennel "A" V out to Channel "s"

Coax

~
+1.11V

50 50 50%
Input r-----...,
, I ----+0.31 V
t- - t++
PUI .. Generetor I
100 ~ 100 V out
-+-L-./I
I I

~
-=

~
AU input and output cables to
the scope are equal lengths of
L _ _ _ _ _ ..I 50-ohm coaxial cable.
Input Puis. t+., C.,. 1.6 (±O.2) ns

Unused outputs connected to a 50-ohm resistor to ground.

4-41
 DUAL CLOCKED R-S FLIP-FLOP
MECL III MC1600 series

MC1666

This device consists of two Set· Reset flip· flops in a

single package which require a clock input to enable the
POSITIVE LOGIC set·reset inputs. Internal input pull·down resistors eliminate
the need to return unused inputs to a negative voltage.
(9) (6) The device is usefu I as a high-speed dual storage element.
2
(11) 5
7 C =t
t
(8) 4 A a 3 (7)

(16) 1 2 t = t 0 15(3)
(14) 9 C
11) 13 R a 14 (2)

tpd "" '.6 ns tvp (51 O-ohm load)

= 1.8 ns typ (50-ohm load)

P D = 220 mW typ!pk 9 (No Load)

TRUTH TABLE
S R C °n+1 vee1 = Pin 1 (5)
<I> <I> 0 On VCC2 = Pin 16 (4)
0 0 On VEE = Pin 8 (12)
1 0 1
0 1 0
1 N.D.
(/) - Do n't Care Numbers at ends of terminals denote pin numbers for L package (Case 620).
N.D. = Not Defined Numbers in parenthesis denote pin numbers for F package (Case 650).

CIRCUIT SCHEMATIC

C VCC2 S a Q R vee1 R Q ·0 S C
(14) (4) (16) (2) (3)11) (5) (8) (6) (7) (9) 111)
9 16 12 14 15 13 1 4 2 3 7

50 k

8
(12)
Vee
Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650).

See Ganeral Information section for packaging.

4-42
 3:
ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
....
(")

en
en
~
meet the de tp8cifications shown in the
test table, aft.r thermal equilibrium has F SUFFIX en
bean established. Air flow greater than 500 CERAMIC PACKAGE r;-
linear fpm should be maintained while the CASE 650 0
6
circuit is either in a test socket or is 9c U
11 ::l
8 A 7 a ~.
mounted on a printed circuit board. Test TEST VOL TAGE VALUES ::l
procedures are shown for only one input (Volts) C
ro
and one output. The other inputs and
outputs are tested in a similar manner.
16U3
14 c
@Test
Temperature V'Hma)( VILmin VIHAmln VllAmax VEE
I a.
Outputs af. t.sted with a 5CHlhm resistor 1 A a 2 -JOoC -1 515
-0875 -1.890 -1 180 -5.2
to -2.0 Vdc. See general information sec- +25 0 C -0.810 -1.095 -1 485 -5.2
-1.850
tion for complete thermal data.
+8SoC -0700 -1 830 -1 025 -1 440 -5.2
MC1666F Test Limits TEST VOL TAGE APPLIED TO
Pon
-30°C +2SoC +85 PINS LISTED BELOW: (Vee l
Under
Characteristic I Symbol I Test Min M" Mon M" Min Max Unit VIHmax VILmln VIHAmm VILAmaM VEE Gnd
Povver Supply Drain Current I IE CD 12 55 - mAde 11.14 12 4.5
Input Current
I ImH I 1
16
- 0.370
0370
-
-
mAde
mAde
1.14
14.16
12
12
4.5
4.5
14 0.225 - mAde 14 12 4.5
ImL 16 - 0.5 - - /JAde 16 12 4.5
1.14 0.5 jJAdc 1,14 12 4.5

~
I. 0" LOyle .. , , Output Voltage VOH
3
3 $
-, 045 -0875 ·0.960 -0 810 -0 890 -0700 Vrl, - 1 12 4.5
3 -, 045 -0875 -0 960 -0810 -0.890 -0700 Vdc 14 - 12 4.5
~
(.oJ
I "0" Lagle "0" Output Voltage VOL
3~
35
-1 890
-1 890
-1650
-, 650
-1 850
-1 850
-1 620
-1620
-t 830
-1 830
-1 575
-1 575
Vrl,
Vdc
-
14
16
-
12
12
4.5
4.5

22~
"0" Lagle "1 'Output Voltage VOH -1 045 -0.875 ·0.960 -0 810 -0 890 -0700 Vrl, - 16 12 4.5
5 -1 045 ~O 875 -0 960 ·0810 -0 890 -0700 Vd, 14 - 12 4.5

~~
"0' Lagle' 0" Output Voltage VOL -1 890 -1 650 -1 850 -1 620 -1 830 -, 575 Vdc - 1 12 4.5
-1 890 -1 650 -1850 -1 620 -1830 -1 575 Vrl, 14 - 12 4.5
"0" LogiC .. ,., Output
33~
VOHA -1.065 -0.980 -0910 Vrl, - 16 1 12 4.5
Threshold Voltage 7 -1.065 ·0.980 - -0910 Vdc 1 14 - 12 4.5
"0" LogiC "0" Output VOLA 3@ -1630 -1 600 -1.555 Velc 16 12 4.5
1
Thleshold Voltdge
"0" LogiC "1" Output VOHA 2@ -1 065 -0 980 -0910 Vdc 1 16 12 4.5
Threshold Voltage
"0" Logic "0" Output VOLA 2@ -1630 -1 600 ., 555 Vdc 16 1 12 4.5
Threshold VOltage 2(Z) -1630 -1600 -1.555 Vd, 14 14 - 12 4.5
SWitching Times (50 H Load) Pulse In Pulse Out -3.2 V +2.0V
Clock Input 114+3+ 3 10 2.7 10 25 11 2.8 ns 14 3 12 4.5

~
t14+3- 3 3 -

t14+2- 2 2
114+2+ 2 2 -
• • • • • •
-

Set Input t16+3+ 3 1a 2.5 10 23 11 2.7 ns

•
16 3
•
12
•
4.5

! ~ ~
2

~
t16+2-

! !
16 2 12 4.5
Reset Input 11+2+ 3
"' ..
ns 1 2 12 4.5
11+3- 2 ns 1 3 12 4.5
Rise Time ,. 2.3 08 2.8 0.8 20 09 2.9 ns 14 2.3 12 4.5
Fall Time ,- 2.3 05 2.4 05 22 05 2.6 ns 14 2.3 - 12 4.5

o Notes appear on page lollowlng Elecl(lcal Characte(lstlcs tables

 ELECTRICAL CHARACTERISTICS 3:
This MECL III circuit has been designed to n
....
meet the de specifications shown in the
test table, after thermal equilibrium has O'l
O'l
been e.tablished. The package should be O'l
hou.d in a suitabte heat sink (lERC-
L SUFFIX C"l
14A2CB or equivalent) or a transverse air

'U
0
flow gr.ater than 500 linear fpm should CERAMIC PACKAGE ~
7 C 2
be maintained while the circuit is either in CASE 620 !:!.
a test socket or is mounted on a printed
4 R a 3 ~
c:
circuit board. Test procedures are shown TEST VOL TAGE VALUES
I CO
for only one input and one output. The
other inputs and outputs are tested in a
similar manner. Outputs are tested with a
!iO-<>hm ...istor to -2.0 Vdc. See general
"U"
9
13
C
A a 14
@Test
Temperature
-JoDe
VIHmax
-0.875
(Volts)

VILmin VIHAmin
-1.890 -1.180
v,LAmaxl Vee
-1.515 I -5.2
C-

information section for complet. thermal +25 0 C ·0.810 ·1.850 -1.095 -1 485 -52
deta. +8SoC -0700 -1.830 -1.025 -1.440 I -5.2
MC1666l Test limits TEST VOL rAGE APPLIED TO
Pin
-lOoe +2S o C +8S PINS LISTED BELOW: (Vee l
Under
Characteristic I Symbol IT... Mo" M .. Min M •• Mon M. . Umt VIHmax VILmin VIHAmin V'LAmax VEE Gnd

P01/\le1 Supply Drain Current I 'E <D 55 mAde 7.9 1,16

Input Current
I lonH I 12
13
0.370
0370
mAde
mAde
9,12
9,13
1,16
1,16
9 0.225 mAde 9 1,16
IlnL 12 0.500 /JAde 12 1,16
9.13 0.500 9,13 1,16
I
/J.Adc
~ 1,16
"0" LogiC "'" Output Voltage VOH -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 13 8
.j:. 15$
15 -1.045 -0.875 -0.960 -0.810 -0890 -0.700 Vdc 8 1,16
~
"0" LogiC "0" Output Voltage VOL 15
15
~ -1.890
-1.890
-1.650
-1.650
-1.850
-1.850
-, 620
-1.620
-1 830
-1.830
-, 575
-1575
Vdc
Vdc
12 8 1,16
1,16
8

'4 ~
"Ci" LogiC "'" Output Voltage VOH -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 12 1,16
14 5 -, 045 -0875 -0.960 -0.Bl0 -0.890 -0.700 Vdc 1,16
"a" LogiC "0" Output Voltage VOL 14 ~ -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc 13 1,16
14 -1890 -, 650 -1.850 -1.620 -1 830 -1.575 Vdc 1,16
"Q" Logic" 1 " Output VOHA 15~ -1.065 -0.980 -0.910 Vdc 12 13 8 1.16
Threshold Voltage 15 -1.065 -0.980 -0.910 Vdc 13 9 8 1,16
"0" LogiC "0" Output VOLA 15 <ID -1.630 -1.600 -1.555 Vdc 13 12 8 1,16
Threshold Voltage
"0" LogiC "1" Output VOHA 14@ -1.065 -0.980 ·0.910 Vdc 13 12 1,16
Threshold Voltage
"0" Logic "0" Output
Threshold Voltage
VOLA 14
14
~ -1.630
-1.630
-1.600
·1.600
-1.555
-1.555
Vdc
Vdc 13
12
9
13 1,16
1.16
SWitching Times (SO 12 Load) Pulse In Pul_Ou -J.2V +2.0 V
Clock Input 19+15+ 15 10 2.7 10 2.5 1.1 2.8 9 15 8 1.16
15

t t
15

t t
19-+15-

Set Input
t9+14-
t9+14+
14
14
15 10
t t
1.0 2.3 1.1 2.7
t
12
14
14
15
t t
t12+15+ 2.5 1.16
I.
~ ! ! ! i ~
112+14- 14 12 1.16
Reset Input 113+14- 14 13 14 1.16
\13+15+ 15 13 15 1.16
Rise Time .+ 14.15 0.8 2.8 0.8 2.5 0.9 2.9 9 14,15 1,16
Fall Time t- 14.15 0.5 2.4 0.5 2.2 0.5 2.6 14,15 1.16

o Notes appear on page following Electrical Charactenstics tables.

MC1666(continued)

NOTES

G) I E is measured with no output pull-down resistors.

(SLV'H)VIL
® Apply Sequentially: Vin1 to C (VIH to VIL)
Vin2 to S (VIH to VIL)
H
1
I L
@ Apply Sequentially: Vin1 to A (VIH to VIL)
Vin2 to S (VIH to VIL)
~ ,:>5", l-
H ® Apply Sequentially: Vin1 to C (VIH to VIL)
Vin2
f L
Vin2 to R (VIH to VIL)

® Apply Sequentially: Vin1 to S (VIH to VIL)

H Vin2 to R (VIH to VIL)
Vin3
~ test
L ® Apply Vin3 to C (VIH to VIL)

(J) Apply Vin3 to S (VIH to VIL)

4-45
Me 1666 (conti nued)

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @25 0 C

Vin V out
To Channel "A" To Chanr.el "8"

All input and output cables to

the scope are equal lengths of Coax 100 Coax Coax
50-ohm coaxial cable.

50 50 50

C2
+2.0 Vdc Q2

1/2

02
52 R2
g g
Input pulses 51
by 2 pulse I
generators ----'----- --~

1 50
Plo---~,,~------------_+----~t->---------------lr_,----~5~0~il~c~o-a-x~-o5 Vin
To Channel "A"

100 100
50

MC1670 ---+1.11 V
Pl
o P2
-----
n ::::120 n.I----------------'
1\-
+0.31 V
-----+1.11V
'-----------+0.31 V

SET/RESET TO a/a ta_

(Switch Sl in position shown)
a

to+

CLOCK TOO/a
(Switch S1 in opposite position)
Q

4-46
 MECL III MC1600 series
DUAL CLOCKED LATCH

MC1668

This device is a Dual Clocked Latch/R-S Flip-Flop.

POSITIVE LOGIC Whenever the Clock is low, the R-S inputs control the
output state. Whenever the Clock is high, the output fol-
lows the data (D) input.
(9) 5
~
S
(10) 6-0 a ""'-----2 (6) TRUTH TABLE
S R D C On+1
(11 ) 7 - C 0""'-----3 (7) 0 0 0 On
R I 0
'" 0 I

(8) 4 ~
0
I
I
I
''""
0
0 ..
0

'"
0 I 0

''"" ''""
(16) 12 I I I
~ •• Output state not defined <P = Don't Care
S
(IS) 1 1 - - 0 O~15(3)

(14) 9 - C a~'4(2)
R Vee1 = Pin 1 (5)
VCC2 '" Pin 16 (4)
(1) 13
~ VEE = P;n 8 (12)

tpd = '.6 ns typ (510-ohm load)

'" 1.8 ns typ (50-ohm load)
Numbers at ends of terminals denote pin numbers for L package (Case 620). Po = 220 mW typ/pkg (No load)
Numbers in parenthesis denote pin numbers for F package (Case 650).

CIRCUIT SCHEMATIC

C VCC2 0 0 a VCCI a o 0 C
9 16 11 14 VEE 15 1 2 VEE 3 6 7
(14) (4) (IS) (2) 8 (12) (3) (5) (6) 8(12) (7) (10) (II)

50 k 50 k

50

(16) (I) (12) (8) (9)

12 13 8 4 5
S R VEE R S

Numbers at ends of terminals denote pin numbers for L package (Case 620).
Numbers in parenthesis denote pin numbers for F package (Case 650).

See General Information section for packaging.

4-47
 ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
meet the de specifications sho,""", in the
test table, after thermal equilibrium has
1:~6 16~ F SUFFIX
~ ..
3:
n
0)

~
15 0 S: 3
been established. Air flow greater than CERAMIC PACKAGE

11~7
500 linear fpm should be maintained while CASE 650
14 R 2
the circuit is either in a test socket or is
mounted on a printed circuit board. Test
C Q
8
~
1
procedures are shown for selected inputs B '*
~
and selected outputs. The other inputs C
and outputs are tested in a similar manner. TEST VOLTAGE VALUES (I)
C.
Outputs are tested with a 50-ohm resistor @Test (Volts)
to -2.0 Vdc. See general information VIHA min VILA mex Vee
section for complete thermal data. -1.180 -1.515 -5.2
-1.095 -1.485 -5.2
+8so cl -0.700 I -I.H.JU -1.u25 -1.440 -5.2
MC1668F Test Limits
Pon TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Under
-lOoe +25 0 C +8soe (Vee)
ChliracteristlC Symbol THt Min I Mu Min I Mu Min I Max Unit VIH mulVIL min I VIHA min I VILA max I VEE Gnd
Power Supply Ora In Current 'E 12 n 55 mAdc 11,14 I 12 4,5
Input Current lin H 1.15,lS(l) 0.370 mAdc 1.15,16 12 4,5
13 0.225 mAdc 14 12 4,5
lin L 1,15,16~ 0.500 .'lAdc 1.15.16 12 4,5
13 0.500 /.IAdc 14 12 4,5
"a" LogiC "1" VOH 3~ -1.045 -0.875 -0960 -1.810 -0.890 -0.700 Vd, 12 4,'
Output Voltage 3@ -1.045 -0.875 -0.960 -1.810 -0.890 -0.700 Vd, 14 12 4,5

~
"0" LogiC "0"
Output LogiC
VOL 3e
3@
-1.890
-1.890
-1.650
-1.650
-1.850
-1.850
-1.620
-1.620
-1.830
-1.830
-1.575
-1.575
Vd,
Vd, 14
16 12
12
4,5
4,5
,i:.
CX)
r.u" LogiC "1"
Output Voltage
VOH 2@
2@
-1,045
-1.045
-0.875
-0.875
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vd,
Vd, 14
16 12
12
4,5
4,5
"a" LogiC "a" VOL 20> -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vd, 12 4,'
Output Voltage 2@ -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vd, 14 12 4,5
"a'"Logic "1'" Output VOHA 3 -1.065 -0.980 -0.910 Vd, 16 12 4,5
Threshold Voltage 3<i)
t 15

"0" LogiC "0'" Outpu t

Threshold Voltage
VOLA
3@
3
3@
• -1.630
• -1.600 • -1.555 Vd,
15 14
16
15
•t
12
+
4,5

'"0" LogiC "I" Output

Threshold Voltage
VOHA
3@
2
2@
-1.065 • -O'r o
+ -0.910

t
• • Vd,
15 14
16
15
12

t
+
4,5

"0" LogiC "0" Output

Threshold Voltage
VOLA
20>
2
2<i)
• -1.630 -1.600

t
-1.555 •t
Vd,
15 14
16
15
12
+
4,5

2@ + + 14 +
•
'i'
Switching Times (50 n Load) Pulse In IPulseout -32 V +2.0 V
Clock Input t13"'3+
113+3-
t,3"'2-
t13+2+
1.0

~
2.7

~ '[
2.5

~ 'r 2f or 3 I! 4,5

~
AiseTime ,+ 2,3 0.8 2.8 0.9 2.5 0.9 2,9 14 2,3 12 4,5
Fall Time t- 2,3 0.5 2.4 0,5 2,2 0.5 2.6 14 2,3 12 4,5
Set Input t16+3+ 1.0 2.5 1.1 2,3 1.1 2.7 16 12 4,5
116+2- 1.0 2,5 1.1 2.3 1.1 2.7 16 12 4,5
Reset Input 11+2'" 1.0 2,5 1.1 2.3 1.1 2,7 12 4,5
t1-l-3- 1.0 2.5 1.1 2.3 1.1 2.7 12 4,5

ONotes appe.. on page following Electrical Characteristics tables.

 ELECTRICAL CHARACTERISTICS

5~ 12~
-
This MECL III circuit has been designed to :s::
meet the de specifications shown in the
test table, after thermal equilibrium has
60 S Q 2 11 0 S Q 15
....
C')
0)
been established. The package should be
~
9 C RQ1 14
housed in a suitable heat sink (I ERC·LIC· : C R Q 3
214A2WCB or equivalent) or a transverse LSUFFIX
airflow greater than 500 linear fpm should 13 CERAMIC PACKAGE
8
be maintained while the circuit is either in a
test socket or is mounted on a printed
CASE 620
...
::J

::J
circuit board. Test procedures are shown c:
for selected inputs and selected outputs.
~
TEST VOLTAGE VALUES
The other inputs and outputs are tested in (Volts)
@lTest
a similar manner. Outputs are tested with Temperature VIH max Vil min VIHA min VILA max VEE
8 5O-ohm resistor to -2.0 Vdc. See general -30°C -0875 -1.890 ~ ':T5i'5 'TI
information section for complete thermal +2SoC -0.810 -1.850 -1.095 -1.485 ·52
data. +S50C -0.700 -1.830 -1025 ~ ~
MCl668L Test Limits
Pin TEST VOL TAGE APPLIED TO PINS LISTED BELOW;

Chilractaristic Symbol
Under
T... Min
-100C
I Max Min
+2SoC
I Max Min
+8S o C
I Max Unit
I
VIH maxlVIL min I VIHA min I VILA max VEE
I (Vee I
Gnd
Power Supply Drain Current IE (HI'Z) 11 55 mAde 7,9 I 1,16
Input Current 1m H 1'1,'2,13(2) 0.370 mAde 11,12,131 1,16
9 0.225 mAde 9 1,16
lin L 111.12.13(i) 0.500 jJAdc 11,12,13 1,16
9 0.500 jJAdc 9 1,16
"0" LogiC "1"
Output Voltage
VOH 15@
15@
-1.045
-1.045
I -0.875
-0.87~
-0.960 1-1.810
-0.960 -1.810
-0.890
-0.890
I -0.700
-0.700
Vdo
Vdo
13 1,16
1,16

"'.i:-" "0" Logic "a"

Output Logic
VOL 15@
1~
-1.890 1-1.650
-1.890 -1.650
-1.850
-1.850
1-' 620
-1.620
-1.830
-1830
I -1.575
-1.575
Vdo
Vdo
12 1,16
1,16
CC "O"Logic "1"
Output Voltage
VOH 14@
14®
-1.045 1-0.875
-1.045 -0,875
-0.960 1-0.810
-0.960 -0.810
-0.890
-0.890
I -0.700
-0.700
Vdo
Vdo
12 1,16
1,16
I
,
"0" Logic "0" VOL 14 Q) -1.890 1-1.650 -1.850 1-1.620 -1.830 -1.575 Vdo '3 1,16
Output Voltage 14@) -1.890 -1.650 -1.850 -1.620 -1830 -1.575 Vdo 1,16
"0" LogiC "1" Output VOHA 15 -1.065 -0.980 -0.910 Vdo 12 13 8 1,16

,•
Threshold Voltage 15 (i)
"
"0" LogIC "0" Output
Threshold Voltage
VOLA
15
15
15®
®
• -1630 -1600

"f V1•
11 9
13 12
11
• •
8 1,16

"0" Logic" '" Output VOLA

15Q)
14 -1.065 -0.980
• -0910
V1
11
13 12 •t •
8 1,16

,
Threshold Voltage 14® 11

"0" Logic "0" Output

Threshold Voltage
VOLA
14Q)
14
14 (i)
• -1.630 -1.600

t
• -1555 Vdo
11
12
11
13 8 • 1,16

Switching Times (SO n Load)

14®
• • • I
PUI~ In Pul~_Out
9

•
-3.2 V +2.0 V

't
Clock Input 15 2.7 1.0 1.1 2.8
2! 15

l
t9+15+

Rise Time
t9+15-
t9+14-
ts+14+
.+
,-
15
14
14
14,15 0.8
~
2.8
~
0.9 2.5
•
0.9
~
2.9
~
15
14
14
14,15
1T 1,16
Fan Time 14,15 0.5 2.4 0.5 2.2 0.5 2.6 14,15 1,16
Set Input 112+15+ 15 1.0 2.5 1.1 2.3 1.1 27 12 15 1,16
t12+14- 14 1.0 25 1.1 23 1.1 27 12 14 1,16
Reset Input 113+14+ 14 1.0 25 1.1 2.3 1.1 2.7 13 14 1,16
tt3+15- 15 1.0 25 1.( 2.3 1.1 27 13 '5 1,16

ONotes appear on page following Electneal Characterlstic51ables

MC1668 (continued)

NOTES

CD I E is measured with no output pulldown resistors.

® Test voltage applied to pin under test. @) Apply S8Cluentially: Vinl to R (V,H to VIL)

(SLVIH)
--.~--.
H Vin2 to C (V'H, V,L)
Vin3 to 0 (V,H to V,L)

V,L Vinl

~ 1~5 ns

Vin2
H ® Apply Sequentially: Vinl to S (V,H to V,L)
Vin2 to C (VIH. V,L)

~5 ns (i)
H
---{ Apply Sequentially: Vinl to A (V,H to V,L)
- Vin2 to C (V,H. V,L)
Vin3
L
~5 ns~ ~
t"" 0 test

4-50
Me 1668 (continued)

SWITCHING TIMES TEST CIRCUIT AND WAVEFORMS@250C

Vin V out
To Channel "A" To Channel "S"

All input and output cables to Coax Coax

Coax 100
the scope are equal lengths of
50-ohm coaxial cable. Vee'" +2.0 Vdc
VEE = -3.2 Vdc

50 50

Cl C2
50
01 02

1/2 1/2

D Ql D Q2
51 Rl 52 R2
o 0
o 0

I nput pulses Plv---~T<~__________~______________________~~~__~5AO~-U====J--05

by 2 pulse
eenerators
P2v--~I<~+_ _ _ _ _ +____________-l--~_-,\5A°;"""--fI-J._OR Coax Vin
To Channel "A"

Coax
100 100

--+1.11 V
Pl
+0.31 V
P2 r-\ r-'\---. ---- +1.11 V
- - - - - - : : ] 2 0 n,f-~-----.J '------- +0.31 V

SET/RESET TO a/a '0-

(Switch 51 in position shown)
0

5
to+

CLOCK TOO/a
(Switch S1 in opposite position)

4-51
 MC1670

The MC1670 is a Type D Master-Slave Flip-Flop
designed for use in high speed digital applications.
Master slave construction renders the MC1670 rela-
tively insensitive to the shape of the clock waveform,
since only the voltage levels at the clock inputs control
the transfer of information from data input (D) to output.
When both clock inputs (Cl and C2) are in the low
state, the data input affects only the "Master" portion of
the flip-flop. The data present in the "Master" is trans-
ferred to the "Slave" when clock inputs (Cl "OR" C2) are
taken from a low to a high level. In other words, the out-
put state of the fl ip-flop changes on the positive transition
of the clock pu lse.
While either Cl "OR" C2 is in the high state, the
"Master" (and data input) is disabled.
Asynchronous Set (S) and Reset (R) override Clock (C)
and Data (D) inputs.
Input pulldown resistors eliminate the need to tie unused
inputs to VEE.

POSITIVE LOGIC NEGATIVE LOGIC

1915 S--------, 191 5 S------,

1111 7 C1 1111 7 e:1~ro,r-"

a 2 161 1141 9 C2-_____../1 a 2 161
1141 9 C2

1151 11 D a 3 171 1151 11 D a 3 171

181 4 R------" 1814 R-------.J

Number at end of terminal denotes pin number for L package (Case 620).
Number in parenthesis denotes pin number for F package (Case 650).

veel = Pin 1 (5)

VCC2 = Pin 16 (4)
VEE::: Pin 8 (12)

Power Dissipation = 220 mW typical (No Load)

TRUTH TABLE
ftog = 350 MHz typ
R S D C On+1
L H 4> 4> H
H L 4> 4> L
H H 4> 4> N.D.

TIMING DIAGRAM L L L L an
L L L -F L
L L L H On
C L L H L On
L L H ...r H

\'------ L L H H On
<p - Don t Care
a NO = Not Defined
CsC1 +C2

See General Information Mction for packsging.

4-52
MC1670 (continued)

ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to
9 S
meet the de specifications shown in the

~
tlst table, after thermal equilibrium has
been established. Air flow greater than 500 11 C1 ~ .... ,:-
Q 6
linear fpm should be maintained while the 13 C2
circuit is either in •
test socket or is
mounted on 8 printed circuit board. Test
procedures are shown for only one input
F SUFFIX
and ana output. Th. other inputs and 15 0 Q 7 CERAMIC PACKAGE
outputs .r. tested in •similar manner .
Outputs are tested with a 50-0hm resistor
CASE 650

to -2.0 Vdc. See general information sec- S A 1 TEST VOL TAGE VALUES
tion for complete thermal data. (Volts)

@THO
Temperature VIHmu VILmin VIHAmin VILAmu VEE
-lOoe -0875 -1890 -1.180 -1.515 -5.2
+25 o C -0.810 -1.850 -1.095 -1485 -5.2
+85 o C -0.700 -'.830 -1.025 -1.440 -5.2
MC1670F Test Limits TEST VOL TAGE APPLIED TO PINS

....
Pin -lOoC +2SoC +8S o C LISTED BELOW:
(VCCI
Uod«
CharacterIstIC THO
Power SupplV Drain
Symbol
12
Min M.. Min
48
M. . Unit
mAde
VIHma .. VILmln VIHAmin VILAm ... VEE
12
'1
" '3 GmI
4,5
Input Current " 550 /JAde 12 4,5
l,n H
550
14
11
15
250
250
270 J
14
11
15
j j
l,n L 8 0.5 /JAde 12 4,5

I
14
14
11
15
j 11
14
14
14
11
15 J
Logie "1" VOH -1045 -0.875 -0.960 -0.810 -0890 -0.700 8.11.15 12 14 4,5

j j
Output Voltage 15 9.14 11
j j j j j 15 9,11
8.14.15
Logic "0" VOL -1.890 -1.650 -1.850 -1.620 -1.830 -1575 15 9,11 12 14 4.5
8,14,15
j j j
Output Voltage
j
11
j j j 15
8.11.15
9,14
j 9 14

Logic "I" VOHA -1.065 -0.980 -0.910 Vdo 8.11.15 12 4.5

Threshold VOllag-e 15 9.14 11

Logic "0"
Threshold Voltage
VOLA
I I -1.630 -1.600
j
-1555
j
Vdo
15

15
9,11
8.14.15
9.11
8,14
9.11
8.14.15
15
15 I
12
8

11
11
11
j
4,5

I j j 15
8.11.15
9.14
8.11
9.14 15
15 j
9

11
14
11

I
Switching Parameters
Clock to Oulpul Delay 111+6+ 14,6
Min
1.0
"'.
2.7
Min
1.1
....
2.5 1.1
....29
-32
~
12
+2.0
~
4,5
(See Figure 11 111_6- 14.6
111+7_ 14.7
111_7+ 14.7
Set to Output Delay 19+6+ 9.6
(See FIgure 2) 19+6- 9,'
Rewt to Output Delay 18+6_ 8.6
(See FIgure 21 18+7+ .,7
OutpIJt
Rise T,me 16+7+ 6.7 0.9 2.7 1.0 2.5 10 2.9
Fall Time 16_7_ 6.' 0.5 2.1 0.6 1.9 0.6 2.3
(See Figure 21
Set Up Time ts"I" 0.4
(See Figure 31 Is"O" 05
Hold Time tH"I" 03
(See Figure 3) tH"O" 0.5
Toggle Frequency 'Tog 270 300 270 MH,
(See Figure 4)

VIH m a . = n . . - - - - 1 . . -

::::::~;
:"
VILmin P2

V'HA I I
VILA ~3

~5nl ~ Ta.,

4-53
Me 1670 (conti nuedl

ELECTRICAL CHARACTERISTICS

!_I~
This MECL III circuit has been designed to
5 S
meet the de specifications shown in the
te .. table, after thermal equilibrium hes
been established. The package should be 7 C1
2
housed in •
suitable he.t sink ilEAC·
14A2CB or equivalent) or a transverse air
9 C2
Q

flow greater than 500 line.r fpm should

be maintained while the circuit is either in LSUFFIX
8 test socket or is mounted on 8 printed CERAMIC PACKAGE
circuit board. Tast procedures are shown
11 0 is 3
CASE 620
for onlv one input and one output. The
other inputs and outputs ar. te.ted in a 4 R I TEST VOLTAGE VALUES
timilar manner. Outputs af' t.,ted with 8 {VoIU)
5().ohm rl.istor to -2.0 veSc. See general
information section for complete thermal n",
Tempeorltur. VIHm... vlLmm VIHAmin VILA max VEE
data. _30°C -0.875 -1.890 -1.180 -1.515 -5.2
+25°C -0.810 -1.850 -1.005 -1.485 -5.2
+B50C -0.700 -1.830 -1.025 -1.440 -5.2
MC1670L Tnt Llmln TEST VOLTAGE APPLIED TO PINS
Pin -JOoC +25 0 C +8SoC LISTED BELOW: (VCCI
U""~
Char.cterlstiC Symbol T", Min M•• M.. M.. Unit VIHmu: VILmin VIHAmin VILAm. . Ve, P, P2 P3 G""
Power Supply Dra,n 'E 8 48 mAdc 7,9 8 1,16
Inpul Curren' I,n H 550 uAdc 1.16
SSO
250

11
250
270 J 11 J
''''L 4 05 uAde
• 1.16

11 J J
Log,c'I' VOH 2 -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdo 4,7,11 5 .. 1,16
OUIVul Vollage 3 5.9

LOg'c "0" VOL

I j I I I
-1890 1650 -1850 -1.620 -1830 -1.575
j
Vdo 11
5,7
4.9,11
5,7 1,16

j
OulPUI Voltage 4,9.11
j j j j j 4,7,11
5,9
Log,c"l" VOHA -1.065 -0.980 -0.910 Vdo 4.7.11 5 1,16
Threshold Voltage 5,9

j j j j j
5,7
4.9,11
5.7
4,9 11
Log,c"O' VOLA -1.630 -1600 -1555 Vdo 5,7 1,16
ThreshOld Voltage 4,9,11
4,7,11

j j 5,9
4,7
5,9 11
11 j
~wllcn,ngParamelers

Clock 100"lpul Delay 17+2+ 9,2 , 0

M.. ....
2,9
-32

~
+2.0

~
1,16
(SeeFlg..orell t7_2_ 9,2
27
" 25 1.1 8

17+3- 9,3
17_3+ 9,3
Sel 10 OulPuI Delay '5+2+
(See Figure 21
Resel IOOulpu! Delay
15+3_ "
5,3
14+2- 4,2
(See Figure 2) '4+3+ 4,3
Output
R'se Time '2+. 13. 2,3 09 27 1.0 2' 1.0 2,9
Fall Time 12-. 13- 2,3 05 21 0,6 '9 06 2,3
(See Figure 21
Set Up Time '5"1" 04
(See Figure 3) 15"0" 05
HOld Time IH"'" 03
(See F'gure 31 'H"O" 05
Toggle Frequency' 270 300 270 MH,
(See Figure 41 I""

4-54
MC1670 (continued)

FIGURE l-PROPAGATION DELAY TEST CIRCUIT

+2.0 Vdc

20 ll FI Coax

50

All input and output cables to

the scope are equal lengths of
50-ohm coaxial cable.
Clock
Input Pulse
Generator
TP out
Data
Input Pulse
Generator

100

l O 1IlF
.

-3.2 Vdc

TP in Clock
+0.31 V

TPin Data

CLOCK DELAY WAVEFORMS

@2s"C
TP out Q

TP out a

FIGURE 2 - SET·RESET DELAY WAVEFORMS@250C

~-,--------- +1.11 V
TPin Set
' - - - - - - - - +0.31 V

TP out

TP out a

4·55
MC1670 (continued)

FIGURE 3 -SET UP AND HOLD TIME TEST CIRCUIT

+2.0 Vdc

Input Pulse (O+--+-+----~

Generators
Q~----~

(ol--~>---+-----'''' 0 All input and output cables to

the scope are equal lengths of
50-ohm coaxial cable.

Open [:

100 t 50 100

l O. 1 1'F

-3.2 Vdc

SET UP TIME WAVEFORMS@ 2s"C

, - - - - -...... - - - - - - + 1 . 1 1 V

' - - - - - - - +0.31 V

TPin2 Clock
+0.31 V

~
TP out Q Output
\'---
HOLD TIME WAVEFORMS @ 250 C

,..----+1.11 V

" - - - - - - ' , - - - - +0.31 V

TPin2 Clock
+0.31 V

QoutPut~
TPout
\'------'/
Set up time I, the minimum time before the positive transition of the clock pulse (C) that information mUlt
be pr...nt at the data (D) Input.
Hold time I, the minimum tlma after the positive tranlitlon of the clock pulse (e) that information mUlt
remain unchangad at the dna (D) input.

4-56
MC1670 (continued)

FIGURE 4 - TOGGLE FREQUENCY TEST CI RCUIT

+2.0 Vdc

Coax
Coax

50
l o.... F

al"'-----~

Sine-Wave Generator, All input and output cables to

the scope are equal lengths of
50-ohm coaxial cable.

VSias = 0.71 Vdc

(Use High '00
I mpedance Probe
to Adjust VBias)

I o. 1IlF
50

de Supply -3.2 Vdc

FIGURE 5 - TOGGLE FREQUENCY WAVEFORMS

TA = 2 SoC

-+1.11V
Clock Input
300 --- +0.71 V Sias
The maximum toggle frequency of the MC1670
MHz-max
-+0.31 V has been exceeded when either:
1. The output peak-To-peak voltage swing falls below
600 mill ivoln.

aora
Output
-r
600 mV min
OR
2. The device ceases to toggle (divide bV two).

FIGURE 6 - MAXIMUM TQGGLE FREQUENCY (TYPICAL)

+1.050 -,
+1.000
+0.950
+-0.900
'6 +0.850
C +0.800
- ......... .......
.....
TA
Vee
Vee
=
=
::<
2SoC
+2.0 Vdc
-3.2 Vdc
Figure 6 illustrates the variation in toggle frequency with the
de offset voltage (VBia,) of the input clock ,ignal. VBia, i, defined
by the test circuit in Figure 4, and waveform Figure 5.
~ +0.150
~ +0.700 '\ Figures 8 and 9 illustrate minimum clock pulse width recom·
~ +0.650
1+0 .500
ii +0.450
- ./ mended for reliable operation of the MC1670.

> +0.400
+0.350
+0.300
+0.250
.75 225 275 325 375 425

fTog (MHz)

4-57
MC1670(continued)

FIGURE 7 - TYPICAL MAXIMUM TOGGLE FREQUENCY

.ersus TEMPERATURE

400

350

300
1".000
, - -
250

-30 o 25 50 85

T A. AMBIENT TEMPERATURE (oC)

FIGURE 8 - MINIMUM "DOWN TIME" TO CLOCK

OUTPUT LOAD = 50 n

I
- - CJCK
.1
;-... --
I 1\ V
L j 1
o or ~ i ..L J II
r \J ~
10 ns/OIV

FIGURE 9 - MINIMUM "UP TIME" TO CLOCK

OUTPUT LOAD = 50 n

I_
V\ a or a r--
.1 /'

r yI
I
L f\ CLOCK

1.0 ns/DIV.

4-58
MC1670 (continued)

u ~Cl
u
>
<>----L
--:.c'Cl
=n
----:"1-
~

~
A A
~
~,i

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4·59
 TRIPLE 2-INPUT
MECL III MC1600 series
EXCLUSIVE-OR GATE

MC1672

This three gate array is designed to provide the positive

logic Exclusive-OR function in high speed applications.
POSITIVE LOGIC These devices contain a temperature compensated internal
bias which insures that the threshold point remains in the
3~
(8)
center of the transition region over the temperature range
S8 2 (6)
(9)
(-30°C to +85 0 C). Input pulldown resistors eliminate the
(16)
13~
6 14 (2)
need to tie unused inputs to VEE.
(10)
(14)
(11)
1:~lS(3)
X=AeS+Aes

ve e l = Pin 1 (5)
NEGATIVE LOGIC VCC2 == Pin 16 (4)
VEE == Pin 8 (12)
(8)
3~2(6)
S B
(9)
tpd == 1.1 ns typ (5l0-ohm load)
(16)
(10)
1:~14(2) == 1.3 os typ (50-ohm load)
Po = 220 mW typ/pkg

1:~lS(3)
Full Load Current, IL = -25 mAde mal(
(14)
(11)

X=AeB+Aes

Number at end of terminal denotes pin number fOl" L package (Case 620).
Number in parenthesis denotes pin number for F package (Case 650).

CIRCUIT SCHEMATIC

VCC2 Vee,
16 (4) 2 (6) 14 (2) 7( 11) 1 (S)

(3)
......-+-1-<> 15

3 (8) 8 13 (16) 11 (14)

(12)
VEE

Number at end of terminal denote. pin number for L package (Case 620).
Number in parenthesis denote. pin number for F package (Ca.. 650).

S . . General 1nformation section for packaging.

4-60
 ELECTRICAL CHARACTERISTICS
This MECL III circuit has been designed to ...3:
C')

~ ~
meet the de specifications shown in the
test table, after thermal equilibrium has
I\)
been established. Air flow greater than
500 linear fpm should be maintained while
the circuit is either in a test socket or is F SUFFIX
8
::I
~
mounted on a printed circuit board. Test CERAMIC PACKAGE
procedures are shown for selected inputs ::I
CASE 650 c:
and selected outputs. The other inputs
and outputs are tested in a similar manner. 8~_X.6
9~
a
Outputs are tested with a 50-ohm resistor
-2.0 Vdc. See general information
16~2
to

TEST VOL TAGE VALUES

(Volts)
@l Tost
Temperature VIHmax V'Lmin VIHAmin VILAmax VEE
-3O"c -0.875 -1.890 -1.180 -1.515 -5.2
+25"c -0.810 -1.850 -1.095 -1.485 -5.2
+85"c -0.700 -1.830 -1.025 -1.440 -5.2
MC 1672F To.t Limits TEST VOLTAGE APPLIED TO
Pin
Under -30"c +25"c +85"c PINS LISTED BELOW (Vce)
~ Characteristic Symbol Test Min Max Min Max Min Max Unit V,Hmax V'Lmin VIHAmin V,LAmax VEE Gnd

~ Power Supply Drain Current IE 12 - - - 55 - - mAde

..
All Inputs - - - 12 4,5
Input Current linH 8,14,16 - - - 350 - - "Adc - - - 12 4,5
0.75 linH
linL .
9,10,11 -
-
-
-
-
0.5
270
-
-
-
-
-
"Adc
"Adc -
-
. -
-
-
-
12
12
4,5
4,5
Logic "1" Output Voltage VOH 6 -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 8 9 - - 12 4,5
6 -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vdc 9 8 - - 12 4,5
Logic "0" Output Voltage VOL 6 -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc 8,9 - - - 12 4,5
6 -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vdc - 8,9 - - 12 4,5
Logic "I" Threshold Voltage VOHA 6 -1.065 - -0.980 - -0.910 - Vdc - - 8 9 12 4,5
6 -1.065 - -0.980 - -0.910 - Vdc - - 9 8 12 4,5
Logic "0" Threshold Voltage VOLA 6 - -1.630 - -1.600 - -1.555 Vdc - - 8,9 - 12 4,5
6 - -1.630 - -1.600 - -1.555 Vdc - - - 8,9 12 4,5
Switching Times (50 n Load) Pulse In Pulse Out
Propagation Delay '8+6+ 6 - 2.0 - 1.8 - 2.3 ns - - 8 6 12 4,5
t8-6+ - 2.0 - 1.8 - 2.3 - -
'8+6- - 2.1 - 1.9 - 2.4 - -
t8-6-
t9+6+
t9-6+
'9+6-
t9-6-
j -
-
-
-
-
2.1
2.5

+
-
-
-
-
-
1.9
2.3

+
-
-
-
-
-
2.4
2.8

+
j -
-
-
-
-
-
-
-
-
-
+
9

+
j jj
Rise Time t6+ 6 - 2.7 - 2.5 - 2.9 ns - - 8 6 12 4,5
Fall Time '6_ 6 - 2.4 - 2.2 - 2.6 ns - - 8 6 12 4,5

-Individually test each input applving V I H or V IL to input under test.

 ELECTRICAL CHARACTERISTICS s:(')
This MECL III circuit has been designed to ...a
~
meet the de specifications shown in the
test table, after thermal equilibrium has
been established. The package should be N

-
housed in a suitable heat sink IIERC·LlC-
214A2WCB or equivalent) or a transverse 8
airflow greater than 500 linear fpm should ....
::J

be maintained while the circuit is either in a ::J

C
test socket or is mounted on a printed
circuit board. Test procedures are shown
for selected inputs and selected outputs. 3~2
LSUFFIX
CERAMIC PACKAGE
a
The other inputs and outputs are tested in 5~ CASE 620

1:~14
a similar manner. Outputs are tested with
a 50-ohm resistor to -2.0 Vdc. See general
information section for complete thermal
data.
1~~15

TEST VOLTAGE VALUES

(Volts)

.".
"T ...
Temper.lure VIHmu Vllmin VIHA min I VILA tUX 1 VEe

m
~
-JO"c
+25 o C
+8Sac
-0.875
-0.810
-1.890
-1.850
-1.180
-1.095
-1.515
-1.485
-5.2
-5.2
-0.700 -1.830 -1.025 -1.440 -5.2
MC1672L Tnt limits
Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW:
Und_ -JO"c +25o C +8SOc (Vee l
Characteristic Symbol T... Min M.. Min M.. Min M.. Unit VIHmu VILmin VIHA min VILA IMX VEE Gnd
Power Supply Drain Current
"
8 •• mAde All Inputs
• 1,16

Input Current I.., H 3,11.13 350 J.lAde 1,16

0.751.., H 5.6,7 270 ,.Ad, 1,16
'mL 0.' /.lAde 1,16
LogIC "'" VOH -1.045 -0.875 -0.960 -0.810 -0.890 -0.700 Vd, 1,16
Output Voltage ·".045 -0.875 -0.960 -0.810 -0.890 -0.700 Vd, 1,16
Logic "0" VOL -1.890 -'.650 -1.850 -1.620 -1.830 -1.575 Vd, 3,' 1,16
Output Voltage ·1.890 -1.650 -1.850 -1.620 -1.830 -1.575 Vd, 3,' 1,16

Logic "'" VOHA -1.065 -0.980 -0.910 Vd, 1,16

Thremold Voltage -1.065 -0.980 -0.910 Vd, 1,16
Logic "0" VOLA -1.630 -1.600 -1.555 Vd, 3,' 1,16
Threshold Voltage -1.630 -1.600 -1.555 Vd, 3,' 1,16
SWltchmg Tunes (50 n LoatU Min M.. Min M.. Min Max Pul.ln Pul.Out -3.2 V +2.0 V
PropagatIon Delay t3+2+
t3-2+
2.0
2.0
1.•
1.•
2.3
2.3 "' 3 2
• 1,16

t3+2_