INTEL MCS 296

Specifications of Processing unit:

Operating frequency: 50MHz
On-chip memory:
RAM:2 Kbytes
Adress space: 6 Kbytes
Accumulator size: 40 bit

On-chip peripherals:
The MCS-296's EPA contains two 16-bit timers and 10 capture-and-compare modules. An event
interrupt generates edges, starts A/D conversions, and resets timers. The HSIO structure has as
many as four input and six output timer/counter driven lines. The 296 also supports a peripheral-
transaction server that is a microcoded, hardware-interrupt handler for responding to data
transfers, starting an A/D conversion, and performing similar tasks.The 8xC196NU and 80296SA
include a PLL. With the PLL, an external clock drives the deviceat one-half or one-fourth the
maximum internal clock frequency. Therefore, a 196/296 system supports a lower frequency
external clock or oscillators while maintaining the maximum internal operating frequency. The
296's chip-select unit allows you to window some external memory locations for direct
addressing, an improvement over the 196.

I/O interfaces:
The microcontroller contains two 4-bit I/O ports and three 8-bit I/O ports. Each port pin can
function as a general-purpose I/O signal or as a special-function signal. General-purpose I/O
signals provide a mechanism to transfer information between the microcontroller and the
surrounding system circuitry. They can read system status, monitor system operation, output
microcontroller status, configure system options, generate control signals, provide serial
communication, and so on. Special-function signals are associated with on-chip peripherals or
system functions.Each port contains dedicated special-function registers (SFRs) that allow you to
select a pin’s mode, configuration, and output value, and read a pin’s input value.

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Register File: A register file is an array of processor registers in a central processing unit.The
register file is divided into an upper register file and a lower register file. The upper register file
consists of general-purpose register RAM. The lower register file contains additional general-
purpose register RAM along with the stack pointer (SP) and the CPU special function
registers (SFRs).

Register set:
Some of the SFR’s of MCS296 are
Stack pointer(SP):

PSW(Processor status word):

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 INTEL MCS 296

ACC_0x(Accumulator register):

Some of other SFR’s are interrupt control, timer control, timer value, serial port control ,serial
port status etc.

INSTRUCTION SET: CISC

The mcs-296 family is a family of highly complex CISC processors with more than 200
instructrions.

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NUMBER OF INSTRUCTIONS WITH CLASSIFICATION

The MCS-296 has approximately 220 instructions comprising one, two, or three operands. Some
instructions are more than one word.
Example:-

SPECIAL INSTRUCTIONS:
Math instructions include add, subtract, multiply, divide, and multiply-accumulate. Special
instructions include a block move of data; indirect-autoincrement addressing; and a table-
indexed jump, which lets you jump via a table value.
Example:-

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ENHANCED INSTRUCTION SET

There are 17 new and modified instructions for the 80296SA, each listed in Table 3-2. These
instructions for handling digital signal processing routines can be divided into four basic
categories:
• Add and subtract instructions — ADDC and SUBC
• Multiply-accumulate (MAC) instructions — MAC, MACR, MACRZ, MACZ, SMAC,
SMACR, SMACRZ, and SMACZ
• Move instructions — MSAC and MVAC
• Repeat instructions — RPT, RPTxxx, RPTI, and RPTIxxx
Additionally, the return from interrupt (RETI) instruction reduces interrupt overhead to aid in
implementing multiply-accumulate operations.

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 INTEL MCS 296

ADDRESSING MODES
This section describes the addressing modes as they are handled by the hardware.
The instruction set uses four basic addressing modes:
• Direct
• Immediate
• Indirect (with or without autoincrement)
• Indexed (short-, long-, or zero-indexed)
1. Direct Addressing
Direct addressing directly accesses a location in the 256-byte lower register file, without
involving the memory controller. Windowing allows you to remap other sections of memory into
the lower register file for direct access. You specify the registers as operands within the
instruction. The register addresses must conform to the alignment rules for the operand type.
Depending on the instruction, up to three registers can take part in a calculation. The following
instructions use direct addressing:
ADD AX,BX,CX ; AX ¬ BX + CX
ADDB AL,BL,CL ; AL ¬ BL + CL

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MULBAX,BL ; AX ¬ AX ´ BL
INCB CL ; CL ¬ CL + 1
2. Immediate Addressing
Immediate addressing mode accepts one immediate value as an operand in the instruction. We
specify an immediate value by preceding it with a number symbol (#). An instruction can contain
only one immediate value; the remaining operands must be direct references. The following
instructions use immediate addressing:
ADD AX,#340 ; AX ¬ AX + 340
DIVB AX,#10 ; AL ¬ AX/10; AH ¬ AX MOD 10
3. Indirect Addressing
The indirect addressing mode accesses an operand by obtaining its address from a WORD
register in the lower register file. You specify the register containing the indirect address by
enclosing it in square brackets ([ ]). The indirect address can refer to any location within the
address space,including the register file. The register that contains the indirect address must be
word-aligned,and the indirect address must conform to the rules for the operand type. An
instruction can contain only one indirect reference; any remaining operands must be direct
references. The following instructions use indirect addressing:
LD AX,[BX] ; AX ¬ MEM_WORD(BX)
ADDB AL,BL,[CX] ; AL ¬ BL + MEM_BYTE(CX)
3.1 Extended Indirect Addressing
Extended load and store instructions can use indirect addressing.
3.2 Indirect Addressing with Autoincrement
We can choose to automatically increment the indirect address after the current access. The
following instructions use indirect addressing with autoincrement:
LD AX,[BX]+ ; AX ¬ MEM_WORD(BX); BX ¬ BX + 2
3.3 Extended Indirect Addressing with Autoincrement
The extended load and store instructions can also use indirect addressing with autoincrement.
The following instructions use extended indirect addressing with autoincrement:
ELD AX,[EX]+ ; AX ¬ MEM_WORD(EX); EX ¬ EX + 2
3.4 Indirect Addressing with the Stack Pointer

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We can also use indirect addressing to access the top of the stack by using the stack pointer as the
WORD register in an indirect reference. The following instruction uses indirect addressing with
the stack pointer:
PUSH [SP] ; duplicate top of stack; SP ¬ SP – 2
4 Indexed Addressing
Indexed addressing calculates an address by adding an offset to a base address.
There are three variations of indexed addressing: short-indexed, long-indexed, and zero-indexed.
4.1 Short-indexed Addressing
In a short-indexed instruction, you specify the offset as an 8-bit constant and the base address as
an indirect address register (a WORD). The following instructions use short-indexed addressing.
LD AX,12H[BX] ; AX ¬ MEM_WORD(BX + 12H)
4.2 Long-indexed Addressing
In a long-indexed instruction, you specify the base address as a 16-bit variable and the offset as
an indirect address register (a WORD). The following instructions use long-indexed addressing.
LD AX,TABLE[BX] ; AX ¬ MEM_WORD(TABLE + BX)
4.3 Extended Indexed Addressing
The extended load and store instructions can use extended indexed addressing. ELD
AX,OFFSET[EX] ; AX ¬ MEM_WORD(EX+OFFSET)
4.4 Zero-indexed Addressing
In a zero-indexed instruction, you specify the address as a 16-bit variable; the offset is zero, and
you can express it in one of three ways: [0], [ZERO_REG], or nothing. Each of the following
load instructions loads AX with the contents of the variable THISVAR.
LD AX,THISVAR[0]
4.5 Extended Zero-indexed Addressing
The extended instructions can also use zero-indexed addressing. The only difference is that you
specify the address as a 24-bit constant or variable. The following extended instruction uses zero
indexed addressing. ZERO_REG acts as a 32-bit fixed source of the constant zero for an
extended indexed reference.
ELD AX,23456H[ZERO_REG] ; AX ¬ MEM_WORD(23456H)

Memory details-

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Type of memory architecture

The Intel MCS-296 is a family of microcontrollers (MCU), an improved version of the Intel
MCS-96, while remaining compatible. The family is often referred to as the 80296. The MCU
has improved math performance making it practical in embedded digital signal processing (DSP)
and feedback control systems
MCS-96 compatibility, pipeline architecture, 6 MB addressable space, 2 KB code/data RAM, 40-
bit accumulator, fast hardware multiplier and accumulator, and 512 Byte register RAM.
An on chip memory controller lets MCS-96/296 use a range memory types and speeds.
Most MCS-96/296 device can access as much as 64 kbs of memory ; some versions can extend
this memory range to 16 Mbytes.
The CPU can use auto programming to program the internal EEPROM with 8 bit external data
interface.

FEATURE BENEFITS

Size of each type of memory

The growing demand for feature-rich applications is driving the demand for microcontrollers
capable of compiling complex code and high- level languages. To meet this need, the 80296SA
microcontroller includes six megabytes of linear memory address space, representing a six-fold
increase in headroom for language code compared to 8xC196NU/NP microcontrollers. The new
microcontroller also features 2 kilobytes of high-speed code/data RAM and 512 bytes of 3-

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ported register RAM. For additional design flexibility, the microcontroller features 19 interrupt
sources, including 14 sources with programmable priorities. It is also a low-noise solution,
featuring PLL technology to minimize radio frequency interference

Talking about the 80296SA, the memory specifications are as follows-

With 24 internal address bits, the microcontroller can address 16 Mbytes of memory. However,
only 20 of the 24 address bits are implemented by external pins: A19:0 in demultiplexed mode,
or A19:16 and AD15:0 in multiplexed mode. If, for example, an internal 24-bit address is
FF2080H, the 20 external-address pins output F2080H. Further, the address seen by an external
device depends on how many of the extended address pins are connected to the device. The 20
external-address pins can address 1 Mbyte of external memory. For purposes of discussion only,
it is convenient to view this 1-Mbyte address space as sixteen 64-Kbyte pages, numbered 00H–
0FH . The 4 upper address pins select a 64-Kbyte page (00H– 0FH), and the lower 16 address
pins select a particular location within a 64-Kbyte page. Because the 4 most-significant bits
(MSBs) of the internal address can take any values without changing the external address, these
4 bits effectively produce 16 copies of the 1-Mbyte address space, for a total of 16 Mbytes in 256
pages, 00H–FFH (Figure 5-1). For example, page 01H has 15 duplicates: 11H, 21H, …, F1H.
The shaded areas in Figure 5-1 represent the overlaid areas.

The memory pages of interest are 00H–0EH and FFH. Pages 01H–0EH are external memory
with unspecified contents; they can store either code or data. Pages 00H and FFH, shown below

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have special significance. Page 00H contains the register file and the special-function registers
(SFRs), while page FFH contains special-purpose memory (chip configuration bytes and
interrupt vectors) and program memory. The microcontroller fetches its first instruction from
location FF2080H. Like the 8XC196NP and 80C196NU, the 80296SA incorporates a chip-select
unit to simplify access to external memory devices. The chip-select unit of the earlier devices
decoded only the lower 20 address bits, enabling unique access to addresses in pages 00H–0EH
and FFH. By decoding all 24 bits of the internal address, the 80296SA’s enhanced chip-select
unit provides a method for uniquely addressing external memory devices in pages 0FH–FEH, as
well. We can assign each chip-select a range of addresses in up to 1 Mbyte segments. Therefore,
with six chip-select outputs, the 80296SA can access up to 6 Mbytes of memory.

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FIG: Pages FFH and00H

MEMORY PARTION OF 80296SA-

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HIGH SPEED INPUT UNIT (HSI): This unit is used to record the time at which an external
event occurs with respect to timer 1. It can monitor four independently configurable HSI lines
and capture the value of Timer 1 when an event takes place. There are 4 lines (HIS.O-HIS.3)
available in this unit .The HIS unit can store upto 8 entries(Timer 1 values). The HSI unit can
generate an interrupt when loading an entry into the HIS holding register or loading the sixth
entry into the FIFO. The four types of events that can trigger captures include "rising edges
only", "falling edges only", "rising or falling edges" or every eighth rising edge.

HIGH SPEED OUTPUT UNIT (HSO): Save This HSO unit is used to trigger events at specified
times based on Timer 1 or Timer 2 with minimal CPU over-head. The 4 events are Starting an
A/D conversion Resetting of Timer2 Setting four software flags Switching six output lines
(HSO.0-HSO.5). The HSO unit stores pending events and the specified time s in a Content
Addressable Memory(CAM) file. This CAM file stores up to 8 commands. Each command
specifies the action time, the nature of the action whether an interrupt is to occur and whether
Timer 1 or Timer 2 is the reference Timer.

TYPICAL APPLICATIONS

MCS 96 microcontrollers are typically used for high-speed event control systems. Commercial
applications include modems, motor-control systems, printers, photocopiers, air conditioner
control systems, disk drives, and medical instruments. Automotive customers use MCS 96
microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking
systems (ABS). The 80296SA is especially well suited to applications that benefit from its fast
instruction execution times and digital signal processing functions, such as mass storage
applications.

Interfacing an Optical Encoder to the HSI Unit

Optical encoders are among one of the more popular devices used to determine position of
rotating equipment. These devices output two pulse trains with edges that occur from 2 to 4000
times a revolution. Frequently there is a third line which generates one pulse per revolution for
indexing purposes. Figure 4-2 shows a six line encoder and typical waveforms. As can be seen,
the two waveforms provide the ability to determine both position and direction. Since a

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microcontroller can perform real time calculations it is possible to determine velocity and
acceleration from the position and time information. Interfacing to the encoder can be an
interesting problem, as it requires connecting mechanically generated electrical signals to the
HSI unit. The problems arise because it is difficult to obtain the exact nature of the signals under
all conditions. The equipment used in the lab was a Pittman 9400 series gearmotor with a 600
line optical encoder from Vernitech. The encoder has to be carefully attached to the shaft to
minimize any runout or endplay. Fortunately, Pitmann has started marketing their motors with
ball bearings and optical encoders already installed. It is recommended that the encoder be
mounted to the motor using the exact specifications of the encoder manufacturer and/or a good
machine shop.

The motor is driven using the PWM output pin for power control and a port pin for direction
control. The 80296/96 drives a 7438 which drives 2 opto-isolators. These in turn drive two
VFETs. A MOV (Metal Oxide Varistor, a type of transient absorber) is used to protect the
VFETs, and a capacitor filters the PWM to get the best motor performance. Figure 4-5 shows the
driver circuitry. To avoid noise getting into the 8096 system, the g15 volt power supply is
isolated from the 8096 logic power supply.

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CONCLUSION

 Since we are applying the features of 80296/96 to determine position of rotating

equipment ,where we use the HSO and HSI i.e. high speed output and high speed input
respectively. This property of high speed is used to monitor the motion of the motor and its
position.
 The PWM output can perform digital to analog conversions and drive several types of
motors that require a PWM waveform for more efficient operation.
 The programmable pulse width modulation (PWM) output signals can be used as control
signals to drive a motor, and for any other application
 The event processor array(EPA) performs high speed i/o functions associated with timers and
counters . In input mode, the EPA monitors an input for signal transition. When an event
occurs, the EPA records the timer value associated with it therefore giving the position of the
motor.

REFERENCE

 1. http://datasheets.chipdb.org/Intel/MCS96/INDEX.HTM
 2. 80296SA Microcontroller User’s Manual
 3. https://en.wikipedia.org/wiki/Intel_MCS-96

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 4. https://nptel.ac.in/courses/Webcourse-contents/IIT%20Kharagpur/Embedded
%20systems/Pdf/Lesson-10.pdf

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