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Inherited connections
In hierarchical designs its recommended to use inherited power nets to power a cell. Inherited nets make it possible to override the net
name when you create an instance of your cell which is especially important if you're planning to use different power nets.

To use inherited power nets just place “vdd_inherit” and “gnd_inherit” from the library “basic” instead of the normal “vdd” and “gnd”
symbols. An example schematic of such a cell is shown in the following picture:

If you don't override the net names at some point, the power lines will be connected to vdd! and gnd!.

To override the net names for an instance, select the instance and open the “Net Expression Available Property Names” dialog by
clicking on

Edit - Net Expression - Available Properties

The following image shows an example where we want to override the cells vdd! net with the vddd! net:

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If you override the nets of a cell, all the instances in the cell will inherit the same net.
It is also possible to create inherited nets for non power nets. When adding a label to a net click the tab “Net Expression”, as shown
below. The “Default Net Name”sets what the net is connected to as default if not connected up at a higher level.

You can set this inherited net on the next level up in the heirarchy either as shown above, or by edditing the options of the cell,
selecting “Add”, then adding a netset as shown below. Here I have assigned the inherited net “CK” to the signal “ck”. In the object
properties window, you can select whether this netset is shown in the schematic or not.

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Layout placement box

The current version of Virtuoso suffers from a bug in updating the red layout placement box of cells. If you create an instance of your
cell in the layout editor and the content of the cell is hidden (stop level 0) it is possible that the red box is much bigger than the actual
layout size.

Currently it seems that the only way to fix the box is to copy the whole layout to a new layout file.

Chip logo
An easy way of creating the chip logo is by using the perl script described here: http://brej.org/blog/?p=59.

For the following steps you need to install the open-source layout tool KLayout which can be downloaded (there are binaries available)
from http://www.klayout.de. I used Version 0.21.13 for this article.

Create the logo as follows:

1. Determine the minimum feature size for the top metal layer (0.6u for the AMS C35B3 process). In the following steps the size is
called s_min

2. Create the logo as a monochrome bitmap. The final logo will have a width of px_x*s_min and a height of px_y*s_min, where px_x is the
width of the bitmap in pixels and px_y the height.

3. Open the logo in GIMP (Version 2.6.8 used for this tutorial) and save the logo as a pnm image. In the appearing window select
“Ascii”.

4. Convert the logo to CIF using the following command in your terminal

./pnm2cif.pl infile.pnm outfile s_min gds_layer_number

s_min has to be specified in units of 10nm and gds_layer_number is the GDSII number of the desired metal layer (defined in the
process). For the AMS C35B3 process (logo on MET3) the line may look as follows

./pnm2cif.pl infile.pnm outfile 60 39

Make sure your pnm image and the script are in the same directory. The command above must be executed in this directory.

The script has some internal bugs which can lead to corrupted CIF files for some input files. To verify that the conversion was successful
you can open the CIF file in a layout viewer (e.g. klayout). If the conversion fails you may need to change the logo in some way (for
example its size).
5. Convert the CIF file to GDSII since virtuoso isn't able to import CIF files. To do so, open the CIF file (e.g. outfile.cif) in KLayout and
save it as a GDS2 file (file-type “GDS2 files”). No changes need to be done in the “Layout Writer Options” dialog.

6. To import the logo into Virtuoso open the following dialog from the Virtuoso main window

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File - Import - Stream

For “Stream File” select the GDSII file generated in the last step.

In the “Library” drop-down you need to select the library in which the cell for the logo will be created. It is possible to define a new
library by typing a new library name in the field.

Select TECH_C35B3 in the “Attach Technology Library” drop-down.

Leave the remaining fields empty.

After the import (initiated by the “Translate” button) the logo is available in the specified library and can be edited and placed like any
other layout-only cell.

Components in series
If you have a cell which requires a lot of identical components in series or in a chain, for example a ring oscillator or a matched resistor
network, it can be tedious to place all these components and manually wire them up, as well as taking up lots of space on the schematic.

There is, however, a better way, as shown with the following example of a ring oscillator made up of 100 inverters and a NAND gate.

In this example, the inputs of the 100 inverters are connected to net “a” of the same number as the inverter, ie. the input of I0<1> is a<1>,
I0<2> is a<2> etc.

However, the output is connected to net “a” with a number 1 higher, ie the output of I0<1> connects to a<2>, I0<2> to a<3>, therefore
connecting the inverters in a chain from 1 to 100, output to input.

The final inverter connects to the “OUT” pin and to the input of the NAND gate to complete the chain.

Plotting schematics and layouts to PostScript

Create a file ”.cdsplotinit” in your project directory with the following content:

600 dpi Adobe PostScript Level 2 Plotter | Generic 600 dpi Adobe PostScript Level 2 Plotter: \
:manufacturer=Adobe: \
:type=postscript2: \
:maximumPages#30: \
:resolution#600: \
:paperSize="A" 4902 6402 99 99: \
:paperSize="B" 6402 10002 99 99: \
:paperSize="Legal" 4926 8202 90 90: \
:paperSize="A4" 4758 6846 90 90: \
:paperSize="A3" 6846 9720 90 90:

1200 dpi Adobe PostScript Level 2 Plotter | Generic 1200 dpi Adobe PostScript Level 2 Plotter: \

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:manufacturer=Adobe: \
:type=postscript2: \
:maximumPages#30: \
:resolution#1200: \
:paperSize="A" 4902 6402 99 99: \
:paperSize="B" 6402 10002 99 99: \
:paperSize="Legal" 4926 8202 90 90: \
:paperSize="A4" 4758 6846 90 90: \
:paperSize="A3" 6846 9720 90 90:

Restart Cadence if needed.

In the schematic or layout editor click on

File -> Print

to access the printing dialog.

Open the plot options menu by clicking on “Plot Options” and do the following settings:

1. Display Type → Choose wheater whether you want a colored output “diplay” or a monochrome “psb”
2. Plotter Name → Select the resolution of the PostScript file (the output will always be a vector graphic, the resolution defines the
finest details to be exported in the image)
3. Orientation → Select “portrait” to get the screen orientation
4. Select “Center Plot” and “Fit to Page”
5. Select “Send Plot Only To File” and enter a filename for the image in the field right to the checkbox. The filename should end with .ps
since the image will be a PostScript file.

Back in the “Submit Plot” menu you can start the image export by clicking on “OK”. This will create a file with the specified name inside
your project directory.

Selecting a region to plot:

With the button “Select” in the “Submit Plot” window you can select a region in the layout or schematic that you want to plot.

Layout plot page alignment:

It may be possible that plots of layouts may be cropped in the resulting image file. The only workaraound for this is to play with the
“Plot Size”, “Scale” and “Offset” parameters in the “Plot Options” dialog.

Variables as instance parameters

To represent variables used in a schematic of a cell as CDF parameters of that cell, place the following keyword:

pPar("varname")

in the place of that variable. The variable name “varname” is the name of the CDF parameter of the cell and must be enclosed in
quotation marks.

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Update CDF If you already created the symbol view of the cell, the pPar parameters might not become visible in the parent schematic.
The problem can be solved by updating the CDF parameters that can be done the following way:

‣ Close all views

‣ Open one view of the cell in which the pPar is used
‣ Type “artGenerateHierSymbolCDF(geGetEditCellView())” into the CIW (withouth quotes)

Accessing arbitrary local nets

In testbenches it may be required to access nets inside instances (DUT) without changing the cell itself. A way to do so in spectre is to
introduce a special device called “deepprobe”. Since the components doesn't exist in the default installation of Cadence you would
have to introduce it the following way:

‣ Download the packed deepprobe library for either IC5 (marin) or IC6 (ams)
‣ Extract the archive in your project directory which should result in a new subfolder called “deepprobe”.
‣ Add the library to your cds.lib file:

echo 'DEFINE deepprobe ./deepprobe' >> cds.lib

‣ Place the component “deepprobe” from the library “deepprobe” in your schematic and define the desired net in the “Hierarchical
Node” property. The net name ressembles to the default hierarchical net name which is <Instance>.<Instance>.<Net name>. The net
called “net6” in the instance I1 for example will read “I1.net6”.

The solution is taken from http://www.cadence.com/Community/forums/t/12845.aspx.

Layout-only cells
To work with layout-only cells in Virtuoso-XL:

‣ Add a boolean property “ignoreDummyDevices” to the layout view (value true)

‣ Add “ignoreDummyDevices” to the list of “properties used to ignore objects” in Options→LayoutXL
‣ Run Connectivity→Check→Against Sources after each Component and Net update

Connections to arbitrary metal regions (Virtuoso-XL)

Virtuoso-XL marks nets during top-level routing as not-connected if they end somewhere different than the actual pin region of the cell
(e.g. a trace of metal within the cell, leading to the target pin). This behaviour is caused by the design hierarchy (Virtuoso-XL with its
default settings will only search for connection in the current hierarchy level) and is neither a design error nor a problem during LVS.
Virtuoso-XL can be reconfigured to search connections in deeper hierarchical levels with the following settings:

Options -> Layout XL

Change “Extract Connectivity to Level” to the desired hierarchical depth (usually much higher than 0 which means only on the current
level).

Access psf database (spectre simulation results) from matlab

Start matlab_R2012a for example within the marin35 environment (for other processes adjust path) and then enter

!echo $CDS_LIC_FILE %check if spectre licence is available

% add lib path mypath='/opt/icenv_marin35/cadence/IC/MMSIM_11.10.509'; setenv('LD_LIBRARY_PATH', [mypath '/tools/dfII/lib:'

mypath '/tools/lib/64bit']);

%update matlabpath variable to add toolbox

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addpath('/opt/icenv_marin35/cadence/IC/MMSIM_11.10.509/tools/spectre/matlab/64bit');//

Then you should be able to access the data with

mysimdata=cds_srr('psf','tran-tran')

More information can be found within this file: cadence_spectre_matlab_toolbox.pdf

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