Beruflich Dokumente
Kultur Dokumente
Chip A Chip B
L22 Rwire
Rs1 L11 R1
Cutset
Rs2 L22 R2
* Brian Young, “Digital Signal Integrity: Modeling and Simulation
with Interconnects and Packages”
EE382M VLSI-II Class Notes Foil # 10 The University of Texas at Austin
Example - Three Wires & Two Sources
• Resulting loop impedance model for three parallel wires
driven by two Thevenin sources
mutual resistances
i2Rg
0.5*C1g 0.5*C1g
M12-M1g-M2g+Lgg
0.5*C12 v2
0.5*C12
i1Rg
13
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 13
When Inductance is Important
• Nets ring and net delays become unpredictable unless:
– Net topologies are constrained
• Point to point nets
• Periodically loaded nets
• Near and far end clusters
– Nets are driven appropriately
• Not to strong and not to weak
• Not to fast and not to slow
– Nets are terminated appropriately
• Source termination
• Far end termination
– Resistance to Vdd or Gnd or any Thevenin Voltage
• AC termination = RC circuit
• Active hold clamps
• Diode or Schottky diode clamps
14
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 14
Transmission Line Behavior
• Perfectly source terminated point to point, loss-less net
τf
Rs = Zo Zo = L
C
τf = LC
far end
τf
Rs = 3Zo Zo = L
C
τf = LC
Approximates
far end RC step response
V(t)
near end
time
16
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 16
Transmission Line Behavior
• Over driven point to point, loss-less net
τf
Rs = 1/3 Zo Zo = L
C
τf = LC
far end
V(t)
near end
time
17
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 17
Reflection and Transmission
ZL - Zo
1, ZL= ∞
Γv = Γv = 0, ZL= Zo
ZL+ Zo
-1, ZL= 0
2ZL
Τv = 1 + Γ v =
ZL+ Zo
18
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 18
Equivalent Circuits Along Line
Rs near end
+
Vs Zo Vinc
-
Zo along line
2Vinc Zo Zdiscontinuity
Zo far end
2Vinc ZL
19
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 19
Discontinuities Along Line
Rs = Zo Vs=1
1
C 1/2
Vs
1/2 (1- e-2t/ZoC)
Vs=1
Rs = Zo 1
1/2
Vs L 1- 1/2(1- e-2Zot/L)
20
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 20
Well Behaved Net Topologies
• Point to Point Nets
Source terminated
Rs = Zo τf
21
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 21
Well Behaved Net Topologies
• Periodically Loaded Nets
Rs = Zeff
CL CL CL CL
L
Zeff =
With periodic loading C + nCL
τf = L(C+nCL)
22
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 22
Well Behaved Net Topologies
• Periodically Loaded Nets
L
Zeff =
With periodic loading C + nCL
τf = L(C+nCL)
23
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 23
Well Behaved Net Topologies
• Near end (or Star) cluster
Rs = Zo/N
24
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 24
Well Behaved Net Topologies
• Far-end cluster
Rs = Zo/N Zo/N
25
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 25
Well Behaved Net Topologies
• Double far-end terminated bus
Rs << Zo
Vterm Vterm
CL CL CL CL CL
26
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 26
Ideal Transmission Lines
Ideal
I(z) Telegrapher’s Equation
∂i ∂V
= −C
∂z ∂t ∂ 2V ∂ 2V
= LC 2
V(z) ∂V ∂i ∂z 2
∂t
= −L
∂z ∂t
− j ( γz −ωt ) j ( γz +ωt )
V = Re [V +
e +V −
e ]
Steady State Solution:
1 + − j ( γz −ωt ) j ( γz +ωt )
I = Re ( [V e +V e
−
])
Z
L
where Z= γ = ω LC
C
27
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 27
Transmission Lines with Loss
Rs << Zo
Vs τf
where τf = length / velocity
1
(1- e-R*length/2Zo)
29
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 29
Distortionless Transmission Line
Oliver Heaviside (1887)
G/C = R/ L
L
= LC ( jω + R /L)
=
C
30
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 30
Waveforms Along a Distortionless Line
Rs << Zo
Vs τf
where τf = length / velocity
1
(1- e-R*length/Zo)
31
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 31
Basic CMOS I/O and Receiver
Design
enable Pad
data
enable
0 1
0 0 Hi Z
data
1 1 Hi Z
33
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 33
CMOS I/O Receiver
• Any two input gate that
– Has good noise immunity
– Provides on-chip control when off-chip inputs float
• Example: two input nand
enable
enable 0 1
Pad 0 1 1
data out data
1 1 0
X 1 X
34
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 34
Actual CMOS I/O and Receiver
Design
36
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 36
Output Impedance Control
• Device “resistances” are too variable for source
termination
– Devices are non-linear
– Variations due to Vdd, Temp, and process variations
alone are >2X in linear region!
37
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 37
Impedance Control Using On-Chip Resistors
• Given a precise on-chip resistor, this design provides the
best impedance control
enable
Pad
data
38
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 38
Tunable Impedance Control
• Stacked device settings can be preset or dynamically
controlled
p1 p2 p3
enable Pad
data
n1 n2 n3
39
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 39
Slew Rate Control
• Output stage slew rate is controlled to reduce noise
– Cross talk noise
– Simultaneous switching noise
– Reflections at discontinuities
40
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 40
Slew Rate Control
• Output stage is divided and pre-drive signal is designed to
sequentially arrive at the different sections
δ δ
enable Pad
data
δ δ
41
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 41
Slew Rate Control & Impedance Control
• Pre-driver design might even permit crossover currents to
guarantee impedance even during switching
δ δ
enable Pad
data
δ δ
42
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 42
Feedback Slew Rate Control I/O Buffer
enable
Pad
data
newer older
technology technology
44
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 44
Input Design for Higher Voltages
• Modifications for gate oxide & ESD protection
ESD Diodes
ESD Diodes
Pad Pad
V1
Vdd
V1 - Vtn
0
V1
Vdd
0 V1 - Vtp
46
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 46
Dual Supply Designs
• Separately power I/O circuits at a lower voltage
– No additional process steps required
– Extra design to avoid performance penalty
– ESD & simultaneous switching noise compromised
newer older
technology technology
47
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 47
Output Stage at a Lower Voltage
• Slow rising delay due to low overdrive on pfet
• Reduced drive = reduced noise immunity on nand receiver
ESD Diodes
enable
Pad
data
inhibit
48
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 48
Output Stage at a Lower Voltage
• Improve rising delay with nfet pull up
• Change p/n beta ratio on nand to lower switch point
ESD Diodes
enable
Pad
data
49
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 49
Dual Supply Designs
• Separately power the I/O circuits at a higher voltage
– More complicated circuits
– ESD & simultaneous switching noise compromised
newer older
technology technology
50
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 50
Output Stage at a Higher Voltage
• Slow rising delay due to low overdrive on pfet
• Reduced drive = reduced noise immunity on nand receiver
Vdd2
Level Vdd2
Shifter
Vdd1
enable Vbias
Pad
data
Vdd1
51
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 51
Floating Well Designs
• Enabled output stage sends lower voltage - Vdd1
• Disabled output stage tolerates higher voltage - Vdd2
Vdd1 Vdd1
enable Vdd1
Pad
data
Vdd1
52
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 52
Open Drain Signaling
• Avoids complexity of multiple chip power supplies
– Off-chip termination resistors pull net up
– On-chip nfet devices pull net down
• Increases transmission line design complexity
• Wired OR functionality
Driving Chip
Vtt Vtt
CL CL CL CL CL
53
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 53
Other Circuits
• Differential I/O Circuits
– Reduces simultaneous switching noise
– Improves receiver common mode noise immunity
– Receives smaller signal levels
– “Pseudo” to full differential possible
• Hysteresis Receivers
– High noise immunity
– Excellent for low-speed asynchronous test & control
signals
• Hold Clamps
54
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 54
Differential Output Buffers
out
Differential Outputs
out Vdd
out out
Vbias
55
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 55
Differential Transmission Lines
Zo
Zo
Differential = coupled pair
Zeff < Zo
coupled
Zeff < Zo
56
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 56
Differential Far End Termination
R = Zo Vtt
R = Zo
Differential Termination
R = 2 Zo
57
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 57
Differential Receivers
out
Differential Receiver
out Vdd
out out
Vbias
58
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 58
Self Biased Differential Receiver
• Combines best of nfet and pfet differential receivers
Vdd
Pbias
Vdd
out out
out out
Nbias
59
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 59
Self Biased Differential Receiver
• Combines best of nfet and pfet differential receivers
– Rail to rail output swing
– Excellent common mode noise rejection
Vdd
out
or reference
60
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 60
Hysteresis Input Receivers
• Separates rising & fall edge dc transfer curves
Pad Vin
Vout
inhibit
Pad Vin Vout
falling rising
Vout
and only
Vin
EE382M VLSI-II Class Notes Foil # 61 The University of Texas at Austin
Hold Clamps
I/O
63
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 63
ESD Circuits
• Non-breakdown based circuits Primary ESD Circuit in
– Diodes CMOS Designs
– Bipolar Junction Transistor
– MOS FET
64
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 64
Dual Diode ESD Circuits
ESD Diodes
ESD Diodes
Pad Pad
65
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 65
FET ESD Circuits: non-breakdown mode
nfet in “diode”
configuration
ESD Diodes
Pad
66
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 66
FET ESD Circuits: breakdown mode
ESD Diodes
Pad
second
breakdown
I
snapback
nfet protects Vgs > Vt
by clamping voltage
after device snapback
V
67
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 67
Diode ESD Circuits
• fet devices are parasitic npn & pnp bipolar circuits
• vertical pnp device to substrate
• horizontal npn device to guard rings (before trench isolation)
• low vdd to gnd impedance to due on-chip capacitance
provide additional discharge paths
Pad Pad
68
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 68
Parasitic Bipolar Circuits
• fet devices are parasitic npn & pnp bipolar circuits
• vertical pnp device to substrate
69
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 69
ESD Test Models
• Human Body Model
– Requirements 2 - 4 kVolts
– Positive or negative discharge between any two pins
R = 1.5 KΩ
VHBM DUT
C = 100 pF
ipeak = VHBM/1500
i(t)
L = 0.5 - 0.75 μH
VMM DUT
R < 8.5 Ω
C = 200 pF
71
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 71
ESD Performance Factors
• Diode symmetry is important
– Bipolar conduction increases with temperature
– Hot spots conduct more, heat up more, conduct more,
… and finally burn out
• Layout corners are rounded to reduce electric fields
• Decoupling capacitance needed between all supplies
• Functional performance requirements impose ESD size &
load capacitance constraints
• Parasitic bipolar effects abound
• Breakdown clamps don’t scale
72
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 72
Increasing Bandwidth
Chip A
clock
source
74
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 74
Common Clock Transfers
Cycle time to meet setup time
max(Tclk - A+TAclk +Tdrive+ Ttof+ Treceive + Tsetup ) - min(TBclk - Tclk - B) < Tcycle
TBclk
TAclk PLL
PLL
Chip B
Tclk - A Tclk - B
clock
source
75
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 75
Source Synchronous I/O
• Send source clock with source data
• Resolve clock phase differences with τ1, τ2, & τ3
Chip B
Chip A
τ3
τ1 τ2 PLL
PLL
clock
source
76
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 76
Bus Pumping
• With Ttof > Tcycle, multiple bits are present on the wire
Chip A Chip B
τ3
τ1 τ2 PLL
PLL
clock
source
77
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 77
Dual Data Rate
• Conventional source synchronous design
– Data launched & captured on single clock edge
– Clock switches at f
– Maximium data rate = 1/2 * f
• Dual data rate - if clock can switch at f, why not data?
– Data is launched & captured on both clock edges
– Clock switches f
– Maximum data rate = f
Clock
Data
78
The University of Texas at Austin
EE382M VLSI-II Class Notes Foil # 78
Simultaneous Bidirectional Signaling
• Two chips send & receive data simultaneously on a
point to point net
• Waveforms superimpose on the transmission line
• Each chip selects it’s receiver reference voltage based
on the data it sent
• Sending data is subtracted from total waveform
Chip A Chip B
Rs = Zo
Vs τf
where τf = length / velocity
1/2
(1- e-R*length/2Zo)
1 0 0 1 0 0 1 0 0 1 0 0
Receiver
Switch Point
Drive harder
EE382M VLSI-II Class Notes Foil # 81 The University of Texas at Austin
Increasing Bandwidth
• Preceding techniques cannot be achieved through
clever circuit design alone
• Requires good packaging technology & net design
– Good termination
– Minimal capacitive & inductive discontinuities
– Low cross-talk
– Low simultaneous switching noise