CHAPTER 1

INTRODUCTION OF CCD CIRCUIT

1.1 INTRODUCTION

The sensors used in the cameras are mainly of two types CMOS sensing
image sensors and CCD device. The difference between the CCD and the
CMOS device is the high pixel image rate at the output. The minimum pixel
rate of the Charge coupled device is given as 1000 * 1000. In the CCD the light
energy is allowed to fall on the upper part of the CCD. When the charge from
the light is absorbed by the CCD the voltage from the one terminal of the device
shifted to the other terminal of the device. It contains a large amount of the
capacitor arrays that store the charge when it is shifted to the other terminal.
The charge at the end of the array is taken and the analog signal is produced.
Hence the light energy is converted into the analog signal. In this project the
same process is recreated such that the cost of the CCD is taken care of and the
noise characteristics are calculated. The following points are calculated for the
project.

 Settling time of the output signal

 Bandwidth of the output signal
 RMS noise value of the circuit at the certain bandwidth.

The project consists of mainly two parts one is microcontroller and

other is the micro controller interface circuit. The micro controller used in this
project is UC3U – Xplained. The microcontroller interface circuit consists of D
– Flip flop, D – Latch, Digital to analog converter, analog multiplexer and an
operational amplifier.

1
 1.2 HISTORICAL BACKGROUND

The charge coupled device was invented by Willard Boyle and Geroge E.
Smith at AT&T Bell Labs, United states in 1969. It was first named as “Charge
‘Bubble’ Devices” because at that time the lab was working on semiconductor
bubble memory. It can also be used as a shift register. The device was based on
the ability of the device to transfer the charge from one capacitor to another
along the surface of semiconductor. This principle of operation is also used in a
device called as bucket brigade device. It was developed in late 1960s at Philips
Research Labs. Micheal Tompsett obtained the first patent on application of the
charge coupled device.

When the first CCD is made it is used as a simple 8 bit shift register with
the IC technology. It is used as a crude eight pixel linear imaging device and to
demonstrate as a shift register. A research team led by Micheal Tompsett were
able to capture images with linear devices. Many companies picked up the
invention and began to further develop the idea of the CCD some of the
companies are Fairchild semiconductor, RCA and Texas Instruments. But, Sony
mass produced CCD for their camcorders. They invested a huge amount in the
development of the Charge coupled devices.

In 2006, they were awarded National Academy of engineering Charles

stark draper prize, and in 2009 Noble prize for Physics is awarded Boyle and
Smith. In the recent years they were awarded IEEE Edison medal in 2012. They
were given the IEEE award for pioneering contributions to imaging devices
including CCD imagers, cameras and thermal images.

2
 1.3 BASIC BLOCK DIAGRAM

PC Micro Latch
Controller

F – Clock

R – Clock

Analog
Op- DAC
Multiplexer
Output amp

Fig 1.3 Basic Block Diagram

The figure 1.3 describes the block diagram of the proposed system for the
low cost and low noise charge coupled device. The F and R clocks are the
external signals that are given to the system from Arduino or video card.

1.4 COMPONENTS
1.4.1 PC:
In the PC an image is simulated and the each pixel of the image is
converted into the binary data of 0’s and 1’s. The data of the image is
converted into a text file and is sent into the microcontroller for the
further processing of the data.

3
1.4.2 Microcontroller
In the micro controller the data from the PC is taken and it is sent to
the analog and the digital section for the further processing of the data.
It produces a 12 – bit data that is sent into a digital to analog section
so that the 12 bit digital data is converted into the analog signal.

1.4.3 Latch
The latch used in the circuit is used to store the data and then send the
data to the further section when required. In this circuit, latch is used
as a buffer. It consists 8 buffers connecting the input and output; it is
operated due to variation in the clock. The clock signal required for
the processing of the data is given by the flip flops. The flip flops get
an F – Clock signal from the external pin. Latch is used to reduce the
delay in the circuit. As the micro controller cannot send the data when
we require it, a latch is used so that it stored the data and sends it when
required.

1.4.4 Op Amp
The operational amplifier is used to limit the output data to a certain
bandwidth according to the rise time or the settling time of the output
signal. It is also used to limit the noise of the output signal to less than
20μV rms by limiting the bandwidth of the signal.

4
 CHAPTER 2
LITERATURE REVIEW

2.1 INTRODUCTION

The image sensors are becoming an essential part of today’s cameras as they
offer advantages such as low noise and high pixel rate of the image. One of
such sensors in Charge coupled device and it used for various applications,
to detect the altitude of the satellite, to improve the pixel rate in the image in
digital cameras, optical scanners as light sensing devices, it is also used in
astrophotography.

They are very sensitive to the infrared rays, which allows photography in
infrared, it is also used as a main component in the night vision devices and
also in the zero lux of the video recording and photography. While
purchasing a CCD the parameters that is taken into consideration are array
size of the capacitors, the highest pixel size that can be produced by the
CCD, Intercede dynamic range of total values of the brightest light level,
Dark noise produced by the device, Full well capacity, Quantum effiency.

In the present literature review a brief description of various techniques and

work carried out on the optical properties of the CCD such as specific
modules were presented. The efforts and main conclusions of the previous
studies are compared and discussed. The following literature surveys are
taken into consideration and the data that is collected in the literature papers
are noted down. The papers referred are High energy proton induced signal
in charge coupled devices and Image recovery from the data acquired with a
charge coupled device camera.

5
2.2 RELATED WORK
1. M. S. Robbis, Marconi, High energy proton induced signal in charge
coupled devices , Chelmsford, UK, 2009.

This paper mainly explains that the signal of the CCD in 10

and 60 MeV proton as discussed and a modified theory of the proton
signal with measurements on devices from applied technologies with
different pixel sizes. The previously developed models are developed
with better agreement at low proton fluency. The select levels of the
circuit are selected by the video signal as he input. The select signals has
three levels and each level describes the data in the each pixel of the
image.

2. Donald L. Synder, Abed M. Hammoud and Richard L. White, Image

recovery from the data acquired with a charge coupled device camera
2013.

A model is created for collecting the data with the use of

the charge coupled device and then it is used for the developing of a new
method for restoring the data of the objects. It contains effects such as
point spread, photo conversion noise, and readout noise and charge
carriers from the bias current that is present in the internal and external
background radiation. Basically this system converts the data back to the
image format. This system recovers the mage from the data acquired
from the charge coupled device.

6
 3. Hainaut, Oliver R, Basic CCD image processing, retrieved January 15,
2011.

An image intensifier includes three functional elements:

photocathode, a micro-channel plate (MCP) and a phosphor screen. These
three elements are mounted one close behind the other in the mentioned
sequence. The photons which are coming from the light source fall onto
the photocathode, thereby generating photoelectrons. The photoelectrons
are accelerated towards the MCP by an electrical control voltage, applied
between photocathode and MCP. The electrons are multiplied inside of
the MCP and thereafter accelerated towards the phosphor screen. The
phosphor screen finally converts the multiplied electrons back to photons
which are guided to the CCD by a fiber optic or a lens.

2.3 SUMMARY

In this literature survey, the papers and journals discussed about the
select levels of the charge coupled device and the image recovery from the data
derived from the CCD. By using the second literature survey the reverse process
is used for the conversion of the data from the image to the data format. The
select levels that are to be selected of the image are selected by the first
literature survey. There are three select levels in the output of the circuit.

7
 CHAPTER 3
DESIGN OF CHARGE COUPLED DEVICE
CIRCUIT OUTPUT.

Charge coupled device (CCD) circuit output should produce a waveform with
the following characteristics.

Table 3.1 Circuit output characteristics.

Sl No Characteristics Value
1. Frequency 1MHz

2. Voltage Range 10V – 9.6V

3. Settling Time 100ns

4. Total Noise < 20μV

3.1 OBJECTIVE
The main objective of this project is to design a circuit that works as an
alternative for the charge coupled device that is of low cost and low noise. The
microcontroller is given a 12 bit digital input through the computer and the
external clocks F – Clock and R – Clock are given to the system. Whenever, the
two clocks change the output also change according to the input. The F – Clock
and the R – Clock are given through the external video card or it is generated by
the Arduino Uno.

As discussed in the previous chapter the output of the circuit has mainly
three select levels ‘Vm’, ‘Vr’ and ‘Vf’. The ‘Vm’ level is fixed but the ‘Vr’ and
‘Vf’ levels are adjustable i.e. both the levels are programmable and its value can
be varied by changing the digital inputs and clocks.

8
3.2 TIMING DIAGRAM

Vm
Op amp o/p Vr
(a) Vf
166ns

R – Clk
(b)
1 μs

F – Clk
(c)

Latch Clk
(d)

DAC I\P

(e)

Fig 3.2 Timing diagram of the circuit

9
 The timing diagram is shown above. The output of the system is the
waveform – (a). The voltage level Vm in the (a) is the fixed at a level of 10V.Vr
and Vf are the voltage levels that vary due to the change in the input. The values
of voltage in the Vr and Vf vary from 9.8V to 9.5V. The waveform (b) is the R –
clk that is given to the multiplexer. The waveform (c) is the F – clk that is given
to the D – Flip Flops and the micro-controller. The waveform (d) is the clock
that is produced by the flip flops. The waveform (e) determined the DAC input.

3.3 SETTLING TIME

The settling time of the output signal can be calculated by determining

the settling time of the each component. The settling time of the op amp is
determined by seeing the datasheet and it is found that it is 95ns. The digital to
analog converter settling time is said to be 35ns. The settling time of the analog
multiplexer is 10ns. The formula for finding the settling time of the output
signal is given as

TS = √𝑇𝑠12 + 𝑇𝑠22 + 𝑇𝑠32

TS = √(952 + 352 + 102 )

TS = 100ns.

10
 CHAPTER 4
CIRCUIT DESIGN

The circuit is designed based on the low noise and high speed conditions. The
latch (74HC373), flip flop (74HC74), DAC (AD565A), analog multiplexer
(74HC4051) and the operational amplifier (AD829).

4.1 CLOCK GENERATION

Fig 4.1.1 Circuit for clock generation

11
From the figure 3.1 we can determine the signal that is used as a clock for the
latches. The flip flop used in this circuit is “74HC74”. It is dual D – Flip flop
IC.

Fig 4.1.2 Pin diagram for D flip flop

The IC has common supply at pin number 14. The 5Vp digital input
is given at the supply pin and the input pin of both the flip flops i.e. pin number
2, 12. The F – Clk is given form the external source to the flip flops at the pin
number 3 and 11. An inverter is placed between the two flip flops so that the
clock is inversed in at pin 11. The output from the pin 6 is taken and it is sent
through the two inverters so that there is a little delay in the output and it is
connected to the clear (pin 3). The output from the pin 5 (Q) is given to the one
input of an OR gate. The D Flip flop output is only based on the clock and the
input given to the system when the reset and clear are high. The IC we use is a
positive edge trigger IC. When the clear and the preset values are low the output
varies rapidly and it does not depend on the clock to get a positive edge trigger.
The preset and the clear pins are used for the generation of the clock. There is a
little bit of time delay in the IC, the time delay of the flip flop is as given below
according to the datasheet.

12
 Table 4.1.1 Time delay in D flip flop

SL NO. PIN DELAY TIME

1. Clk to Q 44ns
2. CLR to nQ 50ns
3. PRESET to nQ 50ns

Due to the time delays in the flip flop the circuit has some delay in
producing the output. Due to the two inverters the delay in the wire is 24ns as
each inverter has a delay of 12ns. In the similar process the connections to the
second flip flop in the circuit are given. The 5Vp digital power is given to the
pin 12 and the inverted clock to the pin 11. The output of nQ2 is given to the
clear pin and two inverters are placed in between the connection.
The output from the pin 9 is given to the other input of the OR gate.
The output from the OR gate is given as the clock for the latches. The signal
from the OR gate has a delay of 44ns compared to the original clock due to the
internal circuit delay. The input signal of the OR gate has an on time of 74ns
and the off time of 1882ns for the input coming from the first flip flop. The
signal coming from the second flip flop is delayed by 56ns and it has an on time
of same 74ns as the first flip flop. However it has an off time of 1870ns. This
difference is due to the inverter in between the two flip flops. The timing
diagram of the clock generated is given below:

13
 1 μs

F – Clk

44ns 74ns 1882ns

O/P from
Pin 5

Inverted F-Clk

12ns 988 ns

56ns 74ns 1870ns

O/P from pin 9

52ns 74ns 874ns 64ns 74ns 862ns

Output

Fig 4.1.3 Clock timing diagram

14
4.2 OP AMP CIRCUIT:
4.2.1 LPF Circuit:
The Op Amp used in this circuit is AD829. It is a high speed and a
low noise op amp. The voltage noise of the op - amp is 1.7nv/√Hz and the input
current noise density of 1.5 pA/√Hz. The op amp is placed in a non-inverting
mode so that the input signal is not inverted. The main task of the op amp in this
circuit is to band limit internal bandwidth of the op - amp.
For the op amp in a unity gain condition the bandwidth of the
circuit is found to be 25MHz. Due to this if an input is given to the circuit the
higher frequency noises also pass through the circuit. Due to this higher level
noise is observed at the output. To compensate this condition internal low pass
filter connection is used.
The bandwidth of the signal is found out by the rise time of the
output signal. The rise time of the output signal is given as the 250ns. By using
the following formula the band width of the signal can be found out. Another op
amp IC that can be used as an alternative for this AD829 is AD797 but the slew
rate is very low compared to the op amp AD829, but irrespective of the slew
rate this IC can also be used.
0.35
Bandwidth (MHz) =
rise time(ns)

We know that,
Rise time = 100ns

0.35
Bandwidth (MHz) =
100 ∗ 10−9
(S)

Bandwidth = 0.0035*109 Hz

Bandwidth = 3.5 * 106 Hz

Bandwidth = 3.5 MHz

15
 For the circuit to band limit the signal at 3.5MHz a non-inverting low
pass filter is used so that the frequencies above 3.5MHz are eliminated. The low
pass RC filter is a filter composed of a resistor and capacitor which passes
through low frequency signals, while blocking the high frequency signals.
A general low pass non inverting op amp circuit is as given below:

Fig 4.2.1 LPF Op amp circuit

The figure 4.2.1 determines the low pass op amp circuit filter to limit the
output signal bandwidth. Then by further calculation the value of resistor is
found to be 470Ω. The circuit of the op amp that is used is given below: The
resistor and capacitor values are found out by considering the bandwidth of the
signal. The following formula is used:
1
𝑓𝑐 = 𝐻𝑒𝑟𝑡𝑧
2𝜋𝐶𝑅2

16
As we know that the cut off frequency of the circuit is given as 3.5 MHz by
assuming the value of the capacitor first we can find the value of the resistor.
Assume the value of the capacitor is 90pF.
The following figure determines the op amp circuit that is used in the
microcontroller interface circuit. The low pass filter circuit is introduced in the
feedback so that the internal bandwidth of the op amp reduces from 25MHz to
3.5 MHz.

Fig 4.2.2 Op amp circuit

The DAC reference out in is connected to the input of the op amp along with
the output of the analog multiplexer. The reference pins in the DAC simplifies
the connection of the DAC to the operational amplifier. It is given in a non-
inverting mode because the data that is given to the input should not be inverted
and the output should be bandlimited.

17
4.2.2 Compensation Capacitor:

According to the datasheet of the op amp AD829, the operational

amplifier is stable with no external compensation for the noise gains greater
than 20. For lower gains, two different methods of frequency compensating the
amplifier can be used to achieve closed loop stability: shunt and current
feedback compensation. Hence a capacitor of 100pf is used as compensation
capacitor at pin 5 of the op amp. The datasheet also determines the table in
which the value of the compensation capacitor is used based on the noise gain
and the resistors used at the inverting and non-inverting terminals of the
operational amplifier.

Table 4.2.2 Compensation capacitor values

Follower Slew 3Db

R1 R2 CCOMP
Gain Rate Bandwidth

1 Open Open 68 16 66

2 1k 1k 25 38 71

5 511 2.0 k 7 90 76

10 226 2.05 k 3 130 65

20 105 2k 0 230 55

25 105 2.49k 0 230 39

100 20 2k 0 230 7.5

18
 CHAPTER 5
NOISE CALCULATIONS
5.1 OP AMP NOISE MODEL
In the figure 5.1, the total noise of all sources is shown referred to input
(RTI). The RTI noise is useful because it can be compared directly to input
signal level. The total noise referred to output (RTO) is obtained simply
multiplying the RTI noise by the noise gain.

Fig 5.1 Op amp noise model

R2 2
Vn2 + 4kTR3 + 4KTR1 [ ]
R1+R2
 RTI Noise = √𝐵𝑊 ∗ √
R1.R2 2 R1 2
+In2 R32 + In2 [ ] + 4kTR2 [ ]
R1+R2 R1+R2

 RTO Noise = NG. RTI Noise

 BW = 1.57 fCL

19
 The above model assumes that the feedback network is purely
resistive. If it contains reactive elements (usually capacitors), the noise gain
is not constant over the bandwidth of interest. However, for precision
applications where the feedback network is most likely resistive, the
equations are valid. A resistor basically produces a noise which is names as
Johnson noise and is equal to √4𝑘𝑇𝐵𝑅 where k is the Boltzmann’s constant
(1.38 * 10-23 J/K), T is the absolute temperature, BW is bandwidth in Hz and
R is the resistance in Ω.
The noise gain (NG) of a non-inverting amplifier is generally given as

𝑅2
𝑁𝐺 = 1 + (1)
𝑅1

And the noise gain for the inverting amplifier is given as:

𝑅2
𝑁𝐺 = − (2)
𝑅1

In the circuit that we use we are using the equation 1 as we are using a non-
inverting amplifier. The voltage noise varies for various operational
amplifiers from under 1nV/√Hz to 20nV/√Hz, or even more. Compared to the
JFET input amplifiers the bipolar input op amps tend to have low input
voltage noise density, at the cost of large input capacitance and hence large
input devices. Compared to the voltage noise density the current noise density
varies more widely, from around 0.1fA/√Hz (in JFET input op - amps) to
several pA/√Hz. For bipolar or JFET input devices where all the bias current
flows into the input junction, the current noise is simply the Schottky (or
shot) noise of the bias current. The shot noise spectral density is simply 2IBq

20
amps/Hz, where IB is the bias current (in amps) and q is the charge on an
electron (1.6*10–19 C). It cannot be calculated for bias-compensated or current
feedback op amps where the external bias current is the difference between
two internal current sources.
Current noise is only important when it flows through an
impedance and in turn generates a noise voltage. The equation of the RTI
noise shows hoe the current noise flowing in the resistors contribute to the
total noise. The choice of a low noise op amp therefore depends on the
impedances around it. Consider another op amp, a bias compensated op amp
with low voltage noise, but quite high current noise. The formulae for the
related to input (RTI) noise is derived by the usage of the superposition
theorem and the concept of the virtual short in the circuit. The source resistor
always produces a Johnson’s noise of 4KTR. The noise voltage to the op amp
input from the source by the resistor R and R1. Therefore the voltage noise
𝑅1
for the resistor R is given as 4KTR(𝑅+𝑅1)2 . R1 is typically used to terminate

the input of the device so that R=R1. The amplifiers noise is a combination of
the voltage noise of the op amp, current noise of the op amp and the voltage
noise of the other components of the circuit. In the same way if the voltage
noise at the resistor 1 is taken into consideration then the voltage noise of the
𝑅
resistor 1 i.e. R1 is given as 4KTR1(𝑅+𝑅1)2. With a source resistance of 3k

ohms, the current noise increases a hundredfold to 300Nv, while the voltage
noise is unchanged, and the Johnsons noise increased tenfold. The bandwidth
is multiplied by 1.57 because the LPF cuts the frequency at certain frequency
by practically the frequency is not accurately dropped, a slight delay is there
in the cut-off frequency and the noises in that frequency is also included in
the noise calculations.

21
5.2 NOISE MODEL OF OP AMP CIRCUIT
Noise voltage i.e. V associated with AD829 is 1.7nv/√Hz and the
input current noise density is 1.5pA/√Hz.

Fig 5.2 Band limiting Op amp circuit noise model

The figure 5.2 determines the noise model of the operational
amplifier circuit that is designed.
The RTI noise of the circuit is as given below:

R2 2
Vn2 + 4kTR3 + 4KTR1 [ ]
R1+R2
RTI Noise = √𝐵𝑊 ∗ √
R1.R2 2 R1 2
+In2 R32 + In2 [ ] + 4kTR2 [ ]
R1+R2 R1+R2

BW = 1.57 fCL
BW = 1.57 * 3.5MHz
BW = 5.4MHz.
𝐹ℎ
Vn = 𝑉 √𝐹𝑐 ln + (𝐹ℎ − 𝐹𝑙)
𝐹𝑙

But as fh>> fl

22
 (fh- fl) can be written as fh
3.5𝑀
Vn = 1.7√60 ln + 3.5𝑀
100

Vn = 1.7 (1870.9)

Vn = 3.18μV.
In = 1.5 (1870.9)
In = 2806 pA.
𝑅2
√4𝑘𝑇𝑅1 ∗ = √500(3.5𝑀 − 100) ∗ 1.28 ∗ 10−10 ∗ 0.5
𝑅1 + 𝑅2
= 8465 * 10-10
= 0.8μV
𝑅1
√4𝑘𝑇𝑅2 ∗ = √500(3.5𝑀 − 100) ∗ 1.28 ∗ 10−10 ∗ 0.5
𝑅1 + 𝑅2

= 8465 * 10-10
= 0.8μV
√4𝑘𝑇𝑅3 = √250(3.5𝑀 − 100) ∗ 1.28 ∗ 10−10

= 11971.5 * 10-10

= 1.197 μV

INR3 = 2806 pA * 250

= 701500 * 10-12

= 0.7 μV
R1.R2 500.500
IN = 2806 pA ∗
R1+R2 1000

= 0.7 μV

23
 RTI Noise = √3.182 + 0.82 + 0.82 + 1.192 + 0.72 + 0.72

= √14.75

= 3.84 μV

The RTI noise derived is considered when there is no source at the op

amp input but the noise from the DAC also goes to the input of the op amp.
Hence consider the noise coming from the DAC is 6 μV. Then the RTI noise of
the system becomes

RTI Noise = √14.75 + 36

= √50.75

= 7.12 μV
𝑅2
Noise gain = 1 +
𝑅1

470
=1+
470

=2

RTO Noise = RTI noise * NG

= 7.12 * 2

= 14.24 μV

From the above equation we found out that the noise in the system
satisfies our required condition of <20μV rms. Hence this system can be used to
reduce the noise of the output.

24
5.3 VOLTAGE REGULATOR CIRCUIT
The analog multiplexer requires a voltage of 5.6V as the
power supply. A voltage regulator is used to regulate the voltage at the power
supply pin. Here LM317 IC is used as a voltage regulator. LM317 is an
adjustable 3 terminal positive voltage regulator capable of supplying 1.5A
current over a 1.2V to 37V output range.

Fig 5.3 Voltage regulator circuit

𝑅21
Output voltage VO is given as VO = 1.25 [1 + ]
𝑅22

Let’s take R22 to be 470ohm. Then to get the output

voltage ad 5.6V, R21 is approximately 120ohm. There is an adjustable resistor to
adjust the output voltage exactly to +5.6V. By pass capacitors are added to
reduce the noise. A capacitor is added between adjustment terminal and ground
to improve ripple rejection by 15dB. Output capacitor is added to improve the
transient response. From the figure 4.4 the two capacitors c21 and c19 are the
bypass capacitors. They are added to reduce the noise and to improve the ripple
rejection.

25
5.4 MICROCONTROLLER INTERFACE CIRCUIT

Fig 5.4 Microcontroller Interface circuit

26
 CHAPTER 6
MICRO CONTROLLER.
6.1 EVALUATION KIT

The microcontroller used in this system is UC3 A3 XPLAINED.

The microcontroller is selected based on the external memory, the speed of the
GPIO pins and the number of the input and output pins. UC3 A3XPLAINED is
an evaluation kit that is mainly used to process that data from the SD card or the
external memory of the microcontroller. At first a total of 15 evaluation kits are
considered for this project.

 UC3 – LO XPLAINED
 XMEGA – A1 XPLAINED
 XMEGA – 1284P XPLAINED
 XMEGA B1 XPLAINED
 XMEGA – A3BU
 SAM4S XPLAINED
 SAM 3U EK
 SAM 3N EK
 SAM 3S WK
 UC 3L EK
 UC3C EK XPLAINED
 UC3 A3
 EVK1100
 EVK 1400
 EVK 1200

Of these 15 evaluation kits based on the GPIO pins the speed and
the USB port the kit is selected the all the microcontroller kits contains the USB

27
data supply except SAM 3N EK. The external memory is used in the data for
the evaluation kits are sufficient for the micro controllers, SAM 4S, SAM 3U,
SAM 3S, UC3L, EVK 1100 and UC3A3 XPLAINED.

The UC3 A3 XPLAINED has a USB and an Ethernet port

for the supply of the power and the sending of the data. It has a micro SD slot
for the insertion of the SD card to the device. The data is stored in the external
memory and it is inserted in the slot of the microcontroller. The data in the
micro controller is processed and it sent into the further stages for the
development of the signal. The pin out of the kit is as given below:

Fig 6.1.1 Pinout of the evaluation kit

28
The block diagram of the microcontroller is as given below:

Fig 6.1.2 Block Diagram of microcontroller

29
The hardware component of the device is given below:

Fig 6.1.3 UC3 A3 XPLAINED

The kit needs a power supply that can deliver 5V and up to 500mA
current. The actual requirement of current for the board is much less than
500mA. The power can be supplied to the board via USB connected to the pin
10 on the header J3.The voltage is regulated to 3.3V with an on board regulator.
The kit is programmed by an external programming tool Actel Studio 4 through
USB bootloader which is pre-programmed on the device. The device has five
header jumpers. Each header contains 10 pins. Of these five headers, two
headers have already fixed communication interface. The headers J2 and J3 has
general purpose digital input and output. For the SDRAM footprints are
available for adding either an industrial standard or a propriety Atmel Data
Flash serial flash.

30
 CHAPTER 7
RESULTS AND DISCUSSION

1.

Fig 7.1 F Clock

The figure 7.1 indicates the f clock that is given to the microcontroller and
the flip flops. This result is the output that is derived from the Arduino uno by
the processing of the program that is mentioned above. This clock is used for
the generation of the clock signal for the latches by using the flip flops.

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2.

Fig 7.2 R Clock

The output waveform at figure 7.2 is the R clock signal that is given
to the analog multiplexer. This R clock determines which input channel that
should be selected. The on time of the signal is given as 166ns.

3.

Fig 7.3 Clock Generated

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 The Figure 7.3 is the clock that is generated by using the
flip flops. This clock is given to the latch and this determines when the output
from the latch should be sent to the digital to analog signal.

4.

Fig 7.4 Output of the Op amp circuit.

The output waveform in the figure 7.4 is the output of

the charge coupled device that is of low noise i.e. 14uV(rms). This determines
the image signal that is converted into the analog signal.

33
 CHAPTER 8
CONCLUSION

The PCB that works as an alternative for the CCD has been designed by
using D flip flop, latch, digital to analog converter (DAC), analog multiplexer
and an operational amplifier.

The circuit that has been designed is interfaced with the microcontroller
and a computer for the circuit to work as a low noise and low cost charge
coupled device.

REFERENCES

1. M. S. Robbis, Marconi, High energy proton induced signal in charge

coupled devices , Chelmsford, UK, 2009.

2. Donald L. Synder, Abed M. Hammoud and Richard L. White, Image

recovery from the data acquired with a charge coupled device camera 2013.
3. Hainaut, Oliver R, Basic CCD image processing, retrieved January 15,
2011.
4. Hainaut, Oliver R, Retouching of astronomical data for the production of
outreach images, retrieved October 7, 2009.
5. Amplifier for signal conditioning from www.analog.com

6. Datasheets from www.datasheets.com

7. UC3 A3 XPLAINED User Guide

34
 APPENDIX:
int data=0;
int i=0;
const int maxChars = 3;
char chData[maxChars];
int index=0;
const int F_Clk_pin = 10; //PB2
const int R_Clk_pin = 11; //PB3
int F_Clk_state=0;
int R_Clk_state=0;
//unsigned long currMillis=0;
//unsigned long oldMillis=0;
//int F_Clk_time=5000;
//int R_Clk_time=5000;
void setup() {
// put your setup code here, to run once:
Serial.begin(9600);
pinMode(F_Clk_pin, OUTPUT);
pinMode(R_Clk_pin, OUTPUT);
DDRD = 0xFF;
DDRB = DDRB | 0b00000011;
PORTD=0x00;
}
void loop() {
// put your main code here, to run repeatedly:
Serial.write('1');
serialEvent();
Serial.write('0');

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//write data to GPIO
PORTD = (char)(data<<2);
PORTB = (PORTB&0b11111100) | (((char)data)&0b00000011);
digitalWrite(F_Clk_pin,HIGH);
digitalWrite(R_Clk_pin,HIGH);
delay(1);
digitalWrite(R_Clk_pin,LOW);
delay(4);
digitalWrite(F_Clk_pin,LOW);
delay(4);
Serial.write('1');
serialEvent();
Serial.write('0');
//write data to GPIO
PORTD = (char)(data<<2);
PORTB = (PORTB&0b11111100) | (((char)data)&0b00000011);
digitalWrite(F_Clk_pin,HIGH);
delay(5);
digitalWrite(F_Clk_pin,LOW);
delay(4);
/*
currMillis=millis();
if(currMillis - oldMillis >F_Clk_time) {
oldMillis = currMillis;
if (R_clk_state == LOW)
R_Clk_state = HIGH;
else
R_Clk_state = LOW;
}
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*/
}
void serialEvent() {
while(1) {
if(Serial.available()) {
char ch = Serial.read();
//Serial.write(ch);
if((index<(maxChars-1))&&(isDigit(ch))) {
chData[index++]=ch;
}
else if(index==(maxChars-1)) {
chData[index++]=ch;
data = atoi(chData);
index=0;
break;
}
else {
chData[index++]=0;
}
}
}
}

37