Name: Grandhi Vyasa Maharshi

IDNo: 2018HT80538
Assignment: No 2
Subject: MELZG641 – IC Design Using CAD
MailId: 2018HT80538@wilp.bits-pilani.ac.in

1) Write all the parameters that you know when you do timing
analysis like slack, WNS, TNS etc?
The "Worst Negative Slack (WNS)" reported by commands like report_timing_summary is
actually the worst positive slack. If WNS is positive then it means that the path passes. If it is negative,
then it means the path fails. So, this is really a misnomer.

The "Total Negative Slack (TNS)" is the sum of the (real) negative slack in your design. If 0, then
the design meets timing. If it is a positive number, then it means that there is negative slack in the design
(hence your design fails). It cannot be negative.

Going on, the "Worst Hold Slack (WHS)" is correct - it is the worst hold slack in the design. Like
WNS if positive, it means the path passes, if negative it fails.

Conversely "Total Hold Slack (THS)" is also a misnomer. It is really the sum of the (real) negative
hold slack. If zero, your design passes, if positive, your design fails.

2) Setup Time: The minimum time required to arrive data before active clock edge.
3) Setup Violation: To avoid setup violation data should arrive in required time ,In timing
analysis when we do setup checks we use name called slack (setup slack).If this is positive means
there is no setup violation.If it is negative means there is setup violation.

Slack (+ve) -No setup violation);

Slack ( -ve)-setup violation));

In equation: Tperiod -Tsetup (required time) >/= Tclk->q + Tcomb(arrival Time) ( There is no setup
violation) and slack is +ve

Tperiod – Tsetup(required time) < Tclk->q + Tcomb(arrival time) (There is setup

violation as slack is -ve)

Slack = Required Time -data arrival time.

4) Hold Time: The minimum time the data should be stable after the clock edge.
5) Hold Violation: Thold > Tcq+Tcomb; (negative hold slack)
 6) Arrival Time: The arrival time of a signal is the time elapsed for a signal to arrive at a certain
point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. To calculate
the arrival time, delay calculation of all the components in the path will be required. Arrival times,
and indeed almost all times in timing analysis, are normally kept as a pair of values - the earliest
possible time at which a signal can change, and the latest.
7) Required Time: Another useful concept is required time. This is the latest time at which a
signal can arrive without making the clock cycle longer than desired. The computation of the
required time proceeds as follows: at each primary output, the required times for rise/fall are set
according to the specifications provided to the circuit. Next, a backward topological traversal is
carried out, processing each gate when the required times at all of its fanouts are known.

8) Slack: The slack associated with each connection is the difference between the required time
and the arrival time. A positive slack s at some node implies that the arrival time at that node may
be increased by s, without affecting the overall delay of the circuit. Conversely, negative
slack implies that a path is too slow, and the path must be sped up (or the reference signal
delayed) if the whole circuit is to work at the desired speed.

9) Critical Path: The critical path is defined as the path between an input and an output with the
maximum delay. Once the circuit timing has been computed by one of the techniques listed
below, the critical path can easily be found by using a traceback method.

10) Timing Paths:

Clk to Q delay

Input to Reg delay

Reg to output delay

Input delay

Output delay

Input to output (asynchronous)

Delays (Propagation delay, Net delays, etc)

11) Difference Between Static Timing Analysis and Dynamic Timing

Analysis?
Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be
compromised but not timing! Timing analysis can be static or dynamic. Dynamic timing analysis verifies
functionality of the design by applying input vectors and checking for correct output vectors whereas
Static Timing Analysis checks static delay requirements of the circuit without any input or output vectors.
Dynamic timing analysis has to be accomplished and functionality of the design must be cleared before
the design is subjected to Static Timing Analysis (STA). Dynamic Timing Analysis (DTA) and Static Timing
Analysis (STA) are not alternatives to each other. Quality of the Dynamic Timing Analysis (DTA) increases
with the increase of input test vectors. Increased test vectors increase simulation time. Dynamic timing
analysis can be used for synchronous as well as asynchronous designs. Static Timing Analysis (STA) can’t
run on asynchronous deigns and hence Dynamic Timing Analysis (DTA) is the best way to analyze
asynchronous designs. Dynamic Timing Analysis (DTA) is also best suitable for designs having clocks
crossing multiple domains.

12) Statitical Static Timing Analysis:

Conventional static timing analysis (STA) has been a stock analysis algorithm for the design
of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor
devices and interconnect has introduced a number of issues that cannot be handled by traditional
(deterministic) STA. This has led to considerable research into statistical static timing analysis, which
replaces the normal deterministic timing of gates and interconnects with probability distributions, and
gives a distribution of possible circuit outcomes rather than a single outcome.

Comparison with conventional STA

Deterministic STA is popular for good reasons:

• It requires no vectors, so it does not miss paths.

• The run time is linear in circuit size (for the basic algorithm).
• The result is conservative.
• It typically uses some fairly simple libraries (typically delay and output slope as a function of input
slope and output load).
• It is easy to extend to incremental operation for use in optimization.
STA, while very successful, has a number of limitations:

• Cannot easily handle within-die correlation, especially if spatial correlation is included.

• Needs many corners to handle all possible cases.
• If there are significant random variations, then in order to be conservative at all times, it is too
pessimistic to result in competitive products.
• Changes to address various correlation problems, such as CPPR (Common Path Pessimism Removal)
make the basic algorithm slower than linear time, or non-incremental, or both.
SSTA attacks these limitations more or less directly. First, SSTA uses sensitivities to find correlations among
delays. Then it uses these correlations when computing how to add statistical distributions of delays.
There is no technical reason why determistic STA could not be enhanced to handle correlation and
sensitivities, by keeping a vector of sensitivities with each value as SSTA does. Historically, this seemed
like a big burden to add to STA, whereas it was clear it was needed for SSTA, so no-one complained. See
some of the criticism of SSTA below where this alternative is proposed.
Methods
There are two main categories of SSTA algorithms – path-based and block-based methods.
A path-based algorithm[1] sums gate and wire delays on specific paths. The statistical calculation is simple,
but the paths of interest must be identified prior to running the analysis. There is the potential that some
other paths may be relevant but not analyzed so path selection is important.
A block-based algorithm[2] generates the arrival times (and required) times for each node, working
forward (and backward) from the clocked elements. The advantage is completeness, and no need for path
selection. The biggest problem is that a statistical max (or min) operation that also considered correlation
is needed, which is a hard technical problem.
There are SSTA cell characterization tools that are now available such as Altos Design Automation's Variety
tool.

13) How Glithces and clock skew effect Timings?

itter is nothing but the displacement of signal from its original position.This movement may lag or
lead from its original or ideal position.As a speed increases, the edge deviation cause a significant
problems like signal integrity,skew,race condition and other timing problems.

Classification
1. cycle-to-cycle jitter

Cycle-to-cycle jitter is the change in an output’s transition in time in relation to the transition during the
previous cycle.

2.period jitter

Period jitter is the maximum change in a signal transition from the ideal position in time. Phase jitter,
also called long-term jitter, in the maximum change in an output signal transition from its ideal position
over many cycles (typically 10 to 20 microseconds).

3.phase jitter

Phase jitter may leads to the displacement of phase from one signal to another.
Figure A: cycle to cycle jitter

skew
Skew deals with the propagation delay of the output signal.It is the variation of propagation delay
differences between output signals.Excessive skew, especially for clock signals, can cause race conditions
and other timing errors that result in system data faults. At the very least, poor skew will force a slower
maximum system speed, and this, in turn, will limit system performance.

14) Interface Timing Analysis is critical?

As we know interface signals from one interface to another interface may vary with respect
to PVT conditions which causes performance issue and its critical to do timing analysis in such
condition and we use different variations of .libs to check interface timing.
Example:: to clauculate Inteface timings.

In a simple view, a signal (data) is launched by a driver and the signal (data) is received by the
receiver with respect to a reference (clock) signal, as shown in Figure 1.

The figure shows the signal at the driver output arriving at the receiver after a interconnect delay with
time valid before the reference signal (tvb) and time valid after the reference signal (tva). The signal at
the receiver input is expected to remain valid a minimum time required before the reference signal (tsu,
setup time) and minimum time required after the reference signal (th, hold time) to guarantee correct
operation of the interface. Therefore, the mathematical expressions to guarantee correct operation
would be; tvb  tsu tva  th The timing margins would be defined as tsum = tvb – tsu (set up margin) thm
= tva – th (hold margin). Driver Receiver data interconnect delay Interconnect tvb tva data tsu th data
tsum thm reference Data launched at driver Data arrives at receiver Data expected at receiver reference
5 | P a g e The signal at the driver is launched with known timing parameters (from the data sheet of the
component) with respect to a reference signal (for example: clock signal). Normally the same reference
signal is used at the driver and the receiver. Calculations of the valid-before and valid-after times at the
receiver could be performed and derived through modeling of the IO buffers and simulations to determine
the propagation delay across the interconnect. The types of interfaces will be discussed to further the
details of computation of timing margins with respect to the reference signals used in the interfaces. At
the lower part of the timing diagrams describing interfaces, margin equations are shown for calculations
using the datasheet parameters. The QSI equations with translated parameters are given within the text
explaining the diagrams. The synchronous interface first described here is referred to as a common clock
interface.

Common Clock Interface:

Synchronous interfaces in early systems, were common-clock, like PCI, PCIx and SDR memory. SDR (single-
data rate) SDRAMs, though earlier memory technology but still used in systems today, are designed with
a reference signal supplied to both the driver and the receiver from the same source. Such a design is
commonly referred to as a common-clock interface and is described in Figure 2.

The driver sends the data signal with respect to the clock, named clkD, and the receiver receives the data
signal with the clock clkR. The timing parameters of the data with respect to the clock at the driver and
the receiver are provided in the respective data sheets. The simulation software tools would determine
the propagation delays on all the interconnects. Timing margins of the data signal are affected by the clock
skew which is defined as the difference between the arrival times of the clock signal at the driver and
receiver inputs. The clock skew is calculated from the clkD and clkR propagation delays plus the skew
between the outputs of the clock source and the jitter that the clock source may have.
 15) What is CDC?
CDC means Clock Domain Crossing, means the data crossing between two different
clock frequencies which are independent to each other (means the two clocks which are not from same
source). While clock domain crossing we have issue called metastability, which means the state of data
is unpredictable. This metastable araises when setup hold time is not met. There are several CDC
techniques we used in industry to avoid CDC issue.

1) Two flop synchronizer or three flop synchronizer. (slow to high frequencies and high to
slow based on MTBF scenario).
2) Pulse Synchronizer (Pulse from High to slow frequencies).
3) Mux synchronizer (Data transfer between high to slow with control signal).
4) Async FIFOs (burst Data transfer between high to slow frequencies).

16) Add 5-6 summary bullets on layout synthesis from paper given to
you?
➢ The goals of the benchmarking efforts as related to layout synthesis are discussed in the
context of other benchmark activities conducted at MCNC.
➢ Layout synthesis is traditionally done in several consecutive steps: placement, global
routing, and detailed routing is the typical sequence.
➢ when preparing the benchmarks for layout synthesis the goal of the benchmark is to
measure the performance of the entire design process.
➢ The set of benchmarks: standard cell layouts, gate array layouts, building block (macro
block) layouts, mixed macro block/standard cell layouts, flexibility benchmarks (cell
synthesis for various floorplanning, and compaction.
➢ Layout benchmarks with specified function may also be considered as candidates for logic
resynthesis. Which is for future conclusion.