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Bluetooth Car entertainment system CEM5000/00/55/51

CEM5000X/78

CONTENTS
Technical specification ..................................................................1-2

Service measurement setup..........................................................1-3


Service aids .................................................................................1-4

Instructions on CD playability ...............................................2-1.. 2-2

Block diagram ................................................................................3-1


Wiring diagram ..............................................................................4-1

Main board
Circuit diagram ..................................................................5-1..5-5
Layout diagram..................................................................5-6..5-7

Panel board
Circuit diagram .........................................................................6-1
Layout diagram..................................................................6-2..6-3

Servo board
Circuit diagram...................................................................7-1..7-2
Layout diagram .........................................................................7-3

Exploded view diagram .................................................................8-1


Revision list ...................................................................................9-1

© Copyright 2010 Philips Consumer Electronics B.V. Eindhoven, The Netherlands


All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted, in any form or by any means, electronic, mechanical, photocopying,
or otherwise without the prior permission of Philips.

Published by LX 1036 Service Audio Subject to modification 3141 785 35011

Version 1.1
1-2

TECHNICAL SPECIFICATION

Radio

Power supply 12 V DC (10.8 V Frequency 87.5 - 108.0 MHz (Europe)


- 15.8 V), nega ve range - FM 87.5 - 107.9 MHz
ground (American)
Fuse 15 A Frequency 522 - 1620 KHz (Europe)
Suitable speaker 4-8 range - 530 - 1710 HKz (American)
impedance AM(MW)
Maximum power 50 W x 4 channels Usable 8 V
output sensi vity - FM
Con nuous power 24 W x 4 channels
output (4 10% T.H.D.) Usable 30 V
Pre-Amp output 2.0 V ( USB play sensi vity -
voltage mode; 1 kHz, 0 dB, 10 AM(MW)
k load)
Subwoofer output 2.0 V (USB play Bluetooth
voltage mode: 61 Hz, 0 dB, 10
Output power 0 dBm (Class 2)
k load)
Frequency band 2.4000 GHz - 2.4835 GHz
Aux-in level 500 mV
ISM Band
Dimensions (W x H 188 x 58 x 212 mm
Range 3 meters(free space)
x D)
Standard Bluetooth 2.0 speci? ca on
Weight 1.67 kg
Opera on -20°c -- 70°c
temperature

VERSION VARIATION

Type /Versions: CEM5000

Service policy /05 /00 /55 / 58 /51 /98


Board in used:
SERVO BOARD C/M C/M C/M
MAIN BOARD C/M C/M C/M
PANEL BOARD C/M C/M C/M

Type /Versions: CEM5000

Features Feature diffrence /05 /00 /55 /5 8 /51 / 98


RDS
VOLTAGE SELECTOR
ECO STANDBY - DARK

* TIPS : C -- Component Lever Repair.


M -- Module Lever Repair
-- Used
1-3

MEASUREMENT SETUP

Tuner FM

Bandpass
DUT 250Hz-15kHz LF Voltmeter
e.g. 7122 707 48001 e.g. PM2534
RF Generator
e.g. PM5326
Ri=50:

S/N and distortion meter


e.g. Sound Technology ST1700B

Use a bandpass filter to eliminate hum (50Hz, 100Hz) and disturbance from the pilottone (19kHz, 38kHz).

Tuner AM (MW,LW)
Bandpass
250Hz-15kHz LF Voltmeter
DUT e.g. 7122 707 48001 e.g. PM2534

RF Generator
e.g. PM5326
S/N and distortion meter
e.g. Sound Technology ST1700B
Ri=50:

Frame aerial
e.g. 7122 707 89001

To avoid atmospheric interference all AM-measurements have to be carried out in a Faraday´s cage.
Use a bandpass filter (or at least a high pass filter with 250Hz) to eliminate hum (50Hz, 100Hz).

CD Recorder
Use Audio Signal Disc SBC429 4822 397 30184 Use Universal Test Cassette CrO2 SBC419 4822 397 30069
(replaces test disc 3) or Universal Test Cassette Fe SBC420 4822 397 30071

DUT
DUT LF Generator L
L e.g. PM5110

R
R
S/N and distortion mete
S/N and distortion meter e.g. Sound Technology ST170
e.g. Sound Technology ST1700B

LEVEL METER
LEVEL METER e.g. Sennheiser UPM550
e.g. Sennheiser UPM550 with FF-filter
with FF-filter
1-4

SERVICE AIDS

GB WARNING ESD
All ICs and many other semi-conductors are
susceptible to electrostatic discharges (ESD).
Careless handling during repair can reduce life
drastically.
When repairing, make sure that you are
connected with the same potential as the mass
of the set via a wrist wrap with resistance.
Keep components and tools also at this
potential.

GB
Safety regulations require that the set be restored to its original CLASS 1
condition and that parts which are identical with those specified,
be used LASER PRODUCT
Safety components are marked by the symbol ! .

Lead free
2-1

INSTRUCTIONS ON CD PLAYABILITY

Customer complaint
"CD related problem"

Set remains closed!


1
check playability

playability N
ok ?

Y 3
For flap loaders (= access to CD drive possible)
"fast" lens cleaning cleaning method 4 is recommended

check playability

playability N
ok ?

Play a CD
for at least 10 minutes

check playability

playability N
ok ?

add Info for customer Exchange CDM


"SET OK" 2

return set

1 - 4 For description - see following pages


2-2

INSTRUCTIONS ON CD PLAYABILITY

1 4
PLAYABILITY CHECK LIQUID LENS CLEANING
Before touching the lens it is advised to clean the
surface of the lens by blowing clean air over it.
For sets which are compatible with CD-RW discs
This to avoid that little particles make scratches on
use CD-RW Printed Audio Disc ....................7104 099 96611
the lens.
TR 3 (Fingerprint)
TR 8 (600µ Black dot) maximum at 01:00
Because the material of the lens is synthetic and coated
• playback of these two tracks without audible disturbance with a special anti-reflectivity layer, cleaning must be done
playing time for: Fingerprint 10seconds with a non-aggressive cleaning fluid. It is advised to use
Black dot from 00:50 to 01:10 “Cleaning Solvent
• jump forward/backward (search) within a reasonable time

The actuator is a very precise mechanical component and


may not be damaged in order to guarantee its full function.
For all other sets Clean the lens gently (don’t press too hard) with a soft and
use CD-DA SBC 444A..................................4822 397 30245 clean cotton bud moistened with the special lens cleaner.
TR 14 (600µ Black dot) maximum at 01:15
TR 19 (Fingerprint) The direction of cleaning must be in the way as indicated in
TR 10 (1000µ wedge) the picture below.

• playback of all these tracks without audible disturbance


playing time for: 1000µ wedge 10seconds
Fingerprint 10seconds
Black dot from 01:05 to 01:25
• jump forward/backward (search) within a reasonable time

2
CUSTOMER INFORMATION

It is proposed to add an addendum sheet to the set which


informs the customer that the set has been checked
carefully - but no fault was found.
The problem was obviously caused by a scratched, dirty or
copy-protected CD. In case problems remain, the customer
is requested to contact the workshop directly.
The lens cleaning (method 3) should be mentioned in the
addendum sheet.

The final wording in national language as well as the printing


is under responsibility of the Regional Service Organizations.
3-1 3-1

SET BLOCK DIAGRAM


4-1 4- 1

SET WIRING DIAGRAM


5-1 5-1

CIRCUIT DIAGRAM - MAIN BOARD


PART 1
5-2 5-2

CIRCUIT DIAGRAM - MAIN BOARD


PART 2
5-3 5-3

CIRCUIT DIAGRAM - MAIN BOARD


PART 3
5-4 5-4

CIRCUIT DIAGRAM - MAIN BOARD


PART 4
5-5 5-5

CIRCUIT DIAGRAM - MAIN BOARD


PART 5
5-6 5-6

LAYOUT DIAGARM - MAIN BOARD


TOP SIDE VIEW
5-7 5-7

LAYOUT DIAGARM - MAIN BOARD


BOTTOM SIDE VIEW
6-1 6-1

CIRCUIT DIAGARM - PANEL BOARD

RED+8V
LCD-59P1
R963 NC LCD-59P
BLUE+8V
RED+8V

108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
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71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
470

470
470

470

270

270

270

270

270

270

270

270
470

470

470

470

470

470
470

270
270

270
NC R964

S10
S11
S12
S13
S14
S15
S16
S17
S18
S19

S20
S21
S22
S23
S24
S25
S26

S28
S11
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S20
S21
S22
S23
S24
S43
S44
S45
S74
S73
S72
S71
S70
S69
S68
S11

S27
2SD1132

S1
S2
S3
S4
S5
S6
S7
S8
S9
Q901

R995
22K BLUE+8V

R948

R953

R994

R992

R990

R985
R996

R993

R991

R986
R945
R942

R944
R935

R940

R941

R946

R947

R949
R943

R952

R989
2SD1132 LED7 LED9
Q903 LED3 LED6 LED13 LED1 LED2 LED17 LED18 LED19

S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
22K
R938 LED15 R+B
R+B R+B R+B R+B R+B R+B R+B R+B R+B
1K R+B
R939

PT6578LQ
RED+8V

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
BLUE+8V
9014C 1K
S76 76 S50
R937

270

470

270

470

270

470

270

470

270

470
Q904 S77 77 50 S49

270

470

270

470

270

470
S78 78 49 S48
S79 79 48 S47
S80 80 47 S46
S81 81 46 S45

S[1:120]
R975

R976

R955

R954

R956

R957

R969

R970

R971

R972
10K R965 9014C S82 82 45 S44

R987
R967

R968

R973

R974

R988
S83 83 44 S43
Q902 84 43
LED8 LED10 S42
R936 1K LED16 LED4 LED5 LED12 LED14 LED11 85 42 S41
86 IC901 41 S40
P3
9014C 87 40 S39
R+B R+B R+B 88 PT6578LQ 39 S38
Q905 R+B R+B VDD
R+B R+B R+B 89 38 S37
VLCD
90 37 S36
12K 12K VLCD0
R958 91 36 S35
12K VLCD1
R980 92 35 S34
VLCD2
C906 C903 C901 93 34 S33
VLCD3
1K R981 94 33 S32
1K VLCD4
104 95 32 S31
R966 104 104 104 VSS
R934 C902 12K 96 31 S30
OSC
12K R999 97 30 S29
R982 INH
98 29 S28
CE
99 28 S27
CLK
100 27 S26
C904 DI
26
680p
L1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
470

270
270

270
R983 FB
L2
5K6
FB

R961
R959

R960
R950

3K3

LED34 LED30 LED31 LED32

S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
24

S1
S2
S3
S4
S5
S6
S7
S8
S9
USB_UP LED LED LED Q907
R901A
23 LED

6V8
USB_DN 9013C

4K7

6V8
22
USB+5V 2P
2P 2P 2P
6V8
21 6V8
USB_GND

R997

ZD902
ZD901 C910 C912 C911

ZD903
20 ZD904 LCD-49P1
+8V C905
19 LCD-49P
BT_LED
GND 18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
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25
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29
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31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
R933 22
17
INH
16 R932 22
DATA

S76
S83
S82
S81
S80
S79
S78
S77
S76
S83
S82
S81
S80
S79
S78
S77

S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S46
S47
S48
S49
S50
S51
S66
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S67
S76
15 R931 22
S[1:120]
CLK
14 R930 22
CE
GND 13

12
CON901

LCD+8V
ENCODER 11
KEY1 10

9
REMOTE
8
KEY2
24PIN

+5V 7

6
AUX-L
5
GND
4
AUX-R
3
AGND 1
2 2
USB_DN 3
R929
1 REMOTE
USB_UP 10
EC901
IC902 R901 R906
10uF R902 R903 R904 R905 R907 R908 R909 R910 R911 R912
100
R962 220 330 470 680 1K 1K5 3K3 4K7 8K2 18K
180 2K2

SW1 SW2 SW3 SW4 SW7 SW13


SW5 SW6 SW8 SW9 SW10 SW11 SW12
M1 M2 M3 M4 SUB-W
M5 M6 TUNE/SEEK-UP TUNE/SEEK-DN AUDIO/EQ NC NC NC
PAUSE SCAN REPEAT SHUFFLE
TRACK-UP TRACK-DN
LED33
LED

R979 9014C 82K


ZR902 22P
Q906 47K R928 R924 R923 R922 R921 R920 R919 R918 R917 R916 R915 R914 R913
22P ZR901
R927
1K
1
2
3
4

330 470 680 1K 1K5 2K2 4K7 8K2 18K


USB 180 220 3K3
USBIN SW25 SW22 SW15
SW24 SW23 SW21 SW20 SW19 SW18 SW17 SW16 SW14
VOL1 MENU POWER CALL END-CALL NC DN
INFO MODE Back Browser UP
EJECT
VOL

AUX-JACK

AUX1
6-2 6-2

LAYOUT DIAGRAM - PANEL BOARD


7-1 7-1

CIRCUIT DIAGRAM - SERVO BOARD


PART 1
7-2 7-2

CIRCUIT DIAGRAM - SERVO BOARD


PART 2
7-3 7-3

LAYOUT DIAGRAM - SERVO BOARD


TOP SIDE VIEW
7-4 7-4

LAYOUT DIAGRAM - SERVO BOARD


BOTTOM SIDE VIEW
9-1

Revision list
Version1.0 ( 3141 785 35010)
*Initial Release

Version1.1 ( 3141 785 35011)


*new -/51 added.
TENTATIVE Version No.18052009

LV47002P Development Specification Proposal


(BTL 4 channel Car Audio Power Amplifier)

The LV47002P is the IC for 4-channel BTL power amplifier that is developed for car audio system.
Pch DMOS in the upper side of the output stage and Nch DMOS in the lower side of the output stage are
complimentary. High power and high quality sound are realized by that.
This IC incorporate various functions (standby switch, muting function, and various protection circuit) necessary for
car audio system. Also, it has a self-diagnosis function.

1. Application : 4-channel BTL power amplifier for car audio system


2. Package type : HZIP25
3. Functions and Features :
- High power : - Pomax=48W (typical)
(Vcc=15.2V, f=1kHz , JEITAmax , RL=4Ω)
- Po = 28W (typical)
(Vcc=14.4V, f=1kHz , THD=10% , RL=4Ω)
- Po = 21W (typical)
(Vcc=14.4V, f=1kHz , THD=1% , RL=4Ω)
- Built-in muting function (pin 22)
- Built-in Standby switch function (pin 4)
- Built-in Self-diagnosis function (pin 25) : Signal output in case of output offset detection, shorting to VCC,
shorting to ground , and load shorting.
- Electric mirror noise decrease
- Built-in various protection circuit (shorting to ground, shorting to VCC, load shorting, over voltage and
thermal shut down )
- No external anti-oscillation part necessary.

Note1 : Please do not mistake connection.


A wrong connection may produce destruction, deterioration and damage for the IC or equipment.
Note2 : The protective circuit function is provided to temporarily avoid abnormal state such as incorrect output
connection. But, there is no guarantee that the IC is not destroyed by the accident.
The protective function do not operate of the operation guarantee range. If the outputs are connected
incorrectly, IC destruction may occur when used outside of the operation guarantee range.
Note3 : External parts, such as the anti-oscillation part, may become necessary depending on the set condition.
Check their necessity for each set.
TENTATIVE 2


4. Maximum Ratings at Ta = 25℃
Parameter Symbol Conditions Ratings Unit
Maximum supply Voltage Vcc max 1 No signal, t=1 minute 26 V
Vcc max 2 During operations 18 V
Maximum output current Io peak Per channel 4.5/ch A
Allowable Power dissipation Pd max With an infinity heat sink 50 W
Operating temperature Topr -40 to 85 ℃
Storage temperature Tstg -40 to 150 ℃
Thermal resistance between the junction and case θj-c 1 ℃/W


5. Recommended operating range at Ta=25℃
Parameter Symbol Conditions Ratings Unit
Recommended supply voltage Vcc 14.4 V
Recommended load resistance RL op 4 Ω
Operating supply voltage range Vcc op A range not exceeding Pdmax 9 to 16 V

℃, Vcc=14.4V, RL=4Ω, f=1kHz, Rg=600Ω


6. Electrical Characteristics at Ta=25℃
Parameter Symbol Conditions min typ max Unit
Quiescent current Icco RL=∞, Rg=0Ω 200 400 mA
Standby current Ist Vst=0V 10 uA
Voltage gain VG Vo=0dBm 25 26 27 dB
Voltage gain difference ∆VG -1 +1 dB
Output power Po THD=10% 23 28 W
Pomax1 JEITA max 43 W
Pomax2 Vcc=15.2,JEITA max 48 W
Output offset voltage Vn offset Rg=0Ω -100 +100 mV
Total harmonic distortion THD Po=4W 0.03 0.2 %
Channel separation CHsep Vo=0dBm, Rg=10kΩ 55 65 dB
Ripple rejection ratio SVRR Rg=0Ω, fr=100Hz , Vccr=0dBm 45 65 dB
Output noise voltage VNO Rg=0Ω, B.P.F.=20Hz to 20kHz 80 200 uVrms
Input resistance Ri 40 50 65 kΩ
Mute attenuation Matt Vo=20dBm ,MUTE : ON 75 90 dB
Standby Pin Vstby H AMP : ON 2.5 Vcc V
Control voltage Vstby L AMP : OFF 0.0 0.5 V
Mute Pin Vmute H MUTE : OFF OPEN -
Control voltage Vmute L MUTE : ON 0.0 1.5 V
Output offset detection
Detection threshold voltage Vosdet ±1.2 ±1.8 ±2.4 V
Note : 0dBm = 0.775Vrms

Note : Information in this document is subject to change without notice.


TENTATIVE 3

7. LV47002P Test and Application circuit

cc

a cc cc

rotective D
circ it

D i le
ilter D

D D

te
te
D
circ it Lo Level
te

rotective D
circ it

tan
itch D

The components and constant values within the test circuit are used for confirmation of characteristics
and are not guarantees that incorrect or trouble will not occur in application equipment.

Note : Information in this document is subject to change without notice.


TENTATIVE 4

8. Explanation for the functions

1. Standby switch function (pin 4)


Threshold voltage of the pin 4 is set by about 2VBE.
The amplifier is turned on by the applied voltage of 2.5V or more. Also, the amplifier is turned off by the applied
voltage of 0.5V or less.

Fig1 Standby equivalent circuit

2. Muting function (pin 22)


The muted state is obtained by setting pin 22 to the ground potential, enabling audio muting.
The muting function is turned on by the applied voltage of 1V or less to the resistance of 10kΩ. And the muting
function is turn off when this pin opens.
Also, the time constant of the muting function is determined by external capacitor and resistor constants.
It is concerned with a pop noise in amplifier ON/OFF and mute ON/OFF. After enough examination, please set it.

Fig2 Mute equivalent circuit

3. ACGND pin (pin 16)


The capacitor of the pin 16 must use the same capacitance value as the input capacitor.
Also, connect to the same PREGND as the input capacitor.

Note : Information in this document is subject to change without notice.


TENTATIVE 5

4. Self-diagnosis function (pin 25)


By detecting the unusual state of the IC, the signal is output to the pin 25.
Also, by controlling the standby switch after the signal of the pin 25 is detected by the microcomputer,
the burnout of the speaker can be prevented.
1) Shorting to VCC / Shorting to ground : The pin 25 becomes the low level.
2) Load shorting : The pin 25 is alternated between the low level and the high level according to the output signal.
3) Output offset detection : when the output offset voltage exceeds the detection threshold voltage,
the pin 25 becomes the low level.
* Note: The output offset abnormality is thought of as the leakage current of the input capacitor.
In addition, the pin 25 has become the NPN open collector output (active low).
The pin 25 must be left open when this function is not used.

5. Sound Quality (low frequencies)


By varying the value of input capacitor, low-frequency characteristic can be improved.
However, it is concerned the shock noise. Please confirm in each set when the capacitance value varies.

6. Pop noise
For pop noise prevention, it is recommended to use the muting function at the same time.
- Please turn on the muting function simultaneously with power supply on when the amplifier is
turned on. Next, turn off the muting function after the output DC potential stabilization.
- When the amplifier is turn off, turn off the power supply after turning on the muting function.

. Oscillation Stability
Pay due attention on the following points because parasitic oscillation may occur due to effects of the capacity
load, board layout, etc.
(1) Capacity load
When the capacitor is to be inserted between each output pin and GND so as to prevent electric mirror noise,
select the capacitance of maximum 1500 pF. (Conditions: Our recommended board, RL = 4Ω)
(2) Board layout
- Provide the VCC capacitor of 0.1µF in the position nearest to IC.
- PREGND must be independently wired and connected to the GND point that is as stable as possible,
such as the minus pin of the 2200µF VCC capacitor.
In case of occurrence of parasitic oscillation, any one of following parts may be added as a countermeasure.
Note that the optimum capacitance must be checked for each set in the mounted state.
- Series connection of CR (0.1µF and 2.2Ω) between BTL outputs
- Series connection of CR(0.1µF and 2.2Ω) between each output pin and GND.

Note : Information in this document is subject to change without notice.


TENTATIVE 6
Icco - Vcc VN - Vcc
250 14
RL=Open RL=Open
200 R =0Ω 12 R =0Ω
10
Icco (mA)

150

VN (V)
8
100 6
4
50
2
0 0
6 8 10 12 14 16 18 6 8 10 12 14 16 18
Vcc (V) Vcc (V)

Po - Vcc(THD=10%) Po - f(THD=1%)
50 25
f=1kHz
RL=4Ω
40 20
THD=10%
all channel is similar
Po (W)

30
Po (W) 15

20 10
all channel is similar Vcc=14.4V
10 5 RL=4Ω
THD=1%
0 0
8 10 12 14 16 18 10 100 1000 10000 100000
Vcc (V) f (Hz)

THD - Po(f=1kHz) THD - Po(f=100Hz)


10 10
Vcc=14.4V ch1 Vcc=14.4V ch1
RL=4Ω ch2 RL=4Ω ch2
f=1kHz f=100Hz ch3
THD (%)

ch3
THD (%)

1 1
ch4 ch4

0.1 0.1

0.01 0.01
0.1 1 10 100 0.1 1 10 100
Po (W) Po (W)

THD - Po(f=10kHz) THD - f


10 10
Vcc=14.4V ch1 Vcc=14.4V ch1
RL=4Ω ch2 RL=4Ω ch2
f=10kHz Po=4W
ch3 ch3
1 1
THD (%)

THD (%)

ch4 ch4

0.1 0.1

0.01 0.01
0.1 1 10 100 10 100 1000 10000 100000
Po (W) f (Hz)

Note : Information in this document is subject to change without notice.


TENTATIVE 7
f-Response VNO - Rg
1 150
Vcc=14.4V
RL=4Ω
Response (dB)

VNO(µVrms)
100
all channel is similar
-1
ch1
50 ch2
-2 Vcc=14.4V ch3
RL=4Ω
Vo=0dBm ch4

-3 0
10 100 1000 10000 100000 10 100 1000 10000 100000
f (Hz) Rg (Ω

→)
CH.Sep - f(CH1→ →)
CH.Sep - f(CH2→
80 80

60 60
CH.sep (dB)

40 CH.sep (dB) 40
Vcc=14.4V ch1→ch2 Vcc=14.4V ch2→ch1
RL=4Ω ch1→ch3 RL=4Ω ch2→ch3
20 20
Rg=10kΩ Rg=10kΩ
Vo=0dBm ch1→ch4 Vo=0dBm ch2→ch4

0 0
10 100 1000 10000 100000 10 100 1000 10000 100000
f (Hz) f (Hz)

→)
CH.Sep - f(CH3→ →)
CH.Sep - f(CH4→
80 80

60 60
CH.sep (dB)

CH.sep (dB)

40 40
Vcc=14.4V ch3→ch1 Vcc=14.4V ch4→ch1
RL=4Ω RL=4Ω
20 Rg=10kΩ ch3→ch2 20 ch4→ch2
Rg=10kΩ
Vo=0dBm ch3→ch4 Vo=0dBm ch4→ch3

0 0
10 100 1000 10000 100000 10 100 1000 10000 100000
f (Hz) f (Hz)

SVRR - Vcc SVRR - fR


80 80

60 60
SVRR (dB)

SVRR (dB)

40 VccR=0dBm ch1 40 ch1


fR=100Hz Vcc=14.4V
ch2 ch2
Rg=0Ω VccR=0dBm
ch3 Rg=0Ω
20 RL=4Ω 20 ch3
CVcc=0.1μF ch4 RL=4Ω
CVcc=0.1μF ch4

0 0
8 10 12 14 16 18 10 100 1000 10000 100000
Vcc (V) fR (Hz)

Note : Information in this document is subject to change without notice.


TENTATIVE 8

Offset DIAG - Vcc Pd - Po


4 60
RL=4Ω f=1kHz
R =0Ω 50 RL=4Ω
3 Pd=Vcc×Icc-Po×4ch
Vosdet (V)

40
Detection Level

Pd (W)
2 30

20
1 Vcc=14.4V
10 Vcc=16V

0 0
8 10 12 14 16 18 0.1 1 10 100
Vcc (V) Po (W)

Icco - Vst Mute ATT - V Mute


250 100
Vcc=14.4V
RL=Open
200 R =0Ω 80

Mute ATT(dB)
Icco (mA)

150 60

100 40
Vcc=14.4V
50 20 RL=4Ω
Vo=20dBm

0 0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0
Vst (V) V Mute(V)

Note : Information in this document is subject to change without notice.


TDA7419

3 BAND CAR AUDIO PROCESSOR


PRELIMINARY DATA

1 FEATURES Figure 1. Package


■ 4 STEREO INPUTS
■ SOFT STEP VOLUME
■ BASS, MIDDLE, TREBLE AND LOUDNESS
■ DIRECT MUTE AND SOFTMUTE
SO-28
■ FOUR INDEPENDENT SPEAKER OUTPUTS
■ SUB WOOFER OUTPUT
■ SOFT STEP SPEAKER/SUBWOOFER Table 1. Order Codes
CONTROL Part Number Package
■ 7 BANDS SPECTRUM ANALYZER TDA7419 SO-28
■ DIGITAL CONTROL: TDA7419TR SO-28 in Tape & Reel
– I2C-BUS INTERFACE
cessor with fully integrated audio filters. The digital
2 DESCRIPTION control allows programming in a wide range of filter
characteristics. By the use of BICMOS-process and
The TDA7419 is a high performance signal proces-
linear signal processing low distortion and low noise
sor specifically designed for car radio applications.
are obtained.
The device includes a high performance audiopro-

Figure 2. Block Diagram


ACOUTL/ ACOUTR/ ACINL/ ACINR/
SAOUT SACLK MUTE AC2OUTL AC2OUTR FILOL FILOR

Spectrum
Analyzer

DIFFL

DIFFG
Softstep
Softstep HPF Mix OUTLF
InGain Loudness SoftMute Treble Middle Bass
MonoFader
DIFFR AutoZero Volume

SE1L Softstep HPF


MonoFader
Mix OUTRF
INPUT
SE1R
MULTIPLEXER

SE2L Softstep
OUTLR
MonoFader
SE2R

Softstep OUTRR
MonoFader

OUTSW/
Subwoofer Softstep
LPF MonoFader OUTLR2

MIX/
Softstep OUTSW/
MonoFader OUTRR2

SUPPLY DIGITAL CONTROL I2C BUS

VDD GND CREF VREFOUTF SCL SDA AC2INL/ AC2INR/


SE3L SE3R

Rev. 1
November 2004 1/30

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TDA7419

Table 2. Supply
Symbol Parameter Test Condition Min. Typ. Max. Unit

Vs Supply Voltage 7.5 8.5 10.5 V

Is Supply Current Vs = 8.5V 30 35 40 mA

SVRR Ripple Rejection @ 1KHz Audioprocessor(all Filters flat) 60 dB

Table 3. Thermal Data


Symbol Parameter Value Unit

RTh j-pins Thermal Resistance Junction-pins max 85 °C/W

Table 4. Absolute Maximum Ratings


Symbol Parameter Value Unit

Vs Operating Supply Voltage 10.5 V

Tamb Operating Temperature Range -40 to 85 °C

Tstg Storage Temperature Range -55 to +150 °C

ESD
All pins are protected against ESD according to the MIL883 standard.

Figure 3. Pin connection (Top view)

ACOUTR/AC2OUTR 1 28 MIX/OUTSW/OUTRR2
ACINR/FILOR 2 27 VREF
ACINL/FILOL 3 26 SAOUT
ACOUTL/AC2OUTL 4 25 SAIN
SE3L/ACINL 5 24 VDD
SE3R/ACINR 6 23 SDA
SE2L 7 22 SCL
SE2R 8 21 MUTE
SE1L 9 20 OUTLF
SE1R 10 19 OUTLR
DIFFL 11 18 OUTRR
DIFFG 12 17 OUTRF
DIFFR 13 16 OUTSW/OUTLR2
CREF 14 15 GND
D04AU1569

2/30
TDA7419

Table 5. Pin Description


Pin
Pin Name Function I/O
N#
1 ACOUTR / AC2OUTR AC coupling right output / DSO filter AC2OUT right channel O
2 ACINR / FILOR AC coupling right input / DSO filter FILO right channel I/O
3 ACINL / FILOL AC coupling left input / DSO filter FILO left channel I/O
4 ACOUTL / AC2OUTL AC coupling left output / DSO filter AC2OUT left channel O
5 SE3L / ACINL Single-ended input 3 left channel / AC coupling left input I
6 SE3R / ACINR Single-ended input 3 right channel / AC coupling right input I
7 SE2L Single-ended input 2 left channel I
8 SE2R Single-ended input 2 right channel I
9 SE1L Single-ended input 1 left channel I
10 SE1R Single-ended input 1 Right channel I
11 DIFFL Pseudo differential stereo input left I
12 DIFFG Pseudo differential stereo input common I
13 DIFFR Pseudo differential stereo input right I
14 CREF Reference capacitor O
15 GND Ground S
16 OUTSW / OUTLR2 Subwoofer output / 2nd rear left output O
17 OUTRF Front right output O
18 OUTRR Rear right output O
19 OUTLR Rear left output O
20 OUTLF Front left output O
21 MUTE External mute pin I
22 SCL I2C bus clock I
23 SDA I2C bus data I/O
24 VDD Supply S
25 SAIN Spectrum analyzer clock input I
26 SAOUT Spectrum analyzer output O
27 VREF Vref output O
28 MIX / OUTSW / OUTRR2 Mix input / Additional subwoofer output / 2nd rear right output I/O

3/30
TDA7419

3 Audio Processor Features:


Input Multiplexer QD / SE: quasi-differential stereo inputs, with selectable single-ended mode
SE1: stereo single-ended input
SE2: stereo single-ended input
SE3 / AC2IN: stereo single-ended input / DSO filter input
In-Gain 0 to 15dB, 1dB steps
internal offset-cancellation (AutoZero)
separate second source-selector
Mixing stage mixable to front speaker-outputs
Loudness 2nd order frequency response
programmable center frequency (400Hz/800Hz/2400Hz)
15dB with 1dB steps
selectable low & high frequency boost
selectable flat-mode (constant attenuation)
Volume +15dB to -79dB with 1dB step resolution
soft-step control with programmable blend times
Bass 2nd order frequency response
center frequency programmable in 4 steps (60Hz/80Hz/100Hz/200Hz)
Q programmable 1.0/1.25/1.5/2.0
DC gain programmable
-15 to 15dB range with 1dB resolution
Middle 2nd order frequency response
center frequency programmable in 4 steps (500Hz/1KHz/1.5KHz/2.5KHz)
Q programmable 0.5/0.75/1.0/1.25
DC gain programmable
-15 to 15dB range with 1dB resolution
Treble 2nd order frequency response
center frequency programmable in 4 steps (10KHz/12.5KHz/15KHz/17.5KHz)
-15 to 15dB range with 1dB resolution
Spectrum analyzer seven bandpass filters
2nd order frequency response
programmable Q factor for different visual appearance
analog output
controlled by external serial clock
Speaker 4 independent soft step speaker controls, +15dB to -79dB with 1dB steps
Independent programmable mix input with 50% mixing ratio for front speakers
direct mute
Subwoofer 2nd order low pass filter with programmable cut off frequency
single-ended mono output
independent soft step level control, +15dB to -79dB with 1dB steps
Mute Functions direct mute
digitally controlled SoftMute with 3 programmable mute-times(0.48ms/0.96ms/
123ms)
Effect gain effect, or high pass effect with fixed external components

4/30
TDA7419

4 ELECTRICAL CHARACTERISTICS
Table 6. Electrical Characteristcs
VS = 8.5V; Tamb = 25°C; RL= 10kΩ ; all gains = 0dB; f = 1kHz; unless otherwise specified
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT SELECTOR
Rin Input Resistance All single ended inputs 70 100 130 kΩ
VCL Clipping level 2 VRMS
SIN Input Separation 80 100 dB
GIN MIN Min. Input Gain 0 dB
GIN MAX Max. Input Gain 15 dB
GSTEP Step Resolution 1 dB
VDC DC Steps Adjacent Gain Steps 1 mV
GMIN to GMAX 4 mV
Voffset Remaining offset with AutoZero 0.5 mV
DIFFERENTIAL STEREO INPUTS
Rin Input Resistance Differential 70 100 KΩ
CMRR Common Mode Rejection Ratio VCM =1 VRMS@ 1kHz 46 70 dB
VCM =1 VRMS@ 10kHz 46 60 dB
eNo Output Noise @ Speaker Outputs 20Hz-20kHz,flat;all stages 0dB 12 µV
MIXING CONTROL
MLEVEL Mixing Ratio Main / Mix Source -6/-6 dB
GMAX Max Gain 13 15 17 dB
AMAX Max Attenuation -83 -79 -75 dB
ASTEP Step Resolution 0.5 1 1.5 dB
LOUDNESS CONTROL
AMAX Max Attenuation 15 dB
ASTEP Step Resolution 1 dB
fPeak Peak Frequency fP1 400 Hz

fP2 800 Hz

fP3 2400 Hz
VOLUME CONTROL
GMAX Max Gain 15 dB
AMAX Max Attenuation -79 dB
ASTEP Step Resolution 0.5 1 1.5 dB
EA Attenuation Set Error G = -20 to +20dB -0.75 0 +0.75 dB
G = -79 to -20dB -4 0 3 dB
ET Tracking Error 2 dB
VDC DC Steps Adjacent Attenuation Steps 0.1 3 mV
From 0dB to GMIN 0.5 5 mV
SOFT MUTE
AMUTE Mute Attenuation 80 100 dB

5/30
TDA7419

Table 6. Electrical Characteristcs (continued)


VS = 8.5V; Tamb = 25°C; RL= 10kΩ ; all gains = 0dB; f = 1kHz; unless otherwise specified
Symbol Parameter Test Condition Min. Typ. Max. Unit
TD Delay Time T1 0.48 1 ms
T2 0.96 2 ms
T3 70 123 170 ms
VTH Low Low Threshold for SM Pin 1 V
VTH High High Threshold for SM Pin 2.5 V
RPU Internal pull-up resistor 32 45 58 kΩ
VPU Internal pull-up Voltage 3.3 V
BASS CONTROL
Fc Center Frequency fC1 54 60 66 Hz
fC2 72 80 88 Hz
fC3 90 100 110 Hz
fC4 180 200 220 Hz
QBASS Quality Factor Q1 0.9 1 1.1
Q2 1.1 1.25 1.4
Q3 1.3 1.5 1.7
Q4 1.8 2 2.2
CRANGE Control Range ±14 ±15 ±16 dB
ASTEP Step Resolution 0.5 1 1.5 dB
DCGAIN Bass-DC-Gain DC = off -1 0 +1 dB
DC = on (shelving filter, use for -4.4 dB
cut only)
MIDDLE CONTROL
CRANGE Control Range ±14 ±15 ±16 dB
ASTEP Step Resolution 0.5 1 1.5 dB
fc Center Frequency fC1 400 500 600 Hz
fC2 0.8 1 1.2 kHz
fC3 1.2 1.5 1.8 kHz
fC4 2 2.5 3 kHz
QBASS Quality Factor Q1 0.45 0.5 0.55
Q2 0.65 0.75 0.85
Q3 0.9 1 1.1
Q4 1.1 1.25 1.4
TREBLE CONTROL
CRANGE Clipping Level ±14 ±15 ±16 dB
ASTEP Step Resolution 0.5 1 1.5 dB
fc Center Frequency fC1 8 10 12 kHz
fC2 10 12.5 15 kHz
fC3 12 15 18 kHz
fC4 14 17.5 21 kHz
SPEAKER ATTENUATORS
GMAX Max Gain 14 15 16 dB

6/30
TDA7419

Table 6. Electrical Characteristcs (continued)


VS = 8.5V; Tamb = 25°C; RL= 10kΩ ; all gains = 0dB; f = 1kHz; unless otherwise specified
Symbol Parameter Test Condition Min. Typ. Max. Unit
AMAX Max Attenuation -83 -79 -75 dB
ASTEP Step Resolution 0.5 1 1.5 dB
AMUTE Mute Attenuation 80 90 dB
EE Attenuation Set Error 2 dB
VDC DC Steps Adjacent Attenuation Steps 0.1 5 mV
AUDIO OUTPUTS
VCL Clipping level d = 0.3% 2 VRMS
ROUT Output impedance 30 100 Ω
RL Output Load Resistance 2 kΩ
CL Output Load Capacitor 10 nF
VDC DC Voltage Level 3.8 4.0 4.2 V
SUBWOOFER ATTENUATOR
GMAX Max Gain 14 15 16 dB
AMAX Max Attenuation -83 -79 -75 dB
ASTEP Step Resolution 0.5 1 1.5 dB
AMUTE Mute Attenuation 80 90 dB
EE Attenuation Set Error 2 dB
VDC DC Steps Adjacent Attenuation Steps 1 5 mV
SUBWOOFER LOWPASS
fLP Lowpass Corner Frequency fLP1 72 80 88 Hz
fLP2 108 120 132 Hz
fLP3 144 160 176 Hz
HPF EFFECT
GMAX Max Gain 22 dB
GMIN Min Gain 4 dB
ASTEP Step Resolution 2 dB
SPECTRUM ANALYZER CONTROL
VSAOut Output Voltage Range 0 3.3 V
fC1 Center Frequency Band 1 62 Hz
fC2 Center Frequency Band 2 157 Hz
fC3 Center Frequency Band 3 392 Hz
fC4 Center Frequency Band 4 1 kHz
fC5 Center Frequency Band 5 2.51 kHz
fC6 Center Frequency Band 6 6.34 kHz
fC7 Center Frequency Band 7 16 kHz
Q Quality Factor Q1 1.8
Q2 3.5
fSAClk Clock Frequency 1 100 kHz
tSadel Analog Output Delay Time 2 µs
trepeat Spectrum Analyzer Repeat Time 50 ms
tintres Internal Reset Time 4.5 ms

7/30
TDA7419

Table 6. Electrical Characteristcs (continued)


VS = 8.5V; Tamb = 25°C; RL= 10kΩ ; all gains = 0dB; f = 1kHz; unless otherwise specified
Symbol Parameter Test Condition Min. Typ. Max. Unit
GENERAL
eNO Output Noise BW=20Hz to 20 kHz all gain = 12 µV
0dB
BW=20Hz to 20 kHz Output 6 µV
muted
S/N Signal to Noise Ratio all gain = 0dB flat; Vo =2VRMS 100 dB
D Distortion VIN = 1VRMS; all stages 0dB 0.01 %
SC Channel Separation left/right 90 dB

5 DESCRIPTION OF THE AUDIOPROCESSOR

5.1 Input stages


In the basic configuration, one stereo quasi-differential and three (two in case of DSO applications) single
ended stereo inputs are available.

5.1.1 Quasi-differential stereo Input (QD)


The QD input is implemented as a buffered quasi-differential stereo stage with 100k input-impedance at
each input. The attenuation is fixed to -3dB in order to adapt the incoming signal level.

5.1.2 Single-ended stereo input (SE1, SE2, SE3/AC2IN)


The input-impedance at each input is 100k and the attenuation is fixed to -3dB for incoming signals. The
input for SE3 is also configurable as part of the interface for external filters in DSO applications (AC2IN)

Figure 4. Input Stage

QD_L
QD_G QD Main
QD_R QD Source

SE4 In Gain

SE1_L

SE1_R
SE1 SE1

SE2_L
SE2
SE2_R
SE2

AC2IN_L/SE3L
SE3
SE3
AC2IN_R/SE3R

Second
Source

Output Stage

8/30
TDA7419

5.2 AutoZero
The AutoZero allows a reduction of the number of pins as well as external components by canceling any
offset generated by or before the In-Gain-stage (Please notice that externally generated offsets, e.g. gen-
erated through the leakage current of the coupling capacitors, are not canceled).
The auto-zeroing is started every time the input source is changed and needs max. 0.3ms for the align-
ment. To avoid audible clicks the Audio processor is muted before the loudness stage during this time.
The AutoZero feature is only present in the main signal-path.

5.2.1 AutoZero-Remain
In some cases, for example if the P is executing a refresh cycle of the IIC-Bus-programming, it is not use-
ful to start a new AutoZero-action because no new source is selected and an undesired mute would ap-
pear at the outputs. For such applications, it can be switched in the AutoZero-Remain-Mode (Bit 6 of the
subaddress-byte). If this bit is set to high, the AutoZero will not be invoked and the old adjustment-value
remains.

5.3 Loudness
There are four parameters programmable in the loudness stage:

5.3.1 Attenuation
Figure 5 shows the attenuation as a function of frequency at fP = 400Hz

Figure 5. Loudness Attenuation @ fP = 400Hz.

- 5

- 10

- 15

- 20

10 100 1K 10K

9/30
TDA7419

5.3.2 Peakr Frequency


Figure 6 shows the three possible peak-frequencies 400Hz , 800Hz and 2.4kHz.

Figure 6. Loudness Center frequencies @ Attn. = 15dB

- 5

- 10

- 15

- 20

10 100 1K 10K

5.3.3 Low & High Frequency Boost


Figure 7 shows the different Loudness-shapes in low & high frequency boost.

Figure 7. Loudness Attenuation , fC = 2.4KHz

- 5

- 10

- 15

- 20

10 100 1K 10K

10/30
TDA7419

5.3.4 Flat Mode


In flat mode the loudness stage works as a 0dB to -15dB attenuator.

5.4 SoftMute
The digitally controlled SoftMute stage allows muting/demuting the signal with a I2C-bus programmable
slope. The mute process can either be activated by the SoftMute pin or by the I2C-bus. This slope is real-
ized in a special S-shaped curve to mute slow in the critical regions (see Figure 8).
For timing purposes the Bit0 of the I2C-bus output register is set to 1 from the start of muting until the end
of demuting.

Figure 8. Sofmute Timing

1
EXT.
MUTE

+SIGNAL

REF

-SIGNAL

1
I2C BUS
OUT
D97AU634 Time

Note: Please notice that a started Mute-action is always terminated and could not be interrupted by a change of the mute -signal

5.5 SoftStep-Volume
When the volume-level is changed audible clicks could appear at the output. The root cause of those clicks
could either be a DC-Offset before the volume-stage or the sudden change of the envelope of the audi-
osignal. With the SoftStep feature both kinds of clicks could be reduced to a minimum and are no more
audible. The blend-time from one step to the next is programmable in four steps.

Figure 9. SoftStep Timing

VOUT

1dB

0.5dB

Time
SS Time
-0.5dB

-1dB
D00AU1170

Note: For steps more than 0.5dB the SoftStep mode should be deactivated because it could generate a hard 1dB step during the blend-time.

11/30
TDA7419

5.6 Bass
There are four parameters programmable in the bass stage:

5.6.1 Attenuation
Figure 9 shows the attenuation as a function of frequency at a center frequency of 80Hz.

Figure 10. Bass Control @ fC = 80Hz, Q = 1

15.0

10.0

5.0

dB
0.0

-5.0

-10.0

-15.0

10.0 100.0 1.0K 10.0K


Hz

5.6.2 Center Frequency


Figure 11 shows the four possible center frequencies 60, 80, 100 and 200Hz.

Figure 11. Bass center Frequencies @ Gain = 15dB, Q = 1

16

12

- 4

10 100 1K 10K

12/30
TDA7419

5.6.3 Quality Factors


Figure 12 shows the four possible quality factors 1, 1.25, 1.5 and 2.

Figure 12. Bass Quality factors @ Gain = 14dB, fC = 80Hz

15.0

12.5

10.0

7.5

5.0

2.5

0.0

10.0 100.0 1.0K 10.0K

5.6.4 DC Mode
It is used for cut only for shelving filter. In this mode the DC-gain is increased by 4.4dB. Inaddition the pro-
grammed center frequency and quality factor is decreased by 25% which can be used to reach alternative cen-
ter frequencies or quality factors.

Figure 13. Bass normal and DC Mode @ Gain = 14dB, fC = 80Hz


15.0

12.5

10.0

7.5

5.0

2.5

0.0

10.0 100.0 1.0K 10.0K

Note: The center frequency, Q and DC-mode can be set fully independently.

13/30
TDA7419

5.7 Middle
There are three parameters programmable in the middle stage:

5.7.1 Attenuation
Figure 14 shows the attenuation as a function of frequency at a center frequency of 1kHz.

Figure 14. Middle Control @ fC = 1 kHz, Q = 1

5.7.2 Center Frequency


Figure 14 shows the four possible center frequencies 500Hz, 1kHz, 1.5kHz and 2.5kHz.

Figure 15. Middle center Frequencies @ Gain = 14dB, Q = 1

14/30
TDA7419

5.7.3 Quality Factors


Figure 16 shows the four possible quality factors 0.5, 0.75, 1 and 1.25.

Figure 16. Middle Quality factors @ Gain = 14dB, fc = 1kHz

5.8 Treble
There are two parameters programmable in the treble stage:

5.8.1 Attenuation
Figure 16 shows the attenuation as a function of frequency at a center frequency of 17.5kHz.

Figure 17. Treble Control @ fC = 17.5kHz

20

15

10

- 5

- 10

- 15

- 20

10 100 1K 10K

15/30
TDA7419

5.8.2 Center Frequency


Figure 18 shows the four possible center frequencies 10k, 12.5k, 15k and 17.5kHz.

Figure 18. Treble Center Frequencies @ Gain = 15dB

20

15

10

- 5

10 100 1K 10K

5.9 Subwoofer Filter


The subwoofer lowpass filter has butterworth characteristics with programmable cut-off frequency (80/
120/160Hz)

Figure 19. Subwoofer Control

16/30
TDA7419

5.10 Spectrum Analyzer


A fully integrated seven-band spectrum analyzer with programmable quality factor is present. The spec-
trum analyzer consists of seven band pass filters with rectifier and sample capacitor that stores the max-
imum peak signal level since the last read cycle. This peak signal level can be read by a microprocessor
at the SAout-pin. To allow easy interfacing to an analog port of the microprocessor, the output voltage at
this pin is referred to device ground.
The microprocessor starts a read cycle with the negative going clock edge at the SAclk input. On the fol-
lowing positive clock edges, the peak signal level for the band pass filters is subsequently switched to
SAout. Each analog output data is valid after the time tSadel. A reset of the sample capacitors is induced
whenever SAclk remains high for the time tintres. Note that a proper reset requires the clock signal SAclk
to be held at high potential. Figure 20 shows the block diagram and figure 21 illustrates the read cycle
timing of the spectrum analyzer.

Figure 20. Spectrum analyzer block diagram

Figure 21. Timing of the spectrum analyzer

17/30
TDA7419

5.11 AC-Coupling
In some applications additional signal manipulations are desired, such as additional band equalizations.
For this purpose, an AC-Coupling can be placed before the loudness attenuator or speaker-attenuators,
which can be activated or internally shorted by I2C-Bus. In short condition, the input-signal of the speaker-
attenuator is available at the AC-Outputs. The input-impedance of this AC-Inputs is 50kΩ.

Figure 22. Diagram of AC coupling

ACOUTL ACOUTR ACINL ACINR

From Input MUX


To Output
InGain Filters Speakers

5.12 DSO Applications


For DSO applications, DSO filter is available for additional processing after the speaker control. It is a 2nd
order Butterworth highpass filter with selectable flat mode. Figure 23 shows the diagram of the DSO that
includes an external RC network.

Figure 23. DSO diagram

External RC network

ACOUT SE3IN ACIN


/AC2OUT /AC2IN /FILO

Gain Control

From speaker To
output

18/30
TDA7419

5.13 Output Selector and Mixing


The output-selector allows the front and rear speakers to connect to different sources. The setup of the
output selector is shown in Figure 24. A Mixing-stage is placed after the front speaker-attenuator and can
be set to mixing-mode. Having a full volume-attenuator for the mix-signal, the stage offers a wide flexibility
to adapt the mixing levels.

Figure 24. Output Selector

Mix_in
Attenuator

Front
Main
Attenuator
Rear
Second
Attenuator

Subwoofer
BassL+BassR Subwoofer output
Attenuator
filter

5.14 Audioprocessor Testing


In the test mode, which can be activated by setting bit D7 of the IIC subaddress byte and bit D0 of the
testing audioprocessor byte, several internal signals are available at the SE1R pin. In this mode, the input
resistance of 100kOhm is disconnected from the pin. Internal signals available for testing are listed in the
data-byte specification.

5.15 Test Circuit

Figure 25. Test Circuit

19/30
TDA7419

6 I2C BUS SPECIFICATION

6.1 Interface Protocol


The interface protocol comprises:
– a start condition (S)
– a chip address byte (the LSB determines read/write transmission)
– a subaddress byte
– a sequence of data (N-bytes + acknowledge)
– a stop condition (P)
– the max. clock speed is 500kbits/s
– 3.3V logic compatible
6.1.1 Receive Mode
S 1 0 0 0 1 0 0 R/W ACK TS AZ AI A4 A3 A2 A1 A0 ACK DATA ACK P

S = Start
R/W = "0" -> Receive Mode (Chip can be programmed by µP)
"1" -> Transmission Mode (Data could be received by µP)
ACK = Acknowledge
P = Stop

TS = Testing mode
AZ = Auto zero remain
AI = Auto increment

6.1.2 Transmission Mode


S 1 0 0 0 1 0 0 R/W ACK X X X X X X X SM ACK P

SM = Soft mute activated for main channel


X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated without new
chip address.

6.1.3 Reset Condition


A Power-On-Reset is invoked if the Supply-Voltage is below than 3.5V. After that the following data is writ-
ten automatically into the registers of all subaddresses:

MSB LSB

1 1 1 1 1 1 1 0

20/30
TDA7419

6.2 Subaddress (receive mode)

Table 7. Subaddress (receive mode)


MSB LSB FUNCTION
I2 I1 I0 A4 A3 A2 A1 A0
Testing Mode
0 Off
1 On
Auto Zero Remain
0 Off
1 On
Auto Increment Mode
0 Off
1 On
0 0 0 0 0 Main Source Selector
0 0 0 0 1 Main Loudness
0 0 0 1 0 Soft Mute / Clock Generator
0 0 0 1 1 Volume
0 0 1 0 0 Treble
0 0 1 0 1 Middle
0 0 1 1 0 Bass
0 0 1 1 1 Second Source Selector
0 1 0 0 0 Subwoofer / Middle / Bass
0 1 0 0 1 Mixing / Gain Effect
0 1 0 1 0 Speaker Attenuator Left Front
0 1 0 1 1 Speaker Attenuator Right Front
0 1 1 0 0 Speaker Attenuator Left Rear
0 1 1 0 1 Speaker Attenuator Right Rear
0 1 1 1 0 Mixing Level Control
0 1 1 1 1 Subwoofer Attenuator
1 0 0 0 0 Spectrum Analyzer / Clock Source / AC Mode
1 0 0 0 1 Testing Audio Processor

21/30
TDA7419

6.3 Data Byte Specification

Table 8. Main Selector (0)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Source Selector
0 0 0 QD/SE: QD
0 0 1 SE1
0 1 0 SE2
0 1 1 SE3
1 0 0 QD/SE: SE
1 0 1 mute
1 1 x mute
Input Gain
0 0 0 0 0dB
0 0 0 1 1dB
: : : : :
1 1 1 0 14dB
1 1 1 1 15dB
Auto Zero
0 on
1 off

Table 9. Main Loudness (1)


MSB LSB FUNCTION

D7 D6 D5 D4 D3 D2 D1 D0

Attenuation
0 0 0 0 0dB
0 0 0 1 -1dB
: : : : :
1 1 1 0 -14dB
1 1 1 1 -15dB

Center Frequency
0 0 Flat
0 1 400Hz
1 0 800Hz
1 1 2400Hz

High Boost
0 on
1 off

Loudness Soft Step


0 on
1 off

22/30
TDA7419

Table 10. Soft Mute / Clock Generator (2)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Soft Mute
0 on
1 off
Pin Influence for Mute
0 Pin and IIC
1 IIC
Soft Mute Time
0 0 0.48ms
0 1 0.96ms
1 x 123ms
Soft Step Time
0 0 0 0.160ms
0 0 1 0.321ms
0 1 0 0. 642ms
0 1 1 1.28ms
1 0 0 2.56ms
1 0 1 5.12ms
1 1 0 10.24ms
1 1 1 20.48ms
Clock Fast Mode
0 on
1 off

Table 11. Volume / Speaker / Mixing / Subwoofer Attenuation (3, 10-15)


MSB LSB FUNCTION

D7 D6 D5 D4 D3 D2 D1 D0

Gain/Attenuation
0 0 0 0 0 0 0 +0dB
0 0 0 0 0 0 1 +1dB
: : : : : : : :
0 0 0 1 1 1 1 +15dB
0 0 1 0 0 0 0 -0dB
0 0 1 0 0 0 1 -1dB
: : : : : : : :
1 0 1 1 1 1 0 -78dB
1 0 1 1 1 1 1 -79dB
1 1 x x x x x mute

Soft Step
0 on
1 off

23/30
TDA7419

Table 12. Treble Filter (4)


MSB LSB FUNCTION

D7 D6 D5 D4 D3 D2 D1 D0

Gain/Attenuation
0 1 1 1 1 -15dB
0 1 1 1 0 -14dB
: : : : : :
0 0 0 0 1 -1dB
0 0 0 0 0 0dB
1 0 0 0 0 0dB
1 0 0 0 1 +1dB
: : : : : :
1 1 1 1 0 +14dB
1 1 1 1 1 +15dB

Treble Center Frequency


0 0 10.0kHz
0 1 12.5kHz
1 0 15.0kHz
1 1 17.5kHz

Reference Output Select


0 External Vref (4V)
1 Internal Vref (3.3V)

Table 13. Middle Filter (5)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Gain/Attenuation
0 1 1 1 1 -15dB
0 1 1 1 0 -14dB
: : : : : :
0 0 0 0 1 -1dB
0 0 0 0 0 0dB
1 0 0 0 0 0dB
1 0 0 0 1 +1dB
: : : : : :
1 1 1 1 0 +14dB
1 1 1 1 1 +15dB
Middle Q Factor
0 0 0.5
0 1 0.75
1 0 1
1 1 1.25
Middle Soft Step
0 on
1 off

24/30
TDA7419

Table 14. Bass Filter (6)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Gain/Attenuation
0 1 1 1 1 -15dB
0 1 1 1 0 -14dB
: : : : : :
0 0 0 0 1 -1dB
0 0 0 0 0 0dB
1 0 0 0 0 0dB
1 0 0 0 1 +1dB
: : : : : :
1 1 1 1 0 +14dB
1 1 1 1 1 +15dB
Bass Q Factor
0 0 1.0
0 1 1.25
1 0 1.5
1 1 2.0
Bass Soft Step
0 on
1 off

Table 15. Second Source Selector (7)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Source Selector
0 0 0 QD/SE: QD
0 0 1 SE1
0 1 0 SE2
0 1 1 SE3
1 0 0 QD/SE: SE
1 0 1 mute
1 1 x mute
Input Gain
0 0 0 0 0dB
0 0 0 1 1dB
: : : : :
1 1 1 0 14dB
1 1 1 1 15dB
Rear Speaker Source
0 main source
1 second source

25/30
TDA7419

Table 16. Subwoofer /Middle / Bass (8)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Subwoofer Cut-off Frequency
0 0 flat
0 1 80Hz
1 0 120Hz
1 1 160Hz
Middle Center Frequency
0 0 500Hz
0 1 1000Hz
1 0 1500Hz
1 1 2500Hz
Bass Center Frequency
0 0 60Hz
0 1 80Hz
1 0 100Hz
1 1 200Hz
Bass DC Mode
0 on
1 off
Smoothing Filter
0 on
1 off (bypass)

Table 17. Mixing / Gain Effect (9)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Mixing to Left Front Speaker
0 on
1 off
Mixing to Right Front Speaker
0 on
1 off
Mixing Enable
0 on
1 off
Subwoofer Enable (OUTLR2 & OUTRR2)
0 on
1 off
Gain Effect for DSO Filter
0 0 0 0 4dB
0 0 0 1 6dB
: : : : :
1 0 0 0 20dB
1 0 0 1 22dB
1 0 1 x 0dB
1 1 x x 0dB

26/30
TDA7419

Table 18. Spectrum Analyzer / Clock Source / AC Mode (16)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Spectrum Analyzer Filter Q Factor
0 3.5
1 1.75
Reset Mode
0 IIC
1 Auto
Spectrum Analyzer Source
0 Bass
1 InGain
Spectrum Analyzer Run
0 on
1 off
Reset
0 on
1 off
Clock Source
0 internal
1 external
Coupling Mode
0 0 DC Coupling (without DSO)
0 1 AC coupling after InGain
1 0 DC Coupling (with DSO)
1 1 AC coupling after Bass

Table 19. Testing Audio Processor (17)


MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
Audio Processor Testing Mode
0 off
1 on
Test Multiplexer
0 0 0 0 0 Left InGain
0 0 0 0 1 Left InGain
0 0 0 1 0 Left Loudness
0 0 0 1 1 Left Loudness
0 0 1 0 0 Left Volume
0 0 1 0 1 Left Volume
0 0 1 1 0 Left Treble
0 0 1 1 1 Left Treble
0 1 0 0 0 Left Middle
0 1 0 0 1 SMCLK
0 1 0 1 0 Left Bass
0 1 0 1 1 VrefSCR
0 1 1 0 0 VGB1.26
0 1 1 0 1 SSCLK
0 1 1 1 0 Clock200
0 1 1 1 1 Mon
1 0 0 0 x Ref5V5
1 0 0 1 x BPout<1>
1 0 1 0 x BPout<2>
1 0 1 1 x BPout<3>
1 1 0 0 x BPout<4>
1 1 0 1 x BPout<5>
1 1 1 0 x BPout<6>
1 1 1 1 x BPout<7>
x x Not used

27/30
TDA7419

Figure 26. SO-28 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299

L 0.4 1.27 0.016 0.050


SO-28
S 8 ° (max.)

28/30
TDA7419

Table 20. Revision History


Date Revision Description of Changes

November 2004 1 First Issue

29/30
TDA7419

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.


All other names are the property of their respective owners

© 2004 STMicroelectronics - All rights reserved

STMicroelectronics group of companies


Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com

30/30
TDA7703/TDA7703R
Highly Integrated Tuner for AM/FM-Carradio
TARGET DESIGN SPECIFICATION

MAIN FEATURES

ƒ FULLY INTEGRATED VCO FOR WORLD TUNING


ƒ HIGH PERFORMANCE PLL FOR FAST RDS SYSTEM
ƒ AM/FM MIXERS WITH HIGH IMAGE REJECTION LQFP44
ƒ INTEGRATED AM-LNA AND AM-PINDIODE
ƒ AUTOMATIC SELF ALIGNMENT FOR IMAGE REJECTION
ƒ INTEGRATED IF-FILTERS WITH HIGH SELECTIVITY, DYNAMIC RANGE AND
ADAPTIVE BANDWIDTH CONTROL
ƒ DIGITAL IF SIGNAL PROCESSING WITH HIGH PERFORMANCE AND FREE OF
DRIFT
ƒ HIGH PERFORMANCE STEREODECODER
2
ƒ I C BUS CONTROLLED
ƒ SINGLE 5V SUPPLY
ƒ SINGLE QFP44 PACKAGE
ƒ RDS DEMODULATION WITH GROUP AND BLOCK SYNCHRONIZATION (TDA7703R
ONLY)

Part number Package Packing


TDA7703 LQFP44 (10x10x1.4 mm)
Tray
TDA7703R LQFP44 (10x10x1.4 mm)

6.Jan.09 Rev. 1.0 1/22


1.0 DESCRIPTION RDS decoder with group and block
synchronization.
The TDA7703/TDA7703R, a.k.a. HIT44,
belong to the HIT (Highly Integrated Tuner) The utilization of digital signal processing
family, a new generation of high performance results in numerous advantages against
tuners for carradio applications. today’s tuners:
They contain mixers and IF amplifiers for AM • Very low number of external components
and FM, fully integrated VCO and PLL • Very small space and easy application
synthesizer, IF-processing including adaptive • Very high selectivity due to digital filters
bandwidth control and Stereodecoder. The • High flexibility by software control
TDA7703R contains additionally an on-chip • Automatic alignment

2.0 FUNCTIONAL BLOCK DIAGRAM

2/22
TDA7703/TDA7703R

3.0 PINOUT

Figure 2

4.0 PIN ASSIGNMENT

Pin No. Pin Name Description


1 LF1 PLL loopfilter output
2 TCAGCFM FM AGC time constant
3 FMMIXDEC FM mixer decoupling
4 FMIXIN FM mixer input
5 GND-RF RF Ground
6 FMPINDRV FM AGC PIN diode driver
7 VCC-RF 5V supply for RF section
8 TCAM AM AGC time constant
9 PINDDEC AM AGC internal PIN diode decoupling
10 PINDIN AM AGC internal PIN diode input
11 GND-LNA GND of AM LNA, AM internal PIN diode , AM mixer, IF
12 LNAIN AM LNA input
13 LNADEC AM LNA decoupling
14 LNAOUT AM LNA output first stage
15 LNAIN2 AM LNA input 2nd stage
16 LNAOUT2 AM LNA output
17 LNADEC2 AM LNA decoupling 2nd stage

Rev. 1.0 3/22


TDA7703/TDA7703R

18 AMMIXIN AM mixer input


19 VREF165 1.65V reference voltage decoupling
20 VREFDEC 3.3V reference voltage decoupling
21 GND-DIG Digital GND
22 VCC-DIG 5V supply for digital logic
23 VCCREG1V2 VCC of 1.2V regulator
24 REG1V2 1.2V regulator output
25 VDD-3V3 3.3V VDD output / decoupling
26 SDA I2C bus data
27 SCL I2C bus clock
28 VDD-1V2 1.2V DSP supply
29 RDSINT I2C address selection (TDA7703)
2
RDS interrupt and I C address selection (TDA7703R)
30 RSTN Reset pin (active low)
31 VDD-1V2 1.2V DSP supply
32 GND-1V2 Digital GND for 1.2V VDD
33 VCC-DAC 5V supply of audio DAC
34 OSCOUT Xtal osc output
35 OSCIN Xtal osc input
36 GND-DAC Audio DAC GND
37 DACOUTL Audio output left
38 DACOUTR Audio output right
39 GND-IFADC IF ADC GND
40 VCC-IFADC 5V supply of IF ADC
41 VCC-PLL 5V supply of PLL
42 GND-PLL PLL GND
43 VCC-VCO 5V supply of VCO
44 GND-VCO VCO GND

Table 1

Rev. 1.0 4/22


TDA7703/TDA7703R

5.0 FUNCTION DESCRIPTION

5.1 FM-Mixer
The IMR mixer is optimized for optimum performance in case of a passive tuned prestage and for a
passive fixed bandpass without tuning for low-cost application.
The input frequency is downconverted to low IF with high image rejection.

5.2 FM - AGC
The programmable RFAGC senses the mixer input, the IFAGC senses the IFADC input to avoid
overload.
The PIN diode driver is able to drive external PIN diodes with up to 15mA current.
The time constant of the FM-AGC is defined with an external capacitor.

5.3 AM – LNA
The AM-LNA is integrated with low noise and high IIP2 and IIP3. The gain of the LNA is controlled
by the AGC. The maximum gain is set with an external resistor, typ. 26 dB with 1 Kohm.

5.4 AM-AGC
The programmable AM-RF-AGC senses the mixer input and controls the internal PIN diode and
LNA-gain.
First the LNA gain is reduced by about 10dB, then the PIN diodes are used to attenuate the signal.
The time constant of the AM-AGC is defined by an external capacitor and programmable internal
currents.

5.5 AM - Mixer
The IMR mixer supports LW and MW.
The input frequency is converted to low IF with high image rejection.

5.6 IF A/D CONVERTERS


A high performance IQ-IFADC converts the IF-signal to digital IF for the digital signal processing.

5.7 AUDIO D/A CONVERTERS


A stereo DAC provides the left / right audio signal after IF-processing and stereodecoding of the
DSP.

5.8 VCO
The VCO is fully integrated without any external tuning component. It covers all FM frequency
bands including EU, US, Japan, EastEU and the LW and MW AM-bands.

5.9 PLL
The high speed PLL is able to tune within about 300us for fast RDS applications (for TDA7703R).
The frequency step can go down to 5 kHz in FM and 500 Hz in AM.

5.10 Crystal oscillator


The device works with a standard 37.05 MHz fundamental tone crystal, and can be used also with
a 3rd overtone 37.05 MHz crystal.

5.11 DSP
The DSP and its hardware accelerators are performing all the digital signal processing. The main
program is fixed in ROM. Additional control parameters are accessible and can be set in the RAM.
It performs:

• digital downconversion of the IF


• bandwidth selection with variable controlled bandwidth
• FM/AM demodulation with softmute, weak signal processing and quality detection
• FM stereo decoding including highcut, stereoblend
• RDS demodulation including block and group synchronization with generation of an RDS
interrupt for the main uP (TDA7703R only)
• Autonomous control of RDS-AF tests (TDA7703R only)

Rev. 1.0 5/22


TDA7703/TDA7703R

5.12 I2C ADDRESS SELECTION / RDS INTERRUPT INTERFACE PIN


As explained also in 5.13.1, there is one pin (RDSINT, pin 29) dedicated to selecting the I2C
address of the device. In the TDA7703R only this pin serves the additional function of RDS
interrupt output to communicate to the uP when a new RDS block is available. This pin is voltage-
tolerant up to 3.5V and can drive currents up to 0.5mA.

5.13 SERIAL INTERFACE


The device is controlled with a standard I2C bus interface.
Through the serial bus, the processing parameters can be modifed and the signal quality
parameters and the RDS information (TDA7703R only) can be read out.
The operation of the device is handled through high level commands sent by the main car-radio uP
through the serial interface, which allow to simplify the operations carried out in the main uP. The
high level commands include among others:
- set frequency (which allows to avoid computing the PLL divider factors);
- start seek (the seek operation can be carried out by the TDA7703/TDA7703R) in a completely
autonomous fashion);
- RDS seek/search (jumps to AF and quality measurements are automatically sequenced)
(TDA7703R only).

5.13.1 I2C BUS ADDRESS MODE CHOICE


The device can communicate with the main uP via I2C, with two possible different addresses. The
configuration is chosen by setting the proper value (0V or VDD) at pin 29 and it is latched (e.g. made
effective) when the RSTN line transitions from low to high (when RSTN is low, the IC is in reset
mode).
The voltage level forced to pin 29 must be released to start the system operation a suitable time
after the RSTN line has gone high.

If pin 29 is kept low when RSTN rises, the I2C address is 0xC2(w)/0xC3(r).
If pin 29 is kept high when RSTN rises, the I2C address is 0xC8(w)/0xC9(r).

The status of pin 29 during the reset phase can be set to:
high, through an external <10 kohm resistor tied to 3.3V (pin 25), or
low, by not forcing any voltage on it from outside, as a 50 kohm internal pull-down resistor is present.

To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the RSTN line low until
the IC supply pins have reached their steady state, and then an additional time Treset (see section 6.9).

5.13.2 I2C BUS PROTOCOL

The I2C protocol requires two signals: clock (SCL) and data (SDA – bidirectional). The protocol requires an
acknowledge after any 8 bit transmission.

A “write” communication example is shown in the figure below, for an unspecified number of data bytes (see
Communication Protocol Manual for frame structure decription):

SDA a7 a6 … a0 d7 d6 … d0

SCL clk1 clk2 … clk8 clk9 clk1 clk2 … clk8 clk9

START address ACK data ACK STOP

Figure 3 I2C “write” sequence

The sequence is made of the following phases:


- START: SDA line transitioning from H to L with SCL H. This signifies a new transmission is starting;
- data latching: on the rising SCL edge. The SDA line can transition only when SCL is low (otherwise
its transitions are interpreted as either a START or a STOP transition);
- ACKnowledge: on the 9th SCL pulse the uP keeps the SDA line H, and the TDA7703 pulls it down if
communication has been successful. Lack of the acknowledge pulse generation from the TDA7703
means that the communication has failed;

Rev. 1.0 6/22


TDA7703/TDA7703R

- a chip address byte must be sent at the beginning of the transmission. The value can be C2 or C8
(according to the mode chosen at start-up during boot) for “write”;
- as many data bytes as one wants can follow the address before the communication is terminated.
See the next section for details on the frame format;
- STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the transmission.

Red lines represent transmissions from the TDA7703 to the uP.

A “read” communication example is shown in the figure below, for an unspecified number of data bytes (see
later on for frame structure decription):

SDA a7 a6 … a0 d7 d6 … d0

SCL clk1 clk2 … clk8 clk9 clk1 clk2 … clk8 clk9

START address ACK data ACK STOP

Figure 4 I2C “read” sequence

The sequence is very similar to the “write” one and has the same constraints for start, stop, data latching.
The differences follow:
- a chip address must always be sent by the uP to the TDA7703; the address must be C3 (if C2 had
been selected at boot) or C9 (if C8 had been selected at boot);
- a header is transmitted after the chip address (the same happens for “write”) before data are
transferred from the TDA7703 to the uP. See the next section for details on the frame format;
- when data are transmitted from the TDA7703 to the uP, the uP keeps the SDA line H;
- the ACKnowledge pulse is generated by the uP for those data bytes that are sent by the TDA7703 to
the uP. Failure of the uP to generate an ACK pulse on the 9th CLK pulse has the same effect on the
TDA7703 as a STOP.

The max. clock speed is 500kbits/s.

Rev. 1.0 7/22


TDA7703/TDA7703R

6.0 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
VCC Abs. Supply Voltage 5.5 V
Tstg Storage Temperature -55 150 °C

6.2 THERMAL DATA

Symbol Parameter Test Condition, Comments


Value Units
LQFP44 10x10, double-layer
Rth Thermal Resistance TBD K/W
PCB
LQFP44 10x10, single-layer
Rth Thermal Resistance TBD K/W
PCB

6.3 GENERAL KEY PARAMETERS

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
VCC 5V supply voltage 4.7 5 5.25 V
ICC supply current @ 5V see note (1) 220 295 mA
Tamb Ambient Temperature Range -20 70 °C
VVCCREG12 VCCREG12 supply voltage see note (2) 2 V
Digital core 1.2V supply when supplied externally
V1V2 (3) 1.08 1.2 1.32 V
voltage see note
V1V2 = 1.08V
120 mA
see note (3)
Digital core 1.2V supply V1V2 = 1.2V
I1V2 (3) 80 135 mA
current see note
V1V2 = 1.32V
(3) 150 mA
see note

(1) preliminary values, still under evaluation, subject to change.

(2) in the typical application supplied from 5V with a series resistor

(3) when the 1.2V supply is applied externally, and not using the internal 1.2V regulator

Rev. 1.0 8/22


TDA7703/TDA7703R

6.4 FM - SECTION

VCC = 4.7V to 5.25V; Tamb = 27°C; fc = 76 to 108 MHz; 60dBμV antenna level; mono signal, unless otherwise specified.
Antenna level equivalence: 0dBμV = 1μVrms, ref. deviation = 40 kHz

< table to be inserted >

6.5 AM - SECTION

< table to be inserted >

6.6 VCO

< table to be inserted >

6.7 Phase Locked Loop

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
Tsettle settling time FM Δf < 10Khz 300 µs
FM step FM Frequency step 5 Khz
AM step AM frequency step 500 Hz

6.8 IF ADC

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
DRFM Dynamic range in FM BW = ±100 kHz 90 dB
mixer 1 1.1 1.9
Input noise referred to mixer
vnoiseFM nV/√Hz
input
mixer 2 0.7 1.2
DRAM Dynamic range in AM BW = ±3 kHz 103 dB
Input noise referred to mixer
vnoiseAM 8.1 13.6 nV/√Hz
input

6.9 Audio DAC

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
Vout Max. output voltage Full scale 1 Vrms
BW Bandwidth 1dB attenuation 15 Khz
Rout Output resistance 600 750 900 Ω
onoise Output noise 60 95 uVrms
D Distortion -6 dBFS 0.03 0.04 %

6.10 IO interface pins

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
Iout = 500uA (max total
High level output voltage 2.9 3.2 V
current sum of all GPIOs)
Low level output voltage Iout = -1mA 0.1 0.3 V
Input voltage range 0 3.5 V
High level input voltage 2.0 V
Low level input voltage 0.8 V
Minimum time during which
Treset Reset time pin RSTN must be low so as 10 us
to reset the device
Boot mode configuration latch Minimum time during which
Tlatch 10 us
time the voltage applied at pins 25

Rev. 1.0 9/22


TDA7703/TDA7703R

and 39 must be kept in order


to latch the correct boot mode
(serial bus configuration)

Rev. 1.0 10/22


TDA7703/TDA7703R

6.12.1 I2C interface

The following parameters apply to the serial bus communication when I2C protocol has been selected at
start-up. For the other electrical characteristics of the pins, section 6.9 applies. The parameters of the
following table are defined as in Figure 1.

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
fSCL SCL Clock frequency 100 500 kHz
tAA SCL low to SDA data valid 300 ns
time the bus must be kept
tbuf free before a new 4.7 us
transmisison
tHD-STA START condition hold time 4.0 us
tLOW Clock low period 4.7 us
tHIGH Clock high period 4.0 us
tSU-SDA START condition setup time 4.7 us
tHD-DAT Data input hold time 0 us
tSU-DAT Data input setup time 250 ns
tR SDA & SCL rise time 1000 ns
tF SDA & SCL full time 300 ns
tSU-STOP Stop condition setup time 4.0 us
tDH Data out time 300 ns

Figure 1 I2C bus timing diagram

Rev. 1.0 11/22


TDA7703/TDA7703R

7.0 Overall system performance

7.1 FM overall system performance


Antenna level equivalence: 0dBμV = 1μVrms (Antenna terminal voltage with 50Ω source); no antenna dummy
Reference deviation = 40 kHz, de-emphasis = 50 us, faudio = 1 KHz, Vrf = 60 dBu
Unless otherwise specified.

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
Tuning range FM Eu (can be modified by the user) 87.5 108 MHz
Tuning step FM Eu (can be modified by the user) 100 kHz
Tuning range FM US (can be modified by the user) 87.5 107.9 MHz
Tuning step FM US (can be modified by the user) 200 kHz
Tuning range FM Jp (can be modified by the user) 76 90 MHz
Tuning step FM Jp (can be modified by the user) 100 kHz
Tuning range FM EEu (can be modified by the user) 65 74 MHz
Tuning step FM EEu (can be modified by the user) 100 kHz
Sensitivity S/N =26dB -4 dBu
@ 10dBu, no highcut, DISS
S/N TBD dB
BW = #2
@ 60dBu, mono 75 dB
@ 60dBu, Deviation = 75
Ultimate S/N 81 dB
kHz, mono
@ 60dBu, stereo 73 dB
Distortion Deviation= 75 kHz 0.05 %
Max deviation THD=3% TBD kHz
ΔF=100kHz, SINAD=30dB
desired 40 dBu, dev=40kHz,
Adjacent channel Selectivity TBD dB
400Hz
undesired. dev=40kHz, 1Khz
ΔF=200kHz, SINAD=30dB
desired 40 dBu, dev=40kHz,
Alternate Channel Selectivity TBD dB
400Hz
undesired. dev=40kHz, 1kHz
Desired = 10dBu
Max. Strong Signal Interferer SINAD = 30dB TBD dBu
Undesired ΔF = 1MHz
Desired = 40dBu,
dev=40kHz, 400Hz,
SINAD=30dB
Undesired1 =±400kHz, TBD dBu
dev=40kHz, 1 kHz
Undesired2=±800kHz, no
3 signal performance mod
Desired = 40dBu,
dev=40kHz, 400Hz,
SINAD=30dB
TBD dBu
Undesired1 =±1MHz,
dev=40kHz, 1 kHz
Undesired2=±2MHz, no mod
AM suppression m=30% 70 dB
Image rejection 70 dB
-0.33 -0.27
Logarithmic field strength @40 dBu (equiv. (equiv.
-0.3 -
indicator read “FM_Smeter_log” to 37 to 43
dBu) dBu)

Rev. 1.0 12/22


TDA7703/TDA7703R

7.2 AM MW overall system performance

Antenna level equivalence: 0dBμV = 1μVrms


Level referred to SG output
before antenna dummy; capacitive dummy 15pF+65pF
Reference modulation = 30%, faudio=400Hz, Frf=999kHz (1000 kHz for US), Vrf = 74 dBu
Unless otherwise specified

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
Tuning range MW Eu/Jp (can be modified by the user) 531 1629 kHz
Tuning step MW Eu/Jp (can be modified by the user) 9 kHz
Tuning range MW US (can be modified by the user) 530 1710 kHz
Tuning step MW US (can be modified by the user) 10 kHz
Sensitivity S/N =20dB 28 dBu
Ultimate S/N @ 80dBu 66 dB
Ref.=74dBu
AGC F.O.M. 50 60 dB
-10dB drop point
Distortion M=80% 0.3 %
ΔF=9kHz, SINAD=26dB
Adjacent channel Selectivity 33 dB
undesired. m=30%, 1kHz
ΔF=18kHz, SINAD=26dB
Alternate Channel Selectivity 50 dB
undesired. m=30%, 1kHz
ΔF=±40kHz
Strong signal interferer (1) desired=40dBu
17 dB
SNR undesired=100dBu, m=30%,
1kHz
ΔF=±40kHz
Strong signal interferer (1) desired=40dBu
1 dB
suppression undesired=100dBu, m=30%,
1kHz
ΔF=±40kHz
desired=80dBu
Strong signal interferer (1) undesired=100dBu, m=30%,
10 dB
cross-modulation 1kHz
maximum SNR of undesired
channel
ΔF=±400kHz
Strong signal interferer (2) desired=40dBu
18 dB
SNR undesired=100dBu, m=30%,
1kHz
ΔF=±400kHz
Strong signal interferer (2) desired=40dBu
1 dB
suppression undesired=100dBu, m=30%,
1kHz
ΔF=±400kHz
desired=80dBu
Strong signal interferer (2) undesired=100dBu, m=30%,
10 dB
cross-modulation 1kHz
maximum SNR of undesired
channel
Desired = 40dBu
SINAD = 26dB, blocking<6dB
Max. Strong signal interferer 89 dBu
Undesired ΔF = 400kHz,
m=30% (crossmod. test)
Image rejection 70 dB
TBD TBD
Logarithmic field strength @TBD dBu (equiv. (equiv.
TBD -
indicator read “AM_Smeter_log” to TBD to TBD
dBu) dBu)

Rev. 1.0 13/22


TDA7703/TDA7703R

7.3 AM LW overall system performance

Antenna level equivalence: 0dBμV = 1μVrms before antenna dummy; capacitive dummy 15pF+65pF
Reference modulation = 30%, faudio=400Hz, Frf=216kHz, Vrf = 74 dBu
Unless otherwise specified

Limits
Symbol Parameter Test Condition, Comments Units
Min Typ Max
Tuning range LW (can be modified by the user) 144 288 kHz
Tuning step LW (can be modified by the user) 1 kHz
Sensitivity S/N =20dB 30 dBu
Ultimate S/N @ 80dBu 66 dB
Ref.=74dBu
AGC F.O.M. 50 60 dB
-10dB drop point
Distortion M=80% 0.3 %
Image rejection 70 dB

Rev. 1.0 14/22


TDA7703/TDA7703R

8.0 FRONT-END PROCESSING

All the parameters in this section refer to the programmability of the FE part of the device
(registers). The part of the registers that are not described here have either fixed values (shown
in the tables with a black background) or values written by the tuner drivers, and therefore not
directly by the user (shown in the tables with a red background, if the registers are written
exclusively by the tuner drivers, and with orange background if they can be written by the user
for the manual FE alignment operation). The user can write the FE registers through the
dedicated commands, and must take care that the fixed values sent through such means are as
indicated in the tables below. After modifying a register containing at least one red background
bit, the user should send again the set band, set frequency and set image rejection commands
for proper operation.

< tables to be inserted>

Rev. 1.0 15/22


TDA7703/TDA7703R

9.0 WEAK SIGNAL PROCESSING


All the parameters in this section refer to the programmability of the DSP part of the device. The
typical values are those set by default parameters (start-up without parametric change from main
uP); the max and the min values refer to the programmability range. The values are referred to
the typical application. Wherever the possible values are a discrete set, all the possible
programmable values are displayed.

9.1 FM IF-processing

9.1.1 Dynamic channel selection filter (DISS)


(discrete set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
IF filter #2 - ±80 - kHz
DISS BW IF filter #1 response: - 3dB - ±60 - kHz
IF filter #0 - ±40 - kHz

9.1.2 Soft mute


(continuous set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
audio atten = 1 dB
SMsp Start point vs. field strength read “FM_softmute” 0 6 20 dBu
no adjacent channel present
audio atten = SMd + 1 dB
SMep End point vs. field strength read “FM_softmute” -6 -6 10 dBu
no adjacent channel present
SMd Depth -30 -15 0 dB
Field strength LPF cut-off
SMtauatt frequency for soft mute 0.1 100 4000 Hz
activation
Field strength LPF cut-off
SMtaurel frequency for soft mute 0.1 1 4000 Hz
release

9.1.3 Adjacent channel mute


(continuous set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
audio atten = 1 dB
Start point vs. field strength read “FM_softmute”
ACMsp TBD TBD TBD dBu
ratio (undesired/desired) adjacent channel at 150 kHz,
Fedv=40 kHz
audio atten = ACMd + 1 dB
End point vs. field strength read “FM_softmute”
ACMep TBD TBD TBD dBu
ratio (undesired/desired) adjacent channel at 150 kHz,
Fedv=40 kHz
ACMd Depth SMd 0 0 dB
ACMFSdes Adjacent channel mute weak
TBD TBD TBD dBu
ens field desensitazion threshold

Rev. 1.0 16/22


TDA7703/TDA7703R

9.1.3 Stereo blend


(continuous set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
field strength = 80 dBu, pilot
MaxSep Maximum stereo separation 0 40 50 dB
deviation = 6.75 kHz
separation = MaxSep - 1 dB
SBFSsp Start point vs. field strength 20 50 60 dBu
no multipath present
separation = 1 dB
SBFSep End point vs. field strength 20 30 60 dBu
no multipath present
Field strength-related
Vrf step-like variation from 20
SBFStM2S transition time from mono to 0.001 3 20 s
dBu to 80 dBu
stereo
Field strength-related
Vrf step-like variation from 80
SBFStS2M transition time from stereo to 0.001 0.5 20 s
dBu to 20 dBu
mono
separation = MaxSep - 1 dB
equivalent 19 kHz AM
SBMPsp Start point vs. multipath 5 10 80 %
modulation depth;
field strength = 80 dBu
separation = 1 dB
equivalent 19 kHz AM
SBMPep End point vs. multipath 5 30 80 %
modulation depth;
field strength = 80 dBu
multipath -related transition Vrf step-like variation from 20
SBMPtM2S 0.001 1 20 s
time from mono to stereo dBu to 80 dBu
multipath -related transition Vrf step-like variation from 80
SBMPtS2M 0.001 0.001 20 s
time from stereo to mono dBu to 20 dBu
Threshold on pilot tone
Pil ThrM2S Pilot detector stereo threshold deviation for mono-stereo 0.8 2.74 7 kHz
transition
Difference in pil. det.
Pilot detector threshold deviation threshold for stereo
Pil ThrHyst - 0.01 - kHz
hysteresis to mono transition compared
to PilThrM2S

Rev. 1.0 17/22


TDA7703/TDA7703R

9.1.4 High cut control


(continuous set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
minimum RF level for widest
HCFSsp Start point vs. field strength HC filter (filter # 7) 0 50 50 dBu
no multipath present
maximum RF level for
HCFSep End point vs. field strength narrowest HC filter (filter # 0) 0 30 40 dBu
no multipath present
Field strength-related
Vrf step-like variation from 60 (1)
HCFStW2N transition time from wide to -
dBu to 10 dBu
narrow band
Field strength-related
Vrf step-like variation from 0 (1)
HCFStN2W transition time from narrow to 14 100 s
dBu to 60 dBu
wide band
minimum RF level for widest
HC filter (filter # 7)
HCMPsp Start point vs. multipath equivalent 19 kHz AM 5 10 150 (2) %
modulation depth;
field strength = 80 dBu
maximum RF level for
narrowest HC filter (filter # 0)
HCMPep End point vs. multipath equivalent 19 kHz AM 5 30 150 (2) %
modulation depth;
field strength = 80 dBu
multipath -related transition
Vrf step-like variation from 20
HCMPtN2W time from narrow to wide 0.001 0.001 20 s
dBu to 80 dBu
band
multipath -related transition Vrf step-like variation from 80
HCMPtW2N 0.001 0.001 20 s
time from wide to narrow dBu to 20 dBu
Filter #7, -3 dB response
Maximum cut-off frequency of HCmin
HCmaxBW frequency, input signal with 14 18 kHz
high cut filter bank BW
pre-emphasis
Filter #0, -3 dB response
Minimum cut-off frequency of HCma
HCminBW frequency, input signal with 0.1 3 kHz
high cut filter bank xBW
pre-emphasis
HCnumFilt Number of discrete HC filters - - 8 (3) - -
(1): depends only on field strength filter time constant
(2): means that 100% equivalent 19 kHz AM modulation depth will not achieve full band narrowing
(3): intermediate filters (#6 - #1) cut-off frequencies exponentially spaced between HCmaxBW and HCminBW

9.1.6 De-emphasis filter


(discrete set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
De-emphasis time constant 1 - - 50 - us
DEtc
De-emphasis time constant 2 - - 75 - us

9.1.7 Stereo decoder

Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
PilSup Pilot signal suppression Pilot 9%, 19Khz, ref=40Khz - 60 - dB
F = 38 Khz - 70 - dB
SubcSup Subcarrier suppression F = 57 Khz - 70 - dB
F = 76 Khz - 80 - dB

Rev. 1.0 18/22


TDA7703/TDA7703R

9.2 AM IF-processing

9.1.1 Channel selection filter


Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
CSF BW Channel selection filter BW response: - 3dB - ±3.7 - kHz

9.2.1 Soft mute


(continuous set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
audio atten = 1 dB
SMsp Start point vs. field strength read “FM_softmute” 0 25 40 dBu
no adjacent channel present
audio atten = SMd + 1 dB
SMep End point vs. field strength read “FM_softmute” 0 0 30 dBu
no adjacent channel present
SMd Depth -40 -24 0 dB
Transition time for field
SMtauatt strength-dependent soft mute 0.001 0.1 10 s
activation
Transition time for field
SMtaurel strength-dependent soft mute 0.001 3 10 s
release

9.2.2 High cut control


(continuous set)
Range
Symbol Parameter Test Condition, Comments Units
Min Typ Max
minimum RF level for widest
HCFSsp Start point vs. field strength HC filter (filter # 7) 0 40 50 dBu
no multipath present
maximum RF level for
HCFSep End point vs. field strength narrowest HC filter (filter # 0) 0 30 50 dBu
no multipath present
Field strength-related
Vrf step-like variation from 60
HCFStW2N transition time from wide to 0.001 0.2 20 s
dBu to 10 dBu
narrow band
Field strength-related
Vrf step-like variation from 0
HCFStN2W transition time from narrow to 0.001 10 20 s
dBu to 60 dBu
wide band
Filter #7, -3 dB response
Maximum cut-off frequency of HCmin
HCmaxBW frequency, input signal with TBD TBD kHz
high cut filter bank BW
pre-emphasis
Filter #0, -3 dB response
Minimum cut-off frequency of HCma
HCminBW frequency, input signal with TBD TBD kHz
high cut filter bank xBW
pre-emphasis
HCnumFilt Number of discrete HC filters - - 8 - -

Rev. 1.0 19/22


TDA7703/TDA7703R

10.0 APPLICATION SCHEMATIC

Figure 5 (FM Eu/US/JP, AM LW/MW application)

Rev. 1.0 20/22


TDA7703/TDA7703R

11 PACKAGE INFORMATION

Rev. 1.0 21/22


TDA7703/TDA7703R

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.

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Rev. 1.0 22/22