Decoupled 4T dynamic CAM suitable for
high density storage
M. Chae, J.-W. Lee and S.H. Hong
A new four-transistor dynamic CAM (DCAM) is introduced. The
DCAM design addresses the inherent data retention problem by pro-
posing a modified sensing scheme. The results indicate over an order
of magnitude improvement in data retention time. In addition, the
DCAM structure realises a decoupled match-line structure, which
enables high density configurations not possible from previous 4T
CAM approaches.
Introduction: The importance of a high density CAM is becoming more
pronounced as fast and accurate data search operations are the key
driving forces in the modern information technology era. It is well
known that hardware search using a CAM or ternary CAM yields the
fastest results. However, a conventional CAM has two major disadvan-
tages. The first disadvantage is the large cell size of the CAM. A conven-
tional CAM requires nine transistors and is larger than a conventional 6T
SRAM. The second disadvantage is the subthreshold leakage current,
which becomes worse as the technology is scaled for higher densities.
Although there are efforts to reduce leakage current using design
approaches [1], the impact is not as high as resorting to costly modifi-
cation of the process technology. However, a possible solution to this
problem was presented in [2]. Their approach was to use dynamic mem-
ories. Since dynamic memories only have leakage through the transfer
gates connected to the word-lines (WLs), the leakage can easily be con-
trolled by using higher threshold transistors for the transfer gates.
Furthermore, a WL has a high capacitance owing to its global connec-
tion, and therefore, Vgs of the transfer gate is less susceptible to noise
coupling. On the other hand, a static CAM cell has the leakage
problem in the two cross-coupled inverters. The internal gates of the
cross-coupled inverters are more susceptible to noise, owing to small
capacitance. This leads to a significant subthreshold leakage current.
The proposed DCAM solves these two disadvantages by implementing
a new four-transistor cell in a dynamic configuration. However, using the
DCAM creates a new problem of data retention. Therefore, this Letter
focuses on describing the detailed functionality of the proposed
DCAM and on extending the data retention time.
BLB BL
WL
write (WL = 1)
logic1 logic0
net1 M1
BL BLB BL BLB
1 X 0 X
M2 net2 M3
search (WL = 0)
ML
logic1 logic0
M4
BL BLB BL BLB
1 0 0 1
Fig. 1 Proposed DCAM cell
4T DCAM cell: The concept of the dynamic CAM was first introduced
using five transistors [3]. Since then, efforts have been made to reduce
further the transistor count. A 4T dynamic CAM which was presented
in [4] suffered match-line leakage owing to match-line coupling
effects. This effect prevented their use as high density memories. The
same group later introduced dynamic CAMs with decoupled match-
lines using more than four transistors [5]. Fig. 1 shows the proposed
four-transistor DCAM cell which is suitable for the high density CAM
systems. It also has the decoupled match-line configuration through
the use of M4. There are basically two types of operation for a typical
CAM. One is data write and the other is data search. The data is
stored on the gates of M2 and M3. The tables in Fig. 1 show how the
bit-line values BL and BLB can be forced for write and search.
During the write operation, the word-line WL is raised high and BL
and BLB are forced according to the table for logic 1 or logic 0
storage. During the search operation, match-line ML is first precharged
to a high value while WL, BL and BLB are held low. This event
initialises net2 to a low value. The net2 will have at most |Vtp| (V),
where Vtp is the threshold voltage of the PMOS transistor. Therefore,
the magnitude of the threshold voltage of M4 should be made higher
ELECTRONICS LETTERS 31st March 2011 Vol. 47 No. 7
through the use of a high threshold transistor to prevent inadvertent
pull-down of ML. Subsequently, data is searched by either raising BL
or BLB. If a match occurs, the net2 stays low and the match-line is
kept floating at a high voltage. If the search fails, the net2 is raised
and ML pulled down. For instance, when net1 is high, M2 is on and
M3 is off. If the compared value is also high, forcing BL high and
BLB low, will leave ML in the precharged state indicating a match. If
the compared value is low, the high value of BLB will raise net2
through M2 and pull down ML, indicating a failed search.
DCAM cell access circuitry: Fig. 2 shows the necessary sensing and
driving circuitry to access the DCAM. For M2 and M3, each transistor
is illustrated with the parasitic gate-source and gate-drain capacitances
because they are the storage media and affect the data retention time.
The relative size difference of M2 (both width and length are proportion-
ally made large) and M3 in the Figure indicates the reliance of M2 gate
capacitances for data storage on net1. This approach is necessary to both
maximise the gate capacitance for data storage on the M2 and minimise
the effect of gate-source capacitance coupling through M3. If the PMOS
M3 is not properly sized in relation to M2, the data on net1 is adversely
affected, if the net1 stores a low value and a logic 1 search operation is
performed. The BL high will be coupled through the gate-source capaci-
tance of M3 and raise net1, which in turn prevents M3 from turning on.
But, since M2 is much larger than M3, the coupling effect on the M3
side can be moderated such that the PMOS is kept turned off. The oppo-
site effect of M2 weakly turning on, owing to rising of BLB when the
stored data is low, is effectively handled by the use of the high threshold
transistor for M4. The BL is accessed through M6 and BLB is accessed
through M5. Note that for BLB access, the BLB can be deliberately
forced low using the multiplexer shown in Fig. 2. This is necessary to
provide the initialisation sequence as well as a data retention improving
write scheme. The data retention is adversely affected by the capacitive
coupling between the BLB and the gate of M2. If the gate of M2 was
storing a high value, a sudden rise of BLB from 0V to Vdd, pushes
the gate of M2 to a value much higher than Vdd. This causes a
sudden increase in gate leakage through M2. This effect will be more
pronounced as the gate oxide layer thickness is reduced with technology
scaling. On the other hand, gate leakage due to BL side lowering is neg-
ligible since the initial value of BL was 0. Thus, for the proposed
DCAM cell, it is important to keep BLB low, most of the time. This cri-
terion is enforced by keeping BLB low during the write operations.
There are, however, further circuit improvements that can be made for
refresh operations such as adding a bit-line isolation transistor at location
X in Fig. 2 to limit the swing of BLB at the cell side (BLB above X)
while full sensing is allowed on the sensor side (BLB under X). Once
sensing is under way, the bit-line is cut off at X and the cell side of
the BL is pulled down to ground. This will minimise the coupling
effect and the gate leakage.
BLB BL
write WL
val_select
net1 M1
keep_low G G
WL M2 net2 M3
data
S
ML
D D S
datab M4
write
Vdd
search precharge ML sap
val_select
initialise
X
keep_low
WL
data
datab
write
san
val_select
keep_low M5 M6 write
datab 1
sel
smart_val data
0 bleq
Vdd/2 Vdd/2
Fig. 2 Proposed and implemented access scheme for DCAM cell
Results: Fig. 3a shows the entire architecture of the DCAM chip. A 64-
bit word can be searched from the stored 64 words. It is designed and
fabricated using a 0.13 mm seven-layer metal CMOS process. The cell
was conservatively drawn and was 3.3 × 3.9 mm. By sharing the
n-well area for PMOS between two cells, it is possible to significantly
reduce the size. As shown in the Figure, the digital control block
allows a simple serial interface to the DCAM memory array. The chip
uses 4 bits of inputs which are ‘reset_n’, ‘clk’, ‘enable’ and ‘input’.
The outputs are a serial data stream ‘output’ indicating the matched
result and a ‘fail’ bit indicating failure to find any matches. In the
case of multiple matches, the digital controller is designed to output
only the lowest matched address. Two types of tests were performed.
One was a functionality test to verify write and search operations and
the other was a data retention test. The functionality test showed
expected operation as shown in Fig. 3b. The top trace is the serial
output of the DCAM chip, the second trace is the serial input stream.
The test involved seven consecutive writes followed by a search oper-
ation. The searched data matches the 64-bit data of the sixth write
which was written in row address 5. The output correctly indicates a
match at row address 5 as shown in the blown-up portion of the
output trace. For the retention test, the ‘val_select’ signal of Fig. 2 is
used to either select the complementary data signal or zero. When
BLB was kept high, the retention time of data high in net1 was a
mere 83 ms using a 1.2 V power supply. On the other hand, with BLB
kept low, the retention time was significantly improved to 1ms.
Conclusion: A four-transistor dynamic CAM cell suitable for high
density memory configuration is introduced. In addition, owing to the
dynamic storage, the low standby power dissipation further helps in
accommodating higher densities. The proposed DCAM cell, combined
with a modified bit-line control scheme, demonstrated a significant
improvement in the data retention time.
Acknowledgments: This work was supported by the Korea Science and
Engineering Foundation (KOSEF) grant funded by the Korea govern-
ment (MEST) (no. 2010-0015259). The CAD tools used in this work
was supported by the IDEC
# The Institution of Engineering and Technology 2011
17 November 2010
doi: 10.1049/el.2010.7283
M. Chae, J.-W. Lee and S.H. Hong (College of Electronics and
Information, Kyung Hee University, 1, Seocheon-dong, Giheung-gu,
Yongin-si, Gyeonggi-do 446-701, Republic of Korea)
E-mail: daniel@khu.ac.kr

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a b

Fig. 3 Memory system architecture, and write and search test result
a Memory system architecture
b Write and search test result

ELECTRONICS LETTERS 31st March 2011 Vol. 47 No. 7