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rmat
Mark Litterick
Verilab GmbH.
SNUG 2016 1
Agenda
SNUG 2016 2
Introduction
SNUG 2016 3
Active and Passive Operation
observe internal generate
• Active DUT behavior response
(no stimulus) UVC B ENV stimulus
– generate or affect stimulus (DUT is master)
• Passive PASSIVE PASSIVE
MASTER SLAVE
– observe and check behavior
• Master DUT UVC C
– initiates protocol traffic M
ACTIVE
M S SLAVE
• Slave UVC A
– responds to initiator ACTIVE S UVC D
• Verification components MASTER S M M
PASSIVE
S
– all combinations required SLAVE
– active/passive master/slave generate observe external
request stimulus DUT behavior
(DUT is slave) (no response)
SNUG 2016 4
Proactive Masters and Reactive Slaves
REQ
EXPLICIT 1 PROACTIVE 2
TEST STIMULUS MASTER DUT
3
RESP
• Proactive Masters:
– Test controls when sequences are executed on the UVC and request timing to DUT
– Stimulus blocks test flow waiting for DUT response
REQ
IMPLICIT OR REMOTE 1
DUT PROVOCATION DUT 2 REACTIVE
SLAVE
3
RESP
• Reactive Slaves:
– Timing of DUT requests is unpredictable (e.g. due to embedded microcode execution)
– UVC must react to request and respond autonomously without blocking test flow
SNUG 2016 5
Proactive Master Architecture
constrained-random DUT interaction via
sequence-based stimulus signal interface
UVC ENVIRONMENT
MASTER AGENT
SVA
SEQUENCER DRIVER
REQ REQ
ITEM
VIF
INTERFACE
DUT
MONITOR (SLAVE)
RESP
• coverage
VIF
• checks
TRANSACTION
SNUG 2016 6
Proactive Master Operation
test or higher-level: generate sequence item drive request signals
start / do sequence & pass to driver via TLM according to protocol
on sequencer (& wait for response)
UVC ENVIRONMENT
MASTER AGENT
SVA
SEQUENCER DRIVER
1 REQ REQ
ITEM 3
VIF
2
INTERFACE
DUT
MONITOR 4 (SLAVE)
RESP
5 • coverage
VIF
• checks
TRANSACTION
SNUG 2016 7
Reactive Slave Architecture
forever sequence
executed on sequencer
similar architecture
to proactive master
UVC ENVIRONMENT
SLAVE AGENT
SVA
other common
SEQUENCER DRIVER architectures
RESP RESP
ITEM are discussed
VIF
INTERFACE
TLM FIFO in the paper...
DUT
REQ MONITOR (MASTER)
REQ
• coverage
VIF
• checks
TRANSACTION
SVA
SEQUENCER DRIVER
0 RESP RESP
ITEM 3
VIF
2
INTERFACE
TLM FIFO
DUT
1 REQ MONITOR (MASTER)
REQ
• coverage
VIF
4 • checks
TRANSACTION
SNUG 2016 9
Monitor Code normal analysis port
(for complete transactions) UVC ENV
SLAVE AGENT
class my_slave_monitor extends uvm_monitor;
... S D
DUT
uvm_analysis_port #(my_transaction) transaction_aport;
uvm_analysis_port #(my_transaction) request_aport; M
my_transaction m_transaction;
... additional analysis port
task monitor_bus();
(for request transactions)
forever begin
// decode bus signals in accordance with protocol
... publish observed request
// when request is complete...
(to sequencer)
request_aport.write(m_transaction);
...
// continue to decode response... publish complete transaction
transaction_aport.write(m_transaction); (to any subscribers)
end
endtask
endclass
SNUG 2016 10
Sequencer Code
UVC ENV
SLAVE AGENT
class my_slave_sequencer extends
uvm_sequencer #(my_slave_seq_item); S D
DUT
...
uvm_analysis_export #(my_transaction) request_export; M
uvm_tlm_analysis_fifo #(my_transaction) request_fifo;
...
function new(string name, uvm_component parent); additional analysis export
... and TLM analysis FIFO
request_export = new(”request_export", this);
request_fifo = new(”request_fifo", this);
endfunction
construct TLM components
function void connect_phase(...);
...
request_export.connect(request_fifo.analysis_export);
endfunction
endclass connect analysis export direct to FIFO
(no need to implement write method)
SNUG 2016 11
Sequence Code
UVC ENV
class my_slave_response_seq extends SLAVE AGENT
uvm_sequence #(my_slave_seq_item);
my_slave_seq_item m_item; S D
my_transaction m_request; call forever loop inside sequence DUT
... (sequence runs throughout phase: M
task body(); ...do not raise and drop objections!)
forever begin
p_sequencer.request_fifo.get(m_request); wait for a transaction request
case (m_request.m_direction)
(fifo.get is blocking)
...
READ : begin
generate response item
`uvm_do_with(m_item,{
m_item.m_resp_kind == READ_RESPONSE;
based on observed request
m_item.m_delay <= get_max_delay();
m_item.m_data == get_data(m_request.m_addr);
...
}) note: code examples assume:
end • protocol defines base transaction
... • seq_item extends base transaction
SNUG 2016
(to add constraints and control knobs) 12
Driver Code
UVC ENV
SLAVE AGENT
class my_slave_driver extends uvm_driver #(my_slave_seq_item);
my_slave_seq_item m_item; S D
... DUT
task run_phase(...); M
...
forever begin
seq_item_port.get_next_item(m_item);
drive_item(m_item);
seq_item_port.item_done();
end
standard driver-sequencer interaction
endtask
SNUG 2016 13
Agent Code
UVC ENV
SNUG 2016 14
Test Environment Code
TEST ENV
• Select default sequence in environment (can override it from test):
UVC ENV
class my_test_env extends uvm_env;
... SLAVE AGENT
function void build_phase(...); S D
... DUT
uvm_config_db #(uvm_object_wrapper)::set(this, M
"uvc_env.slave_agent.sequencer.main_phase",
"default_sequence”,
my_slave_response_seq::type_id::get()); set the default_sequence for the
main_phase of slave sequencer
• OR start explicit sequence from test (leave default as null):
note: default_sequence for sequencer
class my_test extends uvm_test; component is deprecated in UVM-1.2
...
=> use the main_phase instead
task run_phase(...);
...
start a specific sequence on
fork the required slave sequencer
slave_seq.start(test_env.uvc_env.slave_agent.sequencer);
join_none
SNUG 2016 15
Additional Features
Storage, Control Agent, & Error Injection
SNUG 2016 16
Reactive Slave with Memory/Storage
SNUG 2016 17
Slave With Storage Architecture
important to note that
slave storage is not part
of DUT memory model
(...part of target slave)
UVC ENVIRONMENT
SLAVE AGENT
SVA
SEQUENCER DRIVER
RESP RESP
handle from ITEM
VIF
INTERFACE
sequencer TLM FIFO
for stimulus DUT
REQ MONITOR (MASTER)
REQ
• coverage
VIF
STORAGE
small or sparse • checks
memory array TRANSACTION
with API
SVA
SEQUENCER DRIVER response data
RESP RESP
ITEM
VIF
INTERFACE
TLM FIFO
tests: DUT
REQ MONITOR (MASTER)
• preload memory REQ
• coverage
VIF
• check content STORAGE
• checks monitor: update
• modify content TRANSACTION storage based on
observed traffic
// in sequences via sequencer
p_sequencer.slave_sequencer.storage.write(...) storage.init(); // on reset
// or via test component hierarchy storage.write(m_addr, m_data);
if(env.slave.storage.read(addr)!= ’h1234)...
SNUG 2016 19
Reactive Slave With Control Agent
SNUG 2016 20
Control Agent Architecture & Operation
control agent is not controlling slave generates responses
slave response directly, but and publishes transactions
high-level scenario timing
UVC ENVIRONMENT
based on observed DUT traffic
SLAVE AGENT
SVA
test sequence waits SEQUENCER DRIVER
RESP RESP
ITEM
VIF
for slave traffic of
INTERFACE
1
particular kind... TLM FIFO
DUT
CONTROL AGENT REQ MONITOR (MASTER)
REQ
• coverage
VIF
SEQUENCER DRIVER STORAGE
2 • checks
0 ITEM 3 TRANSACTION
0
SNUG 2016 23
Error Injection Architecture & Operation
increment counter add error counters if >0 set error knob in item inject error in next
from test scenario to config object and decrement counter autonomous response
UVC ENVIRONMENT
CONFIG OBJECT SLAVE AGENT
SVA
• crc_error_count
SEQUENCER DRIVER
• latency_error_count 2 ITEM
RESP RESP
3
VIF
INTERFACE
• length_error_count
TLM FIFO
DUT
CONTROL AGENT REQ MONITOR (MASTER)
REQ
• coverage 1
VIF
SEQUENCER DRIVER STORAGE
• checks
0 ITEM TRANSACTION
SNUG 2016 25
ny Thank You
rmat
SNUG 2016 26