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PREINFORME N 6

PUNTO B.2.

QUARTUS

library ieee;
use ieee.std_logic_1164.all;
entity puntob2 is
port(x : in std_logic;
clk : in std_logic;
z : out std_logic);
end puntob2;

architecture fun of puntob2 is


type estados is (A, B, C, D, E, F); --estados internos
signal est_ant, est_sig: estados;
begin
proceso_1: process (est_ant, x, clk)
begin
case est_ant is
when A=> z <='0';
if x<='0' then est_sig<=A;
else est_sig<=B;
end if;

when B=> z <='0';


if x<='0' then est_sig<=A;
else est_sig<=C;
end if;

when C=> z <='0';


if x<='0' then est_sig<=D;
else est_sig<=B;
end if;

when D=> z <='1';


if x<='0' then est_sig<=E;
else est_sig<=D;
end if;

when E=> z <='1';


if x<='0' then est_sig<=E;
else est_sig<=F;
end if;

when F=>
if x<='0' then est_sig<=A;
z <= '0';
else est_sig<=D;
z <= '1';
end if;
end case;
end process proceso_1;

proceso_2:process (clk)
begin
if (clk'event and clk='1') then
est_ant <= est_sig;
end if;
end process proceso_2;

end fun;

XILINX

Como el codigo VHDL es el mismo para quartus entpnces mostraremos solo el vector de pruebas.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY waveform IS
END waveform;

ARCHITECTURE behavior OF waveform IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT puntob2
PORT(
x : IN std_logic;
clk : IN std_logic;
z : OUT std_logic
);
END COMPONENT;

--Inputs
signal x : std_logic := '0';
signal clk : std_logic := '0';

--Outputs
signal z : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: puntob2 PORT MAP (
x => x,
clk => clk,
z => z
);

proceso_1:process
begin
wait for 10 ns;
clk <= not clk;
end process;

proceso_2:process
begin
wait for 40 ns;
x <= not x;
end process;

END;

WINCUPL
Name puntob2 ;
PartNo 00 ;
Date 11/5/2018 ;
Revision 01 ;
Designer Engineer ;
Company viacom ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 1 = clk ; /* */
PIN 2 = xs ; /* */

/* *************** OUTPUT PINS *********************/


PIN 15 = f ; /* */
PIN 16 = q2 ; /* */
PIN 17 = q1 ; /* */
PIN 18 = q0 ; /* */

field maquina=[q2,q1,q0];

$define Sa 'b' 000


$define Sb 'b' 001
$define Sc 'b' 010
$define Sd 'b' 011
$define Se 'b' 100
$define Sf 'b' 101
$define Sg 'b' 110
$define Sh 'b' 111

sequence maquina{
present Sa
if xs next Sb;
if !xs next Sa;
present Sb
if xs next Sc;
if !xs next Sa;
present Sc
if xs next Sb out f;
if !xs next Sd;
present Sd
if xs next Se out f;
if !xs next Sd out f;
present Se
if xs next Sf out f;
if !xs next Se out f;
present Sf
if xs next Sd out f;
if !xs next Sa;
}

PROTEUS
(D0) ?
U2:A U1:B U1:A

12
11
3

2
D

D
CLK

CLK

CLK
1 4 13 10 1 4
R S R S R S

Q
6

5
74HC74 74HC74 74HC74

1
2 U3:A 12 U4:A
13 74HC11 1
3
3 2
4 U3:B 6
5 74HC11 74HC32

1
U6:A 3 U4:B
2 74HC08 4
6
9 5
10 U3:C 8
11 74HC11 74HC32

0 1
2 U7:A 9 U6:B
1 2 8 74HC4075 4
6
5 U4:C
9
9 74HC08 8
74HC08 8 10
10 U6:C
74HC32

12
U4:D 11 U6:D
13 74HC32 12
11
13
U9:B
74HC08 4

1 5
6
?
U8:A 3
2 74HC08 1 74HC32
U9:A 3 U8:B
2 74HC32 4
6
5

74HC08

PUNTO C.3.

QUARTUS

library ieee;
use ieee.std_logic_1164.all;
entity funcion is
port(x : in std_logic_vector(1 downto 0);
clk : in std_logic;
f : out std_logic);
end funcion;

architecture fun of funcion is


type estados is (A, B, C, D); --estados internos
signal est_ant, est_sig: estados;
begin
proceso_1: process (est_ant, x, clk)
begin
case est_ant is
when A=> f <='0';
if x="01" then est_sig<=A;
elsif x="10" then est_sig<=A;
else est_sig<=B;
end if;
when B=>f<='0';
if x="01" then est_sig<=A;
elsif x="10" then est_sig<=A;
else est_sig<=C;
end if;

when C=>f<='0';
if x="01" then est_sig<=A;
elsif x="10" then est_sig<=A;
else est_sig<=D;
end if;

when D=>
if x="01" then est_sig<=A;
elsif x="10" then est_sig<=A;
f<='0';
else est_sig<=B;
f<='1';
end if;
end case;
end process proceso_1;

proceso_2:process (clk)
begin
if (clk'event and clk='1') then
est_ant <= est_sig;
end if;
end process proceso_2;

end fun;

XILINX

Ya que el código VHDL será el mismo para Quartus como para Xilinx, solo mostraremos el test
bench.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY wave IS
END wave;

ARCHITECTURE behavior OF wave IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT puntoc3
PORT(
x : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
f : OUT std_logic
);
END COMPONENT;

--Inputs
signal x : std_logic_vector(1 downto 0) := (others => '0');
signal clk : std_logic := '0';

--Outputs
signal f : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: puntoc3 PORT MAP (
x => x,
clk => clk,
f => f
);

proceso_1:process
begin
wait for 10 ns;
clk <= not clk;
end process;

proceso_2:process
begin
wait for 80 ns;
x(0) <= not x(0);
end process;

proceso_3:process
begin
wait for 160 ns;
x(1) <= not x(1);
end process;

END;

WINCUPL
Name puntob2 ;
PartNo 00 ;
Date 11/5/2018 ;
Revision 01 ;
Designer Engineer ;
Company viacom ;
Assembly None ;
Location ;
Device g22v10 ;

/* *************** INPUT PINS *********************/


PIN 1 = clk ; /* */
PIN 2 = x1 ; /* */
PIN 3 = x2 ; /* */

/* *************** OUTPUT PINS *********************/


PIN 15 = z ; /* */
PIN 17 = q1 ; /* */
PIN 18 = q0 ; /* */

field maquina=[q1,q0];

$define Sa 'b'00
$define Sb 'b'01
$define Sc 'b'10
$define Sd 'b'11

sequence maquina{
present Sa
if !x1 & !x2 next Sb;
if !x1 & x2 next Sa;
if x1 & x2 next Sb;
if x1 & x2 next Sa;
present Sb
if !x1 & !x2 next Sc;
if !x1 & x2 next Sa;
if x1 & x2 next Sc;
if x1 & x2 next Sa;
present Sc
if !x1 & !x2 next Sd;
if !x1 & x2 next Sa;
if x1 & x2 next Sd;
if x1 & x2 next Sa;
present Sd
if !x1 & !x2 next Sd out z;
if !x1 & x2 next Sa;
if x1 & x2 next Sd out z;
if x1 & x2 next Sa;
}

PROTEUS

PUNTO D.

QUARTUS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity flipflop is
port (D, clock :in std_logic;
Q : buffer std_logic);
end flipflop;
architecture Behavioral of flipflop is
begin
process(D, clock)
begin
if (clock'event and clock='1') then
Q <= D;
else Q <= Q;
end if;
end process;

end Behavioral;
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity reg_10_faq is
port (re : in std_logic_vector(3 downto 0);
clock_1: in std_logic;
Qo : out std_logic_vector(3 downto 0));
end reg_10_faq;

architecture ar_2 of reg_10_faq is


component flipflop is
port( D: in std_logic;
clock: in std_logic;
Q: buffer std_logic);
end component;

signal x: std_logic_vector(3 downto 0);


begin
f_1 : flipflop port map (re(0), clock_1, x(0));
f_2 : flipflop port map (re(1), clock_1, x(1));
f_3 : flipflop port map (re(2), clock_1, x(2));
f_4 : flipflop port map (re(3), clock_1, x(3));
Qo <= x;

end ar_2;
-----------------------------------------------------------
component mux2_1
port( x:in std_logic;
y:in std_logic;
sell: in std_logic;
Z: out std_logic);
end component;

----------------------------------------------------------
component fflop is
port( D: in std_logic;
clock: in std_logic;
Q: buffer std_logic);
end component;
----------------------------------------------------------
component fulladder
port (A0, B0, Cin0 : in std_logic;
S0, Cout0 : out std_logic);
end component;

XILINX

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY wave IS
END wave;

ARCHITECTURE behavior OF wave IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT puntoc3
PORT(
X,s : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
f : OUT std_logic
);
END COMPONENT;

--Inputs
signal x : std_logic_vector(1 downto 0) := (others => '0');
signal clk : std_logic := '0';

--Outputs
signal f : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: puntoc3 PORT MAP (
x => x,
clk => clk,
f => f
);

proceso_1:process
begin
wait for 10 ns;
clk <= not clk;
end process;

proceso_2:process
begin
wait for 80 ns;
x(0) <= not x(0);
end process;

proceso_3:process
begin
wait for 160 ns;
x(1) <= not x(1);
end process;

proceso_4:process
begin
wait for 160 ns;
s(1) <= not x(1);
end process;

proceso_5:process
begin
wait for 160 ns;
s(1) <= not x(1);
end process;
END;

PROTEUS
U7:A
4

2 5
D Q
S

3
CLK
6
Q U6
R

2 4
1A 1Y
1

74HC74 9 3
U4:C 1B
8 5 7
2A 2Y
10 74HC08 6
U7:B 11
2B
9
10

3A 3Y
10
3B
12 9 14 12
D Q 4A 4Y
S

13
4B
11
CLK
1
A/B
8 15
Q E
R

74HC157
13

74HC74

U1:A
4

2 5
S

D Q U5
3 2 4
CLK 1A 1Y U8
4 3
1B
Q
6 74HC08
U4:B
6 5
2A 2Y
7 6
1X0 1Y
7
?
R

5 6 5
2B 1X1
11 9 4
3A 3Y 1X2
1

74HC74 10 3
3B 1X3
14 12
U2:B 4A 4Y
13 10 9
10

4B 2X0 2Y
11
2X1
12 9 1 12
D Q A/B 2X2
S

15 13
E 2X3
11
CLK

Q
8
74HC157
A 0 14
2
A
B
R

B 0 1
15
1E
2E
13

74HC74
74HC153

U1:B
10

12 9
S

D Q
11
CLK
8
Q U3 U9:A
R

2 4 2 4
1A 1Y A Y0
13

74HC74 3 3 5
1B B Y1
1 5 7 6
U2:A U4:A 2A 2Y Y2
3 6 1 7
2B E Y3
4

2 74HC08 11 9
3A 3Y
2 5 10 74HC139
S

D Q 3B
14 12

13
4A 4Y
5

1
3 13
CLK 4B
6 1
Q A/B
R

15
E
6

12

2
11

X
3

74HC74 74HC157

1
74HC08 74HC08 74HC08

U11:A U11:B U4:D


1

12

13

U11:A(A)

?
UNIVERSIDAD MAYOR DE SAN ANDRÉS
FACULTAD DE INGENIERÍA
CARRERA DE INGENIERIA ELECTRÓNICA

SISTEMAS DIGITALES
1
PREINFORME DE LABORATORIO
Aplicación de LOS CIRCUITOS
SECUENCIALES

DOCENTE: Ing. OROPEZA ROBERTO

AUXILIAR: Univ. JESSICA

ESTUDIANTE: Univ. VALDEZ VILASECA YHASSIR A.

GRUPO: “D – 5”

PUNTOS DISEÑO O SIMULACION TOTAL


TEORIA

NOTA :

LA PAZ-BOLIVIA
2018