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VIN + VIN+ 3
VOUTA 1 14 VOUTD
4 VIN–
A D
MCP6001 VOUT VINA– 2 - + + - 13 VIND–
- MCP6001U VINA+ 3 12 VIND+
SOT-23-5 VDD 4 11 VSS
VSS
VIN+ 1 5 VDD VINB+ 5 10 VINC+
+
VSS 2 VINB– 6 - + + - 9 VINC–
R1 - B C
R2 VIN– 3 4 VOUT VOUTB 7 8 VOUTC
R1
Gain = 1 + ------
R2
VREF
Non-Inverting Amplifier
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD /2, RL = 10 kΩ
to VDD /2, and VOUT ~ VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -7.0 — +7.0 mV VCM = VSS
Input Offset Drift with Temperature ∆VOS/∆TA — ±2.0 — µV/°C TA= -40°C to +125°C,
VCM = VSS
Power Supply Rejection PSRR — 86 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current: IB — ±1.0 — pA
Industrial Temperature IB — 19 — pA TA = +85°C
Extended Temperature IB — 1100 — pA TA = +125°C
Input Offset Current IOS — ±1.0 — pA
Common Mode Input Impedance ZCM — 1013||6 — Ω||pF
Differential Input Impedance ZDIFF — 1013||3 — Ω||pF
Common Mode
Common Mode Input Range V CMR VSS − 0.3 — VDD + 0.3 V
Common Mode Rejection Ratio CMRR 60 76 — dB VCM = -0.3V to 5.3V, VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 88 112 — dB VOUT = 0.3V to VDD - 0.3V,
VCM = VSS
Output
Maximum Output Voltage Swing VOL, VOH VSS + 25 — V DD − 25 mV VDD = 5.5V
Output Short-Circuit Current ISC — ±6 — mA VDD = 1.8V
— ±23 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.8 — 5.5 V
Quiescent Current per Amplifier IQ 50 100 170 µA IO = 0, VDD = 5.5V, VCM = 5V
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Industrial Temperature Range TA -40 — +85 °C
Extended Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C (Note)
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 θJA — 331 — °C/W
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Thermal Resistance, 8L-PDIP θJA — 85 — °C/W
Thermal Resistance, 8L-SOIC (150 mil) θJA — 163 — °C/W
Thermal Resistance, 8L-SOIC (208 mil) θJA — 118 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-PDIP θJA — 70 — °C/W
Thermal Resistance, 14L-SOIC θJA — 120 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note: The industrial temperature devices operate over this extended temperature range, but with reduced perfor-
mance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum
specification of +150°C.
22% 100
1225 Samples
Percentage of Occurrences
20%
VCM = VSS
18%
FIGURE 2-1: Input Offset Voltage FIGURE 2-4: CMRR, PSRR vs. Ambient
Histogram. Temperature.
100 120 0
VCM = VSS
90 100 -30
Open Loop Gain (dB)
80
PSRR- 80 -60
70 Phase
PSRR+ 60 -90
60
40 -120
50 CMRR
40 20 -150
Gain
30 0 -180
VCM = VSS
20 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
-20 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 -210
1.E+07
FIGURE 2-2: PSRR, CMRR vs. FIGURE 2-5: Open-Loop Gain, Phase vs.
Frequency. Frequency.
14% 55%
1230 Samples 605 Samples
Percentage of Occurrences
50%
Percentage of Occurrences
FIGURE 2-3: Input Bias Current at +85°C FIGURE 2-6: Input Bias Current at +125°C
Histogram. Histogram.
1,000 18%
1225 Samples
Input Noise Voltage Density
Percentage of Occurrences
16% VCM = VSS
14% TA = -40°C to +125°C
12%
(nV/Hz)
10%
100
8%
6%
4%
2%
Eni = 6.1 µVP-P, f = 0.1 to 10 Hz
0%
10
-8
-6
-4
-2
8
-12
-10
10
12
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
FIGURE 2-7: Input Noise Voltage Density FIGURE 2-10: Input Offset Voltage Drift
vs. Frequency. Histogram.
0 200
VDD = 1.8V
Input Offset Voltage (µV)
-200 100
50 VDD = 5.5V
-300
0
-400 VDD = 1.8V
TA = -40°C
TA = +25°C -50
-500
TA = +85°C -100
-600 TA = +125°C
-150
V CM = VSS
-700
-200
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V) Output Voltage (V)
FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 1.8V. Output Voltage.
0 35
VDD = 5.5V
Output Short Circuit Current
Input Offset Voltage (µV)
-100 30
+ISC, V DD = 5.5V
-200 25
-300 20
(mA)
-ISC, V DD = 5.5V
-400 TA = -40°C 15
TA = +25°C
-500 10 -ISC, VDD = 1.8V
TA = +85°C
TA = +125°C
-600 5
+ISC, VDD = 1.8V
-700 0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125
FIGURE 2-9: Input Offset Voltage vs. FIGURE 2-12: Output Short-Circuit Current
Common Mode Input Voltage at VDD = 5.5V. vs. Ambient Temperature.
1.0
0.08
0.04
0.7
0.6 0.02
0.5
0.00
0.2 -0. 04
0.1
0.0
-0. 06
FIGURE 2-13: Slew Rate vs. Ambient FIGURE 2-16: Small Signal Non-Inverting
Temperature. Pulse Response.
1,000 5.0
Output Voltage Headroom (mV)
G = +1 V/V
4.5 V DD = 5.0V
4.0
10 2.0
1.5
1.0
FIGURE 2-14: Output Voltage Headroom FIGURE 2-17: Large Signal Non-Inverting
vs. Output Current Magnitude. Pulse Response.
10 160
TA = +125°C
Output Voltage Swing (VP-P)
140
VDD = 5.5V
Quiescent Current
per amplifier (mA)
120 TA = 85°C
100 TA = 25°C
VDD = 1.8V
1 80 TA = -40°C
60
40
20
VCM = VDD - 0.5V
0.1 1.E+03 1.E+04 1.E+05 1.E+06
0
1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Frequency (Hz) Power Supply Voltage (V)
FIGURE 2-15: Output Voltage Swing vs. FIGURE 2-18: Quiescent Current vs.
Frequency. Power Supply Voltage.
5
VOUT
RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V.
4
Refer to Figure 2-14 for more information.
3
2
3.3 Capacitive Loads
1 Driving large capacitive loads can cause stability prob-
lems for voltage feedback op amps. As the load capac-
0
itance increases, the feedback loop’s phase margin
-1 0.E+00 1.E-05 2.E-05 3.E-05 4.E-05 5.E-05 6.E-05 7.E-05 8.E-05 9.E-05 1.E-04
decreases, and the closed loop bandwidth is reduced.
Time (10 µs/div) This produces gain peaking in the frequency response,
with overshoot and ringing in the step response. A unity
FIGURE 3-1: The MCP6001/2/4 Shows gain buffer (G = +1) is the most sensitive to capacitive
No Phase Reversal. loads, but all gains show the same general behavior.
The input stage of the MCP6001/2/4 op amp uses two When driving large capacitive loads with these op
differential input stages in parallel; one operates at low amps (e.g., > 100 pF when G = +1), a small series
common mode input voltage (VCM) and the other at resistor at the output (RISO in Figure 3-3) improves the
high VCM. With this topology, the device operates with feedback loop’s phase margin (stability) by making the
VCM up to 300 mV above VDD and 300 mV below VSS. output load resistive at higher frequencies. It does not,
The Input Offset Voltage is measured at however, improve the bandwidth.
VCM = VSS - 300 mV and V DD + 300 mV to ensure
proper operation.
Input voltages that exceed the input voltage range
(VSS - 0.3V to VDD + 0.3V at 25°C) can cause exces- – RISO
sive current to flow into or out of the input pins. Current
MCP600X VOUT
beyond ±2 mA can cause reliability problems. Applica-
tions that exceed this rating must be externally limited VIN + CL
with a resistor, as shown in Figure 3-2.
VIN
+ D1 RISO VC1
MCP6002 + RISO VC2
1/2 MCP6002 + VOUT
– C1
A R1 – 1/2 MCP6001
B C2
–
C
Sample
Switch
Clear
Switch
tSAMP
Sample Signal
tCLEAR
Clear Signal
tDETECT
CLK
FIGURE 3-7: Peak Detector with Clear and Sample CMOS Analog Switches.
XNN A57
YWW 307
5 4 Industrial Extended 5 4
Device
Temp Code Temp Code
XXXXXXXX MCP6002
XXXXXNNN I/P057
YYWW 0307
XXXXXXXX MCP6002
XXXXYYWW I/SN0307
NNN 057
XXXXXX 6002
YWWNNN 307057
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
XXXXXXXXXXXXXX MCP6004-I/P
XXXXXXXXXXXXXX
YYWWNNN 0307057
XXXXXXXXXX MCP6004ISL
XXXXXXXXXX
YYWWNNN 0307057
XXXXXX 6004ST
YYWW 0307
NNN 057
E
E1
p B
n 1
Q1
A2 A
c
A1
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
E1
p
B
p1 D
n 1
c
A A2
φ A1
L
β
E1
n 1
A A2
L
c
A1
β B1
p
eB B
E1
D
2
B n 1
h α
45°
c
A A2
φ
β L A1
E1
D
2
B
n 1
A A2
c
φ
A1
(F) L
β
E1
n 1
α
A A2
c L
A1
β B1
eB
B p
E1
B n 1
α
h
45°
c
A A2
φ
A1
L
β
E1
2
n 1
B
α
A
β A1 A2
L
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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05/30/03