Sie sind auf Seite 1von 52

Logic Cells

Logic Cells

All FPGAs contain a basic logic cell replicated in a regular array across the chip

There are three different types of basic logic cells:

multiplexer based

look-up table based

programmable array based

Logic Cells

Logic cells must be flexible, able to implement a variety of logic functions

This requirement leads us to consider a variety of “universal logic components” as basic building blocks

Multiplexers(MUXs) are one of the most attractive

Not too small a building block

Flexible

Easy to understand

ACTEL Logic Cells

Row based architecture

Few ACTEL FPGA comes under this category

ACTEL FPGA

ACT 1 Simple Logic Module

• Multiplexer-based

module.

logic
are
always

in

the

routing

• Logic functions implemented by interconnecting signals from the routing tracks to the data inputs and select lines of the multiplexers.

• Inputs can also be tied to a logical 1 or 0, since these

signals

available

channel.

Actel ACT1 Multiplexer Based Logic Cell

Logic functions can be built by connecting logic signals to some or all of the Logic Module’s inputs and by connecting the remaining Logic Module inputs to VDD or GND

Figure 5.1 The Actel ACT1 architecture. (a) Organization of the basic cells. (b) The ACT1 logic module. (c) An implementation using pass transistors. (d) An example logic macro.

Shannon’s Expansion Theorem

We can use Shannon’s expansion theorem to expand a function:

F = A · F (A = ‘1’) + A' · F (A = ‘0’)

Where F(A=‘1’) is the function evaluated with A=‘1’ and F(A=‘0’) is the function evaluated with A=‘0’

Example: F = A' · B + A · B · C' + A' · B' · C

= A · (B · C') + A' · (B + B' · C)

F (A = '1') = B · C' is the cofactor of F with respect to ( wrt ) A or F A

Eventually we reach the unique canonical form , which uses only minterms (A minterm is a product term that contains all the variables of F—such as A · B' · C)

Final result for example above should be:

F = A' · B · C + A' · B' · C + A · B · C' + A' · B · C'

Using Shannon’s Expansion Theorem to Map a Function to an ACT1 Logic Module

Another example: F = (A · B) + (B' · C) + D Expand F wrt B: F = B · (A + D) + B' · (C + D) = B · F2 + B' ·

F1

Where F1= (C + D)

and F2 = (A + D)

The function F can be implemented by 2:1 MUX, with B selecting between two inputs: F (B = '1') and F (B = '0')

F also describes the output of the ACT 1 LM(logic module)

Now we need to split up F1 and F2

Expand F1 wrt C: F1 = C + D = (C · 1) + (C' · D) Expand F2 wrt A: F2 = A + D = (A · 1) + (A' · D);

Using Shannon’s Expansion Theorem to Map a Function to an ACT1 Logic Module (cont )

C connects to the select line of a first-level mux in the ACT1 LM with ‘1’ and D as the inputs to the mux

A connects to the select line of another first-level mux in the ACT1 LM with ‘1’ and ‘D’ as inputs to the mux

B connects to the select line of the output mux with F1 and F2, the outputs of the first level muxes, connected to the inputs

See Figure 5.1(d) for implementation

2 to 1 MUX using ACT 1 Logic Module

• 8 Input combinational
function
• 2-to-1 Multiplexer
Y = A • S’
+
B • S
A
B
S
0
1

Example of Implementing a Function with an ACT1 LM (cont )

Implementation of a three- input AND gate

SR Latch using ACT 1 Logic Module

Implementation of S-R Latch

Qnext = S + R'Q =S+R’Q(S+S’) =S+R’QS+R’QS’

Qnext = S + R'Q =S(R+R’)+R’Q =SR+SR’+R’Q

S. K. Tiwari (Asst. Prof.) Department of Electronics & Communication Engineering, MIT, Manipal

Ways to Arrange a Karnaugh Map of 2 Variables

Figure 5.2 The logic functions of two variables.

Boolean Functions of Two Variables Using a 2:1 Mux

ACT1 LM(Logic Module) as a Function Wheel

Figure 5.3 The ACT1 logic module as a Boolean function generator. (a) A 2:1 MUX viewed as a logic wheel. (b) The ACT1 logic module viewed as two function wheels.

A 2:1 Mux viewed as a function WHEEL

Any of the gates shown in the WHEEL can be generated by appropriate connections of A0, A1, SA, 0 and 1

ACT1 LM as a Function Wheel (cont.)

A 2:1 MUX is a function wheel that can generate BUF, INV, AND-11, AND1-1, OR, AND

Define a function WHEEL (A, B) = MUX (A0, A1, SA)

MUX (A0, A1, SA) = A0 · SA' + A1 · SA

Each of the inputs (A0, A1, and SA) may be A, B, '0', or '1'

The ACT 1 LM is built from two function wheels, a 2:1 MUX, and a two-input OR gate:

ACT 1 LM = MUX [WHEEL1, WHEEL2, OR (S0, S1)]

Example of Implementing a Function with an ACT1 LM

Example of using the WHEEL functions to implement:

F = NAND (A, B) = (A · B)’

1. First express F as the output of a 2:1 MUX:

expand F wrt A (or wrt B; since F is symmetric)

F = A · (B') + A' · ('1')

2. Assign WHEEL1 to implement INV (B), and WHEEL2 to implement '1'

3. Set the select input to the MUX connecting WHEEL1 and WHEEL2, S0 + S1 = A. We can do this using S0 = A, S1 =

‘0'

Example of Implementing a Function with an ACT1 LM (cont )

Implementation of a three- input AND gate

Example of Implementing a Function with an ACT1 LM (cont )

A single Actel ACT1 LM can implement all combinational two- input functions, most three input functions and many four input functions

A transparent D latch can be implemented with one ACT1 LM and an edge triggered D flip-flop can be implemented with two LM’s

Example of Implementing a Function with an ACT1 LM (cont )

1. Consider a ACT 1 Logic Module(or Modules), Show how to implement

(a). A three input NOR gate

(b). A three input majority function

(c). A 2:1 MUX

(e). A three input XOR gate

(f). A four input MUX

(g). A JK latch

(h). A 2:4 Decoder

2. Solve p5.16 from MJS smith

Architecture of ACTEL FPGA

• The Actel ACT family interconnect scheme shown in previous slide is similar to a channeled gate array. • The channel routing uses dedicated rectangular areas of fixed size within the chip called wiring channels (or just channels ). • The horizontal channels run across the chip in the horizontal direction. In the vertical direction there are similar vertical channels that run over the top of the basic logic cells, the Logic Modules.

Horizontal and Vertical Channel Architecture(ACTEL)

Actel ACT – Routing resources

The ACT1 interconnection architecture uses 25 horizontal tracks per channel for signal routing including with three tracks dedicated to VDD, GND, and the global clock(GCLK).

Horizontal segments vary in length from four columns of Logic Modules to the entire row of modules (Actel call these long segmetns long lones)

Eight vertical tracks per logic module are available for inputs

Four from the Logic Module above the channel and four from the Logic Module below)

These connections are the input stubs

Actel ACT – Routing resources

The single logic module output connects to a vertical track that extends across the two channels above the module and across the two channels below the module.

This is the output stub.

One vertical track per column is a long vertical track (LVT) that spans the entire height of the chip.

Thus there are a total of 13 vertical tracks per column in the ACT1 architecture (eight for inputs, four for outputs, and one for an LVT)

Actel ACT – Routing resources

If the LM at the end of a net is less than two rows away from the driver module, a connection requires two anti-fuses, a vertical track, and two horizontal segments.

If the modules are more than two rows apart, a connection between them will require a long vertical track together with another vertical track and two horizontal tracks.

To connect these tracks will require a total of four anti-fuses in series and this will add delay due to the resistance of the anti- fuse.

Poly-Diffusion Anti-fuse

An anti-fuse is the opposite of a regular fuse. It is an open path until a programming current is forced through it by applying a high programming voltage across it.

Advantage: small (allow denser switch population).

Poly-Silicon Diffusion Antifuse

An antifuse is the opposite of a regular fuse.

An antifuse is normally an open circuit until you force a programming current through it (about 5 mA).

In a poly–diffusion antifuse the high current density causes a large power dissipation in a small area, which melts a thin insulating dielectric between polysilicon and diffusion electrodes and forms a thin (about 20 nm in diameter), permanent, and resistive silicon link.

antifuse polysilicon

ONO dielectric

n +

antifuse diffusion 2 l

Figure shows a poly–diffusion antifuse with an oxide–nitride–oxide ( ONO ) dielectric sandwich of: silicon dioxide (SiO 2 ) grown over the n -type antifuse diffusion, a silicon nitride (Si 3 N 4 ) layer, and another thin SiO 2 layer.

The layered ONO dielectric results in a tighter spread of blown antifuse resistance values than using a single-oxide dielectric.

The effective electrical thickness is equivalent to 10 nm of SiO 2 (Si 3 N 4 has a higher dielectric constant than SiO 2 , so the actual thickness is less than 10 nm)

Metal-Metal Anti-fuse

Cross section of a metal-metal anti-fuse

Figure shows a QuickLogic metal–metal antifuse (ViaLink )

The link is an alloy of tungsten, titanium, and silicon with a bulk resistance of about 500 µΩ cm.

Connections to a metal–metal antifuse are direct to metal—the wiring layers. Connections from a poly– diffusion antifuse to the wiring layers require extra space and create additional parasitic capacitance.

Direct connection to the low-resistance metal layers makes it easier to use larger programming currents to reduce the antifuse resistance.

Actel ACT2 and ACT3 Logic modules

The C-module is for combinational logic

Actel introduced S-modules (sequential) which basically adds a flip flop to the Mux based C- module

ACT 2 S-module

ACT 3 S-module

Actel ACT2 and ACT3 Logic Modules

Figure 5.4 The ACT2 and ACT3 logic modules. (a) The C-module. (b) The ACT2 S-module. (c) The ACT3 S- module. (d) The equivalent circuit of the SE. (e) The SE configured as a positive edge- triggered D flip-flop.

ACT 2 Logic Module: C-Mod

8-input combinational function

ACT2 C-Module

Example of a Logic Function Implemented with the Combinatorial Logic Module

Y= ABCDE

Realization using 4:1 MUX

S1
S0(A)
OUT
0
0
1
0
1
0
● NOT
0
0
1
0
1
0

Realization using 4:1 MUX

B
A
Y
0
0
0
0
1
1
1
0
1
1
1
1

OR

B
A
Y
0
0
0
0
1
0
1
0
0
1
1
1

Realization using 4:1 MUX

AND

Example of Implementing a Function with an ACT2 C-Module

1. Consider a ACT 2 C-Module(or Modules), Show how to implement

(a). A three input NOR gate

(b). A three input majority function

(c). A 2:1 MUX

(e). A three input XOR gate

(f). A 2:4 Decoder

ACT 2S and ACT3 S-Modules (Sequential Logic Module)

• Up to 7, 8-input function plus D-type flip-flop with CLR, CLK

• The storage element can be either a register or a latch. – It can also be bypassed so the logic module can be used as a Combinatorial Logic Module

Positive edge-triggered register based on a master-slave configuration.

Positive latch
Negative latch

ACT 2 and ACT 3 S-Logic Modules

The SE configured as a positive-edge-triggered D flip-flop

C2=CLK, C1=0 and CLR=1

Home Work

Find the condition for –ve edge triggered flip- flop?

CLR=‘1’, CLK=C1 and C2=‘1’

Work Out

P5.4: Show that how the Actel ACT2 and ACT3 sequential element of fig 5.4 (used in the S-module) can be wired to implement:

a. a positive edge triggered flip flop with clear

b. a negative edge triggered flip flop with clear

Example to realize using ACT 2 S, C- Modules

One input one-output sequence detector that produces an output value 1 every time the sequence 0101 is detected and an output value 0 at all other times. For example, if the input sequence is 010101 then the corresponding output sequence is 000101.

Alternative Approach

Realizing using ACT2 S & C-modules

z

Actel Logic Module Analysis

Actel uses a fine-grain architecture which allows you to use almost all of the FPGA

Synthesis can map logic efficiently to a fine-grain architecture

Matched to small anti-fuse programming technology

LMs balance efficiency of implementation and efficiency of utilization

A simple LM reduces performance, but allows fast and robust place-and-route

[1]

Reference

Chapter-5

from

Application

Specific

ICs

by