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Logic Cells
Figure 5.1 The Actel ACT1 architecture. (a) Organization of the basic cells. (b) The ACT1
logic module. (c) An implementation using pass transistors. (d) An example logic
macro.
Shannon’s Expansion Theorem
● We can use Shannon’s expansion theorem to expand a
function:
F = A · F (A = ‘1’) + A' · F (A = ‘0’)
– Where F(A=‘1’) is the function evaluated with A=‘1’ and F(A=‘0’) is the
function evaluated with A=‘0’
• 8 Input combinational
function
• 2-to-1 Multiplexer
Y = A • S’ + B • S
A
B
S
0
1
Example of Implementing a Function
with an ACT1 LM (cont..)
● Implementation of a three-
input AND gate
SR Latch using ACT 1 Logic Module
• Implementation of S-R
Latch
Qnext = S + R'Q
=S+R’Q(S+S’)
=S+R’QS+R’QS’
Qnext = S + R'Q
=S(R+R’)+R’Q
=SR+SR’+R’Q
S. K. Tiwari (Asst. Prof.) Department of Electronics & Communication Engineering, MIT, Manipal
Ways to Arrange a Karnaugh Map of 2
Variables
Figure 5.3 The ACT1 logic module as a Boolean function generator. (a) A 2:1 MUX viewed
as a logic wheel. (b) The ACT1 logic module viewed as two function wheels.
– Each of the inputs (A0, A1, and SA) may be A, B, '0', or '1'
n+ antifuse diffusion
2l
• 8-input combinational
function
ACT2 C-Module
Example of a Logic Function Implemented with
the Combinatorial Logic Module Y= ABCD’E’
Realization using 4:1 MUX S1 S0(A) OUT
0 0 1
0 1 0
● NOT 0 0 1
0 1 0
Realization using 4:1 MUX B A Y
0 0 0
0 1 1
1 0 1
● OR 1 1 1
Realization using 4:1 MUX B
0
A
0
Y
0
0 1 0
1 0 0
● AND 1 1 1
Example of Implementing a Function
with an ACT2 C-Module
● 1. Consider a ACT 2 C-Module(or Modules), Show how to
implement
– (a). A three input NOR gate
– (b). A three input majority function
– (c). A 2:1 MUX
– (d). A Half Adder
– (e). A three input XOR gate
– (f). A 2:4 Decoder
ACT 2S and ACT3 S-Modules (Sequential Logic Module)
Positive latch
Negative latch
ACT 2 and ACT 3 S-Logic Modules
The SE configured as a positive-edge-triggered D
flip-flop
z
Actel Logic Module Analysis
● Actel uses a fine-grain architecture which allows you to
use almost all of the FPGA
● Synthesis can map logic efficiently to a fine-grain
architecture
● Matched to small anti-fuse programming technology
● LMs balance efficiency of implementation and efficiency
of utilization
● A simple LM reduces performance, but allows fast and
robust place-and-route
Reference