Manual Digitaal

Philips Semiconductors FAST Products Product specification
Quad 2-input NAND gate 74F00
FEATURE TYPE TYPICAL TYPICAL

• Industrial temperature range available PROPAGA- SUPPLY
TION CURRENT
(–40°C to +85°C) DELAY ( TOTAL)
74F00 3.4ns 4.4mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE INDUSTRIAL RANGE
DESCRIPTION VCC = 5V ±10%, VCC = 5V ±10%,
Tamb = 0°C to +70°C Tamb = –40°C to +85°C
14–pin plastic DIP N74F00N I74F00N
14–pin plastic SO N74F00D I74F00D
INPUT AND OUTPUT LOADNG AND FAN OUT TABLE

74F (U.L.) HIGH/LOW LOAD VALUE HIGH/
PINS DESCRIPTION
LOW
Dna, Dnb Data inputs 1.0/1.0 20µA/0.6mA
Qn Data output 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC DIAGRAM FUNCTION TABLE

1
INPUTS OUTPUT
D0a 3
D0b 2 Q0 Dna Dnb Qn
4 6 L L H
D1a
D1b 5 Q1
L H H
9 8
D2a H L H
D2b 10 Q2
H H L
12 11
D3a
13 Q3 NOTES:
VCC = Pin 14 D3b 1. H = High voltage level
GND = Pin 7
2. L = Low voltage level
PIN CONFIGURATION LOGIC SYMBOL IEC/IEEE SYMBOL
1 &
3
1 2 4 5 9 10 12 13 2
D0a 1 14 V
CC
D0b 2 13 D3b 4
6
Q0 3 12 D3a 5
D0a D0bD1a D1b D2a D2b D3a D3b
D1a 4 11 Q3
9
D1b 5 10 D2b 8
Q0 Q1 Q2 Q3 10
Q1 6 9 D2a
GND 7 8 Q2 12
11
3 6 8 11 13
VCC = Pin 14
GND = Pin 7
October 4, 1990 1 853-0325 00623

Quad 2-input NOR gate 74F02

TION DELAY CURRENT
(–40°C to +85°C) ( TOTAL)
74F02 3.4ns 4.4mA
ORDER CODE

PINS DESCRIPTION
LOW

2
INPUTS OUTPUT
D0a 1
D0b 3 Q0 Dna Dnb Qn
5 L L H
D1a 4
D1b 6 Q1
L H L
8
D2a 10 H L L
D2b 9 Q2
H H L
11 13
D3a
12 Q3 NOTES:
D3b 1. H = High voltage level
VCC = Pin 14
GND = Pin 7 2. L = Low voltage level
2 1
2 3 5 6 8 9 11 12 1
3
Q0 1 14 VCC
D0a 2 13 Q3
5
D0b 3 12 D3b 4
D0a D0b D1a D1b D2a D2b D3a D3b 6
Q1 4 11 D3a
D1a 5 10 Q2 8
Q0 Q1 Q2 Q3
10
D1b 6 9 D2a 9
GND 7 8 D2b
11
1 4 10 13
13
12
VCC = Pin 14
GND = Pin 7
October 4, 1990 1 853-0326 00622

Hex inverter 74F04

TION DELAY CURRENT
(–40°C to +85°C) ( TOTAL)
74F04 3.5ns 6.9mA
ORDER CODE

PINS DESCRIPTION
LOW
nA Data inputs 1.0/1.0 20µA/0.6mA
nY Data output 50/33 1.0mA/20mA

INPUTS OUTPUT
1 2
1A Y A Y
3 4
2A 2Y L H
5 6 H L
3A 3Y
9 8 NOTES:
4A 4Y 1. H = High voltage level
11 10 2. L = Low voltage level
5A 5Y
VCC = Pin 14 13
6A 12
GND = Pin 7 6Y
1 1 2
1 3 5 9 11 13
1A 1 14 V
CC 3 4
1Y 2 13 6A
1A 2A 3A 4A 5A 6A
2A 3 12 6Y 5 6
2Y 4 11 5A
1A 2A 3A 4A 5A 6A 9 8
3A 5 10 5Y
3Y 6 9 4A
11 10
GND 7 8 4Y
2 4 6 8 10 12
13 12
VCC = Pin 14
GND = Pin 7
October 4, 1990 1 853-0327 00621

Hex inverter/buffer drivers (open-collector) 74F06, 74F06A,

74F07, 74F07A
FEATURES OF 74F06, 74F07 FEATURES OF 74F06A, 74F07A TYPICAL TYPICAL

• Open Collector output drive 64mA • Open Collector output drive 48mA PROP- SUPPLY
TYPE AGATION CURRENT
• High speed • High speed DELAY ( TOTAL)
• 12V output termination voltage • 30V output termination voltage 74F06 3.5ns 30mA
• Symmetrical propagation delays • Replaces 7406 and 7407 74F06A 9.0ns 30mA
• Improved performance upgrade for 7406 74F07 4.5ns 32mA

and 7407 74F07A 10.0ns 32mA
• Reduced IOH leakage @ 30V
COMMERCIAL RANGE
DESCRIPTION VCC = 5V ±10%, DRAWING NUMBER
Tamb = 0°C to +70°C
14–pin plastic Dual In-line Package N74F06N, N74F06AN 0405B
14–pin plastic Small Outline N74F07D, N74F07AD 175D

74F06/74F06A 74F06/74F06A 74F06/74F06A
1 2
1 3 5 9 11 13
A0 1 14 V
CC 3 4
Y0 2 13 A5
A0 A1 A2 A3 A4 A5
A1 3 12 Y5 5 6
Y1 4 11 A4
Y0 Y1 Y2 Y3 Y4 Y5 9 8
A2 5 10 Y4
Y2 6 9 A3
11 10
GND 7 8 Y3
2 4 6 8 10 12
13 12
VCC = Pin 14
GND = Pin 7

74F07/74F07A 74F07/74F07A 74F07/74F07A
1 2
1 3 5 9 11 13
A0 1 14 V
CC 3 4
Y0 2 13 A5
A0 A1 A2 A3 A4 A5
A1 3 12 Y5 5 6
Y1 4 11 A4
Y0 Y1 Y2 Y3 Y4 Y5 9 8
A2 5 10 Y4
Y2 6 9 A3
11 10
GND 7 8 Y3
2 4 6 8 10 12
13 12
VCC = Pin 14
GND = Pin 7
July 24, 1992 1 853–1122 07270

Hex inverter/buffer drivers (open-collector) 74F06, 74F06A,

74F07, 74F07A
LOGIC DIAGRAMS
74F06/74F06A 74F07/74F07A
1 2 1 2
A0 Y0 A0 Y0
3 4 3 4
A1 Y1 A1 Y1
5 6 5 6
A2 Y2 A2 Y2
9 8 9 8
A3 Y3 A3 Y3
11 10 11 10
A4 Y4 A4 Y4
13 13
A5 12 A5 12
Y5 Y5
VCC = Pin 14
GND = Pin 7
INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS DESCRIPTION
LOW
An Data inputs (’F06, ’F07) 1.0/1.0 20µA/0.6mA
An Data inputs (’F06A, ’F07A) 1.0/0.7 20µA/0.4mA
Yn Data outputs (’F06) OC/106.7 OC/64mA
Yn Data outputs (’F06A) OC/80 OC/48mA
Yn Data outputs (’F07) OC/106.7 OC/64mA
Yn Data outputs (’F07A) OC/80 OC/48mA
NOTES:
1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
2. OC = Open Collector
FUNCTION TABLE
INPUTS OUTPUTS
’F06, ’F06A ’F07, ’F07A
An Yn Yn
L H L
H L H
NOTES:
1. H = High voltage level
July 24, 1992 2

Philips Semiconductors Product specification
Quad 2-input AND gate 74F08
• 74F08 Available for industrial range (–40°C to +85°C) PIN CONFIGURATION
D0a 1 14 VCC
TYPE TYPICAL TYPICAL
PROPAGATION SUPPLY CURRENT D0b 2 13 D3b
DELAY (TOTAL) Q0 3 12 D3a
74F08 4.1ns 7.1mA D1a 4 11 Q3
D1b 5 10 D2b
Q1 6 9 D2a
GND 7 8 Q2
SF00038
COMMERCIAL RANGE INDUSTRIAL RANGE DRAWING
DESCRIPTION
VCC = 5.0V ±10%, Tamb = 0°C to +70°C VCC = 5.0V ±10%, Tamb = –40°C to +85°C NUMBER
14-pin plastic DIP N74F08N I74F08N SOT27-1
14-pin plastic SO N74F08D I74F08D SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

1
INPUTS OUTPUT
D0a 3
D0b 2 Q0 Dna Dnb Qn
D1a
4 L L L
6
D1b 5 Q1
L H L
9
D2a 8 H L L
D2b 10 Q2
H H H
12 11
VCC = Pin 14 D3a NOTES:
13 Q3
GND = Pin 7 D3b H = High voltage level
SF00052
L = Low voltage level
LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC)
1 &
1 2 4 5 9 10 12 13 3
2
4
6
D0a D0bD1a D1b D2a D2b D3a D3b 5
9
Q0 Q1 Q2 Q3 8
10
12
3 6 8 11 11
13
VCC = Pin 14
GND = Pin 7
SF00040 SF00053
1995 Apr 19 1 853–0328 15145

Gates 74F10, 74F11
74F10 Triple 3-input NAND gate

74F11 Triple 3-input AND gate
TYPE TYPICAL TYPICAL ORDERING INFORMATION

PROPAGATION SUPPLY CURRENT ORDER CODE
DELAY (TOTAL)
DESCRIPTION COMMERCIAL RANGE
74F10 3.5ns 3.3mA VCC = 5V ±10%, Tamb = 0°C to +70°C
74F11 4.2ns 5.3mA 14-pin plastic DIP N74F10N, N74F11N
14-pin plastic SO N74F10D, N74F11D

Dna, Dnb, Dnc Data inputs 1.0/1.0 20µA/0.6mA
Qn Data output (74F10) 50/33 1.0mA/20mA
Qn Data output (74F11) 50/33 1.0mA/20mA
PIN CONFIGURATIONS
74F10 74F11
D0a 1 14 VCC D0a 1 14 VCC
D0b 2 13 D0c D0b 2 13 D0c
D1a 3 12 Q0 D1a 3 12 Q0
D1b 4 11 D2c D1b 4 11 D2c
D1c 5 10 D2b D1c 5 10 D2b
Q1 6 9 D2a Q1 6 9 D2a
GND 7 8 Q2 GND 7 8 Q2
SF00055 SF00056
LOGIC SYMBOLS
74F10 74F11
1 2 13 3 4 5 9 10 11 1 2 13 3 4 5 9 10 11
D0a D0b D0c D1a D1b D1c D2a D2b D2c D0a D0b D0c D1a D1b D1c D2a D2b D2c
Q0 Q1 Q2 Q0 Q1 Q2
12 6 8 12 6 8
VCC = Pin 14 VCC = Pin 14
GND = Pin 7 GND = Pin 7
SF00057 SF00058
September 20, 1989 1 853–0329 97683

Gates 74F10, 74F11
IEC/IEEE SYMBOLS
74F10 74F11
1 & 1 &
2 12 2 12
13 13
3 3
4 6 4 6
5 5
9 9
10 8 10 8
11 11
SF00059 SF00060
LOGIC DIAGRAMS
74F10 74F11
1 1
D0a D0a
2 12 2 12
D0b Q0 D0b Q0
13 13
D0c D0c
3 3
D1a D1a
4 6 4 6
D1b Q1 D1b Q1
5 5
D1c D1c
9 9
D2a D2a
10 8 10 8
D2b Q2 D2b Q2
11 11
D2c D2c
VCC = Pin 14 VCC = Pin 14
SF00061 SF00062
FUNCTION TABLE
OUTPUTS
INPUTS
74F10 74F11
Dna Dnb Dnc Qn Qn
L L L H L
L L H H L
L H L H L
L H H H L
H L L H L
H L H H L
H H L H L
H H H L H
NOTES:
September 20, 1989 2

Dual 4-input NAND gate 74F20
TYPE TYPICAL TYPICAL PIN CONFIGURATION

PROPAGATION SUPPLY CURRENT
DELAY (TOTAL) D0a 1 14 VCC
74F20 3.5ns 2.2mA D0b 2 13 D1d
NC 3 12 D1c
ORDERING INFORMATION D0c 4 11 NC
COMMERCIAL RANGE D0d 5 10 D1b

DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
Q0 6 9 D1a
14-pin plastic DIP N74F20N GND 7 8 Q1
14-pin plastic SO N74F20D SF00065

Dna, Dnb, Dnc, Dnd Data inputs 1.0/1.0 20µA/0.6mA
Q0, Q1 Data outputs 50/33 1.0mA/20mA

INPUTS OUTPUT
1
D0a Dna Dnb Dnc Dnd Qn
2
D0b 6 L X X X H
4 Q0
D0c X L X X H
5
D0d X X L X H
X X X L H
9
D1a H H H H L
10
D1b 8
NOTES:
12 Q1 1. H = High voltage level
D1c
13
D1d 3. X = Don’t care
VCC = Pin 14
GND = Pin 7
SF00066
LOGIC SYMBOL IEC/IEEE SYMBOL
1 &
1 2 4 5 9 10 12 13
2
6
4
D0a D0b D0c D0d D1a D1b D1c D1d 5
9
Q0 Q1
10
8
12
6 8
13
VCC = Pin 14
GND = Pin 7
SF00067 SF00068
March 3, 1989 1 853–0332 95935

Philips Semiconductors–Signetics FAST Products Product specification
Triple 3-input NOR gate 74F27

TION CURRENT
(–40°C to +85°C) DELAY ( TOTAL)
74F27 3.0ns 6.5mA
ORDER CODE

74F (U.L.) HIGH/ LOAD VALUE HIGH/
PINS DESCRIPTION
LOW LOW
Dna, Dnb, Dnc Data inputs 1.0/1.0 20µA/0.6mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

1 INPUTS OUTPUT
D0a
2 12 Dna Dnb Dnc Qn
D0b Q0
13 L L L H
D0c
3
X X H L
D1a
6 X H X L
4
D1b Q1
H X X L
D1c 5
Notes to function table
9 1. H = High voltage level
D2a
10 8 2. L = Low voltage level
D2b Q2
D2c 11
VCC = Pin 14
GND = Pin 7
1 1
1 2 13 3 4 5 9 10 11
D0a 1 14 VCC 2 12
D0b 2 13 D0c 13
D1a 3 12 Q0 D0a D0b D0c D1a D1b D1c D2a D2b D2c 3
D1b 4 11 D2c 4 6
D1c 5 10 D2b
Q0 Q1 Q2 5
Q1 6 9 D2a
9
GND 7 8 Q2
10 8
12 6 8
11
VCC = Pin 14
GND = Pin 7
February 5, 1991 1 853 0049 01638

8-input NAND gate 74F30
TYPE TYPICAL TYPICAL PIN CONFIGURATION

DELAY (TOTAL) Da 1 14 VCC
74F30 3.2ns 1.7mA Db 2 13 NC
Dc 3 12 Dh
ORDERING INFORMATION Dd 4 11 Dg
COMMERCIAL RANGE De 5 10 NC
DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
Df 6 9 NC
14-pin plastic DIP N74F30N GND 7 8 Q
14-pin plastic SO N74F30D SF00070

Dn Data inputs 1.0/1.0 20µA/0.6mA
Q Data output 50/33 1.0mA/20mA

INPUTS OUTPUT
1
Da Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Qn
2
Db L X X X X X X X H
3
Dc X L X X X X X X H
4
Dd 8 X X L X X X X X H
5 Q
De X X X L X X X X H
6
Df X X X X L X X X H
11 X X X X X L X X H
Dg
12 X X X X X X L X H
Dh
VCC = Pin 14
GND = Pin 7 X X X X X X X L H
SF00071
H H H H H H H H L
NOTES:
3. X = Don’t care
1 &
1 2 3 4 5 6 11 12
2
Da Db Dc Dd De Df Dg Dh 4
8
5
Q
6
11
8
12
VCC = Pin 14
GND = Pin 7
SF00072 SF00073
March 3, 1989 1 853–0050 95941

Quad 2-input OR gate 74F32
FEATURE
• Industrial temperature range available TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL)
(–40°C to +85°C) 74F32 4.1ns 8.2mA
ORDER CODE

PINS DESCRIPTION
LOW

1 INPUTS OUTPUT
D0a 3
2 Q0
D0b Dna Dnb Qn
D1a
4
6
L L L
D1b 5 Q1
L H H
9
D2a 8 H L H
D2b 10 Q2
H H H
12 11
D3a Notes to function table
13 Q3
D3b
VCC = Pin 14 1. H = High voltage level
GND = Pin 7 2. L = Low voltage level
1
1 3
1 2 4 5 9 10 12 13 2
D0a 1 14 V
CC
D0b 2 13 D3b 4
6
Q0 3 12 D3a D0a D0b D1a D1b D2a D2b D3a D3b 5
D1a 4 11 Q3
9
D1b 5 10 D2b Q0 Q1 Q2 Q3 8
10
Q1 6 9 D2a
GND 7 8 Q2
12
3 6 8 11 11
13
VCC = Pin 14
GND = Pin 7
October 4, 1990 1 853 0333 00624

Philips SemiconductorsFAST Products Product specification
Dual D-type flip–flop 74F74
FEATURE (SD) and reset (RD) are asynchronous tion of the clock for predictable
• Industrial temperature range available active low inputs and operate indepen- operation. Clock triggering occurs at a
(–40°C to +85°C) dently of the clock input. When set and voltage level and is not directly related
reset are inactive (high), data at the D to the transition time of the positive–go-
DESCRIPTION input is transferred to the Q and Q out- ing pulse. Following the hold time inter-
The 74F74 is a dual positive edge–trig- puts on the low–to–high transition of the val, data at the D input may be changed
gered D–type flip–flop featuring individu- clock. Data must be stable just one set- without affecting the levels of the output.
al data, clock, set, and reset inputs; also up time prior to the low–to–high transi-
true and complementary outputs. Set
TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT( TOTAL)
74F74 125MHz 11.5mA
ORDER CODE

PINS DESCRIPTION
LOW LOW
D0, D1 Data inputs 1.0/1.0 20µA/0.6mA
CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20µA/0.6mA
SD0, SD1 Set inputs (active low) 1.0/3.0 20µA/1.8mA
RD0, RD1 Reset inputs (active low) 1.0/3.0 20µA/1.8mA
Q0, Q1, Q0, Q1 Data outputs 50/33 1.0mA/20mA

2 12
4 &
S 5
1 14 V D0 D1 3
RD0
CC 3 CP0 C1
2
D0 2 13 RD1
4 1D 6
SD0
1
CP0 3 12 D1 1 RD0 R
SD0 4 11 CP1 11 CP1

10
10 SD1 S 9
Q0 5 10 SD1 11
13 RD1 C2
Q0 6 9 Q1 12
Q0 Q0 Q1 Q1 2D
8
GND 7 8 Q1 13 R
5 6 9 8
VCC = Pin 14
GND = Pin 7
October 23, 1990 1 853 0335 00784

Dual D-type flip–flop 74F74

INPUTS OUTPUTS OPERATING
SD RD CP D Q Q MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
4, 10
SD L L X X H H Undetermined*
H H ↑ h H L Load ”1”
RD
1, 13 5, 9
Q H H ↑ l L H Load ”0”
H H ↑ X NC NC Hold
6, 8 Notes to function table
3, 11 Q
CP 1. H = High voltage level
2. h = High voltage level one setup time prior to low–to–high clock
transition
2, 12
D 3. L = Low voltage level
4. l = Low voltage level one setup time prior to low–to–high clock
transition
5. NC= No change from the previous setup
6. X = Don’t care
7. ↑ = Low–to–high clock transition
8. ↑ = Not low–to–high clock transition
VCC = Pin 14 9. * = This setup is unstable and will change when either set or reset
GND = Pin 7 return to the high level
ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the oper-
ating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in high output state –0.5 to VCC V
IOUT Current applied to output in low output state 40 mA
Tamb Operating free air temperature range Commercial range 0 to +70 °C

Industrial range –40 to +85 °C
Tstg Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT
MIN NOM MAX
VCC Supply voltage 4.5 5.0 5.5 V
VIH High–level input voltage 2.0 V
VIL Low–level input voltage 0.8 V
IIk Input clamp current –18 mA
IOH High–level output current –1 mA
IOL Low–level output current 20 mA
Tamb Operating free air temperature range Commercial range 0 +70 °C
Industrial range –40 +85 °C
October 23, 1990 2

SN54/74LS83A
4-BIT BINARY FULL ADDER
WITH FAST CARRY
The SN54 / 74LS83A is a high-speed 4-Bit binary Full Adder with internal
carry lookahead. It accepts two 4-bit binary words (A1 – A4, B 1 – B4) and a
Carry Input (C0). It generates the binary Sum outputs ∑1 – ∑4) and the Carry 4-BIT BINARY FULL ADDER
Output (C4) from the most significant bit. The LS83A operates with either WITH FAST CARRY
active HIGH or active LOW operands (positive or negative logic). The
SN54 / 74LS283 is recommended for new designs since it is identical in LOW POWER SCHOTTKY
function with this device and features standard corner power pins.
CONNECTION DIAGRAM DIP (TOP VIEW)

B4 Σ4 C4 C0 GND B1 A1 Σ1
16 15 14 13 12 11 10 9 J SUFFIX
CERAMIC
CASE 620-09
NOTE:
16
The Flatpak version has the 1
same pinouts (Connection
Diagram) as the Dual In-Line
Package.
1 2 3 4 5 6 7 8 N SUFFIX
A4 Σ3 A3 B3 VCC Σ2 B2 A2 PLASTIC
16 CASE 648-08
PIN NAMES LOADING (Note a)
1
HIGH LOW
A1 – A4 Operand A Inputs 1.0 U.L. 0.5 U.L.
B1 – B4 Operand B Inputs 1.0 U.L. 0.5 U.L.
C0 Carry Input 0.5 U.L. 0.25 U.L. D SUFFIX
Σ1 – Σ4 Sum Outputs (Note b) 10 U.L. 5 (2.5) U.L. SOIC
16
C4 Carry Output (Note b) 10 U.L. 5 (2.5) U.L. 1 CASE 751B-03
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) ORDERING INFORMATION
Temperature Ranges.
SN54LSXXJ Ceramic
SN74LSXXN Plastic
LOGIC DIAGRAM SN74LSXXD SOIC
C0 A1 B1 A2 B2 A3 B3 A4 B4 VCC = PIN 5
13 10 11 8 7 3 4 1 16 GND = PIN 12
= PIN NUMBERS
LOGIC SYMBOL
10 11 8 7 3 4 1 16
B1 A2 B2 A3 B3 A4 B4
13 C0 C4 14
∑1∑2 ∑3 ∑4 C4
9 6 2 15 14
C1 C2 C3
9 6 2 15 14
∑1 ∑2 ∑3 ∑4 C4
FAST AND LS TTL DATA

5-81
SN54/74LS83A
FUNCTIONAL DESCRIPTION
The LS83A adds two 4-bit binary words (A plus B) plus the incoming carry. The binary sum appears on the sum outputs (∑1 – ∑4)
and outgoing carry (C4) outputs.
C0 + (A1+B1)+2(A2+B2)+4(A3+B3)+8(A4+B4) = ∑1+2∑2+4∑3+8∑4+16C4
Where: (+) = plus
Due to the symmetry of the binary add function the LS83A can be used with either all inputs and outputs active HIGH (positive
logic) or with all inputs and outputs active LOW (negative logic). Note that with active HIGH Inputs, Carry Input can not be left open,
but must be held LOW when no carry in is intended.
Example:
C0 A1 A2 A3 A4 B1 B2 B3 B4 ∑1 ∑2 ∑3 ∑4 C4
Logic Levels L L H L H H L L H H H L L H
Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 (10+9 = 19)
Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0 (carry+5+6 = 12)
Interchanging inputs of equal weight does not affect the operation, thus C0, A1, B1, can be arbitrarily assigned to pins 10, 11,
13, etc.
FUNCTIONAL TRUTH TABLE

C (n–1) An Bn ∑n Cn
L L L L L
L L H H L
L H L H L
L H H L H
H L L H L
H L H L H
H H L L H
H H H H H
C1 — C3 are generated internally
C0 — is an external input
C4 — is an output generated internally
GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

5-82
4-bit magnitude comparator 74F85
FEATURES PIN CONFIGURATION

• High-impedance NPN base inputs for reduced loading
(20µA in High and Low states)
B3 1 16 VCC
• Magnitude comparison of any binary words IAB 4 13 A2
DESCRIPTION A>B 5 12 A1
The 74F84 is a 4-bit magnitude comparator that can be expanded to
A=B 6 11 B1
almost any length. It compares two 4-bit binary, BCD, or other
monotonic codes and presents the three possible magnitude results A<B 7 10 A0
at the outputs. The 4-bit inputs are weighted (A0–A3) and (B0–B3) GND 8 9 B0
where A3 and B3 are the most significant bits. The operation of the
74F85 is described in the Function Table, showing all possible logic SF00075
conditions. The upper part of the table describes the normal
operation under all conditions that will occur in a single device or in
a series expansion scheme. In the upper part of the table the three TYPE TYPICAL TYPICAL
outputs are mutually exclusive. In the lower part of the table, the PROPAGATION SUPPLY CURRENT
outputs reflect the feed-forward conditions that exist in the parallel DELAY (TOTAL)
expansion scheme. The expansion inputs IA>B, and IA=B and IAB, A=B and AB, IA=B and IA<B inputs
of the next higher stage. Stages can be added in this manner to any COMMERCIAL RANGE
DESCRIPTION
length, but a propagation delay penalty of about 15ns is added with VCC = 5V ±10%, Tamb = 0°C to +70°C
each additional stage. For proper operation, the expansion inputs of 16-pin plastic DIP N74F85N
the least significant word should be tied as follows: IA>B = Low,
IA=B = High, and IAB Expansion inputs (active High) 1.0/0.033 20µA/20µA
A<B, A=B, A>B Data outputs (active High) 50/33 1.0mA/20mA
10 12 13 15 9 11 14 1 10 COMP
0
12
13 P
A0 A1 A2 A3 B0 B1 B2 B3 15
3
2 IAQ
4 IA>B 1
3
A>B A=B A
GND = Pin 8 5 6 7
SF00076 SF00077
September 27, 1994 2 853–0055 13903

LOGIC DIAGRAM
15
A3
1
B3
5
A>B
13
A2
14
B2
2
IAB
12
A1
11
B1
7
AB IAB AB3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2<B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L
A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L
A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H
A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H
A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L
A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L
H = High voltage level
X = Don’t care

APPLICATION
The parallel expansion scheme shown in Figure 1 demonstrates the
INPUTS most efficient general use of these comparators. The expansion
inputs can be used as a fifth input bit position except on the least
(LSB) B23 B3
significant device, which must be connected as in the serial scheme.
A23 A3
B22 B2
The expansion inputs used by labeling IA>B as an “A” input, IA<B as
A22 A2 a “B” input and setting IA=B = Low. The 74F85 can be used as a 5-bit
B21 B1 AB be expanded to any number of bits as shown in Table 1.
A20 A0
B19 IAB NUMBER OF TYPICAL SPEEDS
WORD LENGTH
PACKAGES 74F
B18 B3
A18 A3 1–4 bits 1 12ns
B17 B2
5–24 bits 2–6 22ns
A17 A2
B16 B1 AB
A15 A0
B14 IAB
B13 B3 B3
A13 A3 A3
B12 B2 B2
A12 A2 A2 OUTPUTS
B11 B1 AB B0 A>B
A10 A0 A0
B9 IAB A>B
B8 B3
A8 A3
B7 B2
A7 A2
B6 B1 AB
A5 A0
B4 IAB
B3 B3
A3 A3
B2 B2
A2 A2
B1 B1 AB
A0 A0
L IAB
SF00079
Figure 1. Comparison of Two 24-Bit Words

Quad 2-input Exclusive-OR gate 74F86
FEATURE PIN CONFIGURATION

• Industrial temperature range available (–40°C to +85°C)
D0a 1 14 VCC
D0b 2 13 D3b
TYPE TYPICAL TYPICAL SUPPLY
PROPAGATION CURRENT Q0 3 12 D3a
DELAY (TOTAL)
D1a 4 11 Q3
74F86 4.3ns 16.5mA
D1b 5 10 D2b
Q1 6 9 D2a
GND 7 8 Q2
SF00038
ORDER CODE
DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C VCC = 5V ±10%, Tamb = –40°C to +85°C
14-pin plastic DIP N74F86N I74F86N
14-pin plastic SO N74F86D I74F86D

NOTE:
1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

1
INPUTS OUTPUT
D0a 3
D0b 2 Q0 Dna Dnb Qn
D1a
4 L L L
6
D1b 5 Q1
L H H
9
D2a 8 H L H
D2b 10 Q2
H H L
12 11
VCC = Pin 14 D3a NOTES:
13 Q3
GND = Pin 7 D3b
SF00090
1 =
1 2 4 5 9 10 12 13 3
2
4
6
D0a D0bD1a D1b D2a D2b D3a D3b 5
9
Q0 Q1 Q2 Q3 8
10
12
3 6 8 11 11
13
VCC = Pin 14
GND = Pin 7
SF00040 SF00091
February 9, 1990 1 853–0336 98773

Dual J-K negative edge-triggered flip-flop 74F112
FEATURE PIN CONFIGURATION

• Industrial temperature range available (–40°C to +85°C)
CP0 1 16 VCC
DESCRIPTION K0 2 15 RD0
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,
J0 3 14 RD1
feature individual J, K, Clock (CPn), Set (SD) and Reset (RD)
inputs, true (Qn) and complementary (Qn) outputs. SD0 4 13 CP1
The SD and RD inputs, when Low, set or reset the outputs as shown Q0 5 12 K1
in the Function Table, regardless of the level at the other inputs. Q0 6 11 J1
A High level on the clock (CPn) input enables the J and K inputs and Q1 7 10 SD1
data will be accepted. The logic levels at the J and K inputs may be
GND 8 9 Q1
allowed to change while the CPn is High and flip-flop will perform
according to the Function Table as long as minimum setup and hold SF00103
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL)

74F112 100MHz 15mA
ORDER CODE
DESCRIPTION COMMERCIAL RANGE INDUSTRIAL RANGE
16-pin plastic DIP N74F112N I74F112N
16-pin plastic SO N74F112D I74F112D

J0, J1 J inputs 1.0/1.0 20µA/0.6mA
K0, K1 K inputs 1.0/1.0 20µA/0.6mA
SD0, SD1 Set inputs (active Low) 1.0/5.0 20µA/3.0mA
RD0, RD1 Reset inputs (active Low) 1.0/5.0 20µA/3.0mA
CP0, CP1 Clock Pulse input (active falling edge) 1.0/4.0 20µA/2.4mA
Q0, Q0; Q1, Q1 Data outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
February 9, 1990 1 853–0338 98775

Dual J-K negative edge-triggered flip-flop 74F112

3 11 2 12
3 5
1J
1
C1
J0 D1 K0 K1 2 6
1 CP0 1K
15
4 SD0 R
15 RD0 4
S
13 CP1
11
10 SD1 2J
14 RD1 13 9
C2
Q0 Q0 Q1 Q1 12
2K
14 7
R
10
S
VCC = Pin 16 5 6 9 7
GND = Pin 8
SF00104 SF00105
LOGIC DIAGRAM
5, 9 6, 7
Q Q
4, 10 15, 14
SD RD
2, 12 3, 11
K J
VCC = Pin 16 1, 13
GND = Pin 8
CP
SF00106
FUNCTION TABLE
INPUTS
OPERATING MODE
SD RD CP J K Q Q
L H X X X H L Asynchronous Set
H L X X X L H Asynchronous Reset
L L X X X H* H* Undetermined *
H H ↓ h h q q Toggle
H H ↓ l h L H Load “0” (Reset)
H H ↓ h l H L Load “1” (Set)
H H ↓ l l q q Hold “no change”
H H H X X Q Q Hold “no change”
h = High voltage level one setup time prior to High-to-Low clock transition
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
↓ = High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
February 9, 1990 2
Philips Semiconductors Products Product specification
13–input NAND Gate FAST 74F133
FAST Products
PRODUCT SPECIFICATION
TYPE TYPICAL PROPAGATION TYPICAL SUPPLY CURRENT

DELAY (TOTAL)
74F133 4.0ns 2.0 mA
ORDER CODE

74F (U.L.) LOAD VALUE
PINS DESCRIPTION
HIGH/LOW HIGH/LOW
DO - D12 Data inputs 1.0/1.0 20µA/0.6mA
Q Data output 50/33 1.0mA/20mA
PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC)
1 1
2 2 &
3 3
D0 1 16 VCC
4 4
D1 2 15 D12 5 5
D2 3 14 D11 6 6
D3 4 13 D10 9
7 7
D4 5 12 D9 10 10
D5 6 11 D8 11 11
D6 7 10 D7 12 12
GND 8 9 Q 13 13
14 14
15 15
VCC = Pin 16
GND = Pin 8
July 2, 1993 1 853-10219

Philips Semiconductors Products Product specification
13–input NAND Gate FAST 74F133
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12

1 2 3 4 5 6 7 10 11 12 13 14 15
9
VCC = Pin 16 Q
GND = Pin 8
FUNCTION TABLE
INPUTS OUTPUT
DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 Q
H H H H H H H H H H H H H L
Any one input = L H
July 2, 1993 2
1–of–8 decoder/demultiplexer 74F138
FEATURE when enabled, provides eight mutually (see Fig. 1). The device can be used as
• Demultiplexing capability exclusive, active low outputs (Q0 – Q7). an eight output demultiplexer by using
• Multiple input enable for easy expan- The device features three enable inputs;
two active low (E0, E1) and one active
one of the active low enable inputs as
the data input and the remaining enable
sion
high (E2). Every output will be high un- inputs as strobes. Enable inputs not
• Ideal for memory chip select decoding less E0 and E1 are low and E2 is high. used must be permanently tied to their
• Industrial temperature range available This multiple enable function allows appropriate active high or active low
(–40°C to +85°C) easy parallel expansion of the device to state.
1–of–32 (5 lines to 32 lines) decoder
with just four 74F138s and one inverter
DESCRIPTION
The 74F138 decoder accepts three
binary weighted inputs (A0, A1, A2) and
TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL)
74F138 5.8ns 13mA
ORDER CODE

PINS DESCRIPTION
LOW LOW
A0 – A2 Address inputs 1.0/1.0 20µA/0.6mA
E0, E1 Enable inputs (active low) 1.0/1.0 20µA/0.6mA
E2 Enable input (active high) 1.0/1.0 20µA/0.6mA
Q0 – Q7 Data outputs 50/33 1.0mA/20mA
DMUX
A0 1 16 V 1 2 3 15
CC 1 0
0 14
A1 2 15 Q0 1
2
A0 A1 A2 G 0 13
A2 3 14 Q1 3 7 2
4 E0 2 12
E0 4 13 Q2 5 E1 3
11
6 E2 4
E1 5 12 Q3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
4 & 10
5
E2 6 11 Q4 5 9
6
Q7 7 10 Q5 15 14 13 12 11 10 9 7 6 7
7
GND 8 9 Q6
VCC = Pin 16
GND = Pin 8
February 14, 1991 1 853–0343 01719

1–of–8 decoder/demultiplexer 74F138

INPUTS OUTPUTS
E0 E1 E2 A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
3
A2 X X L X X X H H H H H H H H
2 L L H L L L L H H H H H H H
A1
L L H H L L H L H H H H H H
1
A0
L L H L H L H H L H H H H H
4
L L H H H L H H H L H H H H
E0
5 L L H L L H H H H H L H H H
E1
E2 6 L L H H L H H H H H H L H H
15 14 13 12 11 10 9 7 L L H L H H H H H H H H L H
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L L H H H H H H H H H H H L
VCC = Pin 16 2. L = Low voltage level
GND = Pin 8 3. X = Don’t care
APPLICATION
A0
A1
A2
A3
A4 74F04
H
A0 A1 A2 A0 A1 A2 A0 A1 A2 A0 A1 A2
E2 E2 E2 E2
E1 74F138 E1 74F138 E1 74F138 E1 74F138
E0 E0 E0 E0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q31
Fig. 1 Expansion of 1–of–32 decoding

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the oper-
ating free air temperature range.)
Tamb Operating free air temperature range Commercial range 0 to +70 °C

February 14, 1991 2

1-of-4 decoder/demultiplexer 74F139

• Demultiplexing capability
• Two independent 1-of-4 decoders Ea 1 16 VCC
• Multifunction capability A0a 2 15 Eb
A1a 3 14 A0b
Q0a 4 13 A1b
DESCRIPTION Q1a 5 12 Q0b
The 74F139 is a high speed, dual 1-of-4 decoder/demultiplexer. This
device has two independent decoders, each accepting two binary Q2a 6 11 Q1b
weighted inputs (A0n, A1n) and providing four mutually exclusive Q3a 7 10 Q2b
active-Low outputs (Q0n–Q3n). Each decoder has an active-Low
GND 8 9 Q3b
Enable (E). When E is High, every output is forced High. The Enable
can be used as the Data input for a 1-of-4 demultiplexer application. SF00129
TYPE TYPICAL TYPICAL

DELAY (TOTAL) ORDERING INFORMATION
COMMERCIAL RANGE
74F139 5.3ns 13mA DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
16-pin plastic DIP N74F139N
16-pin plastic SO N74F139D

Ana, Anb Address inputs 1.0/1.0 20µA/0.6mA
Ea, Eb Enable inputs (active Low) 1.0/1.0 20µA/0.6mA
Q0n–Q3n Data outputs (active Low) 50/33 1.0mA/20mA

1 2 3 15 14 13
DEMUX
2 4
0 0
0
3 G 5
Ea A0a A1a Eb A0b A1b 1 3 1
6
2
DECODER a DECODER b 1 7
3
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b 14 12
13 11
10
4 5 6 7 12 11 10 9
15 9
VCC = Pin 16
GND = Pin 8
SF00130 SF00131
February 23, 1990 1 853–0344 98903

1-of-4 decoder/demultiplexer 74F139

INPUTS OUTPUTS
Ea A0a A1a Eb A0b A1b
1 2 3 15 14 13 E A0 A1 Q0 Q1 Q2 Q3
H X X H H H H
L L L L H H H
L H L H L H H
L L H H H L H
L H H H H H L
NOTES:
3. X = Don’t care
4 5 6 7 12 11 10 9
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
VCC= Pin 16
GND = Pin 8 SF00132

(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
VOUT Voltage applied to output in High output state –0.5 to +VCC V
IOUT Current applied to output in Low output state 40 mA
Tamb Operating free-air temperature range 0 to +70 °C

LIMITS
SYMBOL PARAMETER UNIT
MIN NOM MAX
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –1 mA
IOL Low-level output current 20 mA
Tamb Operating free-air temperature range 0 +70 °C
February 23, 1990 2

8-input priority encoder 74F148

• Code conversions
• Multi-channel D/A converter I4 1 16 VCC
• Decimal-to-BCD converter I5 2 15 EO
• Cascading for priority encoding of “N” bits I6 3 14 GS
• Input enable capability

I7 4 13 I3
EI 5 12 I2
• Priority encoding-automatic selection of highest priority input line A2 6 11 I1
• Output enable-active Low when all inputs are High A1 7 10 I0
• Group signal output-active when any input is Low GND 8 9 A0
SF00181
DESCRIPTION
The 74F148 8-input priority encoder accepts data from eight
active-Low inputs and provides a binary representation on the three
active-Low outputs. A priority is assigned to each input so that when TYPICAL TYPICAL
two or more inputs are simultaneously active, the input with the TYPE PROPAGATION SUPPLY CURRENT
highest priority is represented on the output, with input line I7 having DELAY (TOTAL)
the highest priority. A High on the Enable Input (EI) will force all
74F148 6.0ns 23mA
outputs to the inactive (High) state and allow new data to settle
without producing erroneous information at the outputs. A Group
Signal (GS) output and an Enable Output (EO) are provided with the ORDERING INFORMATION
three data outputs. The GS is active-Low when any input is Low:
COMMERCIAL RANGE
this indicates when any input is active. The EO is active-Low when DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
all inputs are High. Using the Enable Output along with the Enable
Input allows priority encoding of N input signals. Both EO and GS 16-pin plastic DIP N74F148N
are active-High when the Enable Input is High. 16-pin plastic SO N74F148D

I1 – I7 Priority inputs (active Low) 1.0/2.0 20µA/1.2mA
I0 Priority input (active Low) 1.0/1.0 20µA/0.6mA
EI Enable input (active Low) 1.0/2.0 20µA/1.2mA
EO Enable output (active Low) 50/33 1.0mA/20mA
GS Group select output (active Low) 50/33 1.0mA/20mA
A0 – A2 Address outputs (active Low) 50/33 1.0mA/20mA
10 11 12 13 1 2 3 4
10 HPRI/BIN 9
10/Z10 0α
11 7
11/Z11 1α
12 8
I0 I1 I2 I3 I4 I5 I6 I7 2/Z12 2α
13
3/Z13
EO 15 1
5 EI 4/Z14
2 ≥1
GS 14 5/Z15 10
3 11
A0 A1 A2 6/Z16 12 15
4 13 18
7/Z17 14 14
5 15 α
EN = α/V18
16
VCC = Pin 16 17
9 7 6
GND = Pin 8
SF00182 SF00183
March 1, 1990 1 853–0345 98994

LOGIC DIAGRAM
EI I7 I6 I5 I4 I3 I2 I1 I0
5 4 3 2 1 13 12 11 10
9 9 9 14 15
VCC = Pin 16 A2 A1 A0 GS EO
GND = Pin 8
SF00184
FUNCTION TABLE
INPUTS OUTPUTS
EI I0 I1 I2 I3 I4 I5 I6 I7 GS A0 A1 A2 EO
H X X X X X X X X H H H H H
L H H H H H H H H H H H H L
L X X X X X X X L L L L L H
L X X X X X X L H L H L L H
L X X X X X L H H L L H L H
L X X X X L H H H L H H L H
L X X X L H H H H L L L H H
L X X L H H H H H L H L H H
L X L H H H H H H L L H H H
L L H H H H H H H L H H H H
X = Don’t care
March 1, 1990 2
APPLICATION
ENABLE
LSB MSB
I0 I1 I2 I3 I4 I5 I6 I7 I0 I1 I2 I3 I4 I5 I6 I7
EI EI
EO EO
GS GS
A0 A1 A2 A0 A1 A2
A0 A1 A2 A3 FLAG
16-Input Priority Encoder SF00185

VOUT Voltage applied to output in High output state –0.5 to VCC V

LIMITS
MIN NOM MAX
March 1, 1990 3
8-input multiplexer 74F151A

• High speed 8-to-1 multiplexing
• On chip decoding I3 1 16 VCC
• Multifunction capability I2 2 15 I4
• Complementary outputs
I1 3 14 I5
I0 4 13 I6
• See 74F251A for 3-State version Y 5 12 I7
Y 6 11 S0
DESCRIPTION
E 7 10 S1
The 74F151A is a logic implementation of a single-pole, 8-position
switch with the switch position controlled by the state of three Select GND 8 9 S2
(S0, S1, S2) inputs. True (Y) and complementary (Y) outputs are
both provided. The Enable input (E) is active Low. When E is High, SF00742
the Y output is High and the Y output is Low, regardless of all other
inputs. In one package the 74F151A provides the ability to select
from eight sources of data or control information. The device can
provide any logic function of four variables and the negation with TYPICAL TYPICAL
correct manipulation. TYPE PROPAGATION SUPPLY CURRENT
DELAY (TOTAL)
74F151A 4.5ns 17mA
ORDER CODE
VCC = 5V ±10%, Tamb = 0°C to +70°C
16-pin plastic DIP N74F151AN
16-pin plastic SO N74F151AD

I0–I7 Data inputs 1.0/1.0 20µA/0.6mA
S0–S2 Select inputs 1.0/1.0 20µA/0.6mA
E Enable input (active High) 1.0/1.0 20µA/0.6mA
Y, Y Data outputs 150/33 3mA/20mA
NOTE:
4 3 2 1 15 14 13 12
7 MUX
EN
11
0
10
0 5
9 G
I0 I1 I2 I3 I4 I5 I6 I7 7
4 2
11 S0
3 6
10 S1
2
9 S2
1
7 E
Y Y 15
14
13
VCC = Pin 16 12
GND = Pin 8 5 6
SF00743 SF00744
1995 Jul 17 1 853–1158 15459

8-input multiplexer 74F151A
LOGIC DIAGRAM
I0 I1 I2 I3 I4 I5 I6 I7
9 4 3 2 1 15 14 13 12
S2
10
S1
11
S0
7
E
5 6
VCC = Pin 16 Y Y
GND = Pin 8 SF00741
FUNCTION TABLE
INPUTS OUTPUTS
S2 S1 S0 E Y Y
X X X H L H
L L L L I0 I0
L L H L I1 I1
L H L L I2 I2
L H H L I3 I3
H L L L I4 I4
H L H L I5 I5
H H L L I6 I6
H H H L I7 I7
NOTES:
X = Don’t care
1995 Jul 17 2
Dual 4-line to 1-line multiplexer 74F153
LOGIC DIAGRAM
OEa I0a I1a I2a I3a S1 S2 I0b I0b I2b I3b OEb
1 6 5 4 3 2 14 10 11 12 13 15
7 9
VCC = Pin 16 Ya Yb
GND = Pin 8
SF00149
FUNCTION TABLE
INPUTS OUTPUT
S0 S1 En I0n I1n I2n I3n Yn
X X H X X X X L
L L L L X X X L
L L L H X X X H
H L L X L X X L
H L L X H X X H
L H L X X L X L
L H L X X H X H
H H L X X X L L
H H L X X X H H
X = Don’t care
April 14, 1989 2

Dual 4-line to 1-line multiplexer 74F153

• Non-inverting outputs
• Separate enable for each section Ea 1 16 VCC
• Common select inputs S1 2 15 Eb
• See 74F253 for 3-State version I2a 3 14 S0
I2a 4 13 I3b
I1a 5 12 I2b
DESCRIPTION
The 74F153 is a dual 4-input multiplexer that can select 2 bits of I0a 6 11 I1b
data from up to four sources selected by common Select inputs (S0, Ya 7 10 I0b
S1). The two 4-input multiplexer circuits have individual active-Low
Enables (Ea, Eb) which can be used to strobe the outputs GND 8 9 Yb
independently. Outputs (Ya, Yb) are forced Low when the

SF00146
corresponding Enables (Ea, Eb) are High.
The 74F153 is the logic implementation of a 2-pole, 4-position
switch where the switch is determined by the logic levels supplied to
the common select inputs. COMMERCIAL RANGE
DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
TYPICAL TYPICAL 16-pin plastic DIP N74F153N

TYPE PROPAGATION SUPPLY CURRENT
DELAY (TOTAL)
74F153 7.0ns 12mA

I0a – I3a Port A data inputs 1.0/1.0 20µA/0.6mA
I0b – I3b Port B data inputs 1.0/1.0 20µA/0.6mA
S0, S1 Common Select inputs 1.0/1.0 20µA/0.6mA
Ea Port A Enable input (active Low) 1.0/1.0 20µA/0.6mA
Eb Port B Enable input (active Low) 1.0/1.0 20µA/0.6mA
Ya, Yb Port A, B data outputs 50/33 1.0µA/20mA
6 5 4 3 10 11 12 13 14
0
0
2 G
1 3
I0a I1a I2a I3a I0b I1b I2b I3b

1 MUX
EN
14 S0 6
0
2 S1 5 7
1
4
1 Ea 2
3
15 Eb 3
Ya Yb 15
10
11 9
12
7 9 13
VCC = Pin 16
GND = Pin 8
SF00147 SF00148
April 14, 1989 1 853–0100 96351

SN54/74LS160A
SN54/74LS161A
BCD DECADE COUNTERS/ SN54/74LS162A
4-BIT BINARY COUNTERS SN54/74LS163A
The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous count-
ers. They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency division and
other applications. The LS160A and LS162A count modulo 10 (BCD). The BCD DECADE COUNTERS/
LS161A and LS163A count modulo 16 (binary.) 4-BIT BINARY COUNTERS
The LS160A and LS161A have an asynchronous Master Reset (Clear)
input that overrides, and is independent of, the clock and all other control LOW POWER SCHOTTKY
inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that
overrides all other control inputs, but is active only during the rising clock
edge.
BCD (Modulo 10) Binary (Modulo 16)
Asynchronous Reset LS160A LS161A J SUFFIX
CERAMIC
Synchronous Reset LS162A LS163A
CASE 620-09
16
• Synchronous Counting and Loading 1
• Two Count Enable Inputs for High Speed Synchronous Expansion

• Terminal Count Fully Decoded
• Edge-Triggered Operation
N SUFFIX
• Typical Count Rate of 35 MHz PLASTIC
• ESD > 3500 Volts CASE 648-08
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)

D SUFFIX
NOTE: SOIC
16
The Flatpak version
1 CASE 751B-03
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
*MR for LS160A and LS161A
*SR for LS162A and LS163A SN54LSXXXJ Ceramic

SN74LSXXXN Plastic
SN74LSXXXD SOIC
PIN NAMES LOADING (Note a) LOGIC SYMBOL

HIGH LOW
PE Parallel Enable (Active LOW) Input 1.0 U.L. 0.5 U.L.

P0 – P3 Parallel Inputs 0.5 U.L. 0.25 U.L.
CEP Count Enable Parallel Input 0.5 U.L. 0.25 U.L.

CET Count Enable Trickle Input 1.0 U.L. 0.5 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L.
SR Synchronous Reset (Active LOW) Input 1.0 U.L. 0.5 U.L.
Q0 – Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.
TC Terminal Count Output (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
*MR for LS160A and LS161A
*SR for LS162A and LS163A

5-278
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
STATE DIAGRAM
LS160A • LS162A LS161A • LS163A
LOGIC EQUATIONS
0 1 2 3 4 0 1 2 3 4
Count Enable = CEP • CET • PE
TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3
TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3
15 5 15 5 Preset = PE • CP + (rising clock edge)
Reset = MR (LS160A & LS161A)
Reset = SR • CP + (rising clock edge)
14 6 14 6 Reset = (LS162A & LS163A)
13 7 13 7 NOTE:
The LS160A and LS162A can be preset to any state,
but will not count beyond 9. If preset to state 10, 11,
12 11 10 9 8 12 11 10 9 8 12, 13, 14, or 15, it will return to its normal sequence
within two clock pulses.
FUNCTIONAL DESCRIPTION
The LS160A / 161A / 162A / 163A are 4-bit synchronous the Binary counters). Note that TC is fully decoded and will,
counters with a synchronous Parallel Enable (Load) feature. therefore, be HIGH only for one count state.
The counters consist of four edge-triggered D flip-flops with The LS160A and LS162A count modulo 10 following a
the appropriate data routing networks feeding the D inputs. All binary coded decimal (BCD) sequence. They generate a TC
changes of the Q outputs (except due to the asynchronous output when the CET input is HIGH while the counter is in state
Master Reset in the LS160A and LS161A) occur as a result of, 9 (HLLH). From this state they increment to state 0 (LLLL). If
and synchronous with, the LOW to HIGH transition of the loaded with a code in excess of 9 they return to their legitimate
Clock input (CP). As long as the set-up time requirements are sequence within two counts, as explained in the state
met, there are no special timing or activity constraints on any diagram. States 10 through 15 do not generate a TC output.
of the mode control or data inputs. The LS161A and LS163A count modulo 16 following a
Three control inputs — Parallel Enable (PE), Count Enable binary sequence. They generate a TC when the CET input is
Parallel (CEP) and Count Enable Trickle (CET) — select the HIGH while the counter is in state 15 (HHHH). From this state
mode of operation as shown in the tables below. The Count they increment to state 0 (LLLL).
Mode is enabled when the CEP, CET, and PE inputs are HIGH. The Master Reset (MR) of the LS160A and LS161A is
When the PE is LOW, the counters will synchronously load the asynchronous. When the MR is LOW, it overrides all other
data from the parallel inputs into the flip-flops on the LOW to input conditions and sets the outputs LOW. The MR pin should
HIGH transition of the clock. Either the CEP or CET can be never be left open. If not used, the MR pin should be tied
used to inhibit the count sequence. With the PE held HIGH, a through a resistor to VCC, or to a gate output which is
LOW on either the CEP or CET inputs at least one set-up time permanently set to a HIGH logic level.
prior to the LOW to HIGH clock transition will cause the The active LOW Synchronous Reset (SR) input of the
existing output states to be retained. The AND feature of the LS162A and LS163A acts as an edge-triggered control input,
two Count Enable inputs (CET • CEP) allows synchronous overriding CET, CEP and PE, and resetting the four counter
cascading without external gating and without delay accu- flip-flops on the LOW to HIGH transition of the clock. This
mulation over any practical number of bits or digits. simplifies the design from race-free logic controlled reset
The Terminal Count (TC) output is HIGH when the Count circuits, e.g., to reset the counter synchronously after
Enable Trickle (CET) input is HIGH while the counter is in its reaching a predetermined value.
maximum count state (HLLH for the BCD counters, HHHH for
MODE SELECT TABLE

*SR PE CET CEP Action on the Rising Clock Edge ( )
L X X X RESET (Clear) *For the LS162A and
H L X X LOAD (Pn º Qn) *LS163A only.
H H H H COUNT (Increment) H = HIGH Voltage Level
H H L X NO CHANGE (Hold) L = LOW Voltage Level
H H X L NO CHANGE (Hold) X = Don’t Care

5-279
4-bit binary counters 74F161A, 74F163A
FEATURES A Low level at the Master Reset (MR) input sets all the four outputs
• Industrial range available on 74F163A (–40°C to +85°C) of the flip-flops (Q0 – Q3) in 74F161A to Low levels, regardless of
the levels at CP, PE, CET and CEP inputs (thus providing an
• Synchronous counting and loading asynchronous clear function). For the 74F163A, the clear function is
synchronous. A Low level at the Synchronous Reset (SR) input sets
• Two count enable inputs for n-bit cascading all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next
• Positive edge-triggered clock positive-going transition on the clock (CP) input (provided that the
setup and hold time requirements for SR are met). This action
• Asynchronous Master Reset (74F161A) occurs regardless of the levels at PE, CET, and CEP inputs. The
• Synchronous Reset (74F163A) synchronous reset feature enables the designer to modify the
maximum count with only one external NAND gate (see Figure 1).
• High speed synchronous expansion the carry look-ahead simplifies serial cascading of the counters.
Both Count Enable (CEP and CET) inputs must be High to count.
• Typical count rate of 130MHz The CET input is fed forward to enable the TC output. The TC
output thus enabled will produce a High output pulse of a duration
approximately equal to the High level output of Q0. This pulse can
DESCRIPTION be used to enable the next cascaded stage (see Figure 2). The TC
4-bit binary (74F161A, 74F163A) counters feature an internal carry output is subjected to decoding spikes due to internal race
look-ahead and can be used for high-speed counting. Synchronous conditions. Therefore, it is not recommended for use as clock or
operation is provided by having all flip-flops clocked simultaneously asynchronous reset for flip-flops, registers, or counters.
on the positive-going edge of the clock. the clock input is buffered.
The outputs of the counters may be preset to High or Low level. A
Low level at the Parallel Enable (PE) input disables the counting TYPICAL TYPICAL SUPPLY CURRENT
action and causes the data at the D0–D3 inputs to be loaded into TYPE
fMAX (TOTAL)
the counter on the positive-going edge of the clock (provided that
74F161A
the setup and hold requirements for PE are met). Preset takes place 130MHz 46mA
74F163A
regardless of the levels at Count Enable (CEP, CET) inputs.
ORDER CODE
DESCRIPTION DRAWING
COMMERCIAL RANGE INDUSTRIAL RANGE NUMBER
16-pin plastic DIP N74F161AN, N74F163AN I74F163AN SOT38-4
16-pin plastic SO N74F161AD, N74F163AD I74F163AD SOT109-1

D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA
CEP Count Enable Parallel input 1.0/1.0 20µA/0.6mA
CET Count Enable Trickle input 1.0/2.0 20µA/1.2mA
CP Clock input (active rising edge) 1.0/1.0 20µA/0.6mA
PE Parallel Enable input (active Low) 1.0/2.0 20µA/1.2mA
MR Asynchronous Master Reset input 1.0/1.0 20µA/0.6mA
(active Low) for 74F161A
SR Synchronous Reset input 1.0/1.0 20µA/0.6mA
(active Low) for 74F163A
TC Terminal count output 50/33 1.0mA/20mA
Q0 – Q3 Flip-flop outputs 50/33 1.0mA/20mA
NOTE:
1995 Mar 31 1 853–0347 15060

74F161A PIN CONFIGURATION 74F163A PIN CONFIGURATION
MR 1 16 VCC SR 1 16 VCC
CP 2 15 TC CP 2 15 TC
D0 3 14 Q0 D0 3 14 Q0
D1 4 13 Q1 D1 4 13 Q1
D2 5 12 Q2 D2 5 12 Q2
D3 6 11 Q3 D3 6 11 Q3
CEP 7 10 CET CEP 7 10 CET
GND 8 9 PE GND 8 9 PE
SF00656 SF00657
74F161A LOGIC SYMBOL 74F163A LOGIC SYMBOL
3 4 5 6 3 4 5 6
D0 D1 D2 D3 D0 D1 D2 D3
9 PE 9 PE
7 CEP 7 CEP
10 CET TC 15 10 CET TC 15
2 CP 2 CP
1 MR 1 SR
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
VCC = Pin 16 14 13 12 11 VCC = Pin 16 14 13 12 11

SF00658 SF00659
74F161A LOGIC SYMBOL (IEEE/IEC) 74F163A LOGIC SYMBOL (IEEE/IEC)
1 CTR DIV 16 1 CTR DIV 16

R 2R
9 9
M1 M1
7 7
G3 G3
10 10
G4 G4
2 2
C2 /1,3,4+ C2 /1,3,4+
3 14 3 14
1,2 D 1,2 D
4 13 4 13
5 12 5 12
6 11 6 11
15 15
4 CT=15 4 CT=15
SF00660 SF00661
1995 Mar 31 2
STATE DIAGRAM
0 1 2 3 4
15 5
14 6
13 7
12 11 10 9 8
LOGIC EQUATIONS:
COUNT ENABLE = CEP CET PE
TC = Q0 Q1 Q2 Q3 CET
SF00664
APPLICATIONS
+VCC
D0 D1 D2 D3
PE
CEP
CET 74F163A TC
CLOCK CP
SR Q0 Q1 Q2 Q3
SF00665
Figure 1. Maximum count modifying scheme

Terminal count = 6
H H = Enable count
or
L L = Disable count
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
PE PE PE PE PE
CEP CEP CEP CEP CEP
CET 74F163A TC CET 74F163A TC CET 74F163A TC CET 74F163A TC CET 74F163A TC
CP CP CP CP CP
SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3 SR Q0 Q1 Q2 Q3
CP
SF00666
Figure 2. Synchronous multistage counting scheme
1995 Mar 31 3
74F161A MODE SELECT – FUNCTION TABLE

INPUTS OUTPUTS
OPERATING MODE
MR CP CEP CET PE Dn Qn TC
L X X X X X L L Reset (clear)
H ↑ X X l l L L
Parallel load
H ↑ X X l h H (1)
H ↑ h h h X count (1) Count
H X l X h X qn (1)
Hold (do nothing)
H X X l h X qn L
74F163A MODE SELECT – FUNCTION TABLE

INPUTS OUTPUTS
OPERATING MODE
SR CP CEP CET PE Dn Qn TC
l ↑ X X X X L L Reset (clear)
h ↑ X X l l L L
Parallel load
h ↑ X X l h H (2)
h ↑ h h h X count (2) Count
h X l X h X qn (2)
Hold (do nothing)
h X X l h X qn L
h = High voltage level one setup prior to the Low-to-High clock transition
l = Low voltage level one setup prior to the Low-to-High clock transition
qn = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
(1) = The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A)
(2) = The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)
1995 Mar 31 4
74F161A LOGIC DIAGRAM
2
CP
1
MR
9
PE
10
CET
7
CEP
3
D0
D R Q
14
CP Q Q0
4
D1
D R Q
13
CP Q Q1
5
D2
D R Q
12
CP Q Q2
6
D3
D R Q
11
CP Q Q3
15
TC
VCC = Pin 16
GND = Pin 8
SF00662
1995 Mar 31 5
74F163A LOGIC DIAGRAM
2
CP
1
SR
9
PE
10
CET
7
CEP
3
D0
D Q
14
CP Q Q0
4
D1
D Q
13
CP Q Q1
5
D2
D Q
12
CP Q Q2
6
D3
D Q
11
CP Q Q3
15
TC
VCC = Pin 16
GND = Pin 8
SF00663
1995 Mar 31 6
Quad D-type flip–flop (3-State) 74F173
FEATURES control, 3–state buffered outputs, and high, all four flip–flops are reset
• Edge–triggered D–type register master reset (MR). When the two clock (cleared) independently of any other
input condition.
• Gated clock enable for hold ”do noth- enable (E0 and E1) inputs are low, the
data on the D inputs is loaded into the
ing” mode The 3–state output buffers are
register simultaneously with low–to–high controlled by a 2–input NOR gate.
• 3–state output buffers clock (CP) transition. When one or both When both output enable (OE0 and
• Gated output enable control enable inputs are high one setup time OE1) inputs are low, the data in the
• Speed upgrade of N8T10 and current before the low–to–high clock transition, register is presented at the Q output.
sink upgrade the register retains the previous data. When one or both OE inputs are high,
• Controlled output edges to minimize the outputs are forced to a high
ground bounces impedance ”off” state.
• 48mA sinking capability Data inputs and clock enable inputs are
fully edge–triggered and must be stable
The 3–state output buffers are com-
pletely independent of the register op-
only one setup time before the
eration; the OE transition does not affect
DESCRIPTION low–to–high clock transition.
the clock and reset operations.
The 74F173 is a high speed 4–bit The master reset (MR) is an active–high
parallel load registor with clock enable asynchronous input. When the MR is
TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL)

74F173 125MHz 23mA
ORDER CODE
VCC = 5V ±10%, Tamb = 0°C to +70°C
16–pin plastic DIP N74F173N
16–pin plastic SO N74F173D

PINS DESCRIPTION 74F (U.L.) HIGH/ LOAD VALUE
LOW HIGH/LOW
D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA
CP Clock input 1.0/1.0 20µA/0.6mA
E0, E1 Clock enable inputs 1.0/1.0 20µA/0.6mA
MR Master reset input 1.0/1.0 20µA/0.6mA
OE0, OE1 Output enable inputs 1.0/1.0 20µA/0.6mA
Q0 – Q3 Data outputs 750/80 15mA/48mA
August 31, 1990 1 853 1160 00286

9 &
14 13 12 11
OE0 1 16 V 10
CC
C1
OE1 2 15 MR 7
9 D0 D1 D2 D3 1
Q0 3 14 D0 E0 &
10 E1 2 EN
Q1 4 13 D3
7 CP 15
15 R
Q2 5 12 D2 MR
1 OE0 14 3
Q3 6 11 Q2 2 OE1 Q0 Q1 Q2 Q3 1D
13 4
CP 7 10 E1
12 5
GND 8 9 E0 3 4 5 6 11 6
VCC = Pin 16
GND = Pin 8
FUNCTION TABLE
INPUTS OUTPUTS OUTPUTS
MR CP E0 E1 Dn Qn (register)
H X X X X L Reset (clear)
L ↑ l l l L Parallel load
L ↑ l l h H
L X h X X qn Hold (do nothing)
L X X h X qn
1. H = High–voltage level
2. h = High state one setup time before the low–to–high clock transition
3. L = Low–voltage level
4. l = Low state one setup time before the low–to–high clock transition
5. qn = Lower case letters indicate the state of the referenced input (or output) on setup time prior to the low–to–high clock transition
6. X = Don’t care
7. ↑ = Low–to–high clock transition
FUNCTION TABLE
INPUTS OUTPUTS OUTPUTS
Qn (register) OE0 OE1 Qn
L L L L Read
H L L H
X H X Z Disabled
X X H Z
1. H = High–voltage level
2. L = Low–voltage level
3. X = Don’t care
4. Z = High impedance ”off” state
August 31, 1990 2

LOGIC DIAGRAM
D0 D1 D2 D3
14 13 12 11
9
E0
10
E1
7
CP
D Q D Q D Q D Q
CP CP CP CP
Q Q Q Q
RD RD RD RD
15
MR
1
OE0
2
OE1
3 4 5 6
Q0 Q1 Q2 Q3
VCC = Pin 16
GND = Pin 8

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
Tamb Operating free air temperature range 0 to +70 °C


SYMBOL PARAMETER LIMITS UNIT
MIN NOM MAX
VIH High–level input voltage 2.0 V
VIL Low–level input voltage 0.8 V
IIk Input clamp current –18 mA
IOH High–level output current –15 mA
IOL Low–level output current 48 mA
Tamb Operating free air temperature range 0 +70 °C
August 31, 1990 3

Hex D flip-flop 74F174

• Six edge-triggered D-type flip-flops
• Buffered common Clock MR 1 16 VCC
• Buffered, asynchronous Master Reset Q0 2 15 Q5
D0 3 14 D5
DESCRIPTION D1 4 13 D4
The 74F174 has six edge-triggered D-type flip-flops with individual D Q1 5 12 Q4

inputs and Q outputs. The common buffered Clock (CP) and Master
D2 6 11 D3
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
Q2 7 10 Q3
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to GND 8 9 CP
the corresponding flip-flop’s Q output.
SF00188
All Q outputs will be forced Low independent of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where true outputs only are required, and the Clock and
Master Reset are common to all storage elements.
COMMERCIAL RANGE
TYPICAL DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
TYPE TYPICAL fMAX SUPPLY CURRENT
(TOTAL) 16-pin plastic DIP N74F174N
74F174 100MHz 35mA 16-pin plastic SO N74F174D

D0–D5 Data inputs 1.0/1.0 20µA/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
MR Master Reset input (active-Low) 1.0/1.0 20µA/0.6mA
Q0–Q5 Outputs 50/33 1.0mA/20mA
3 4 6 11 13 14 9
C1
1
R
D0 D1 D2 D3 D4 D5
3 2
1D
9 CP
4 5
1 MR
6 7
Q0 Q1 Q2 Q3 Q4 Q5
11 10
13 12
2 5 7 10 12 15
14 15
VCC = Pin 16
GND = Pin 8
SF00189 SF00190
October 7, 1988 1 853–0060 94766

Hex D flip-flop 74F174
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5
3 4 6 11 13 14
D Q D Q D Q D Q D Q D Q
CP CP CP CP CP CP
RD RD RD RD RD RD
9
CP
1
MR
2 5 7 10 12 15
VCC = Pin 16 Q0 Q1 Q2 Q3 Q4 Q5
GND = Pin 8
SF00192
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
MR CP D Qn
L X X L Reset (clear)
H ↑ h H Load “1”
H ↑ l L Load “0”
X = Don’t care
↑ = Low-to-High Clock transition
h = High voltage level one set-up time prior to the Low-to-High Clock transition.
l = Low voltage level one set-up time prior to the Low-to-High Clock transition.


LIMITS
MIN NOM MAX
October 7, 1988 2
Quad D flip-flop 74F175/74F175A

• Four edge-triggered D-type flip-flops
• Buffered common clock MR 1 16 V
CC
• Buffered asynchronous Master Reset Q0 2 15 Q3
• True and complementary outputs Q0 3 14 Q3
• Industrial temperature range available (–40°C to +85°C) D0 4 13 D3
D1 5 12 D2
• PNP light loading inputs (74F175A)
Q1 6 11 Q2
• Improved AC, DC, and functional (74F175A) Q1 7 10 Q2
GND 8 9 CP
DESCRIPTION
SF00718
The 74F175 is a quad, edge-triggered D-type flip-flop with individual
D inputs and both Q and Q outputs. The common buffered Clock
(CP) and Master Reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
TYPE TYPICAL fmax TYPICAL SUPPLY
The register is fully edge-triggered. The state of each D input, one CURRENT (TOTAL)
setup time before the Low-to-High clock transition is transferred to
74F175 140MHz 25mA
the corresponding flip-flop’s Q output.
74F175A 160MHz 22mA
All Q outputs will be forced Low independently of clock or data
inputs by a Low voltage level on the MR input. The device is useful
for applications where both true and complementary outputs are
required, and the CP and MR are common to all storage elements. ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE DRAWING

VCC = 5V ±10%, NUMBER
Tamb = 0°C to +70°C
16-pin plastic DIP 74F175N SOT38-4
16-pin plastic SO 74F175D SOT109-1
16-pin plastic DIP 74F175AN SOT38-4
16-pin plastic SO 74F175AD SOT109-1

74F (U.L.) LOAD VALUE
PINS DESCRIPTION2
HIGH/LOW HIGH/LOW
74F175 1.0/1.0 20µA/0.6mA
D0 – D3 Data inputs
74F175A 1.0/0.033 20µA/20µA
74F175 1.0/1.0 20µA/0.6mA
MR Master reset input (active–Low)
74F175A 1.0/0.033 20µA/20µA
74F175 1.0/1.0 20µA/0.6mA
CP Clock input (active rising edge)
74F175A 1.0/0.033 20µA/20µA
Q0–Q3 True outputs 50/33 1.0mA/20mA
Q0–Q3 Complementary outputs 50/33 1.0mA/20mA
NOTE:
1991 Nov 19 1 853–0047 04742

Quad D flip-flop 74F175/74F175A
1
4 5 12 13 R
9 C1
2
D0 D1 D2 D3 4
1D 3
9 CP 7
1 MR 5
6
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 10
12
11
15
2 3 7 6 10 11 15 14 13
VCC = Pin 16 14
GND = Pin 8 SF00719 SF00720
LOGIC DIAGRAM
D0 D1 D2 D3
4 5 12 13
9
CP
D Q D Q D Q D Q
CP CP CP CP
Q
RD RD RD RD
1
MR
3 2 6 7 11 10 14 15
VCC = Pin 16 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
GND = Pin 8 SF00721
FUNCTION TABLE
INPUTS OUTPUTS H = High voltage level
OPERATING h = High state must be present one setup time before the
MR CP Dn Qn Qn MODE Low-to-High clock transition
L X X L H Reset (clear)
l = Low state must be present one setup time before the
H ↑ h H L Load “1” Low-to-High clock transition
X = Don’t care
H ↑ I L H Load “0” ↑ = Low-to-High clock transition

(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
Commercial range 0 to +70 °C

Tamb Operating free air temperature range
1991 Nov 19 2
Arithmetic logic unit 74F181

• Provides 16 arithmetic operation: add, subtract, compare, and
double; plus 12 other arithmetic operations B0 1 24 VCC
• Provides all 16 logic operations of two variables: Exclusive-OR, A0 2 23 A1
Compare, AND, NAND, NOR, OR, plus 10 other logic operations S3 3 22 B1
• Full look-ahead carry for high speed arithmetic operation on long S2 4 21 A2
words S1 5 20 B2
• 40% faster than ’S181 with only 30% ’S181 power consumption S0 6 19 A3
• Available in 300mil-wide Slim 24-pin Dual In-Line package Cn 7 18 B3
M 8 17 G
DESCRIPTION F0 9 16 C
n+4
The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit F1 10 15 P
(ALU). Controlled by the four Function Select inputs (S0–S3) and F2 11 14 A=B
the Mode Control input (M), it can perform all the 16 possible logic
GND 12 13 F3
operations or 16 different arithmetic operations on active-High or
active-Low operands. The Function Table lists these operations. SF00193
TYPICAL
TYPE TYPICAL PROPAGATION DELAY SUPPLY CURRENT
(TOTAL)
74F181 7.0ns 43mA
COMMERCIAL RANGE
DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
24-Pin Plastic Slim DIP (300 mil) N74F181N
24-Pin Plastic SOL N74F181D

A0–A3 A operand inputs 1.0/3.0 20µA/1.8mA
B0–B3 B operand inputs 1.0/3.0 20µA/1.8mA
M Mode control input 1.0/1.0 20µA/0.6mA
S0–S3 Function select input 1.0/4.0 20µA/2.4mA
Cn Carry input 1.0/5.0 20µA/3.0mA
Cn+4 Carry output 50/33 1.0mA/20mA
P Carry Propagate output 50/33 1.0mA/20mA
G Carry Generate output 50/33 1.0mA/20mA
A=B Compare output OC/33 OC/20mA
F0–F3 Outputs 50/33 1.0mA/20mA
OC = Open Collector
March 3, 1989 1 853–0351 95947

Active-High Operands
6 ALU
2 1 23 22 21 20 19 18 0 [T]
5 15
CP
4 0 17
M CG
3 21
16
A0 B0 A1 B1 A2 B2 A3 B3 CO
8 4 14
7 Cn P=G
7 CI
8 M Cn+4 16
6 S0 A=B 14 2 P0 9
5 S1 G 17 1 Q0
4 S2 P 15 23 P1 10
3 S3 22 Q1
F0 F1 F2 F3 21 P2 11
20 Q2
19 P3 13
18 Q3
9 10 11 13
SF00197
Active-Low Operands
2 1 23 22 21 20 19 18
A0 B0 A1 B1 A2 B2 A3 B3
7 Cn
8 M Cn+4 16
6 S0 A=B 14
5 S1 G 17
4 S2 P 15
3 S3
F0 F1 F2 F3
9 10 11 13
VCC = Pin 24
GND = Pin 12
SF00196
March 3, 1989 2
LOGIC DIAGRAM
6
S0
5
S1
4
S2
3
S3
18
B3
17
G
16
Cn+4
19
A3
20 15
B2 P
21
A2
13
F3
22
B1
23 11
A1 F2
1
B0
14
A=B
10
F1
2
A0
8
M
9
F0
7
Cn
VCC = Pin 24
GND = Pin 12
SF00194
March 3, 1989 3
When the Mode Control input (M) is High, all internal carries are when the unit is in the subtract mode. The A=B output is
inhibited and the device performs logic operations on the individual open-collector and can be wired-AND with other A=B outputs to give
bits as listed. When the Mode control input is Low, the carries are a comparison for more than 4 bits. The A=B signal can also be used
enabled and the device performs arithmetic operations on the two with the Cn+4 signal to indicate A>B and A<B. The Function Table
4-bit words. The device incorporates full internal carry look-ahead lists the arithmetic operations that are performed without a carry in.
and provides for either ripple carry between device using the Cn+4 An incoming carry adds a one to each operation. Thus select code
output, or for carry look-ahead between packages using the signals LHHL generates A minus B minus 1 (two’s complement notation)
P (Carry Propagate) and G (Carry Generate). P and G are not without a carry in and generates A minus B when a carry is applied.
affected by carry in. When speed requirements are not stringent, it Because subtraction is actually performed by complementary
can be used in a simple ripple carry mode by connecting the Carry addition (one’s complement), a carry out means borrow; thus, a
output (Cn+4) signal to the Carry input (Cn) of the next unit. For carry is generated when there is no underflow and no carry is
high-speed operation, the device is used in conjunction with the generated when there is underflow. As indicated, this device can be
74F182 carry look-ahead circuit. One carry look-ahead package is used with either active-Low inputs producing active-Low outputs or
required for each group of four 74F181 devices. Carry look-ahead with active-High inputs producing active-High outputs. For either
can be provided at various levels and offers high speed capability case, the table lists the operations that are performed to the
over extremely long word lengths. operands labeled inside the logic symbol.
The A=B output from the device goes High when all four F outputs
are High and can be used to indicate logic equivalence over 4-bits
MODE-SELECT FUNCTION TABLE

MODE SELECT INPUTS ACTIVE HIGH INPUTS & OUTPUTS ACTIVE LOW INPUTS & OUTPUTS
S3 S2 S1 S0 Logic (M=H) Arithmetic** (M=L) (Cn=H) Logic (M=H) Arithmetic** (M=L) (Cn=L)
L L L L A A A A minus 1
L L L H A+B A+B AB AB minus 1
L L H L AB A+B A+B AB minus 1
L L H H Logical 0 minus 1 Logical 1 minus 1
L H L L AB A plus AB A+B A plus (A+B)
L H L H B (A+B) plus AB B AB plus (A+B)
L H H L A⊕B A minus B minus 1 A⊕B A minus B minus 1
L H H H AB AB minus 1 A+B A+B
H L L L A+B A plus AB AB A plus (A+B)
H L L H A⊕B A plus B A⊕B A plus B
H L H L B (A+B) plus AB B AB plus (A+B)
H L H H AB AB minus 1 A+B A+B
H H L L Logical 1 A plus A* Logical 0 A plus A*
H H L H A+B (A+B) plus A AB AB plus A
H H H L A+B (A+B) plus A AB AB plus A
H H H H A A minus 1 A A
* = Each bit is shifted to the next more significant position.
** = Arithmetic operations expressed in two’s complement notation.
March 3, 1989 4
Look-ahead carry generator 74F182

• Provides carry look-ahead across a group of four ALUs
• Multi-level look-ahead for high speed arithmetic operation over G1 1 16 VCC
long word lengths P1 2 15 P2
G0 3 14 G2
DESCRIPTION P0 4 13 Cn
The 74F182 is a high speed carry look-ahead generator. It accepts
up to four pairs of active-Low Carry Propagate (P0, P1, P2, P3) and G3 5 12 Cn+x
Carry Generate (G0, G1, G2, G3) signals and an active-High Carry P3 6 11 Cn+y
input (Cn) and provides anticipated active-High carries (Cn+x, Cn+y,
P 7 10 G
Cn+z) across four groups of binary adders. The 74F182 also has
active-Low Carry Propagate (P) Carry Generate (G) outputs which GND 8 9 Cn+z
may be used for further levels of look-ahead.
SF00725
The logic equations provided at the outputs are:
Cn+x = G0+P0Cn
TYPICAL TYPICAL
Cn+y = G1+P1G0+P1P0Cn PROPAGATION SUPPLY CURRENT
TYPE
Cn+z = G2+P2G1+P2P1G0+P2P1P0Cn DELAY (TOTAL)
G = G3+P3G2+P3P2G1+P3P2P1G0
P = P3P2P1P0 74F182 5.0ns 21mA
The 74F182 can also be used with binary ALUs in an active-Low or

active-High input operand mode. The connections to and from the
ALU to the carry look-ahead generator are identical in both cases. ORDER CODE
VCC = 5V ±10%, Tamb = 0°C to +70°C

PINS DESCRIPTION 74FAST (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
Cn Carry input 2.5/2.0 50µA/1.2mA
G0, G2 Carry generate inputs (active-Low) 2.5/14.0 50µA/8.4mA
G1 Carry generate input (active-Low) 2.5/16.0 50µA/9.6mA
G3 Carry generate input (active-Low) 2.5/8.0 50µA/4.8mA
P0, P1 Carry propagate inputs (active-Low) 2.5/8.0 50µA/4.8mA
P2 Carry propagate input (active-Low) 2.5/6.0 50µA/3.6mA
P3 Carry propagate input (active-Low) 2.5/4.0 50µA/2.4mA
Cn+x–Cn+z Carry outputs 50/33 1.0mA/20mA
G Carry generate output (active-Low) 50/33 1.0mA/20mA
P Carry propagate output (active-Low) 50/33 1.0mA/20mA
NOTE:
1991 Apr 15 2 853–1161 02162

4 3 2 1 15 14 6 5 CPG
13
CI
4
CP0
C00 12
3
CG0
P0 G0 P1 G1 P2 G2 P3 G3
G 10 2 11
CP1 C01
13 Cn
P 7 1
CG1 9
C02
15
Cn+x Cn+y Cn+z CP2
7
14 CP
CG2
6 10
CP3 CG
5
12 11 9 CG3
VCC = Pin 16
GND = Pin 8
SF00726 SF00727
LOGIC DIAGRAM
G0 3
P0 4 12
Cn+x
13
Cn
G1 1
P1 2
11
Cn+y
G2 14
P2 15
9
Cn+z
G3 5
P3 6
10
G
7
P
VCC = Pin 16
GND = Pin 8
SF00724
1991 Apr 15 3
FUNCTION TABLE
INPUTS OUTPUTS
Cn G0 P0 G1 P1 G2 P2 G3 P3 Cn+x Cn+y Cn+z G P
X H H L
L H X L
X L X H
H X L H
X X X H H L
X H H H X L
L H X H X L
X X X L X H
X L X X L H
H X L X L H
X X X X X H H L
X X X H H H X L
X H H H X H X L
L H X H X H X L
X X X X X L X H
X X X L X X L H
X L X X L X L H
H X L X L X L H
X X X X X H H H
X X X H H H X H
X H H H X H X H
H H X H X H X H
X X X X X L X L
X X X L X X L L
X L X X L X L L
L X L X L X L L
H X X X H
X H X X H
X X H X H
X X X H H
L L L L L
NOTES:
X = Don’t care
1991 Apr 15 4
APPLICATION
Cn Cn
ALU* G ALU* G
P P
A, B
C18
Cn+4 Cn+4 Cn+4 Cn+4 COUT

Cn Cn Cn Cn Cn Cn
(C32)
ALU* G ALU* G ALU* G ALU* G ALU* ALU*
P P P P
P0 G0 P1 G1 P2 G2 P3 G3 P0 G0 P1 G1 P2 G2 P3 G3
G G
CIN Cn 74F182 Cn 74F182
P P
Cn+x Cn+y Cn+z Cn+x Cn+y Cn+z
SF00728
Figure 1. 32-Bit ALU with Ripple Carry Between 16-Bit Look-Ahead ALUs (*ALUs may be either 74F181 or 74F381)

(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)

LIMITS
MIN NOM MAX
Tamb Operating free-air temperature range 0 70 °C
1991 Apr 15 5
Up/Down binary counter with reset and ripple clock 74F191

• High speed –125MHz typical fMAX
• Synchronous, reversible counting D1 1 16 VCC
• 4-Bit binary Q1 2 15 D0
• Asynchronous parallel load capability Q0 3 14 CP
• Cascadable without external logic

CE 4 13 RC
U/D 5 12 TC
• Single up/down control input Q2 6 11 PL
Q3 7 10 D2
DESCRIPTION
GND 8 9 D3
The 74F191 is a 4-bit binary counter. It contains four edge-triggered
master/slave flip-flops with internal gating and steering logic to
provide asynchronous preset and synchronous count-up and SF00729
count-down operations.
Asynchronous parallel load capability permits the counter to be
preset to any desired number. Information present on the parallel TYPICAL
data inputs (D0 - D3) is loaded into the counter and appears on the TYPE TYPICAL fMAX SUPPLY CURRENT
outputs when the Parallel Load (PL) input is Low. This operation (TOTAL)
overrides the counting function. Counting is inhibited by a High level
74F191 125MHz 40mA
on the count enable (CE) input. When CE is Low, internal state
changes are initiated. Overflow/underflow indications are provided
by two types of outputs, the Terminal Count (TC) and Ripple Clock ORDERING INFORMATION
(RC). COMMERCIAL RANGE
DESCRIPTION
The TC output is normally Low and goes High when: 1) the count VCC = 5V ±10%, Tamb = 0°C to +70°C
reaches zero in the countdown mode or 2) reaches “15” in the count 16-pin plastic DIP N74F191N
up mode. The TC output will remain High until a state change
occurs, either by counting or presetting, or until U/D is changed. TC
output should not be used as a clock signal because it is subject to
decoding spikes. The TC signal is used internally to enable the RC
output. When TC is High and CE is Low, the RC follows the clock
pulse. The RC output essentially duplicates the Low clock pulse
width, although delayed in time by two gate delays.

74F(U.L.) LOAD VALUE
PINS DESCRIPTION
HIGH/LOW HIGH/LOW
D0 - D3 Data inputs 1.0/1.0 20µA/0.6mA
CE Count enable input (active Low) 1.0/3.0 20µA/1.8mA
CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
PL Asynchronous parallel load control input (active Low) 1.0/1.0 20µA/0.6mA
U/D Up/down count control input 1.0/1.0 20µA/0.6mA
Q0 - Q3 Flip-flop outputs 50/33 1.0mA/20mA
RC Ripple clock output (active low) 50/33 1.0mA/20mA
TC Terminal count output 50/33 1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
1995 Jul 17 1 853–0352 15459


15 1 10 9
4 EN1 CTR DIV 10

4 D0 D1 D2 D3
CE 5 M2[DOWN] 12
2(CT=0)Z6
M3[UP] 3(CT=15)Z6
5 U/D RC 13
14 13
1,2–/1,3+ 6, 4, 1
14 CP TC 12 G4
11
C5 [LOAD]
11 PL
Q0 Q1 Q2 Q3
15 3
5D [1] +–
1 2
3 2 6 7 [2]
VCC=Pin 16 10 6
GND=Pin 8 [4]
SF00730 9 [8] 7
SF00731
LOGIC DIAGRAM
D0 D1 D2 D3
15 1 10 9
PL 11
5
U/D
4
CE
14
CP
J K J K J K J K
CP CP CP CP
SD RD SD RD SD RD SD RD
Q Q Q Q Q Q Q Q
13 12 3 2 6 7
RC TC Q0 Q1 Q2 Q3
VCC = Pin 16
GND = Pin 8 SF00732
1995 Jul 17 2
MODE SELECT — FUNCTION TABLE

INPUTS OUTPUTS OPERATING MODE
PL U/D CE CP Dn Qn
L X X X L L
Parallel load
L X X X H H
H L l ↑ X Count up Count up
H H l ↑ X Count down Count down
H X H X X No change Hold (do nothing)
TC AND RC FUNCTION TABLE

INPUTS TERMINAL COUNT STATE OUTPUTS
U/D CE CP Q0 Q1 Q2 Q3 TC RC
H H X H H H H L H
L H X H H H H H H
L L H H H H H
L H X L L L L L H
H H X L L L L H H
H L L L L L H
H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
= Low pulse
l = Low voltage level one set-up time prior to the Low-to-High clock transition
1995 Jul 17 3
APPLICATIONS
DIRECTION CONTROL
U/D RC U/D RC U/D RC

ENABLE CE CE CE
CLOCK CP CP CP
a. N-Stage Counter Using Ripple Clock

DIRECTION CONTROL
U/D RC U/D RC U/D RC

ENABLE CE CE CE
CP CP CP
CLOCK
b. Synchronous N-Stage Counter with Common Clock Using Ripple/Clock
DIRECTION CONTROL
ENABLE
U/D U/D U/D

CE * CE * CE
CP TC CP TC CP TC
CLOCK
* = Carry Gate
c. Synchronous N-Stage Counter with Common Clock and Terminal Count SF00733
Figure 1.
The 74F191 simplifies the design of multi-stage counters, as ripple fashion and all clock inputs are driven in parallel. The Low
indicated in Figure 1, each RC output is used as the clock input for state duration of the clock in this configuration must be long enough
the next higher stage. When the clock source has a limited drive to allow the negative-going edge of the RC signal to ripple through
capability this configuration is particularly advantageous, since the to the last stage before the clock goes High. Since the RC output of
clock source drives only the first stage. It is only necessary to inhibit any package goes High shortly after its clock input goes High, there
the first stage to prevent counting in all stages, since a High signal is no such restriction on the High state duration of the clock.
on CE inhibits the RC output pulse as indicated in the Mode Select
In Figure 1c, the configuration shown avoids ripple delays and their
Table. The timing skew between state changes in the first and last
associated restrictions. The combined TC signals from all the
stages is represented by the cumulative delay of the clock as it
preceding stages forms the CE input signal for a given stage. An
ripples through the preceding stages. This is a disadvantage of the
enable signal must also be included in each carry gate in order to
configuration in some applications.
inhibit counting. The TC output of a given stage is not affected by its
Figure 1b shows a method of causing state changes to occur own CE, therefore, the simple inhibit scheme of Figure 1a and 1b
simultaneously in all stages. The RC output signals propagate in does not apply.
1995 Jul 17 4
Up/down binary counter with separate up/down clocks 74F193
FEATURES Multistage counters will not be fully synchronous since there is a

• Synchronous reversible 4-bit counting two-gate delay time difference added for each stage that is added.
• Asynchronous parallel load capability

The counter may be preset by the asynchronous parallel load
capability of the circuit. Information present on the parallel Data
• Asynchronous reset (clear) inputs (D0 - D3) is loaded into the counter and appears on the
outputs regardless of the conditions of the clock inputs when the
• Cascadable without external logic Parallel Load (PL) input is Low. A High level on the Master Reset
(MR) input will disable the parallel load gates, override both clock
inputs, and set all Q outputs Low. If one of the clock inputs is Low
DESCRIPTION
during and after a reset or load operation, the next Low-to-High
The 74F193 is a 4-bit synchronous up/down counter in the binary
transition of the clock will be interpreted as a legitimate signal and
mode. Separate up/down clocks, CPU and CPD respectively,
will be counted.
simplify operation. The outputs change state synchronously with the
Low-to-High transition of either clock input. If the CPU clock is
pulsed while CPD is held High, the device will count up. If CPD clock TYPICAL
is pulsed while CPU is held High, the device will count down. The TYPE TYPICAL fMAX SUPPLY CURRENT
device can be cleared at any time by the asynchronous reset pin. It (TOTAL)
may also be loaded in parallel by activating the asynchronous 74F193 125MHz 32mA
parallel load pin.
Inside the device are four master-slave JK flip-flops with the ORDERING INFORMATION
necessary steering logic to provide the asynchronous reset,
asynchronous preset, load, and synchronous count up and count COMMERCIAL RANGE
DESCRIPTION
VCC = 5V ±10%, Tamb = 0°C to +70°C
down functions.
Each flip-flop contains JK feedback from slave to master, such that a
Low-to-High transition on the CPD input will decrease the count by 16-pin plastic SO N74F193D
one, while a similar transition on the CPU input will advance the
count by one. PIN CONFIGURATION
One clock should be held High while counting with the other,
because the circuit will either count by twos or not at all, depending
on the state of the first JK flip-flop, which cannot toggle as long as D1 1 16 VCC
either clock input is Low. Applications requiring reversible operation Q1 2 15 D0
must make the reversing decision while the activating clock is High
Q0 3 14 MR
to avoid erroneous counts.
CPD 4 13 TCD
The Terminal Count Up (TCU) and Terminal Count Down (TCD)
outputs are normally High. When the circuit has reached the CPU 5 12 TCU
maximum count state of 15, the next High-to-Low transition of CPU Q2 6 11 PL
will cause TCU to go Low. TCU will stay Low until CPU goes High
again, duplicating the count up clock, although delayed by two gate Q3 7 10 D2
delays. Likewise, the TCD output will go Low when the circuit is in GND 8 9 D3
the zero state and the CPD goes Low. The TC outputs can be used
as the clock input signals to the next higher order circuit in a
SF00745
multistage counter, since they duplicate the clock waveforms.

74F(U.L.) LOAD VALUE
PINS DESCRIPTION
HIGH/LOW HIGH/LOW
D0 - D3 Data inputs 1.0/1.0 20µA/0.6mA
CPU Count up clock input (active rising edge) 1.0/3.0 20µA/1.8mA
CPD Count down clock input (active rising edge) 1.0/3.0 20µA/1.8mA
PL Asynchronous parallel load control input (active Low) 1.0/1.0 20µA/0.6mA
MR Asynchronous master reset input 1.0/1.0 20µA/0.6mA
Q0 - Q3 Flip-flop outputs 50/33 1.0mA/20mA
TCU Terminal count up (carry) output (active Low) 50/33 1.0mA/20mA
TCD Terminal count down (borrow) output (active Low) 50/33 1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
1995 Jul 17 1 853-0353 15459

15 1 10 9
11 C3 CTR DIV 16
5 2+ 12
1CT=15
D0 D1 D2 D3 G1
11 PL 4 13
1– 2CT=0
TCU 12
5 CPU G2
14
4 CPD TCD 13 R
14 MR
15 3
Q0 Q1 Q2 Q3 3D [1]
1 2
[2]
10 6
[4]
VCC = Pin 16 3 2 6 7 9 7
[8]
GND = Pin 8 SF00746
SF00747
STATE DIAGRAM
0 1 2 3 4
15 5
14 6
13 7
12 11 10 9 8
COUNT UP
COUNT DOWN
TCU = Q0 . Q1 . Q2 . Q3 . CPU
TCD = Q0 . Q1 . Q2 . Q3 . CPD
Logic Equations for Terminal Count

SF00748
1995 Jul 17 2
LOGIC DIAGRAM
D0 D1 D2 D3
15 1 10 9
11
PL
12
TCU
13
TCD
5
CPU
CPD 4
J CP K J CP J CP K J CP K
RD SD RD SD RD SD RD SD
Q Q Q Q Q Q Q Q
14
MR
3 2 6 7
Q0 Q1 Q1 Q1
VCC = Pin 16
GND = Pin 8 SF00749
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD MODE
H X X L X X X X L L L L H L Reset (clear)
H X X H X X X X L L L L H H
L L X L L L L L L L L L H L
L L X H L L L L L L L L H H Parallel load
L L L X H H H H H H H H L H
L L H X H H H H H H H H H H
L H ↑ H X X X X Count up H1 H Count up
L H H ↑ X X X X Count down H H2 Count down
H = High voltage level NOTES:
L = Low voltage level 1. TCU=CPU at terminal count up (HHHH)
X = Don’t care 2. TCD=CPD at terminal count down (LLLL)
1995 Jul 17 3
Timing Diagram (Typical clear, load, and count sequence)
CLEAR1 MR
PL
LOAD
D0
D1
DATA
D2
D3
COUNT UP2 CPU
COUNT DOWN2 CPD
Q0
Q1
OUTPUTS
Q2
Q3
TCU
TCD
0 13 14 15 0 1 2 1 0 15 14 13
SEQUENCE
COUNT UP COUNT DOWN
CLEAR PRESET
NOTES:
1. Clear overrides load, data, and count inputs.
2. When counting up, count-down input must be High; when counting down, count-up input must be High.
SF00756
Binary Counter
TEST CIRCUIT AND WAVEFORMS
VCC tw AMP (V)

90% 90%
NEGATIVE
VM VM
PULSE
10% 10%
VIN VOUT 0V
PULSE D.U.T.
GENERATOR tTHL (tf ) tTLH (tr )
RT CL RL tTLH (tr ) tTHL (tf )

AMP (V)
90% 90%
POSITIVE
PULSE VM VM
Test Circuit for Totem-Pole Outputs 10% 10%

tw 0V
DEFINITIONS: Input Pulse Definition

RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value. INPUT PULSE REQUIREMENTS
CL = Load capacitance includes jig and probe capacitance; family
see AC ELECTRICAL CHARACTERISTICS for value. amplitude VM rep. rate tw tTLH tTHL
RT = Termination resistance should be equal to ZOUT of
74F 3.0V 1.5V 1MHz 500ns 2.5ns 2.5ns
pulse generators.
SF00006
1995 Jul 17 7
Philips Semiconductors Advanced BiCMOS Products Product specification
Octal transceiver with direction pin, inverting 74ABT640

(3-State)
FEATURES • ESD protection exceeds 2000 V per bus compatible outputs in both send
• Octal bidirectional bus interface MIL STD 883 Method 3015 and 200 V and receive directions. The control
function implementation minimizes
• 3-State buffers per Machine Model
external timing requirements. The
• Power-up 3-State DESCRIPTION
device features an Output Enable (OE)
input for easy cascading and a Direction
• Live insertion/extraction permitted The 74ABT640 high-performance
(DIR) input for direction control.
• Output capability: +64mA/–32mA BiCMOS device combines low static
and dynamic power dissipation with high
• Latch-up protection exceeds 500mA speed and high output drive.
per Jedec JC40.2 Std 17
The 74ABT640 device is an octal
transceiver featuring inverting 3-State
QUICK REFERENCE DATA

CONDITIONS
SYMBOL PARAMETER TYPICAL UNIT
Tamb = 25°C; GND = 0V
tPLH Propagation delay

CL = 50pF; VCC = 5V 3.1 ns
tPHL An to Bn or Bn to An
Input capacitance
CIN VI = 0V or VCC 4 pF
DIR, OE
CI/O I/O capacitance Outputs disabled; VO = 0V or VCC 7 pF
ICCZ Total supply current Outputs disabled; VCC =5.5V 50 µA
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
20-pin plastic DIP –40°C to +85°C 74ABT640N 0408B
20-pin plastic SOL –40°C to +85°C 74ABT640D 0172D
20-pin plastic SSOP Type II –40°C to +85°C 74ABT640DB 1640A
PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC)

1
DIR 19
19 G3
OE
3 EN1 (BA)
2
A0 1
DIR 1 20 VCC 18 3 EN2 (AB)
B0
A0 2 19 3
OE A1
17 2 18
A1 3 18 B0 B1 1
4
A2 4 17 B1 A2
16 2
B2
A3 5 16 B2 5 3 17
A3
A4 6 15 B3 15
B3 4 16
7 14 6
A5 B4 A4
14 5 15
A6 8 13 B5 B4
7 6 14
A7 9 12 B6 A5
13
B5 7 13
GND 10 11 B7 8
A6
12 8 12
B6
9
A7 9 11
11
B7
June 21, 1993 1 853–1612 10082

Philips Semiconductors Advanced BiCMOS Products Product specification
Octal transceiver with direction pin, inverting 74ABT640

(3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 DIR Direction control input
2, 3, 4, 5,
A0 – A7 Data inputs/outputs (A side)
6, 7, 8, 9
18, 17, 16, 15,

B0 – B7 Data inputs/outputs (B side)
14, 13, 12, 11
19 OE Output enable input, B side to A side (active-Low)
10 GND Ground (0V)
20 VCC Positive supply voltage
FUNCTION TABLE
INPUTS INPUTS/OUTPUTS
OE DIR An Bn
L L Bn Inputs
L H Inputs An
H X Z Z

X = Don’t care
Z = High impedance ”off” state
ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
IIK DC input diode current VI < 0 –18 mA
VI DC input voltage3 –1.2 to +7.0 V
IOK DC output diode current VO < 0 –50 mA
VOUT DC output voltage3 output in Off or High state –0.5 to +5.5 V
IOUT DC output current output in Low state 128 mA
Tstg Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
June 21, 1993 2

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