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Mechatronics A Multidisciplinary Approach

Presentation · April 2018

DOI: 10.13140/RG.2.2.34349.38886

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 Mechatronics
A Multidisciplinary Approach
William Bolton

MCH 104
Dr.Eng. Abdullatif BABA 2017 - 2018
Remember Summing Amplifier (Lecture 2):

IA = VA/RA, IB = VB/RB and IC = VC/RC. Also

we must have the same current I passing
through the feedback resistor. The potential
difference across R2 is
As we already noted that : V  V
X out
But : VX  0
 Vout  I * R2
I I A  I B  I C
Vout VA VB VC
   
R2 RA RB RC
if ( RA  RB  RC  R1 )
R2
Vout   (VA  VB  VC )
R1
 Digital to Analog Conversion
S1 2S 2 4S3 8S 4
Vout   R2 (    )Vref
R R R R
S is a binary switch  1 or 0;
R2
If S1 = 1 , S2=S3=S4 = 0 ;
R2
Vout   Vref
R
If S1 =0, S2=1, S3=S4 = 0 ;
2 R2
Vout   Vref
R
If S1 = S2=1, S3=S4 = 0 ;
3R2
Vout   Vref And so on …….. Thus if R2=R; Vout = 0 ̴ 15 Vref
R
 Req1  (2 R // 2 R )  R
R-2R Binary Ladder DAC
Req 2  ( Req1 // 2 R )  R
Req1
RT  Req 3  Req 2 // 2 R
Iin V1 V2 V3
I I*
I1 I2 I3 Vref
I in 
RT
V1 Vref
I1  
2R 2R
I  I in  I1
V1  V2  IR  V2  V1  IR
V2
I2 
2R
I *  I  I2
V2  V3  I * R  V3  V2  I * R
 Rf
Vo  (V 1  V 2  V 3)
2R
R-2R Binary Ladder DAC
Example :

Iin V1 Req1
V2 V3
I I*
I1 I2 I3

Vref = 10 V, Rf = 10KΩ, R=10 KΩ

Find Vo if the input digital word is 1 1 0
R-2R Binary Ladder DAC
Req1  (20 // 20)  10  20 K
Example :
Req 2  (20 // 20)  10  20 K
RT  Req 3  20 // 20  10 K
10V
I in   1mA
10 K
V1 10
I1    0.5mA
2 R 20
I  I in  I1  0.5mA
V1  V2  IR  V2  V1  IR  10  0.5 10  5V
5
I2   0.25mA
20
I *  I  I 2  0.25mA
V2  V3  I * R  V3  V2  I * R  5  0.25 10  2.5V
 10
Vo  (10  5  0)  7.5V
20
R-2R Binary Ladder DAC
ZN558D

8-bit latched input DAC using a

R -2 R ladder network

A latch is just a device to retain

the output until a new one
replaces

Data is held in the latch when

ENABLE is high, the latch being
said to be transparent when
ENABLE is low

ZN558D (DAC)
Devices used in practical designs use integrated R-2R networks and transistor
switching. Ex : DAC 0800

8-bit high-speed current output

digital-analog converter.
Io
We need using the Op-amp to
convert the output to voltage

Example :
If the reference voltage is +10 Vdc
and the reference resistance is 5k.
The value of Rf = 2.5k
And the digital input is 10001101 8-bit binary code converted to 256 levels of Io
D = decimal equivalent of binary input
Example :

Io

Vref 10
I ref    2mA
Rref 5k
Convert the input to decimal value :
D  27 (1)  26 (0)  25 (0)  2 4 (0)  23 (1)  2 2 (1)  21 (0)  20 (1)
D  128  8  4  1  141
 D   141 
I o  I ref    2 mA   1.1016mA
 256   256 
Vo  ( I o ) R f  (1.1016mA * 2.5k)  2.76V
Analog to Digital Converters (ADCs)
Successive approximations

• A voltage is generated by a clock emitting a regular sequence of pulses which are counted,
in a binary manner.
• The resulting binary word converted into analog voltage by a DAC.
• This voltage rises in steps and is compared with the analogue input voltage from the
sensor. When the clock-generated voltage equals the input analogue voltage, the pulses from
the clock will be stopped because the gate is closed.
• The output from the counter at that time is a digital representation of the analogue voltage
Analog to Digital Converters (ADCs)
Ramp converter

Ramp incremental voltage

Time

• The ramp form of ADC involves an analogue voltage which is increased at a constant rate,
and applied to a comparator where it is compared with the analogue voltage from the sensor.
• When the ramp voltage starts, a gate is opened which starts a binary counter counting the
regular pulses from a clock.
• When the two voltages are equal, the gate closes and the word indicated by the counter is
the digital representation of the sampled analogue voltage.
Analog to Digital Converters (ADCs)
Dual Ramp converter

• The analogue voltage is applied to an integrator which drives a comparator.

• The output from the comparator goes high as soon as the integrator output is more than a few millivolts.
• When the comparator output is high, an AND gate passes pulses to a binary counter.
• The counter counts pulses until it overflows. The counter then resets to zero, sends a signal to a switch
which disconnects the unknown voltage and connects a reference voltage, and starts counting again.
• The polarity of the reference voltage is opposite to that of the input voltage.
• The integrator voltage then decreases at a rate proportional to the reference voltage.
• When the integrator output reaches zero, the comparator goes low, bringing the AND gate low and so
switching the clock off. The count is then a measure of the analogue input voltage.
If the comparator is supplied by V+ and V-

V+

V-
If the comparator is supplied by V+ and 0
V+

İf V1>V2
Or
İf V1 = V2
Output = 0
Analog to Digital Converters (ADCs) Reference Input
Flash Converter

Comparators are supplied by V+ and 0 +

-
Suppose the Reference input = 1V ¾

If 0 < analog input < ¼ +

-
Output 0 0 0 00 ½
If ¼ < analog input < ½
Output 0 0 1 01 +
-
If ½ < analog input < ¾ ¼
Output 0 1 1 10
If ¾ < analog input
Output 1 1 1 11

The flash ADC is very fast. For an n -bit converter, 2n -1 separate voltage comparators are used in
parallel, with each having the analogue input voltage as one input. A reference voltage is applied to
a ladder of resistors. Thus when the analogue voltage is applied to the ADC, all those comparators
for which the analogue voltage is greater than the reference voltage of a comparator will give a high
output and those for which it is less will be low. The resulting outputs are fed in parallel to a logic
gate system which translates them into a digital word.

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