A 65-Nm CMOS Constant Current Sourcewith Reduced PVT Variation

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A 65-nm CMOS Constant Current Sourcewith Reduced

PVT Variation
Abstract:
This paper presents a new nanometer-based low-power constant current reference that attains a
small value in the total process–voltage–temperature variation. The circuit architecture is based
on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias
voltage source for the dedicated temperature-compensated voltage to-current conversion in a pre
regulator loop. Fabricated in a UMC 65-nm CMOS process, it consumes 7.18µWwitha1.4V
supply. The measured results indicate that the current reference achieves an average temperature
coefficient of 119 ppm/°C over 12 samples in a temperature range from−30 °C to 90 °C without
any calibration. Besides, a low line sensitivity of 180 ppm/V is obtained. This paper offers a
better sensitivity figure of merit with respect to the reported representative counterparts.The
proposed architecture of this paper analysis the logic size, area and power consumption using
Tanner tool.
Existing System:
Oguey and Aebischer presented a self-biased topologyby means of biasing a triode-biased nMOS
transistor througha saturation-biased transistor in a circuit feedback loop forcurrent generation.
However, it has difficulty canceling thetemperature effect arising from the matching between
themobility temperature exponent and the mobility degradationfactor. Besides, the VTH
mismatch issue betweenthe tracking device pair will degrade the current accuracy.Due to the
topology, the current reference suffers from poorline sensitivity (10%/V). All of these non ideal
effects cause the accuracy of the reference current to deviate significantly from the process
variations (∼±30%). Alternatively,a low-voltage, low-power MOSFET-only self-biased
currentsource was reported. The temperature dependencecould reach as high as 2500 ppm/°C
over the operating range of −20 °C to 70 °C. To improve the temperaturecoefficient (T.C.),
suggested second-order temperaturecompensation. Since both the reference current and its
T.C.are process sensitive, unavoidable trimming is required topreserve the accuracy. Later,
Bendali and Audet showed areference circuit utilizing the zero T.C. point of the transistorto
generate a constant output current. This relies on thetemperature compensation concept using
mutual temperaturecompensation between the carrier mobility and the threshold voltage.
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Following a similar technique, Uenoet al. realized the current reference with an improved T.C.
of46 ppm/°C. Although a low line sensitivity is achieved,it may not be adequate if the circuit is
designed usingnanometer technology. At this juncture, the output current,which is obtained from
the saturation-based transistor to serve as a VI converter, is sensitive to the offset of the
drivingop-amp, thus increasing the process sensitivity. In anotherdesign, a current reference was
generated by means ofa constant overdrive voltage. However, the line sensitivitybecomes a
major concern because the supply voltage needsto be well controlled. Turning to the current
summing design technique, the power consumption is generally highbecause of the circuit’s
complexity. Although the floating-gatetransistor-based current reference offers a precise
current,it is expensive in the trimming method. The same is true of thelow T.C. current reference,
which depends upon a low T.Cprecision-trimmed voltage reference at the expense of
drawingextra power. It is of particular note that these reported designsare implemented using
0.18-μm CMOS technology or above.As the technology is further scaled down to sub100 nm,the
performance of current references will be degraded bythe process–voltage–temperature (PVT)
variations. This stemsfrom the fact that the process variations arising from thelithography
imperfections and uncontrollable factors such asrandom dopant fluctuations, the well proximity
effect,and layout-dependent stress variation impose challenges for robust circuit designs. In
addition, the MOStransistors suffer from a high current leakage level.The temperature-
fluctuation-induced variation in the carriermobility becomes significantly higher for MOSFET
devices inthe exemplary 65-nm CMOS technology than in the 0.18-μm technology. Finally, the
short-channel effect (SCE) contributes another factor that limits the circuit performance
inadvanced nanometer technology. In brief, the lower thechannel length in a technology, the
more difficult it is toachieve a stable reference design because of the relativelypoor output
characteristic of long channel transistors comparedwith those with higher channel lengths in
technologies. As aconsequence, the design in a 65-nm process turns out to bemore challenging
than that in other processes (>65 nm) evenwhen transistors with larger than the minimum size
are used.
Disadvantages:
 Sensitivity is low
Proposed System:

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Table I summarizes the acronyms and nomenclature adoptedin this paper. The constant current
generation is devisedfrom a process-tolerant temperature-compensatedVIconverter.It aims at
establishing a constantVTH0reference compensationvoltage having a first-order T.C. with
reduced process sensitivity in series with another auxiliary compensation voltagehaving a
second-order T.C. with low process sensitivity. Thecombined temperature characteristic will
match the corresponding linear T.C. and nonlinear T.C. of the integratedresistor in the
VIconverter. The outcome leads to a constantcurrent reference with reduced PVT variation. The
operationprinciple of this proposed circuit is illustrated in Fig. 1.
Figure 1: Operation principle of the proposedIREFcircuit with the temperature characteristic of

(a)VGS(T),(b)VAux_Comp(T),(c)VR_Comp(T),(d)RO(T), and (e)IREF
A process-tolerant bias current (IPTol) and a process tracking voltage (VPTrack) are generated
through the IPTol and VPTrack bias circuits in self-biasing topology. When a scaled IPTol is
injected into a MOSFET transistor,it will generate a gate–source voltage VGS(T) with a
firstorder negative T.C., as shown in Fig. 1(a). Fig. 1(c) depictsthe target reference compensation

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voltage VR_Comp(T) that is formed by summing the nonlinear auxiliary compensation voltage
VAux_Comp(T) in Fig. 1(b) with the gate–sourcevoltage VGS(T). On the other hand,
VAux_Comp(T) is synthesized from the current-to-voltage (IV) conversion in which the scaled
IPTol is passed to an active resistor. Theresistor realization is based on a scaled VP Track to bias
the gate of the triode transistor. Since VR_Comp(T) exhibits a similar T.C. to the sense resistor
RO(T)with the temperaturecharacteristic shown in Fig. 1(d), the final output currentIREFcan be
made temperature independent over the operatingtemperature range as illustrated in Fig. 1(e).
Implementation ofproposedcurrentreference:
The current reference depicted in Fig. 2 consists of a pre regulator, a process-tolerant current bias
circuit withan embedded process-tracking voltage bias circuit, and atemperature-compensated VI
converter. For simplicity, the capacitive startup circuit and the biasing circuit are notshown. The
pre regulator loop, which has been reported ina nanometer-based MOSFETVTHmeasurement
circuit,is used to provide good line sensitivity. Referring to Fig. 2,when the op-amp is employed
in the bias current circuit,the drain voltages at nodes N1 and N2 are close to eachother. This
establishes identical currents flowing throughM1 and M2, which are biased in the subthreshold
region.On the other hand,MR1 operates in the triode region as anactive resistor. It is self-biased
by VPTrack, which is generated from M8 in the saturation region. This turns out to be aprocess-
tolerant active resistor RMR1. As such, the current IPTol flowing throughM1 orM2 becomes
process tolerant.

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Figure 2: Schematic of the proposed constant current reference circuit.
Advantages:
 Sensitivity is high
Software implementation:
 Tanner tool

A 65-Nm CMOS Constant Current Sourcewith Reduced PVT Variation

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LeMeniz Infotech

36, 100 Feet Road, Natesan Nagar, Near Indira

Call: 0413-4205444, +91 9566355386, 99625 88976.