COMSATS UNIVERSITY ISLAMABAD, ABBOTTABAD CAMPUS

Department of Electrical Engineering

Lab Sessional 1 – FA18

Class: BEE 7A
Subject: DSD Time: 40 min
Name: __________________ Registration#:_________________

Course Learning
CLOs CLOs PLOs Level %age
Outcomes
Complete knowledge of
Engineering Practice
basic engineering
CLO-1 (Punctuality/body PLO-1 A5 20%
subjects and
language)
prerequisite courses
Draw and label circuit
CLO-12 Programming diagrams and develop PLO-5 P4 60%
code and verify results.

Analysis and logical

CLO-23 Analysis and Logical development of logic
PLO-2 C6 20%
Development gates in Digital System
Design
Task 1:

Psychomotor

Design an 8 bit adder. Such that its design is based on |Carry Look Ahead adder approach. Write Verilog
code for the design and verify the design.

Cognitive

1. Estimate the area in terms of gates.

2. Estimate the DELAY of the ADDER in terms of gates.

Task 2:

Psychomotor

Design an 8 bit adder. Such that its design is based on Carry Select Adder approach. Write Verilog code
for the design and verify the design.

Cognitive

1. Estimate the area in terms of gates.

2. Estimate the DELAY of the ADDER in terms of gates.

Note: - Your performance will be evaluated as per CLOs mentioned above.

 COMSATS UNIVERSITY ISLAMABAD, ABBOTTABAD CAMPUS

Department of Electrical Engineering

Lab Sessional 1 – FA18

Class: BEE 7B
Subject: DSD Time: 40 min
Name: __________________ Registration#:_________________

Course Learning
CLOs CLOs PLOs Level %age
Outcomes
Complete knowledge of
Engineering Practice
basic engineering
CLO-1 (Punctuality/body PLO-1 A5 20%
subjects and
language)
prerequisite courses
Draw and label circuit
CLO-12 Programming diagrams and develop PLO-5 P4 60%
code and verify results.

Analysis and logical

CLO-23 Analysis and Logical development of logic
PLO-2 C6 20%
Development gates in Digital System
Design
Task 1:

Psychomotor

Design a 12 bit adder. Such that its design is based on Carry Select adder approach. Write Verilog code
for the design and verify the design.

Cognitive

3. Estimate the area in terms of gates.

4. Estimate the DELAY of the ADDER in terms of gates.

Task 2:

Psychomotor

Design an 8 bit adder. Such that its design is based on Conditional Sum Adder approach. Write Verilog
code for the design and verify the design.

Cognitive

3. Estimate the area in terms of gates.

4. Estimate the DELAY of the ADDER in terms of gates.

Note: - Your performance will be evaluated as per CLOs mentioned above.