Sie sind auf Seite 1von 6

Agni College of Technology

Lesson Plan - Including Coaching class

Semester : Third Name of The Faculty : R. Ohmsakthi Vel


Branch : Mechatronics Engineering Date of commencement : 18.06.2018
Subject : Digital Electronics Date of closing : 29.09.2018
Sub. Code : EC8392 Class strength : 34
Section : - No. of hours/week : 5
Total hours : 91
Course objectives:
 To present the Digital fundamentals, Boolean algebra and its applications in digital systems
 To familiarize with the design of various combinational digital circuits using logic gates
 To introduce the analysis and design procedures for synchronous and asynchronous sequential circuits
 To explain the various semiconductor memories and related technology
 To introduce the electronic circuits involved in the making of logic gates

Assignments Text Delivered


Unit Topics planned for the Teaching (A)/Tests(T) Book as planned
S. No Date Period(s) (* to be filled
No period(s) Aids planned for No/ Ref
after the
the Topic book No class)

Introduction to Digital Chalk &


1 I 18.06.2018 1 T1
logics and circuits Board
Number Systems: Decimal, Chalk &
2 I 18.06.2018 9 A1 T1
Binary, Octal, Hexadecimal Board
Number systems and Code
3 I 19.06.2018 3,4 Coaching Class
conversions
Chalk &
4 I 19.06.2018 5 Code Conversions T1
Board
Chalk &
5 I 21.06.2018 6 1‘s and 2‘s complements T1
Board
Codes: Binary, BCD, Excess
Chalk &
6 I 22.06.2018 3 3, Gray, Alphanumeric T1
Board
codes
Chalk &
7 I 25.06.2018 1 Boolean theorems A2 T1
Board
Logic gates, Universal Chalk &
8 I 25.06.2018 9 T1
gates Board
Logic gates and Boolean
9 I 26.06.2018 3,4 Coaching Class
theorem
Sum of products and Chalk &
10 I 26.06.2018 5 T1 T1
Product of sums Board
Chalk &
9 I 28.06.2018 6 Minterms and Maxterms T1
Board
Minimization based on Chalk &
10 I 29.06.2018 3 T2 T1
Karnaugh map Board
Minimization based on Chalk &
11 I 02.07.2018 1 T1
Karnaugh map Board
Quine-McCluskey method Chalk &
12 I 02.07.2018 9 T3 T1
of minimization. Board
K-Map & Quine-McCluskey
13 I 03.07.2018 3,4 Coaching Class
method of minimization
Total periods for Unit 1 = 12 periods regular + 6 periods Coaching class
Design of Half and Full Chalk &
14 II 03.07.2018 5 T1
Adders Board
Design of Half and Full Chalk &
15 II 05.07.2018 6 T1
Subtractors Board
Design of Binary Parallel Chalk &
16 II 06.07.2018 3 A3 T1
Adder Board
Chalk &
17 II 09.07.2018 1 Design of BCD Adder T1
Board
Design of Carry look ahead Chalk &
18 II 09.07.2018 9 T1
Adder Board

19 II 10.07.2018 3,4 Adder & Subtractors Coaching Class

Multiplexer, Demultiplexer Chalk &


20 II 10.07.2018 5 T4 T1
and design procedure Board
Design of Magnitude Chalk &
21 II 12.07.2018 6 T1
Comparator Board
Decoder and Design based Chalk &
22 II 13.07.2018 3 T5 T1
on decoder Board
Encoder and Design based Chalk &
23 II 23.07.2018 1 T1
on encoder Board
Chalk &
24 II 23.07.2018 9 Design of Priority Encoder. A4 T1
Board
Design using Decoders,
25 II 24.07.2018 3,4 Encoders, Multiplexer and Coaching Class
Demultiplexer
Total periods for Unit 2 = 10 periods regular + 4 periods Coaching class
Operation and excitation
Chalk &
26 III 24.07.2018 5 tables, Triggering of SR and A5 T1
Board
JK Flip-Flops
Operation and excitation
Chalk &
27 III 26.07.2018 6 tables, Triggering of T and D T1
Board
Flip-Flops
Chalk &
28 III 27.07.2018 3 Master Slave Flip-flops A6 T1
Board
Analysis and design of Chalk &
29 III 28.07.2018 6 T1
clocked sequential circuits Board
Design - Moore/Mealy Chalk &
30 III 30.07.2018 1 T6 T1
models Board
Chalk &
31 III 30.07.2018 9 State minimization T1
Board

32 III 31.07.2018 3,4 Flipflop conversion Coaching Class

Chalk &
33 III 31.07.2018 5 State assignment T1
Board
Circuit implementation Chalk &
34 III 02.08.2018 6 T7 T1
using flipflops Board
Chalk &
35 III 03.08.2018 3 Design of Counters T8 T1
Board
Chalk &
36 III 06.08.2018 1 Ripple Counters T1
Board
Chalk &
37 III 06.08.2018 9 Ring Counters T1
Board

38 III 07.08.2018 3,4 Design of Counters Coaching Class

Shift registers, Universal Chalk &


39 III 07.08.2018 5 T1
Shift Register. Board
Total periods for Unit 3 = 12 periods regular + 4 periods Coaching class
Chalk &
40 IV 09.08.2018 6 Stable and Unstable states A7 T1
Board
Chalk &
41 IV 10.08.2018 3 Output specifications T1
Board
Chalk &
42 IV 11.08.2018 3 Cycles and races T1
Board
Chalk &
43 IV 13.08.2018 1 State reduction T1
Board
Chalk &
44 IV 13.08.2018 9 Race free assignments T1
Board
State Diagram and
45 IV 14.08.2018 3,4 Coaching Class
Reduction
Chalk &
46 IV 14.08.2018 5 Hazards, Essential Hazards A8 T1
Board
Chalk &
47 IV 16.08.2018 6 Pulse mode T1
Board
Chalk &
48 IV 17.08.2018 3 Sequential circuits T1
Board
Design of Asynchronous Chalk &
49 IV 18.08.2018 3 T9 T1
sequential circuits Board
Design of Asynchronous Chalk &
50 IV 20.08.2018 1 T1
sequential circuits Board
Design of Hazard free Chalk &
51 IV 20.08.2018 9 T10 T1
circuits. Board
Design of Asynchronous
52 IV 21.08.2018 5 Coaching Class
sequential circuits
Total periods for Unit 4 = 11 periods regular + 4 periods Coaching class
Basic memory structure:
53 V 21.08.2018 5 PPT T1
ROM, PROM, EPROM
54 V 30.08.2018 6 EEPROM, EAPROM PPT A9 T1
RAM : Static and dynamic
55 V 31.08.2018 3 PPT T1
RAM
Programmable Logic
56 V 03.09.2018 1 PPT T1
Devices: PLA, PAL
Field Programmable Gate
57 V 03.09.2018 9 PPT T1
Arrays (FPGA)
58 V 04.09.2018 3,4 Memory Structure Coaching Class
Implementation of
Chalk &
59 V 04.09.2018 5 combinational logic circuits T11 T1
Board
using PLA.
Implementation of
Chalk &
60 V 06.09.2018 6 combinational logic circuits T1
Board
using PAL.
Digital integrated circuits:
Chalk &
61 V 07.09.2018 3 Logic levels, propagation T1
Board
delay
Power dissipation, fan-out Chalk &
62 V 08.09.2018 6 T1
and fan-in, noise margin Board
Logic families and their Chalk &
63 V 10.09.2018 1 T1
characteristics Board
64 V 10.09.2018 9 RTL, TTL PPT T12 T1
Design a logic circuit using
65 V 11.09.2018 3,4 Coaching Class
PLDs
66 V 11.09.2018 5 ECL, CMOS PPT A10 T1
Total periods for Unit 5 = 12 periods regular + 4 periods Coaching class
Coaching Class ( K-Map
68 I 17.09.2018 1
Minimization)
Coaching Class ( Quine
69 I 17.09.2018 9
McClauskey method)
Coaching Class
70 II 18.09.2018 5 (Combinational circuit
design)
Coaching Class ( Design
71 II 20.09.2018 6
based logic devices)
Coaching Class (Flip-Flop
72 III 21.09.2018 3
conversion)
Coaching Class (Design of
73 III 22.09.2018 5
sequential circuit)
Coaching Class (Design of
74 IV 24.09.2018 1
Asynchronous circuits)
Coaching Class (design of
75 IV 24.09.2018 9
hazard free circuit)
Coaching Class (Memory
76 V 25.09.2018 5
structure)
Coaching Class (Design
77 V 27.092018 6
based on PLA, PAL, FPGA)
University Question paper
78 28.09.2018 3
discussion and revision
University Question paper
79 29.09.2018 6
discussion and revision
Total periods for five units ( Regular) 69
Total periods for five units ( Coaching class) 22
Total periods 91

Text Books:
1 M. Morris Mano and Michael D. Ciletti, “Digital Design”, 5th Edition, Pearson, 2014.

Reference Books:
1 Charles H.Roth. “Fundamentals of Logic Design”, 6th Edition, Thomson Learning, 2013.
2 Thomas L. Floyd, “Digital Fundamentals”, 10th Edition, Pearson Education Inc, 2011
3 S. Salivahanan and S.Arivazhagan “Digital Electronics”, Ist Edition, Vikas Publishing House pvt Ltd, 2012.
4 Anil K.Maini “Digital Electronics”, Wiley, 2014.
5 A. Anand Kumar “Fundamentals of Digital Circuits”, 4th Edition, PHI Learning Private

Course Outcomes:
At the end of the course:
 Use digital electronics in the present contemporary world
 Design various combinational digital circuits using logic gates
 Do the analysis and design procedures for synchronous and asynchronous sequential circuits
 Use the semiconductor memories and related technology
 Use electronic circuits involved in the design of logic gates
NPTEL Videos Used:

http://nptel.ac.in/courses/117103064/
http://nptel.ac.in/courses/117106086/
http://nptel.ac.in/courses/117106114/
http://nptel.ac.in/courses/108105113/

Specific Instructions to the students


This subject is mainly to expose the students to Digital principles and digital system design
as it is an inseparable part of all the applications in modern Mechatronics system. So students
must give proper attention in the class, and the internal assessment tests. This subject will
give them an opportunity to learn about basics of Digital logic circuits, various design aspects in
circuit design. The students are strongly advised to s u b m i t t h e a s s i g n m e n t s i n t i m e
a n d take the tests conducted in the class very seriously. This will not only ensure catching up
with the subject closely as it progresses but will also help the students to secure good
marks in the internal assessment as well as university examination.

Staff Incharge HOD/Mechatronics