Spartan - 6 Project Card: User Manual

SPARTAN – 6 PROJECT CARD
(Model No : VPTB - 16)
User Manual
Version 1.0
Technical Clarification /Suggestion :

✍/☎
Technical Support Division,
Vi Microsystems Pvt. Ltd.,
Plot No :75, Electronics Estate,
Perungudi, Chennai - 600 096, INDIA.
Ph: 91- 44-2496 1842, 91-44-2496 1852
Mail : rnd@vimicrosystems.com
Web : www.vimicrosystem.com
01/12/09/10
CONTENTS
CHAPTER-1 INTRODUCTION 1
CHAPTER- 2 CLOCK SOURCE 3
CHAPTER – 3 SWITCHES & LEDS 4
CHAPTER – 4 LCD DISPLAY 6
CHAPTER – 5 SEVEN SEGMENT DISPLAY 7
CHAPTER – 6 20 PIN HEADER 8
CHAPTER – 7 RTC (REAL TIME CLOCK) 9
CHAPTER – 8 ADC & DAC 11
CHAPTER – 9 BUZZER & RELAY 15
CHAPTER – 10 PROCEDURE TO WORK IN XILINX SOFTWARE 16

SPARTAN – 6 PROJECT CARD VPTB - 16
CHAPTER – 1
INTRODUCTION
The Vi Microsystems Xilinx Spartan-6 FPGA Project Card is a demonstration platform

intended for you to become familiar with the new features and availability of the Spartan-6
FPGA family. This Project Card provides a low-cost, easy to development and evaluation
platform for Spartan-6 FPGA designs.
KEY COMPONENTS AND FEATURES
Figure-A shows the Spartan-6 Low Cost board block diagram, which includes the
following components and features:
 Xilinx Spartan 6 - XC6SLX4, TQ144-2C Package Spartan 6

 3840 equivalent logic cells.
 75kB Max Distributed RAM.
 Twelve 18kB RAM blocks (216).
 8 no’s DSP48A1 slices.
 2 Clock Management Tiles.
 Interfaces
 JTAG programming & configuration port.
 USB to JTAG.
 On Board Flash PROM XCF04S.
 8 input 3pin slide switches.
 8 output Light Emitting Diodes (LED’s).
 4 user push button switches and 2x2 matrix key.
 One RESET push button switch.
 Four digit seven segment display.
 One 16x2 LCD display.
 One Five pin relay with 3 pin connector.
 One Two pin small size buzzer.
Vi Microsystems Pvt. Ltd., [1]

 Eight pin RTC IC (DS1340) with external battery backup.
 One single channel 12 bit SPI high speed ADC (ADC121S101) with i/p range 0 to 5V.
 One single channel 12 bit SPI high speed DAC (DAC121S101) with o/p range 0 to 5V.
BLOCK DIAGRAM

CHAPTER 2
CLOCK SOURCE
Spartan-6 FPGA works in different clock frequencies. But in Spartan 6 Project card we use only
20MHz fixed Oscillator settings (On-Board Clock Fixed), we may change the clock frequency in
program by using clock divider procedure.
Clock connection with FPGA
SCHEMATIC NAME FPGA PIN

CLK P56
Default Factory settings = 20 Mhz

CHAPTER-3
SWITCHES AND LEDs
3.1 Power Switch
The Spartan-6 Project Card has a slide power switch. Moving the power switch Up for
Power ON and down for power OFF (SW1).
3.2. Reset Switch
The Spartan 6 Project Card has a push button switch (named as RESET) which can be
configured as input by assigning the corresponding FPGA pin location.
Name FPGA
Reset(SW2) P37
3.3 Input Switches

There 8 input slide switches are available in Spartan6 Project Card.
Name SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P101 P102 P104 P105 P111 P112 P114 P115
3.4 Push Button Switches
The SPARTAN-6 Project Card board has 8 push button switches. These 8 push buttons
switches are used for giving inputs externally from the user. SWITCH3, SWITCH4, SWITCH5,
SWITCH6 has one side connected to ground and the other side connected to a pin on the
Spartan- 6 device via a 4.7K current limiting resistor. The other end of this resistor is connected
to 3.3V supply.
The other 4 switches are connected as matrix push buttons. These are 2x2 matrix keys.
SWITCH 7, SWITCH 8, SWITCH 17, SWITCH 18 are pull up to 3.3V via 4.7K resistor.

PIN Details for Normal push buttons:
Name Push 1(SW4) Push2(SW5) Push3(SW6) Push4(SW7)
FPGA Pin P124 P116 P117 P123
PIN Details for Matrix key:
Name A(0) A(1) B(0 B(1)

FPGA Pin P120 P119 P118 P121
3.5 Output LEDS
The Spartan-6 Project Card board has eight individual surface-mount LEDs located
immediately right to the slide switches. The LEDs are labeled L4 throughL11 (left to right).
Each LED has one side connected to ground and the other side connected to a pin on the
Spartan- 6 device via a 270E current limiting resistor. To light an individual LED, drive the
associated FPGA control signal High.
FPGA PIN Details
Name LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8

(L4) (L5) (L6) (L7) (L8) (L9) (L10) (L11)
FPGA Pin P126 P127 P131 P132 P133 P134 P137 P138
3.6 PROM LED
PROM led is presented near to the PROM switch, and it is noted as L2 in Spartan-6
FPGA Project Card. when the program is downloaded in to the Project Card, PROM led is in
OFF state. After the downloading of program, the PROM led will blink (ON). This LED
indication is helpful to you to know about the status of downloading of program in to the Project
Card.

CHAPTER-4
LCD DISPLAY
Once mastered, the LCD is a practical way to display a variety of information using
standard ASCII and custom characters. However, these displays are not fast. Scrolling the
display at half-second intervals tests the practical limit for clarity.
LCD Connections with FPGA

LCD D0 D1 D2 D3 D4 D5 D6 D7 RS CS
FPGA Pin P81 P80 P79 P78 P75 P74 P60 P69 P83 P82
The character LCD is power by +5V. The FPGA I/O signals are powered by
3.3V.However; the LCD recognizes the FPGAs output levels as valid Low or High logic levels.
The LCD controller accepts 5V TTL signal levels and the 3.3V LVC MOS outputs provided by
the FPGA meet the 5V TTL voltage level requirements.
The 390ohm series resistors on the data lines prevent over stressing on the FPGA and
Strata Flash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD R/W is High. Most applications treat the LCD as a write only
peripheral and never read from the display and hence in this trainer the R/W pin is grounded by
default.
There are 8 LCD data bits are used and they are represented form LCDD0 to LCDD7. To
select a register and chip for operation, Register Select (RS) and Chip Select (CS) signals are
used for this purpose, to display the character in the LCD. We are using 16 × 2 LCD display, you
have to enable the each line in the LCD display follow the below instructions. (Initialization)
1st line enable  X “80”
2nd line enable  X “C0”
Function set  X “38”
To clear the display  X “01”
Character blinking  X “0F”
Entry mode set  X “06”

CHAPTER-5
SEVEN SEGMENT DISPLAY
There are four seven segment display are placed in Spartan 6 Project Card. Each display
was selected by the select line connected to its corresponding FPGA pin. For that four BC558
(PNP) transistors are used to select individual display. The segment in display is connected to the
FPGA pin via 120 ohm resistor.
FPGA PIN DETAILS
Individual display DISP1 DISP2 DISP3 DISP4

FPGA pin(select line) DISP4 DISP3 DISP2 DISP1
Segment SEGA SEGB SEGC SEGD SEGE SEGF SEGH SEGDP

FPGA pin P94 P95 P98 P99 P100 P93 P92 P97

CHAPTER-6
20 PIN HEADER
There are two 20 pin headers are used for connecting boards externally and for many
applications. By using these connectors we can connect external peripherals into the FPGA kit.
FPGA PIN DETAILS
CONNECTOR SCHEMATIC NAME FPGA PIN

1 VCC (5V) -
2 IO1 P38
3 IO2 P40
4 IO3 P41
5 IO4 P43
6 IO5 P44
7 IO6 P45
8 IO7 P46
9 IO8 P47
10 IO9 P48
11 IO10 P51
12 IO11 P57
13 IO12 P58
14 IO13 P59
15 IO14 P61
16 IO15 P62
17 IO16 P64
18 IO17 P66
19 IO18 P67
20 GND -

CHAPTER-7
RTC (REAL TIME CLOCK)
Spartan 6 project card has one RTC (Real Time Clock) IC DS1340 in its onboard. It’s a
2-wire 8pin RTC IC, uses a low-cost 32.768 kHz crystal, it tracks time using several internal
registers. The clock/calendar automatically adjusts for months with fewer than 31 days, including
corrections for leap years. Each pin function and FPGA connections is given below.
PIN NAME FUNCTION FPGA PIN

1 X1 X1 is the input to the oscillator -
2 X2 X1 is the output to the oscillator -
3 VBACKUP Connection for a Secondary Power Supply. For the -
1.8V and 3V devices, VBACKUP must be held
between 1.3V and 3.7V for proper operation.
VBACKUP can be as high as 5.5V on the 3.3V
device. This pin can be connected to a primary cell
such as a lithium coin cell.
4 GND Ground -
5 SDA Serial Data Input/output. SDA is the data input/output P142
for the 2-wire serial interface. The SDA pin is open
drain and requires an external pull-up resistor.
6 SCL Serial Clock Input. SCL is the clock input for the 2- P143
wire interface and is used to synchronize data
movement on the serial interface.
7 FT/OUT Frequency Test/Output. This pin is used to output P141
either a 512Hz signal or the value of the OUT bit.
When the FT bit is logic 1, the FT/OUT pin toggles at
a 512Hz rate. When the FT bit is logic 0, the
FT/OUT pin reflects the value of the OUT bit.
8 VCC DC Power for Primary Power Supply (3.3V). -
0x07 is the control register to control the data transfer.

DATA TRANSFER SEQUENCE ON THE SERIAL BUS
The RTCC registers are contained in addresses 0x00h-0x06h.

0x00 register contains the time format seconds data, it have BCD ones (bit 0 to 3) and
tens (bit 4 to 6).
0x01 register have time format minutes data in the order of BCD ones (bit 0 to 3) and
tens (bit 4 to 6).
0x02 register have time format hour data, is situated as BCD ones (bit 0 to 3) and tens
(bit 4 to 5).
0x03 register for day.
0x04 register for date, have BCD ones in bit 0 to 3 and tens in bit 4 to 5.
0x05 register for month, have BCD ones in bit 0 to 3 and tens in bit 4.
0x06 register for year, have BCD ones in bit 0 to 3 and tens in bit 4 to 7. Corrections
include for leap year also.
Vi Microsystems Pvt. Ltd., [ 10 ]

CHAPTER-8
ADC & DAC
ADC
Spartan 6 Project Card has one SPI-compatible, single channel Analog to Digital
Converter (ADC) by using AD121S101 IC. It is a single channel, 12 bit, low power, high speed,
and single power supply with 2.7V - 5.25V range, successive approximation, serial interface IC.
And it is a 6 pin IC.
In IC 1st pin (VA) is connected to +3.3V supply and bypassed with 0.1uF capacitor.
2nd pin (GND) is directly connected to ground.
3rd pin (Vin) is a analog input, it ranges from 0V to VA.
4th pin (SCLK) is a serial digital clock input to the ADC IC. This controls the conversion
and readout processes.
5th pin (SDATA) is a serial digital data output.
6th pin (CS bar) is a chip select pin. When it is low then only the ADC conversion process
will start.
There are 16 sclk cycles are required to complete the conversion processs. And two
modes of operations (hold mode, track mode) for single conversion process. The device will
move from hold mode track mode at the 13th rising edge of sclk. When in track mode the
minimum amount of voltage will flow on the LSB bits. This will given in the below timing
diagram.
CS is chip select, which initiates conversions on the ADC and frames the serial data
transfers. SCLK (serial clock) controls both the conversion process and the timing
of serial data. Basic operation of the ADC begins with CS going low, which initiates
a conversion process and data transfer. Subsequent rising and falling edges of
SCLK will be labeled with reference to the falling edge of CS; for example,
"the third falling edge of SCLK" shall refer to the third falling edge of SCLK after
CS goes low.

At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter
moves from track mode to hold mode. The input signal is sampled and held for
conversion on the falling edge of CS. The converter moves from hold mode to track mode
on the 13th rising edge of SCLK. The SDATA pin will be placed back
into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS,
whichever occurs first. After a conversion is completed, CS low again to begin
another conversion.
Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample
bits (including leading zeroes) are clocked out on falling edges of SCLK, and are intended to
be clocked in by a receiver on subsequent falling edges of SCLK. The ADC will produce
three leading zero bits on SDATA, followed by twelve data bits, most significant first.
If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be
captured by the next falling edge of SCLK.
FPGA Pin Connections
ADC PIN ADC CS BAR ADC SDATA ADC SCLK

FPGA PIN P7 P8 P9

DAC
Spartan 6 Project Card has one SPI-compatible, single channel Digital to Analog
Converter (DAC) by using DAC121S101 IC. It is a single channel, 12 bit, low power, high
speed, and power supply with the range of 2.7V - 5.25V, serial interface IC. And it is a 6 pin IC.
In IC 1st pin (DACOUT) is a DAC output pin.

2nd pin (GND) is directly connected to ground.
3rd pin (VIN) is connected to +3.3V supply and bypassed with 0.1uF capacitor.
4th pin (DACIN) is serial Data Input. Data is clocked into the 16-bit shift register on the
falling edges of SCLK after the fall of SYNC.
5th pin (DAC SCLK) is serial Clock Input. Data is clocked into the input shift register on
the falling edges of this pin.
6th pin (SYNC bar) is frame synchronization input for the data input. When this pin goes
low, it enables the input shift register and data is transferred on the falling edges of SCLK.
Input shift register has sixteen bits. The first two bits are "don't cares" and are followed
by two bits that determine the mode of operation (normal mode or one of three power-down
modes). The contents of the serial input register are transferred to the DAC register on the
sixteenth falling edge of SCLK. Normally, the SYNC line is kept low for at least 16
falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge.
However, if SYNC is brought high before the 16th falling edge, the shift register is reset
and the write sequence is invalid. The DAC register is not updated and there is no change
in the mode of operation or in the output voltage.

FPGA PIN CONNECTIONS
DAC PIN DAC CS Bar (SYNC) DAC SCLK DAC IN

FPGA PIN P2 P5 P6

CHAPTER-9
BUZZER & RELAY
BUZZER
5V small size 2 pin buzzer is placed in Spartan 6 Project Card. Its one pin is connected to
5V supply. And the other pin is connected to the collector end of the transistor (BC547). The
transistors base is connected to the FPGA pin via 220ohm resistor. This buzzer is used in many
applications, to indicate the final result is achieved by the beep sound.
FPGA CONNECTIONS
BUZZER PIN BUZZER

FPGA PIN P140
RELAY
5V small size 5 pin relay is used in Spartan 6 Project Card. The pins are NC (normally
closed), NO (normally opened), COM, C1, C2 (coil ends). C1 is connected to cathode of the
diode (IN4001) and also connected to 5V supply. C2 is connected to anode of the diode and also
connected to collector of transistor (SL100). And the base of the transistor is connected to FPGA
pin via 1K resistor, also connected to 5V supply via 10K resistor and connected to ground via
10K resistor. When current is passing to the coil it produces the magnetic field, because of this
the switch is closed depending upon the requirement (NC or NO). COM, NC, NO pins are
connected to the P7 connector. Thus we can use the relay output for the other application.
FPGA CONNECTIONS
RELAY PIN RELAY

FPGA PIN P1

CHAPTER-10
PROCEDURE TO WORK IN XILINX SOFTWARE
1. After installing Xilinx software, go to Start Menu  Programs  Xilinx ISE 12.1
ISE Design toolsProject Navigator (refer Figure-1).
A Window shown in Figure-2 will appear.
Figure-1

Figure-2

2. Select File  New Project
Figure-3

3. A window given in Figure-4 will appear. In the project name field, give your project
Name and select the location where you want to save the project (refer Figure-5). In the
Top-Level Module selects HDL and click Next.
Figure-4

Figure-5
4. A window given in Figure-6 will appear.
In the Device and Design flow for the project, select
Product category  All
Family  Spartan6
Device  XC6SLX4
Package  TQ144
Speed  -2
Synthesis Tool  XST (VHDL / Verilog)
Simulator  ISE Simulator (VHDL / Verilog)
Preferred Language  VHDL
Then click "Next" and "Finish" (refer Figure-6, 7).

Figure-6

Figure-7

5. A Window given in Figure-8 will appear. Select Project New source, a window given
in Figure-9,10 will appear. Then select VHDL module, and specify the file name in appropriate
field(refer Figure-11). Click Next, then if you want you can give inputs & outputs in the
appropriate positions as then in the Figure - 12. You can also skip these information by simply
clicking Next button and click Finish (refer Figure - 13).
Figure-8

Figure-9

Figure-10

Figure-11

Figure-12

Figure-13

6. A window given in Figure-14 will appear. You can type another library functions
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; under the library function
useIEEE.STD_LOGIC_1164.ALL;
refer ISE Window (refer Figure-15).
Figure-14

7. You can type your VHDL code in the right side of window and save the code by pressing
the save button in the tool bar of the ISE window (refer Figure-16).
Figure-15

Figure-16

Figure-17

8. Then select Project  New Source  Implementation Constraint File (refer
Figures- 18). Give filename in the appropriate field and then click next and Finish.
(Refer Figures-19, 20, 21).
Figure-18

Figure-19

Figure-20

Figure-21

9. Click the UCF file in source window. In process window under User constraint double
click the Edit constraints (text) double click (refer Figure-23, 24).
Figure-22

Figure-23

Figure-24

10. In this window type your pin assignments to the inputs and outputs corresponding to the
FPGA pins. Refer Figure-25
Figure-25

11. To download the program into Boundary Scan mode, do the following steps. Come to
Project Navigator window and click SYNTHESIZE-XST and when synthesis is
completed successfully, click IMPLEMENT DESIGN in process for current source.
After implement design has become successful, click GENERATE PROGRAMMING
FILE and then click Configure Device (iMPACT) (refer Figure-26, 27, 28, 29, 30).
Figure-26

Figure-27

Figure-28

Figure-29

Figure-30

12. Click ok to continue the process. Then new impact window will open. Refer figure-31
Figure-31

13. Now one new impact window will open. (Refer figure- 32)
Figure-32

14. Double click the Boundary Scan mode, presented in the left side of the window. Refer
figure- 33, 34.
Figure-33

Figure-34

15. Right click  Initialize chain. You got a connection via the cable. Refer figure 35, 36.
Figure-35

Figure – 36

16. Now the cable is identified IDENTIFY SUCCEEDED. Then select the bit file swled.bit
and select open. Refer figure 37. The new window will open. Here select NO for continues the
process. Refer figure-38. Then the new window will open click Cancel all refer figure 39.
Figure-37

Figure-38

Figure-39

17. The new window will open it is given below. Click Apply then click Ok. Refer figure 40, 41.
Figure-40

Figure-41

18. Then select the Xilinx device and right click then select program. Refer figure –42. Then the
program is downloaded into the kit refer figure 43. Now the program was successfully
downloaded into the kit. Refer figure 44.
Figure-42

Figure-43

Figure-44

PROM FILE GENERATION
19. To generate a PROM file double click Create PROM File in the impact window. Refer
figure 45. Then the new window will open. Refer figure 46. PROM reset (sw2) switch is used to
reset the PROM IC.
Figure-45

Figure-46

20. Select first arrow marks in the window and assign xcf04s [4M]. Then click Add Storage
device. Refer Figure 47, 48, 49.
Figure-47

Figure- 48

Figure 49

21. Click second arrow mark and give output file name and output file location. Then select
MCS in the file format. After doing this above process click OK. Refer figure 50.
Figure 50

22. Click OK to continue the process. One small window will appear, this is about to add a
Xilinx device. Here click OK. Then the new window will open, here select the swled.bit Bit file
and click Open. Refer figure 51, 52.
Figure 51

Figure 52

23. After selecting the bit file a new small window will open. This is about to add another
device. Click NO to continue the process. Then click OK. Refer figure 53, 54.
Figure 53

Figure 54

24. Select impact process window. And Double click Generate file then the PROM file was
generated is notified as GENERATION SUCCEEDED. Refer figure 55, 56.
Figure55

Figure 56

25. Select middle device and right click  Assign new configuration file. New window will
appear. Refer figure 57, 58.
Figure 57

26. Select the MCS file swled.mcs, where you stored and click open. Refer figure 58, 59.
Figure 58

Figure 59

27. Select the middle device, right click  Program. Then the new window will appear, select
PROM Device (PROMxcf04s)  Apply  Ok. Refer figure 60, 61, 62.
Figure 60

Figure 61

Figure 62

28. Then the command was executed. You got a notification as Program Succeeded. Refer
figure 63, 64.
Figure 63

Figure 64

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SPARTAN – 6 PROJECT CARD

(Model No : VPTB - 16)

Technical Clarification /Suggestion :

CHAPTER- 2 CLOCK SOURCE 3

CHAPTER – 3 SWITCHES & LEDS 4

CHAPTER – 4 LCD DISPLAY 6

CHAPTER – 5 SEVEN SEGMENT DISPLAY 7

CHAPTER – 6 20 PIN HEADER 8

CHAPTER – 7 RTC (REAL TIME CLOCK) 9

CHAPTER – 8 ADC & DAC 11

CHAPTER – 9 BUZZER & RELAY 15

CHAPTER – 10 PROCEDURE TO WORK IN XILINX SOFTWARE 16

The Vi Microsystems Xilinx Spartan-6 FPGA Project Card is a demonstration platform

KEY COMPONENTS AND FEATURES

 Xilinx Spartan 6 - XC6SLX4, TQ144-2C Package Spartan 6

Vi Microsystems Pvt. Ltd., [1]

Vi Microsystems Pvt. Ltd., [2]

Clock connection with FPGA

SCHEMATIC NAME FPGA PIN

Default Factory settings = 20 Mhz

Vi Microsystems Pvt. Ltd., [3]

SWITCHES AND LEDs

3.1 Power Switch

3.2. Reset Switch

3.3 Input Switches

3.4 Push Button Switches

Vi Microsystems Pvt. Ltd., [4]

PIN Details for Matrix key:

Name A(0) A(1) B(0 B(1)

3.5 Output LEDS

FPGA PIN Details

Name LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8

3.6 PROM LED

Vi Microsystems Pvt. Ltd., [5]

LCD Connections with FPGA

Vi Microsystems Pvt. Ltd., [6]

SEVEN SEGMENT DISPLAY

FPGA PIN DETAILS

Individual display DISP1 DISP2 DISP3 DISP4

Segment SEGA SEGB SEGC SEGD SEGE SEGF SEGH SEGDP

Vi Microsystems Pvt. Ltd., [7]

FPGA PIN DETAILS

CONNECTOR SCHEMATIC NAME FPGA PIN

Vi Microsystems Pvt. Ltd., [8]

RTC (REAL TIME CLOCK)

PIN NAME FUNCTION FPGA PIN

Vi Microsystems Pvt. Ltd., [9]

The RTCC registers are contained in addresses 0x00h-0x06h.

Vi Microsystems Pvt. Ltd., [ 10 ]

ADC & DAC

Vi Microsystems Pvt. Ltd., [ 11 ]

FPGA Pin Connections

ADC PIN ADC CS BAR ADC SDATA ADC SCLK

Vi Microsystems Pvt. Ltd., [ 12 ]

In IC 1st pin (DACOUT) is a DAC output pin.

Vi Microsystems Pvt. Ltd., [ 13 ]

FPGA PIN CONNECTIONS

DAC PIN DAC CS Bar (SYNC) DAC SCLK DAC IN

Vi Microsystems Pvt. Ltd., [ 14 ]

BUZZER & RELAY

BUZZER PIN BUZZER

RELAY PIN RELAY

Vi Microsystems Pvt. Ltd., [ 15 ]