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SRM UNIVERSITY

FACULTY OF ENGINEERING AND TECHNOLOGY

SCHOOL OF COMPUTING
DEPARTMENT OF CSE
COURSE PLAN
Course Code : CS0207
Course Title : Computer Organization and Architecture
Semester : III
Course Time : July –Nov 2009
Location : S.R.M.E.C – Tech Park

SECTION
A B C D E
Day
Hour Timing Hour Timing Hour Timing Hour Timing Hour Timing

9.20- 9.20-
2.20-
Monday 2 10.10 2 10.10 - - 6 - -
3.10
a.m a.m
11.10- 9.20- 9.20-
1.30-
Tuesday 4 12.00 2 10.10 2 10.10 5 2 9.20-10.10
2.10
noon a.m a.m
1.30- 1.30- 1.30- 9.20-
Wednesday 5 2.20 5 2.20 5 2.20 - - 2,6 10.10,2.20-
p.m p.m p.m 3.10
8.30-
8.30-
Thursday - - - - 1 9.20 1 5 1.30-2.20
9.20
a.m
11.10- 11.10- 10.20-
8.30-
Friday 4 12.00 4 12.00 3 11.10 1 - -
9.20
noon noon am

Faculty Details

Sec. Name Office Office hour Mail id


Tuesday-2nd hour & 4th
A C.Malathy Tech Park hourWednesday-5th malathyc@cse.srmuniv.ac.in
hour,Friday-4th hour
Monday-2nd hour,Tuesday-2nd
K.Annapoorani
B Tech Park hour,Wednesday-5th annapoorani@cse.srmuniv.ac.in
Panaiyappan
hour,Friday-4th hour
Tuesday-2nd hour Wednesday-
C C.Lakshmi Tech Park 5th hour,Thursday-1 st lakshmi@cse.srmuniv.ac.in
hour,Friday-4th hour
D PRAVEEN.N Tech Park Monday - Friday praveen@cse.srmuniv.ac.in
E Akilandeswari. Tech Park Monday - Friday akilandeswari@cse.srmuniv.ac.in
Required Text Books:
1. Carl Hamacher,”Computer Organization”,Fifth Edition,McGrawHill International
Edition, 2002
2. P.Pal Chaudhuri, "Computer Organization and Design" , 2nd Edition, PHI ‘ 2003
3. William Stallings , “Computer Organization and Architecture – Designing for
Performance”, PHI, 2004.
4. John P.Hayes, "Computer Architecture and Organization", III Edition, McGraw
Hill International Editions,1998.
Web resources
www.amazon.com
www.freebookcentre.com

Prerequisite : CS0102 – Digital computer fundamentals

Objectives
1. Gives a knowledge of various architectures
2. CPU, Control unit, I/O Processing
3. Memory and its types
4. Design of the above components

Assessment Details

Cycle Test – I : 10 Marks

Surprise Test – I : 7 Marks

Cycle Test – II : 10 Marks

Surprise Test – II : 8 Marks

Model Exam : 15 Marks

Test Schedule

S.No. DATE TEST TOPICS DURATION


1 Cycle Test - I Unit I & II 2 periods
2 Cycle Test - II Unit III & IV 2 periods
3 Model Exam All 5 units 3 Hrs

Outcomes
Students who have successfully completed this course will have full understanding of the
following concepts

Course outcome Program outcome

To learn An ability to understand the basic functioning of


The basic functional units, operational concepts computer.
and To understand the concepts of addressing modes a
The basic memory operations, addressing modes. To solve various ALU operations.
Basic ALU functions (operations) To implement booth algorithm
Control unit design and memory and its types To understand various types of memory concepts
Input and output processing – bus interface I/O I/O processing.
interface

Detailed Session Plan

UNIT-I INTRODUCTION
Evolution of Computer Systems-Computer Types-Functional units-Basic operational concepts-Bus
structures-Memory location and addresses-memory operations- Addressing modes-Design of a computer
system-Instruction and instruction sequencing, RISC versus CISC
Sessi
Time Teaching
on Topics to be covered Ref Testing Method
(min) Method
No.
Evolution of Computer Systems Group discussion
1 50 1,2 PPT
Quiz
Computer Types Objective type test
2 50 1,2 PPT
Quiz
3 Functional units 50 1 PPT Quiz
Basic operational concepts, Bus structures Quiz
4 50 1 PPT
Memory location and addresses-memory Quiz
5 50 1,3 PPT
operations
Addressing modes Quiz
6 50 1,3 PPT
Objective type test
7 Design of a computer system 50 2 PPT Quiz, Assignment
Instruction and instruction sequencing Group discussion
50 1,3 PPT
8
RISC versus CISC Group discussion
9 50 1,3 PPT
UNIT-II CENTRAL PROCESSING UNIT
Introduction-Arithmetic Logic Unit - Fixed point arithmetic, floating point arithmetic-Execution of a
complete instruction-Basic concepts of pipelining
10 Introduction-Arithmetic Logic Unit 50 1,2 PPT Quiz
Fixed point arithmetic Quiz
11 50 1,2 PPT
Brain storming
Fixed point arithmetic Quiz
12 50 1,2 PPT
Surprise Test
Floating point arithmetic Group discussion
13 50 1,2 PPT
Quiz
14 Floating point arithmetic 50 1,2 PPT Group discussion, Quiz
15 Floating point arithmetic 50 1,2 PPT Quiz, Assignment
Execution of a complete Quiz
16 50 1,2 PPT
instruction
17 Basic concepts of pipelining 50 1,2 PPT Quiz
18 Basic concepts of pipelining 50 1,2 PPT Quiz
UNIT-III CONTROL UNIT DESIGN
Introduction-Control Transfer-Fetch cycle - Instruction Interpretation & Execution - Hardwired control -
Microprogrammed control
Introduction-Control Transfer Quiz
19 50 2 BB,PPT Group discussion
Objective type test
Fetch cycle Quiz
20 50 2 BB,PPT
Group discussion
21 Fetch cycle 50 2 BB,PPT Quiz
Instruction Interpretation & Execution Quiz
22 50 1,2 BB,PPT
Surprise Test
Instruction Interpretation & Execution Quiz
23 50 1,2 BB,PPT
Group discussion
Hardwired control Quiz
24 50 1,2 BB,PPT
Hardwired control Quiz
25 50 1,2 BB,PPT
Group discussion
26 Microprogrammed control 50 1,2 BB,PPT Quiz
Microprogrammed control Quiz
27 50 1,2,3 BB,PPT
Brain storming
UNIT-IV MEMORIES AND SUBSYSTEMS
Semiconductor memory - Static and Dynamic -Associative memory- Cache memory- Virtual memory-
Secondary memories-Optical magnetic tape & magnetic disks & controllers
Semiconductor memory- Static and Group discussion
28 50 1,2,3 BB
Dynamic memory Assignment
Static and Dynamic memory Group discussion
29 50 1,2,3 BB
Quiz
Associative memory Group discussion
30 50 1,2,3 BB
Assignment
Associative memory Group discussion
31 50 1,2,3 BB
Assignment
Cache memory Objective type test
32 50 1,2,3 BB Quiz
Group discussion
Virtual memory Quiz
33 50 1,2,3 BB Group discussion

Secondary memories-Optical magnetic Objective type test


34 50 1,2,3 BB
tape
Magnetic disks & controllers Objective type test
35 50 1,2,3 BB
Magnetic disks & controllers Quiz
36 50 1,2,3 BB
Group discussion
UNIT-V I/O PROCESSING
Introduction-Data transfer techniques- Bus Interface- I/O Channel-I/O Processor, I/O devices -Direct
memory access.

Introduction-Data transfer techniques Group discussion


37 50 1,2 BB
Bus Interface Objective type test
38 50 1,2 BB
39 I/O Channel 50 1,2 BB Brain storming
40 I/O Processor 50 1,2 BB Brain storming
41 I/O Processor 50 2,3 BB Surprise test
Quiz
42 I/O devices 50 2,3 BB Assignment
43 I/O devices 50 2,3 BB Assignment
Direct memory access.
44 50 1,2 BB Brain storming
Direct memory access.
45 50 1,2 BB Brain storming

• BB – Black Board
• PP – Power Point