Beruflich Dokumente
Kultur Dokumente
in JNTU World
ld
COMPUTER
or
ORGANIZATION AND
W
ARCHITECTURE
TU
JN
ORGANISATION AND
ARCHITECTURE
ld
• The components from which computers are built,
or
i.e., computer organization.
• In contrast, computer architecture is the science of
W
integrating those components to achieve a level of
functionality and performance.
• It is as if computer organization examines the
TU
lumber, bricks, nails, and other building material
• While computer architecture looks at the design of
the house.
JN
UNIT-I INTRODUCTION
ld
•Evolution of Computer Systems
•Computer Types
or
•Functional units
•Basic operational concepts
•Bus structures
W
•Memory location and addresses
•Memory operations
TU
•Addressing modes
•Design of a computer system
•Instruction and instruction sequencing,
JN
INTRODUCTION
ld
This chapter discusses the computer hardware,
or
software and their interconnection, and it also
discusses concepts like computer types,
W
evolution of computers, functional units, basic
operations, RISC and CISC systems.
TU
JN
Brief History of Computer
Evolution
ld
Two phases:
VLSI = Very Large
or
1. before VLSI 1945 – 1978 Scale Integration
• ENIAC
W
• IAS
• IBM
• PDP‐8
TU
2. VLSI 1978 Æ present day
• microprocessors !
JN
ld
• Program and data reside in the same memory
or
(stored program concepts – John von Neumann)
• ALP was made used to write programs
W
• Vacuum tubes were used to implement the functions
(ALU & CU design)
• Magnetic core and magnetic tape storage devices are
TU
used
• Using electronic vacuum tubes, as the switching
JN
components
SECOND GENERATION
(1955 – 1965)
ld
or
• Transistor were used to design ALU & CU
• HLL is used (FORTRAN)
W
• To convert HLL to MLL compiler were used
• Separate I/O processor were developed to operate in
parallel with CPU, thus improving the performance
TU
• Invention of the transistor which was faster, smaller
and required considerably less power to operate
JN
THIRD GENERATION
(1965‐1975)
ld
• IC technology improved
• Improved IC technology helped in designing low cost, high
or
speed processor and memory modules
• Multiprogramming, pipelining concepts were incorporated
W
• DOS allowed efficient and coordinate operation of computer
system with multiple users
• Cache and virtual memory concepts were developed
• More than one circuit on a single silicon chip became
TU
available
JN
ld
• CPU – Termed as microprocessor
or
• INTEL, MOTOROLA, TEXAS,NATIONAL
semiconductors started developing microprocessor
• Workstations, microprocessor (PC) & Notebook
W
computers were developed
• Interconnection of different computer for better
communication LAN,MAN,WAN
TU
• Computational speed increased by 1000 times
• Specialized processors like Digital Signal Processor
were also developed
JN
ld
or
• E‐Commerce, E‐ banking, home office
W
• ARM, AMD, INTEL, MOTOROLA
• High speed processor ‐ GHz speed
TU
• Because of submicron IC technology lot of
added features in small size
JN
COMPUTER TYPES
ld
Computers are classified based on the
or
parameters like
• Speed of operation
W
• Cost
• Computational power
TU
• Type of application
JN
DESK TOP COMPUTER
ld
• Processing &storage units, visual display &audio uits,
keyboards
or
• Storage media‐Hard disks, CD‐ROMs
• Eg: Personal computers which is used in homes and offices
W
• Advantage: Cost effective, easy to operate, suitable for general
purpose educational or business application
NOTEBOOK COMPUTER
TU
• Compact form of personal computer (laptop)
• Advantage is portability
JN
WORK STATIONS
ld
• More computational power than PC
•Costlier
•Used to solve complex problems which arises in
or
engineering application (graphics, CAD/CAM etc)
W
ENTERPRISE SYSTEM (MAINFRAME)
•More computational power
TU
•Larger storage capacity
•Used for business data processing in large organization
•Commonly referred as servers or super computers
JN
SERVER SYSTEM
ld
• Supports large volumes of data which frequently need to
or
be accessed or to be modified
•Supports request response operation
W
SUPER COMPUTERS
TU
•Faster than mainframes
•Helps in calculating large scale numerical and algorithm
calculation in short span of time
JN
HANDHELD
ld
• Also called a PDA (Personal
Digital Assistant).
or
• A computer that fits into a
pocket, runs on batteries, and
is used while holding the unit
W
in your hand.
• Typically used as an
appointment book, address
TU
book, calculator, and notepad.
• Can be synchronized with a
personal microcomputer as a
JN
backup.
Basic Terminology
ld
• Computer • Software
– A device that accepts input, – A computer program that tells
or
processes data, stores data, and the computer how to perform
produces output, all according to particular tasks.
a series of stored instructions.
W
• Network
• Hardware – Two or more computers and
– Includes the electronic and other devices that are
mechanical devices that process connected, for the purpose of
TU
the data; refers to the computer sharing data and programs.
as well as peripheral devices.
• Peripheral devices
– Used to expand the computer’s
input, output and storage
JN
capabilities.
Basic Terminology
ld
• Input
– Whatever is put into a computer system.
or
• Data
– Refers to the symbols that represent facts, objects, or ideas.
• Information
W
– The results of the computer storing data as bits and bytes; the words,
numbers, sounds, and graphics.
• Output
– Consists of the processing results produced by a computer.
TU
• Processing
– Manipulation of the data in many ways.
• Memory
– Area of the computer that temporarily holds data waiting to be processed,
stored, or output.
JN
• Storage
– Area of the computer that holds data on a permanent basis when it is not
immediately needed for processing.
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Basic Terminology
ld
•Assembly language program (ALP) – Programs are written
or
using mnemonics
W
form
Basic Terminology
ld
•Interpreter – Converts HLL to MLL, does this job
statement by statement
or
•System software – Program routines which aid the
user in the execution of programs eg: Assemblers,
W
Compilers
Computing Systems
ld
Computers have two kinds of components:
or
• Hardware, consisting of its physical devices
W
(CPU, memory, bus, storage devices, ...)
• Software, consisting of the programs it has
(Operating system, applications, utilities, ...)
TU
JN
Calvin College
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
FUNCTIONAL UNITS OF
COMPUTER
ld
• Input Unit
or
• Output Unit
W
• Central processing Unit (ALU and Control Units)
TU
• Memory
• Bus Structure
JN
The Big Picture
ld
or
Processor
Input
W
Control
Memory
TU
ALU
Output
JN
Since 1946 all computers have had 5 components!!!
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
IMPORTANT
Function SLIDE !
ld
• ALL computer functions are:
or
– Data PROCESSING
– Data STORAGE Data = Information
W
– Data MOVEMENT
– CONTROL Coordinates How
Information is Used
TU
• NOTHING ELSE!
JN
INPUT UNIT:
ld
•Converts the external world data to a binary format, which
or
can be understood by CPU
OUTPUT UNIT:
W
TU
•Converts the binary format data to a format that a common
man can understand
JN
ld
CPU
•The “brain” of the machine
or
•Responsible for carrying out computational task
W
•Contains ALU, CU, Registers
ld
Example
or
Add R1, R2
T1 Enable R1
T2
W
Enable R2
TU
T3 Enable ALU for addition operation
JN
ld
•Control unit works with
a reference signal called
processor clock
or
T1
W
TU steps
R1 R2
R2
ld
MEMORY
or
•Stores data, results, programs
W
•Two class of storage
(i) Primary (ii) Secondary
TU
•Two types are RAM or R/W memory and ROM read only memory
Basic Operational Concepts
ld
or
Basic Function of Computer
W
• To Execute a given task as per the appropriate program
TU
• Program consists of list of instructions stored in
memory
JN
ld
or
W
TU
JN
Registers
Registers are fast stand-alone storage locations that hold data
ld
temporarily. Multiple registers are needed to facilitate the
operation of the CPU. Some of these registers are
or
Two registers-MAR (Memory Address Register) and
W
MDR (Memory Data Register) : To handle the data
transfer between main memory and processor. MAR-
Holds addresses, MDR-Holds data
TU
Instruction register (IR) : Hold the Instructions that is
currently being executed
JN
ld
of PC transferred to MAR)
or
•(MAR) (Address bus) Select a
particular memory location
W
•Issues RD control signals
TU
•Reads instruction present in memory
and loaded into MDR
JN
ld
•Instruction present in IR will be decoded by
which processor understand what operation it
or
has to perform
W
•Increments the contents of PC by 1, so that it
points to the next instruction address
TU
•If data required for operation is available in
register, it performs the operation
JN
ld
•MAR Address bus select memory
location where is issued RD signal
or
•Reads data via data bus MDR
W
•From MDR data can be directly routed to ALU
or it can be placed in register and then
TU
operation can be performed
Interrupt
ld
• An interrupt is a request from I/O device for
or
service by processor
• Processor provides requested service by
W
executing interrupt service routine (ISR)
• Contents of PC, general registers, and some
control information are stored in memory .
TU
• When ISR completed, processor restored, so
that interrupted program may continue
JN
BUS STRUCTURE
Connecting CPU and memory
ld
The CPU and memory are normally connected by three
groups of connections, each called a bus: data bus, address
or
bus and control bus
W
TU
JN
BUS STRUCTURE
ld
•Group of wires which carries information form CPU to peripherals or
vice – versa
or
•Single bus structure: Common bus used to communicate between
peripherals and microprocessor
W
INPUT MEMORY PROCESSOR OUTPUT
TU
JN
ld
Continued:-
or
• To
improve performance multibus structure can be
used
W
•In two – bus structure : One bus can be used to fetch
TU
instruction other can be used to fetch data, required
for execution.
JN
ld
A2 A1 A0 Selected
CONTROL BUS location
0 0 0 0th Location
or
0 0 1 1st Location
0 1 0
W/R
RD 0 1 1
W
CS A0 PROCESSOR
A1 1 0 0
A2
1 0 1
ADDRESS BUS
TU
1 1 0
D7 D0
D0 D7
1 1 1
JN
DATA BUS
ld
Cont:-
or
•23 = 8 i.e. 3 address line is required to select 8
location
W
•In general 2x = n where x number of address lines
(address bit) and n is number of location
TU
•Address bus : unidirectional : group of wires
which carries address information bits form
processor to peripherals (16,20,24 or more parallel
JN
signal lines)
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
ld
Cont:-
or
•Databus: bidirectional : group of wires which
carries data information bit form processor to
peripherals and vice – versa
W
•Controlbus: bidirectional: group of wires
which carries control signals form processor to
TU
peripherals and vice – versa
microprocessor
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
ld
or
W
TU
JN
PERFORMANCE
ld
•Parameters which influence the performance are
or
•Clock speed
W
•Type and number of instructions available
ld
•Main memory is the second major subsystem in a
computer. It consists of a collection of storage locations,
or
each with a unique identifier, called an address.
W
bits called words. A word can be a group of 8 bits, 16
bits, 32 bits or 64 bits (and growing).
TU
•If the word is 8 bits, it is referred to as a byte. The term
“byte” is so common in computer science that
sometimes a 16-bit word is referred to as a 2-byte word,
JN
ld
or
W
TU
JN
Figure 5.3JNTUMain
Downloaded From memory
World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Address space
ld
•To access a word in memory requires an identifier. Although
or
programmers use a name to identify a word (or a collection
of words), at the hardware level each word is identified by an
address.
W
•The total number of uniquely identifiable locations in
TU
memory is called the address space.
ld
or
W
TU
i
JN
Example 1
A computer has 32 MB (megabytes) of memory. How many bits
ld
are needed to address any single byte in memory?
Solution
The memory address space is 32 MB, or 225 (25 × 220). This
or
means that we need log2 225, or 25 bits, to address each byte.
W
Example 2
A computer has 128 MB of memory. Each word in this computer
is eight bytes. How many bits are needed to address any single
TU
word in memory?
Solution
The memory address space is 128 MB, which means 227.
JN
Assignment of byte addresses
ld
• Little Endian (e.g., in DEC, Intel)
or
» low order byte stored at lowest address
» byte0 byte1 byte2 byte3
W
• Eg: 46,78,96,54 (32 bit data)
• H BYTE L BYTE
TU
• 8000 54
• 8001 96
• 8002 78
• 8003
JN
46
• 8004
|
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Big Endian
ld
• Big Endian (e.g., in IBM, Motorolla, Sun, HP)
or
» high order byte stored at lowest address
» byte3 byte2 byte1 byte0
W
• Programmers/protocols should be careful
TU
when transferring binary data between Big
Endian and Little Endian machines
JN
• In case of 16 bit data, aligned words begin at
ld
byte addresses of 0,2,4,………………………….
• In case of 32 bit data, aligned words begin at
or
byte address of 0,4,8,………………………….
• In case of 64 bit data, aligned words begin at
W
byte addresses of 0,8,16,………………………..
• In some cases words can start at an arbitrary
TU
byte address also then, we say that word
locations are unaligned
JN
MEMORY OPERATIONS
ld
• Today, general‐purpose computers use a set of instructions called a
program to process data.
or
• A computer executes the program to create output data from input
data
W
• Both program instructions and data operands are stored in memory
• Two basic operations requires in memory access
TU
• Load operation (Read or Fetch)‐Contents of specified
memory location are read by processor
• Store operation (Write)‐ Data from the processor is stored in
specified memory location
JN
• INSTRUCTION SET ARCHITECTURE:‐Complete
ld
instruction set of the processor
or
• BASIC 4 TYPES OF OPERATION:‐
W
• Data transfer between memory and
processor register
TU
• Arithmetic and logic operation
• Program sequencing and control
JN
• I/O transfer
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Register transfer notation (RTN)
ld
Transfer between processor registers & memory, between
processor register & I/O devices
or
Memory locations, registers and I/O register names are
W
identified by a symbolic name in uppercase alphabets
• LOC,PLACE,MEM are the address of memory location
TU
• R1 , R2,… are processor registers
• DATA_IN, DATA_OUT are I/O registers
JN
ld
•Contents of location is indicated by using square
brackets [ ]
or
•RHS of RTN always denotes a values, and is
called Source
W
•LHS of RTN always denotes a symbolic name
TU
where value is to be stored and is called destination
ld
or
• R2 [LOCN]
W
TU
• R4 [R3] +[R2]
JN
ASSEMBLY LANGUAGE
NOTATION (ALN)
ld
• RTN is easy to understand and but cannot be
or
used to represent machine instructions
• Mnemonics can be converted to machine
W
language, which processor understands
using assembler
Eg:
TU
1. MOVE LOCN, R2
2. ADD R3, R2, R4
JN
TYPE OF INSTRUCTION
ld
¾Three address instruction
or
•Syntax: Operation source 1, source 2, destination
W
•Eg: ADD D,E,F where D,E,F are memory
location
•Advantage: Single instruction can perform the
TU
complete operation
•Disadvantage : Instruction code will be too large to
fit in one word location in memory
JN
ld
•Syntax : Operation source, destination
or
•Eg: MOVE E,F MOVE D,F
W
ADD D,F OR ADD E,F
ld
• Syntax‐ Operation source/destination
or
• In this type either a source or destination
operand is mentioned in the instruction
W
• Other operand is implied to be a processor
register called Accumulator
Eg: ADD B (general)
TU
•
• Load D; ACC [memlocation _D]
• ADD E; ACC (ACC) +(E)
JN
• STORE F; memlocation_ F (ACC )
ld
or
• Location of all operands are defined implicitly
W
• Operands are stored in a structure called
pushdown stack
TU
JN
Continued
ld
¾ If processor supports ALU operations one data in memory and
other in register then the instruction sequence is
or
• MOVE D, Ri
• ADD E, Ri
W
• MOVE Ri, F
¾ If processor supports ALU operations only with registers then
one has to follow the instruction sequence given below
• LOAD D, Ri
TU
• LOAD E, Rj
• ADD Ri, Rj
• MOVE Rj, F
JN
Basic Instruction Cycle
ld
• Basic computer operation cycle
or
– Fetch the instruction from memory into a control
register (PC)
W
– Decode the instruction
– Locate the operands used by the instruction
– Fetch operands from memory (if necessary)
TU
– Execute the operation in processor registers
– Store the results in the proper place
– Go back to step 1 to fetch the next instruction
JN
INSTRUCTION EXECUTION & STRIAGHT LINE
SEQUENCING
ld
Address Contents
}
Begin execution here i Move A,R0
or
i+4 Add B,R0
3-instruction program
i+8 Move R0,C
. segment
W
.
.
A
TU
.
.
.
. C [A]+[B]
.
Downloaded From JNTU World (http://www.alljntuworld.in)
C
www.alljntuworld.in JNTU World
• PC – Program counter: hold the address of the next
ld
instruction to be executed
• Straight line sequencing: If fetching and executing of
instructions is carried out one by one from
or
successive addresses of memory, it is called straight
line sequencing.
W
• Major two phase of instruction execution
• Instruction fetch phase: Instruction is fetched form
memory and is placed in instruction register IR
TU
• Instruction execute phase: Contents of IR is decoded
and processor carries out the operation either by
reading data from memory or registers.
JN
BRANCHING
ld
or
W
TU
JN
BRANCHING
• Branch instruction are those which changes the
normal sequence of execution.
ld
• Sequence can be changed either conditionally or
or
unconditionally.
W
• Accordingly we have conditional branch instructions
and unconditional branch instruction.
TU
• Conditional branch instruction changes the sequence
only when certain conditions are met.
JN
• Unconditional branch instruction changes the
sequence of execution irrespective of condition of
the results. Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
CONDITION CODES
¾ CONDITIONAL CODE FLAGS: The processor keeps track of
ld
information about the results of various operations for
use by subsequent conditional branch instructions
or
• N – Negative 1 if results are Negative
W
0 if results are Positive
• Z – Zero 1 if results are Zero
0 if results are Non zero
TU
• V – Overflow 1 if arithmetic overflow occurs
0 non overflow occurs
• C – Carry 1 if carry and from MSB bit
JN
0 if there is no carry from MSB bit
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
ld
or
W
TU
JN
ld
A cycle is made of three phases: fetch, decode and execute.
or
During the fetch phase, the instruction whose address is determined by
the PC is obtained from the memory and loaded into the IR. The PC is
then incremented to point to the next instruction.
W
During the decode phase, the instruction in IR is decoded and the
required operands are fetched from the register or from memory.
TU
During the execute phase, the instruction is executed and the results are
placed in the appropriate memory location or the register.
JN
Once the third phase is completed, the control unit starts the cycle again,
but now the PC is pointing to the next instruction.
Downloaded From JNTU World (http://www.alljntuworld.in)
Types of Addressing Modes
ld
The different ways in which the location of the operand is
specified in an instruction are referred to as addressing
modes
or
• Immediate Addressing
W
• Direct Addressing
• Indirect Addressing
TU
• Register Addressing
• Register Indirect Addressing
• Relative Addressing
JN
• Indexed Addressing
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Immediate Addressing
• Operand is given explicitly in the instruction
ld
• Operand = Value
or
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
W
• No memory reference to fetch data
• Fast
TU
• Limited range
Instruction
JN
opcode
operand
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Direct Addressing
ld
• Address field contains address of operand
or
• Effective address (EA) = address field (A)
• e.g. ADD A
W
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
TU
• No additional calculations to work out effective address
• Limited address space
JN
Direct Addressing Diagram
ld
Instruction
or
Opcode Address A
Memory
W
TU
Operand
JN
Indirect Addressing (1)
ld
• Memory cell pointed to by address field
or
contains the address of (pointer to) the
operand
W
• EA = [A]
– Look in A, find address (A) and look there for
TU
operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to
JN
accumulator
Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Indirect Addressing (2)
ld
• Large address space
or
• 2n where n = word length
• May be nested, multilevel, cascaded
W
– e.g. EA = (((A)))
• Draw the diagram yourself
TU
• Multiple memory accesses to find operand
• Hence slower
JN
Indirect Addressing Diagram
ld
Instruction
or
Opcode Address A
Memory
W
TU Pointer to operand
Operand
JN
Register Addressing (1)
ld
• Operand is held in register named in address
or
field
• EA = R
W
• Limited number of registers
• Very small address field needed
TU
– Shorter instructions
– Faster instruction fetch
JN
Register Addressing (2)
ld
• No memory access
or
• Very fast execution
• Very limited address space
W
TU
• Multiple registers helps performance
JN
– Requires good assembly programming or compiler
writing Downloaded From JNTU World (http://www.alljntuworld.in)
www.alljntuworld.in JNTU World
Register Addressing Diagram
ld
Instruction
or
Opcode Register Address R
Registers
W
TU
Operand
JN
Register Indirect
Addressing
ld
• C.f. indirect addressing
or
• EA = [R]
• Operand is in memory cell pointed to by
W
contents of register R
• Large address space (2n)
TU
• One fewer memory access than indirect
addressing
JN
Register Indirect
Addressing Diagram
ld
Instruction
or
Opcode Register Address R
Memory
W
Registers
TU
Pointer to Operand Operand
JN
Indexed Addressing
ld
• EA = X + [R]
or
• Address field hold two values
– X = constant value (offset)
W
– R = register that holds address of memory
locations
– or vice versa
TU
`(Offset given as constant or in the index register)
Add 20(R1),R2 or Add 1000(R1),R2
JN
Indexed Addressing Diagram
ld
Instruction
or
Opcode Register R Constant Value
Memory
W
Registers
TU
Pointer to Operand + Operand
JN
Relative Addressing
ld
• A version of displacement addressing
or
• R = Program counter, PC
• EA = X + (PC)
W
• i.e. get operand from X bytes away from
current location pointed to by PC
TU
• c.f locality of reference & cache usage
JN
Auto increment mode
ld
• The effective address of the operand is the
or
contents of a register specified in the instruction.
• After accessing the operand, the contents of this
W
register are automatically incremented to point
to the next item in the list
TU
• EA=[Ri]; Increment Ri ‐‐‐‐ (Ri)+
Eg: Add (R2)+,R0
JN
Auto decrement mode
ld
• The contents of a register specified in the
or
instruction are first automatically
decremented and are then used as the
W
effective address of the operand
TU
• Decrement Ri; EA= [Ri] ‐‐‐‐‐ ‐(Ri)
JN
Addressing Architecture
• Memory‐to‐Memory architecture
ld
– All of the access of addressing ‐> Memory
– Have only control registers such PC
or
– Too many memory accesses
• Register‐to‐Register architecture
– Allow only one memory address
• “load”, “store” instructions
W
• Register‐to‐Memory architecture
– Program lengths and # of memory accesses tend to be intermediate
between the above two architectures
TU
• Single accumulator architecture
– Have no register profile
– Too many memory accesses
• Stack architecture
JN
– Data manipulation instructions use no address.
– Too many memory (stack) accesses
– Useful for rapid interpretation of high‐level lang. programs in which the
Downloaded From JNTU World (http://www.alljntuworld.in)
intermediate code representation uses stack operations.
www.alljntuworld.in JNTU World
Addressing Modes
ld
• Implied mode
or
– The operand is specified implicitly in the definition
of the opcode.
W
• Immediate mode
– The actual operand is specified in the instruction
TU
itself.
JN
Addressing Modes (Summary)
ld
or
W
TU
Base register LDA #ADRS(R1) ACC <- M[R1+ADRS]
JN
Instruction Set Architecture
• RISC (Reduced Instruction Set Computer) Architectures
ld
– Memory accesses are restricted to load and store instruction, and data
manipulation instructions are register to register.
or
– Addressing modes are limited in number.
– Instruction formats are all of the same length.
– Instructions perform elementary operations
W
• CISC (Complex Instruction Set Computer) Architectures
– Memory access is directly available to most types of instruction.
TU
– Addressing mode are substantial in number.
– Instruction formats are of different lengths.
– Instructions perform both elementary and complex operations.
JN
Instruction Set Architecture
ld
• RISC (Reduced Instruction Set Computer)
Architectures
or
– Large register file
– Control unit: simple and hardwired
W
– pipelining
• CISC (Complex Instruction Set Computer)
TU
Architectures
– Register file: smaller than in a RISC
– Control unit: often micro‐programmed
– Current trend
JN
• CISC operation Æ a sequence of RISC‐like operations
CISC Examples
ld
• Examples of CISC processors are the
or
– System/360(excluding the 'scientific' Model 44),
– VAX,
W
– PDP‐11,
– Motorola 68000 family
TU
– Intel x86 architecture based processors.
JN
Pro’s
ld
• Emphasis on hardware
or
• Includes multi-clock complex
instructions
• Memory-to-memory:
W
"LOAD" and "STORE"
incorporated in instructions
• Small code sizes,
TU
high cycles per second
• Transistors used for storing
complex instructions
JN
Con’s
ld
• That is, the incorporation of older instruction sets
or
into new generations of processors tended to force
growing complexity.
• Many specialized CISC instructions were not used
W
frequently enough to justify their existence.
• Because each CISC command must be translated by
the processor into tens or even hundreds of lines of
TU
microcode, it tends to run slower than an equivalent
series of simpler commands that do not require so
much translation.
JN
RISC Examples
ld
• Apple iPods (custom ARM7TDMI SoC)
or
• Apple iPhone (Samsung ARM1176JZF)
• Palm and PocketPC PDAs and smartphones (Intel
XScale family, Samsung SC32442 ‐ ARM9)
W
• Nintendo Game Boy Advance (ARM7)
• Nintendo DS (ARM7, ARM9)
TU
• Sony Network Walkman (Sony in‐house ARM based
chip)
• Some Nokia and Sony Ericsson mobile phones
JN
Pro’s
ld
• Emphasis on software
or
• Single-clock,
reduced instruction only
• Register to register:
W
"LOAD" and "STORE"
are independent instructions
• Low cycles per second,
TU
large code sizes
• Spends more transistors
on memory registers
JN
Performance
ld
• The CISC approach attempts to
or
minimize the number of instructions
per program, sacrificing the number
of cycles per instruction. RISC does
W
the opposite, reducing the cycles per
instruction at the cost of the number
TU
of instructions per program.
JN
Characteristics of RISC Vs CISC
processors
ld
No RISC CISC
or
1 Simple instructions taking one Complex instructions taking
cycle multiple cycles
2 Instructions are executed by Instructions are executed by
W
hardwired control unit microprogramed control unit
3 Few instructions Many instructions
SUMMARY
ld
Computer components and its function
or
Evolution and types of computer
Instruction and instruction sequencing
W
Addressing modes
RISC Vs CISC
TU
JN
REFERENCES
ld
• Carl Hammacher,”Computer
or
Organization,”Fifth Edition,McGrawHill
International Edition,2002
W
• P.Pal Chaudhuri,”Compter Organization and
Design”,2nd Edition ,PHI,2003
TU
• William Stallings,”Computer organization and
Architecture‐Designing for
Performance”,PHI,2004
JN