cd

mkdir labs
cd labs/
cp -rf /projecys/w_pd_1/ecc_top_wrap .
cd ecc_top_wrap
source /tools/synopsys/source/source_new.csh
icc_shell
source scripts/import_design.tcl

# Sanity checks:-
check_library
Check_design
check_timing
report_qor
report_timing
# set_zero_interconnect_delay_mode true (To check signals are reaching the flops
and cells as we dont know RC values)
report_timing
# set_zero_interconnect_delay_mode false
# Start_gui
# create_floorplan -left_io2core 2 -bottom_io2core 2 -right_io2core 2 -top_io2core
2 -control_type aspect_ratio -core_utilization{*/ tocreate floor plan block}
do floorplan
# Complete the IO ports placement(source ./scripts/place_io_ports.tcl)-->edit to
place io prts on 1 side and to alocate metal layer
CHeck check_fp_pin_assignment -block_level
# Complete the Macro Placement
# Fix all the macros (set_attribute [all_macro_cells] is_fixed true)
set_attribute [get_ports] is_fixed true
#Soft blocakages
# Cut-Row (load site row tcl file) (source
/projects/w_pd_1/ecc_top_wrap/scripts/cut_row.tcl )
/*write_floorplan -placement hard_macro test.tcl */> to copy flowerplan as a tcl
file)
# Improve the Tool Run Time using the below command
set_host_options -max_cores 2
# pg rout -->source /projects/w_pd_1/ecc_top_wrap/scripts/pg_rout.tcl
verify_pg_net
source ./scripts/add_physical cells(tap cel, end cape cell place), also add
insert_i/o buffset, spare cells
set_dont_use [get_lib_cells */*LVT*] --> if dont want to use LVT cells in design
# set_separate_process_options -placement false -routing false -extraction false
#source /projects/w_pd_1/ecc_top_wrap/scripts/set_ignored_layers.tcl
# Perform Std Cell Placement using the below command
place_opt -effort low -continue_on_missing_scandef (-cts)
[Place tie cells]
---, remport timing(report_constraint -all_violators,)report conjestion(if conj
hie, use->refine_placement -congestion_effort
-continue_on_missing_scandef)place_opt -effort high -cts
-continue_on_missing_scandef
,
---verify_pg_net, Get_utilization(report_placement_utilization)

---# Check the Placement QoR

# Check Congestion Map(report_conjestn)
# Check Cell Density Map(on gui)
# Check Pin Density Map(on gui)(set_keepout_margin -outer {0.152 1.67 0.152
1.67} [get_selection]
, legalize_placement -incremental, refine_placement -continue_on_missing_scandef)
 # Highlight the Timing Paths using Timing Analysis Window.
# Perform incremental timing optimization
psynopt -area_recovery
# Check the QoR after Incremental Optimization)
# Save the MW cel
# Check the Design Readiness for Clock-Tree
check_clock_tree
# Review all the warnings & understand if they are ok to continue
# Also Refer Command Reference Manual to see the warning details
# Apply CTS settings
set_operating_conditions -min ff1p16vn40c -max ss0p95v125c
set_propagated_clock [all_clocks]
source /projects/w_pd_1/ecc_top_wrap/scripts/cts.tcl
# Check the Clock-Tree QoR Summary using the below command
report_clock_tree -summary
report_clock_tree -verbose
report_clock_timing -type latency -nosplit -nets -verbose
report_clock_timing -type skew -nosplit -nets -verbose
# Perform Clock-Opt ( DRV + Setup time Opt )
clock_opt -only_psyn
# Perform Hold Opt
set_fix_hold [all_clocks]
clock_opt -only_hold_time
# Save MW cel
# Check Post-CTS QoR like Timing, Congestion & Util(report_timing -delay_type
min -slack_lesser_than 0 -max_paths 56(delay type-min is to check for hold))
# Perform incremental timing optimization
psynopt -area_recovery
# Check the QoR after Incremental Optimization
# Perform Routing + Timing Opt using the below command
route_opt
focal_opt (-setup_endpoints all, -hold_endpoints all)
Checks:-- cong, timing,drc(check_rout -drc)[(physical drc->min width, spacing
area), logical drc--> max tran, max cap, max fanout)], signal integraty issue(cross
talk, em issue), lvs, antenna issue
# Save the final routed design as ecc_top_wrap.
### Save the routed design as a verilog file in a folder named output("mkdir
output" inside ecc_top_wrap folder)(Inorder to give input for Prime time's tcl
file)
command:- write_verilog outputs/ecc_top_wrap.v
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Star_RC for extractig SPEF file.
-------->

g /tmp/
cd /tmp/pt.readme
cd /tmp/gvim pt.readme
cd /tmp/
gvim pt.readme
Star_RC:
cd labs1/ecc_top_wrap/
cp -rpf /projects/w_pd_1/ecc_top_wrap/star_rc .
cd star_rc/
gvim run_starrc.csh (Inorder to enable commend for executing cbest or cworst)
gvim extract_cworst_spef.cmd(to edit path of mw cell)(OR)gvim
extract_cbest_spef.cmd(to edit path of mw cell)
cworst-->setup, cbest-->hold
source /tools/synopsys/source/source_new.csh
./run_starrc.csh ->Run starRC.
gvim star_cw/ecc_top_wrap_cworst_star.sum (OR)gvim
star_cb/ecc_top_wrap_cbest_star.sum--->To check the summary
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Prime time to perform ECO.
----------->
Make sure to be in your run dir.. ( Eg : ecc_top_wrap )
source /tools/synopsys/source/source_new.csh
cp -rpf /projects/w_pd_1/ecc_top_wrap/prime_time .
cd prime_time
pt_shell (dont use-->source ./run_pt.csh -> script used for invoking PT &
initialize the setup)
source ./run_pt_ss0p95v125c.tcl -> command file for the PT & loads all the
libraries of ss0p95v125c delay corner(before this done need to save the .v file
from ICC, Look note for details)
edit the above file with correct inputs like verilog netlist from routed DB,
SDC & SPEF

Checks and fixes:

pt_shell>
1 check_timing
2 report_annotated_parasitics
3 report_global_timing
4 report_threshold_voltage_group
5 report_analysis_coverage
6 report_qor
9 report_constraint -all_violators -nosplit > rpts/report_constraint.rpt
12 report_timing -input_pins -nets -max_paths 1000 -significant_digits 3
-slack_lesser_than 0
13 report_timing -input_pins -nets -max_paths 1000 -significant_digits 3
-slack_lesser_than 0 -transition_time -capacitance
16 report_timing -input_pins -nets -transition_time -capacitance -pba_mode
exhaustive
23 set_max_transition 0.3 [current_design]
24 fix_eco_drc -type max_transition -verbose -methods size_cell
26 fix_eco_timing -type setup -methods size_cell, insert_buffer -buffer_list
{buffer name}
Also, if not able to fix in pt, go to icc and add buff to coresponding cell(eg:
insert_buffer I_BLENDER_1/eco_cell_13_0/Y NBUFFX8_LVT)
If this dosent work, try report bottleneck delay_type max/min, -->will show
the list of cells violating, size_cell those manually in icc using (size_cell
I_BLENDER_0/U1516 OR2X2_RVT(OR2X2_RVT-->changed drive strength name))
28 write_changes -format icctcl -output outputs/eco_1_fix_eco.tcl
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# Open ICC_shell, remove filler cells 1st(remove_stdcell_filler -stdcell and
set_attr [get_cells *io_buf*] is_fixed false), load the the saved tcl file to the
final design from prime time.
# place eco_cell -eco_changed_cells
# check_legality(to legalize placement)
set_attr [get_cells *io_buf*] is_fixed true
# route_zrt_eco (to route the eco cells)--> Will gives the DRC summary.
then place the filler cells
# save the mw cel and use that as db for next itteration on starRC and prime time
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To edit tcl:(On linux) -> gvim place_io_ports.tcl
befor tat , need to go the location wher tcl is located(Folow below steps *for eg:)
[guepd0120ce19@vlsichip01 ~]$ pwd --> To check were we are
/home/guepd0120ce19
[guepd0120ce19@vlsichip01 ~]$ cd l ---> To check the files inside
labs/ labs_old/
[guepd0120ce19@vlsichip01 ~]$ cd labs ---> To go specifice file
[guepd0120ce19@vlsichip01 ~/labs]$ ls
ecc_top_wrap
[guepd0120ce19@vlsichip01 ~/labs]$ cd ecc_top_wrap/
[guepd0120ce19@vlsichip01 ecc_top_wrap]$ ls
command.log filenames.log icc_output.txt inputs labs.readme logs mwdb
old_scr rpts scripts
[guepd0120ce19@vlsichip01 ecc_top_wrap]$ cd scripts/
[guepd0120ce19@vlsichip01 scripts]$ ls
add_physical_cells.tcl derive_pg_connect.tcl insert_io_buffer.tcl
load_tluplus_library.tcl ref_scr
cts.tcl design_setup.tcl load_physical_library.tcl
pg_route.tcl set_ignored_layers.tcl
cut_row.tcl import_design.tcl load_timing_library.tcl
place_io_ports.tcl verify_pg_route.tcl
[guepd0120ce19@vlsichip01 scripts]$ gvim place_io_ports.tcl

tcl file will gets open

give insert to edit
gvim____, then gf to edit, :wq!-> to save gvim
-exclude_sides {1,2,3}-> To place all pins at one side (Hear bottom is 4 as the
block is of 4 sides)
- After editing wq! -> for saving the edited tcl file
Then run the tcl on design
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ctrl+r- ppt window (Inside icc)

mv labs(/*folder name/*) labs_old (/* name to move/*)