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1 Introduction

A general definition of embedded systems is computing systems that are tightly

coupled with hardware and software integration, which are designed to perform a

dedicated function. In an embedded system the hardware and software are optimized

for a particular application. The word embedded reflects the fact that these systems

are usually an integral part of a larger system, known as the embedded system. The

Embedded system can be defined as an “Application specific system”. The system

designed for one application cannot be ordinarily used for any other application. Most

of the embedded systems are reactive systems i.e. the embedded system is one that is

in continual interaction with its environment and executes at a pace determined by

that environment.

In many ways virtually unimaginable just a few decades ago, embedded systems are

reshaping the way people live, work, and play. An embedded system comes in an

endless variety of types, each exhibiting unique characteristics. Embedded systems

represent a class of dedicated computer systems designed for specific purposes. Many

of these embedded systems are reliable and predictable. The devices that embed them

are convenient, user-friendly, and dependable. Embedded systems have also changed

the style of home environment internet environment and industrial environment.

Perhaps the most significant application is robotic control parameters like speed and

position controlling which is really just a very large collection of embedded systems

that are interconnected using various process and control technologies.

Lot of industries use embedded systems for process control. The embedded systems

for industrial use are designed to carry out specific tasks such as monitoring the

temperature, pressure, humidity, voltage, current etc., and then take appropriate

action. The robotics are now becoming very powerful and carry interesting and

complicated tasks such as hardware assembly. To facilitate the control of

increasingly complex physical systems such as drive-by-wire automobiles and fly-by­

wire aeroplanes, embedded and networked computer systems with numerous

hardware and software components are increasingly required [1], Embedded systems

in which some specific task has to be done in a specific time period are called real­

time embedded systems. The development of embedded software was done mostly in

assembly languages. However, due to the availability of cross compiler, most of the

development is now in high-level languages such as ‘C\ Embedded systems are

omnipresent and play significant roles in modern-day life.

Tomorrow's embedded devices need to run multimedia applications demanding high

computational power with low energy consumption constraints [2]. The embedded

world has been one of the more mature and relatively steady segments of the

computing universe. Any embedded device can be made more flexible, useful, and

often less expensive by designing it as an intelligent. Traditionally, embedded devices

have been hardware-centric, and embedded software was relatively simple and

carefully designed to optimize performance, and minimize the memory footprint.

However, more than 70% of the development cost for complex system such as

automotive electronics and communication systems is attributable to software

development. This percentage is increasing constantly.

Traditional computer architecture/computer engineering curricula emphasize the

hardware and software fundamentals suitable to general purpose computing.

However, there is a growing realization that special purpose embedded systems

computing requires a different educational emphasis than general purpose computing.

The microcomputer is an embedded chip, which is typically used for control

applications, one emphasis must be on communications protocols with other devices

such as RS-232, SPI, I2C, or CAN. Similarly, for interactions with the non-digital

world, another emphasis must be on analog-to-digital and digital-to-analog

conversion. Because so many control applications are time-critical, another emphasis

must be on timing and interrupts represent only a small fraction of the total number of

microprocessor applications. By some estimates, more than 99% of all

Microcontroller-based systems is special-purpose embedded systems rather than

general-purpose computers. The Microcontroller in embedded systems are typically

optimized to perform a single task, often a control application.

An embedded system can be defined as a computing device that does a specific

focused job. Applications such as the air conditioner, VCD player, DVD player,

printer, fax machine, mobile phone etc. are examples of embedded systems. Each of

these applications will have a processor and special hardware to meet the specific

requirement of the application along with the embedded software that is executed by

the processor for meeting that specific requirement. The embedded software is also

called “firmware”. The embedded system market is one of the highest growth area as

these systems are used in the market segment of consumer electronics, office

automation, industrial automation, biomedical engineering, wireless communications,

data communication, telecommunications, transport, military and so on.

In an embedded system, the system software gets embedded with the application

software, where as it is vice versa in personal computers. The very essence of an

embedded system is iterative, step-wise execution of the embedded program with a

stream of data [3]. Embedded system has only one build i.e. only one executable file.

In this system the operating system is not a distinct entity. Only a required amount of

system software exists to assist the application software. One of the most critical

needs of an embedded system is to decrease power consumption, cost and space. This

can be achieved by integrating more functions in to the CPU chip. Programming

embedded systems is a special discipline and demands that embedded systems

developers have working knowledge of a multitude of technology areas. These areas

range from low-level hardware device, compiler technology, and debugging

techniques, to the inner working of real time operating systems and multithreaded


Microcontroller contains memories, I/O lines, timers/counters, interrupts and serial

communication. Using the Microcontroller is greatest advantage, in its reduced

hardware and increased efficiency. Typically, most embedded control systems are

designed around a Microcontroller, which integrates on chip program memory and

data memory and various peripherals such as timer/counters, serial communication,

I/O ports. Microcontrollers are used in different applications, especially in real time

applications. An embedded system product uses a Microcontroller to do one and only

one task. For example a printer is an embedded system since the Microcontroller

inside it performs one task only, namely getting the data and printing it.

3.2 Recent trends in embedded systems.

Embedded system is a complex object containing a significant percentage of

electronic devices (generally at least one Microcomputer) that interacts with the real

world (physical environment, human users, etc.) through sensing and actuating

devices. The system is heterogeneous, as it is characterized by the co-existence of a

large number of components such as Microcontroller and Digital Signal Processing,

as well as analog components such as A/D and D/A converters, sensors, transmitters

and receivers. In the past, the system design effort has focused on these hardware

parts, leaving the software design to be done afterwards as an implementation step.

New software technologies are important for the future of control (and vice versa) in

an age of increasing complexity [4], For new automotive applications and services,

information technology (IT) has gained central importance. IT-related costs in car

manufacturing are already high and they will increase dramatically in the future [5].

In the coming years, Ada runtime and COTS RTOS supporting Generalised Rate

Monotonic Scheduling (GRMS) have met the DO 178B flight control standard [6],

Embedded operating systems such as VRTX or PSOS were simple flat address space

kernels. However, the new embedded system is characterized by growing software

complexity where embedded software dominates the development cost and schedule.

Linux, for the first time in the industry, provides the potential of an open multi vendor

platform with an exploding base of software and hardware support. The growth in the

use of Linux in embedded systems over the past few years has been astonishing. The

success of Linux in the server or desktop arena over the last few years has received

the most attention, where the most ardent supporters of Linux are attempting to

loosen the strong hold of established operating systems such as Windows. In the

embedded marketplace, by contrast, Linux is already moving toward world


In the embedded operating system UNIX, management of the graphic display is split

between the X server, which knows the hardware and offers a unified interface to user

programs and the window and session managers, which implement a particular policy

without knowing anything about the hardware [7]. It can use the same windows

manager on different hardware, that can also run different configurations on the same

workstation. Even completely different desktop environments, such as KDE and

GNOME, can coexist on the same system. Another example is the layered structure

of TCP/IP networking, the operating system offers the socket abstraction, which

implements no policy regarding the data to be transferred, while different servers are

in charge of the services (and their associated policies). Moreover, server provides

the file transfer mechanism, while users can use whatever client they prefer; both

command-line and graphic clients exist, and anyone can write a new user interface to

transfer files.

A device driver plays a special role in the Linux kernel. They are distinct particular

piece of hardware, which respond to a well-defined internal programming interface.

User activities are performed by means of a set of standardized calls that are

independent of the specific driver mapping. Those calls to device-specific operations

that act on real hardware is then the role of the device driver. This programming

interface is such that drivers can be built separately from the rest of the kernel, and

"plugged in" at runtime when needed. This modularity makes Linux drivers easy to

write, to the point that there are now hundreds of them available. Recent trend in

laboratory as well as in industrial automation designs uses minimal hardware and

maximum support of software [8].

The rate at which new hardware becomes available (and obsolete!) alone guarantees

that driver writers will be busy for the foreseeable future. Individuals may need to

know about drivers in order to gain access to a particular device that is of interest to

them. Hardware vendors, by making a Linux driver available for their products, can

add the large and growing Linux user base to their potential markets. The open source

nature of the Linux system means that if the driver writer wishes, the source to a

driver can be quickly disseminated to millions of users. But most of the principles and

basic techniques are the same for all drivers. Multiprocessor systems, especially those

based on multi core or multithreaded processors, and new operating system

architectures can satisfy the ever increasing computational requirements of embedded

systems [9].

To make device drivers, choosing an acceptable trade-off between the programming

time required and the flexibility of the result is vital. A driver is "flexible” because it

emphasizes that the role of a device driver is providing mechanism, not policy. The

distinction between mechanism and policy is one of the best ideas behind the UNIX

design. Most programming problems can indeed be split into two parts: "what

capabilities are to be provided" (the mechanism) and "how those capabilities can be

used" (the policy). If the two issues are addressed by different parts of the program, or

even by different programs altogether, the software package is much easier to develop

and to adapt to particular needs.

The driver should deal with making the hardware available, leaving all the issues

about how to use the hardware to the applications. A driver, then, is flexible if it

offers access to the hardware capabilities without adding constraints. Model-Driven

Development (MDD) is an emerging paradigm that uses Domain-Specific Modeling

Languages (DSMLs) to provide 'correct-by-construction' capabilities for many

software development activities [10]. For example, a digital I/O driver may only offer

byte-wide access to the hardware in order to avoid the extra code needed to handle

individual bits. This privileged role of the driver allows the driver programmer to

choose exactly how the device should appear. Different drivers can offer different

capabilities, even for the same device. Many device drivers, indeed, are released

together with user programs to help with configuration and access to the target

device. Those programs can range from simple utilities to complete graphical

applications. Examples are the parallel port printer driver operation and the graphical

cadet utility, which adjusts the tunnel program that is part of the PCMCIA driver


The ASICs (Application Specific Integrating Circuits) is third significant trend

emerging in the embedded military market. A number of hardware/ software co­

design experiments to explore the design space and generate optimized

implementations for specific application requirements [11]. With the advantages of

small size, reliability, rapid response, compatibility to standard CMOS technology

and on-chip signal processing, Ion-Sensitive Field Effect Transistor (ISFET)-based

transducers are increasingly being applied in physiological -data acquisition and

environment monitoring [12]. To reduce development cost and avoid duplication of

design effort, FPGA prototypes and ASIC implementations are derived from a

common source. Application-specific processors offer an attractive option in the

design of embedded systems by providing high performance for a specific application

domain [13].

The FPGAs and CPLDs are becoming a popular alternative to ASICs, providing

integrators with an ideal alternative for satisfying feature/performance and

environmental/cost requirements while meeting pressing time-to-market and time-to-

deployment requirements. Unlike ASICs or custom circuits, the architecture of the

FPGA is not fixed prior and therefore the permitted programmability, connectivity,

and rout ability is constrained by that architecture [14]. Recent improvements in

FPGA products, including significantly larger gate counts and software tools for

development and integration, are now increasing their popularity. One of these

significant improvements is the use of high-speed serial ports to connect FPGAs to a

serial switching fabric, such as Rapid I/O. It uses Asymmetric SRAM (ASRAM)

(instead of high-Vt SRAM) cell to implement the configuration memory [15]. This

trend provides a natural, high-speed, bi-directional data path that enables data

movement at very high speeds. The FPGA is nonvolatile type and requires the battery

back to stable the program, where as CPLD is volatile type. The CPLD and FPGA use

VHDL or VeriLog language, as software. The Xillinx’s, Virtex-II, provirtex-V, Altera

software are test bench tools that support VHDL and Verilog languages. When

introducing VHDL, it is very important to keep emphasizing the fact that the VHDL

code is only describing the required behavior of the digital circuit or system and is not

being executed in some way by a ‘hidden’ interpreter or microprocessor on the FPGA

[16]. To reduce development cost and avoid duplication of design effort, FPGA

prototypes and ASIC implementations are derived from a common source.

Application-specific processors offer an attractive option in the design of embedded

systems by providing high performance for a specific application domain [13]. This

architecture is aimed at using hundreds of traditional reconfigurable field

programmable gate arrays (FPGAs) to build the SOLAR (self organizing learning

array) learning machine. SOLAR has many advantages over the traditional neural

network hardware implementation [17]. The use of commercial SRAM-based FPGAs

in satellites and spacecrafts present unique challenges in space radiation environment


Silicon Laboratories manufactures high performance industry’s smallest mixed

single-chip Microcontrollers. Technological advances have made it possible to

integrate on a single chip enormous number of transistors, thus allowing the inclusion

on a single chip of entire systems, including microprocessors, microcontroller,

memories, ASICs, and peripherals. The development of this new class of systems is

called Systems on Chip (SoCs) [19]. The wizard generates both the framework code

required to use the library and a project file that can be loaded into the Silicon

Laboratories software development system. Flexible real-time kernel, called Yartek, is

a low overhead and low footprint, suitable for embedded systems. Yartek has been

developed on a Cold fire microcontroller. An embedded system developed with

Yartek for the implementation of non-visual perception for mobile robots [20]. The

system for temperature measuring was realized based on microcontroller and a digital

temperature sensor [21]. Cygnal Microcontroller, which is used in the present study,

truly a standalone system-on-a-chip solution or embedded control chip. The

Microcontroller is available in 100 Pin TQFP semiconductor package and employs a

pipelined architecture that greatly increases its instruction throughout the standard

8051 architecture. Here Cygnal Microcontroller C8051F020 plays very important role

in the D.C motor control system. It is having a built -in 12-bit ADC, 10-bit ADC, two

12-bit DAC, 64K bytes programmable Flash memory, 256K bytes data RAM and 4K

bytes of XRAM, which are most essential requirements to control D.C motor speed

parameter. The Microcontroller has the following additional peripherals

1. On board JTAG (IEEE 1149.1).

2. 22 interrupt (Two priority levels)

3. Watch dog timer

4. Oscillator (2-16 MHz and External 25 MHz)

5. Five 16 bit (Timer/counter)

6. Two voltage comparator

7. Two UART, SPI and SMBus (I2C compatible)

8. Temperature sensor

9. 64 general I/Os (8 ports)

10. Programmable Counter Array (PCA)

In the present study, the design, development, fabrication, and analysis of

microcontroller based P, PI and PID logic controllers for DC motor speed control

systems are discussed. The work element consists of microcontroller circuits, which

by themselves act as specialized systems that internally contain some peripheral

resources that facilitate their work and their relation with the out side world [22].

However, short-bit-width processors (8 bit processor) continue to dominate

worldwide microcontroller sales volumes [23-25], In 2006, the 8-bit units have

continued to lead all microcontrollers in revenue and unit shipments [25],

Microcontrollers account for the majority of processors produced today, yet their

capabilities are seldom explored in modem computer science curriculum,

3.3 Details of Cygnal Microcontroller C8051F020

3.3.1 Introduction

The Cygnal Microcontroller device is fully integrated mixed-signal, system-on-chip

with 64 digital I/Os. It is a high speed pipelined 8051 compatible CIP-51

Microcontroller core and it can execute 25 million instructions per second. The

C8051F020 device is truly standalone system-on-a-chip solution. The advantages of

single chip Microcontroller is small size, reliability, rapid response, compatibility to

standard CMOS technology and on-chip signal processing, Ion-Sensitive Field Effect

Transistor (ISFET)-based transducers are increasingly being applied in physiological

data acquisition and environment monitoring [26], A single-chip programmable

platform that integrates most of hardware blocks required in the design of embedded

system chips. By integrating both the multithreaded processor and the configurable

logic on a single chip, high-level language-based designs can be easily accommodated

by performing the complex and concurrent functions of a target chip on the

multithreaded processor and implementing the external interface functions into the

configurable logic clusters [27], All analog and digital peripherals are

enabled/disabled and configured by user firmware. The flash memory can be

reprogrammed even in circuit i.e. it contains non-volatile data storage, and also

allowing field upgrades of the 8051 firmware.. On board JTAG (Joint Test Access

Group) debug circuitry allows non- intrusive (without disturbing on chip resources),

fully speed, and in-circuit debugging. This debug system supports inspection and

modification of memory and registers, setting breakpoints, watch points, single

stepping, run and halt commands to installing the production in the final application

of MCU. All analog and digital peripherals are fully functional while debugging using

JTAG. The MCU operating voltage and temperature range is specified 2.7V-to-3.6V

and -45°C to +85°C. The Microcontroller I/O ports, Reset (RST) and JTAG pin are

tolerable for input signal up to 5V.

3.3.2 Architecture

The C8051F020 available in a 100-pin TQFP package and employs a pipelined

architecture that greatly increases its instruction throughout over the standard 8051

architecture. In a standard 8051, all instruction except for MUL and DIV take 12 or

24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz.

The CIP-51 has a total of 109 instructions and it executes 70% of instructions in one

or two system clock cycles. The MCU has an internal, stand-alone clock generator,

which is used by default as the system clock after any reset. If desired, the clock

source may be switched on the fly to the external oscillator, which can use a crystal,

ceramic resonator, capacitor, RC, or external clock source to generate the system

clock. This can be extremely useful in low power applications, allowing the MCU to

run from a slow (power saving) external crystal source, while periodically switching

to the fast (up to 16 MHz) internal oscillator as needed.

Port 4
Port 5
Port 6
Port 7

Fig 3.1 Cygnal Microcontroller C8051F020 peripherals

The Cygnal Microcontroller has internal on chip memories i.e. program memory and

data memory. The program memory is used to store program permanently (non­

volatile memory) and the data memory is using to store the data (volatile). It consists

64K bytes of program memory (Flash) and data memory (RAM) is 256 bytes and 4K

bytes of additional memory. The CIP-51 has a standard 8051 program and data

address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes

dual-mapped. The upper 128 bytes is used as a general-purpose area in RAM which is

accessed in indirect addressing mode. The lower 128 bytes is used as a Special

Function Register (SFR) space, which accesses in direct addressing mode. Generally

all types of Microcontrollers consist only 128 bytes of RAM space. The 128 bytes of

RAM are accessible via direct and indirect addressing. The first 32 bytes are

addressable as four banks of general-purpose registers, which contains 0x00 to Ox IF

memory locations, and the next 16 bytes can be byte addressable or bit addressable. In

the four register banks (RB0-RB3) selecting only one enabled at a time, each bank

consists of eight byte registers designated R0 through R7. The Microcontroller

selecting default register bank RBO. The Register bank RB1-RB3 selecting through

the RSO and RSI control flags in a PSW (Program Status Word). This allows fast

context switching when entering subroutines and interrupt service routines. Indirect

addressing modes use registers RO and R1 as index registers. The CIP-51 in the

C8051F020 MCU additionally has an on chip 4K bytes of RAM block and an external

memory interface (EMIF) for accessing off-chip data memory (RAM). The on chip 4k

bytes block can be addressed over the entire 64K external data memory address range

(overlapping 4k boundaries). External data memory address space can be mapped

either to on-chip memory or to off chip memory, or a combination of the two (address

up to 4k directed to on-chip, above 4k directed to EMIF). The EMIF is also

configurable for multiplexed address/data lines. The Microcontroller Unit (MCU)

program memory consists of 64K bytes of flash. This memory may be reprogrammed

in system in 512 bytes sectors, and requires no special off-chip programming voltage.

The 512 bytes from addresses OxFEOO to OxFFFF are reserved for factory use.

The C8051F020 family has on chip JTAG boundary scan, debugs circuitry that

provides non-intrusive, full speed, in circuit debugging. The JTAG port is folly

compliant to IEEE 1149.1 and provides foil boundary scans for test and measurement

purposes. On-chip test techniques to reduce the dependence on external testers and to

improve high-frequency measurement accuracy have become a major focus in test

research and development [28]. The standard general-purpose eight ports (P0-P7) are

available on the MCU. In the eight ports, four ports (P0-P3) function as a I/O or bit

wise, like P1.0, P3.5 etc., and remaining ports (P4-P7) use only byte wise I/O. The

port I/O behaves like the standard 8051 with a few enhancements and it can be

configured as either a push pull or open drain output. Also, the “weak pull-ups” which

are normally fixed on an 8051 can be globally disabled, providing additional power

saving capabilities for low-power applications. Perhaps the most unique enhancement

is the digital crossbar. This is essentially a large digital switching network that allows

mapping of internal digital system resources to port I/O on P0, PI, P2, and P3. The

CPU (Microprocessor) with standard multiplexed digital I/O, all combinations of

functions are supported. This design can also be made as a standalone system without

PC by programming LED/ LCD display and keypad attachment modules in same

PSoC chip[30]. The four ports P0-P3 not only use I/O and also use same ports for on-

chip peripherals accessing or controlling. The on-chip peripherals are Counter/Timer,

serial buses, Hardware interrupts, ADC start of conversion input (SOC), comparator

output etc., which are configured to appear on the port I/O pins with the help of

specified Crossbar control registers. This allows the user to select the exact mix of

general-purpose port I/O and digital resources needed for the particular application.

The C8051F020 MCU includes an on-board programmable Counter/Timer array

(PCA) in addition to the five 16-bit general-purpose Counter/Timers. The PCA

consists of a dedicated 16-bit Counter/Timer time base with 5 programmable

capture/compare modules. The time base is clocked from one of six sources, the

system clock divided by 12, the system divided by 4, timer 0 overflow, an External

clock input (ECI), the system clock, or the external oscillator sources divided by 8.

Each capture/compare module-can be configured to operate in one of six modes, edge- •

triggered capture, software timer, high speed output, frequency output, 8bit or 16 bit

pulse width modulator. A related topic is pulse-width modulation which incorporates

timers and counters. Many embedded systems are very power-limited [30],

The MCU contains two-voltage comparators, the inputs of each comparator are

available at the package pins. The output of each comparator is optionally available at

the package pins via the I/O crossbar. When assigned to package pins, each

comparator output can be programmed to operate in open drain or push-pull modes.

The hysteresis of each comparator is software-programmable via its respective

comparator control register (CPTOCN and CPT1CN). The program can be both the

amount of hysteresis voltage and positive and negative-going symmetry of this

hysteresis around the threshold voltage. The output of the comparator can be read via

register variable or interrupt source mode with the help of embedded software. Each

comparator can be individually enable or disabled. When disabled, the comparator

output default to the logic low state, its interrupt capability is suspended and its

supply current falls to less than 1 pA. Comparator inputs can be externally driven

from -0.25V to +0.25V without damage or upset.

The CIP-51 includes an extended interrupts system supporting a total of 22 interrupt

sources with two priority levels. If interrupts are enabled for the sources, an interrupt

request is generated when the interrupt-pending flag is set. As soon as execution of

the current instruction is complete, the CPU generates an LCALL to a predetermined

address to begin execution of an interrupt service routine (ISR). Each ISR must end

with an RETI instruction. Each interrupt source can be individually enabled or

disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2

control register). Two of the external interrupt sources (INTO and INTI) are

configurable as active-low-level-sensitive or active-low edge-sensitive inputs

depending on the setting of bits ITO (TCON.O) and IT1 (TCON.2). IEO (TCON.l) and

IE1 (TCON.3) serve as the interrupt-pending flag for the INTO and INTI external

interrupts respectively. If an INTO or INTI external interrupt is configured as edge-

sensitive, the corresponding interrupt-pending flag is automatically cleared by the

hardware when the CPU vectors to the ISR.

The CIP-51 core has two software programmable power management modes, Idle and

Stop modes. Idle mode halts the CPU while leaving the external peripherals and

internal clocks active. In stop mode, the CPU is halted, all interrupts and timers

(except the missing clock detector) are inactive, and the system clock is stopped.

Since clocks are running in Idle mode, power consumption is dependent upon the

system clock frequency and the number of peripherals left in active mode before

entering Idle. Stop mode consumes the least power describing the power control

register PCON in CIP-51 power management mode. Using these advanced techniques

to save power and energy for commodity 8-bit microcontrollers while leveraging their

built-in low-power modes [31J.

The MCU includes a programmable watchdog timer [WDT] running off the system

clock. A WDT overflow will force the MCU into the reset state. To prevent the reset,

the WDT must be restarted by application software before overflow. If the system

experiences a software/hardware malfunction preventing the software from restarting

the WDT, the WDT will overflow and cause a reset. This should prevent the system

from running out of control. Following a reset the.WDT is automatically enabled and

running with the default maximum time interval. If desired the WDT can be disabled

until the next system reset. The state of the RST pin is unaffected by this reset. The

WDT consists of a 21-bit timer running from the programmed system clock. The

timer measures the period between specific writes to its control register. If this period

exceeds the programmed limit, a WDT reset is generated. The WDT can be enabled

and disabled as needed in software, or can be permanently enabled if desired.

Watchdog features are controlled via the watchdog timer control register WDTCN.

3.2.3 12 -bit analog to digital converter (A/D)

The C8051F020 consists two ADCs that are ADCO (12 bit) and ADC1 (8 bit). The

ADCO subsystem consists of a 9-channel, configurable analog multiplexer (AMUXO),

a programmable gain amplifier (PGAO), and a 100 kilo samples for second , 12-bit

successive-approximation-register ADC with integrated track-and-hold and

Programmable Window Detector. The AMUXO, PGAO, Data Conversion Modes, and

Window Detector are all configurable under software control via the Special Function

Registers. The ADCO reference voltages are selected through voltage reference

control register (VREF). The ADCO Control register ADCOCN contain, controls for

ADCO, track-and-hold and PGAO. Eight of the AMUX channels are available for

external measurements while the ninth channel is internally connected to an on-chip

temperature sensor. AMUX input pairs can be programmed to operate in either

differential or single-ended mode. This allows selecting the best measurement

technique for each input channel, and even accommodates mode changes "on-the-fly".

The current and voltage parameters are acquired with the help of data converter [32],

The AMUX defaults to all single-ended inputs upon reset. There are two registers

associated with the AMUX: the Channel Selection register AMXOSL, and the

Configuration register AMXOCF. The PGA amplifies the AMUX output signal by an

amount determined by the states of the AMP0GN2-0 bits in the ADCO Configuration

register, ADCOCF. The PGA can be software-programmed for gains of 0.5, 2, 4, 8 or

16. Gain defaults to unity on reset.

The ADCO conversion speed is 100-kilo samples per second [ksps], its clock is

derived from the system clock divided by the value held in the ADCSC bits of register

ADCOCF. A conversion can be initiated in one of the four ways, depending on the

programmed states of the ADCO Start of Conversion Mode bits (AD0CM1,

AD0CM0) in ADCOCN. Conversions may be initiated by

1. Writing a ‘1’ to the ADOBUSY bit of ADCOCN;

2. A Timer 3 overflow (i.e. timed continuous conversions);

3. A rising edge detected on the external ADC convert start signal, CNVSTR;

4. A Timer 2 overflow (i.e. timed continuous conversions).

The ADOBUSY bit is set to logic 1 during conversion and restored to logic 0 when

conversion is complete. The falling edge of ADOBUSY triggers an interrupt (when

enabled) and sets the ADOINT interrupt flag (ADC0CN.5). Converted data is

available in the ADCO data word MSB and LSB registers, ADCOH, ADCOL.

Converted data can be either left or right justified in the ADCOH: ADCOL register

pair depending on the programmed state of the ADOLJST bit in the ADCOCN register.

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Fig 3.2: block diagram of 12-bit ADCO Control registers

When initiating conversions by writing a ‘1’ to ADOBUSY, the ADOINT bit should

be polled to determine when a conversion has completed (ADCO interrupts may also

be used). The recommended polling procedure is shown below.

Step 1. Write a ‘O’ to ADOINT;

Step 2. Write a ‘ 1’ to ADOBUSY;

Step 3. Poll ADOINT for ‘1’;

Step 4. Process ADCO data.

In the tracking mode, each conversion is preceded by a tracking period of 3 SAR

clocks (after the start-of-conversion signal). When the CNVSTR signal is used to

initiate conversions in low-power tracking mode, ADCO tracks only when CNVSTR

is low; conversion begins on the rising edge of CNVSTR. Tracking can also be

disabled when the entire chip is in low power standby or sleep modes. Low-power

track and-hold mode is also useful when AMUX or PGA settings are frequently

changed, to ensure that settling time requirements are when the ADCO input

configuration is changed (i.e., a different MUX or PGA selection is made), a

minimum settling (or tracking) time is required before an accurate conversion can be

performed. In this low-power tracking mode, three SAR clocks are used for tracking

at the start of every conversion.

AMXOCF: AMUXO Configuration Register (C8051F020)


- - AIN671C AIN451C AIN231C AINO 11C

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO

Bits 7-4: UNUSED, Read =0x0000, Write =don’t care

Bit 3: AIN671C: AIN6, AIN7 Input Pair Configuration Bit

0: AIN6, and AIN7 are independent single-ended inputs

1: AIN6, AIN7 are (respectively) +, - differential input pair

Bit 2: AIN671C: AIN4, AIN5 Input Pair Configuration Bit

0; AIN4 and AIN5 are independent single ended inputs

Bit 1: AIN231C: AIN2 and AIN3 are independent single ended inputs

0: AIN2 and AIN3 are single ended inputs

1: AINO, AIN 1 are (respectively) +,- differential input pair

AMXOSL: AMUXO Channel Select Register (C8051F020)


“ - - AIN671C AIN451C AIN231C AIN011C

Bit7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 BitO

Bit 7-4: UNUSED Read =0000b; Write= don’t care

Bit 3-0: AMXO AD3-0; AMXO Address Bits

0000-1111b; ADC Inputs selected per chart below

3.3.4 Voltage reference (VREF)

The reference circuit offers full flexibility in operating the ADC and DAC modules.

Three-voltage reference inputs allow each ADC and the two DACs to reference an

external voltage reference or the on chip voltage reference output. The ADC0 may

also reference the DAC0 output internally and ADC1 may reference the analog power

supply voltage via the VREF multiplexers.

The internal voltage reference circuit consists of a 1.2V band-gap voltage reference

generator and a gain of two output buffer amplifier. The internal reference may be

routed via the VREF to external system components or to the voltage reference input.

Bypass capacitors are recommended from the VREF to AGND.

The Reference control register, REF0CN enables/disables the internal reference

generator and selects the reference inputs for ADC0 and ADC 1.The BIASE control

bit in REF0CN enables the on board reference generator while the REFBE bit enables

the gain-of-two buffer amplifier which drives the VREF. When disabled, the supply

current drawn by the band-gap and buffer amplifier falls to less than IpA and the

output of the buffer amplifier enters a high impedance state. If the external band-gap

is used as the reference voltage generator, BIASE and REFBE must both be set to

logic l.If the internal reference is not used, REFBE may set to logic 0. Note that the

BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether

the voltage referenced is derived from the on-chip reference or supplied from the off-

chip reference. If neither the ADC nor DAC are being used, both of these bits can be

set to logic 0 to conserve power. Bits ADOVRS and AD1VRS select the ADCO and

ADC1 voltage reference sources respectively. The electrical specifications for the

voltage reference circuit.

The temperature sensor available in the Microcontroller connects to higher order input

of the multiplexed 12 bit Analog to digital converter ADCO, when the control bit

TEMPE bit enabled in the Reference Control Register REFOCN. While disabled, the

temperature sensor defaults to a high impedance state and any A/D measurements

performed on the sensor input place.

REFOCN: Reference control register



Bit 7-5: UNUSED Read=0000b;Write=don’t care

Bit4: ADOVRS:ADCO Voltage Reference Select

0:ADC0 voltage reference from VREF pin

1:ADC0 : voltage reference from DACO output.

Bit3: : ADlRS:ADClVoltage Reference Select

0:ADC 1 voltage reference from VREF1 pin

1 :ADC1 ivoltage reference from AV+

Bit2: TEMPE :Temperature sensor enable bit.

0:lntemal temperature sensor off.

1 -.Internal temperature sensor on.

Bitl: Biase:ADC/DAC bias generator enable bit

0 internal bias generator off

1 :intemal bias generator on

BitO: REFBE:Intemal reference buffer enable bit.

0:lntemal reference buffer off.

1: Internal reference buffer on. Internal voltage reference is driven on the

VREF pin

Fig 3.3 ADC and DAC Voltages References functional block diagram

. 3.3.5 12 -bit digital to analog converter (D/A)

Each C8051f020/l/2/3 device includes two on-chip 12-bit voltage mode digital to

analog converter (DACs).Each DAC has an output swing of OV for a corresponding

input code range of 0x000 to OXfff.The DAC may be enabled/disabled via their

corresponding control registers.DACOCN and DAC1CN while disabled, the DAC

output is maintained in a high-impedance state, and the DAC supply current falls to

IpA or less. The voltage reference for each DAC is supplied at the VRED pin or the

VREF pin. The VREF device may be enabled in order for the DAC outputs to be

valid. Each DAC features a flexible output update mechanism which allows for

seamless full scale changes and supports jitter-free updates for waveform generation.

The following examples are written in terms of DACO, but DAC1 operation is

identical. Reads from DACOL return pre-latch data, meaning the value read is the

same as the last value written to this register, not the value at the DACOL latch. Reads

from DACOH always return the value at the DACOH latch. The Microcontroller

contains mixed array logic of analog, digital and digital communication blocks within

in it.


Fig 3.4 block diagram of DACO Functional Control register

In its default mode the DACO output is updated “on-demand” on a write to the high-

byte of the DACO data register. It is important to note that writes to DACOL are held

and have no effect on the DACO output until a write to DACOH takes place. If writing

a full 12-bit word to the DAC data registers, the 12-bit data word is written to the low

byte and high byte data registers. Data is latched into DACO after a write to the

corresponding DACOH register, so the write sequence should be DACOL followed by

DACOH if the full 12-bit resolution is required. The DAC can be used in 8-bit mode

by initializing DACOL to the desired value and writing data to only DACOH


Fig 3.5 block diagram of DAC1 Functional Control register

Update Output Based on Timer Overflow: Similar to the ADC operation, in which

an ADC conversion can be initiated by a timer overflow independently of the process,

the DAC output can use a Timer overflow to schedule an output update event. This

feature is useful in systems where the DAC is used to generate a waveform of a

defined sampling rate by eliminating the effects of variable interrupt latency and

instruction execution on the timing of the DAC output. When the DACOMD bits are

set to 01, 10 or 11 writes to both DAC data registers are held until an associated

Timer overflow event occurs, at which time the DAC0H:DAC0L contents are copied •

to the DAC input latches allowing the DAC output to change the new value.

iwr R/W R/W R/W R/W R/W R/W Resit Value

Bit7 Bit6 BiiJ BW Bit} Bil2 Bitl BitCi SFR Address:

Bit7: DACOEN: DAOO Enable Bit

ft DACO Disabled. DACO Output pin is disabled; DACO is in low-power shutdown mode
1: DACO Enabled. DACO Output pin is active; DAOO is operational.
Bits6-5: UNUSED. Read = 00b; Write = dent care,
Bits4-3: DACOMDl-O: DAO) Mode Bits.
00: DAC maput updates occur on a write to DACOH,
01: DAC output updates occur on Timer 3 overflow,
lft DAC cutput updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
Bitd-Ci: DACDDF2-0: DACO Data Format Bits:

000: The most significant nibble of the DACO Data Word is in DACOH] 3:0], while the least

■U UslB | | | | | i i DACIL
i i 1 i..... nl|
001; The most significant 5-bits of the DACO Data Word is in DAC0H|4:0], while the least
stanifkant 7-Wta are in DAOQL17 11
■ r:"“r fT-~- '
1 ___111I1 DACIL
1 1 1 1 1 lsb Mmr|I
01ft The most significant 6-bits of the DACO Data Word is in BAC0H[5;0], while the least
significant 6-bits are in DACOLf7:2].
pBEl_ . j..._j____i 1 1 1 I
Oil: The most significant 7 -bits of the DACO Data Word is in DAC0H[6:O], while the least
significant 5-bits are in DACDLf 7:3],
liilq MSB | i r ] i
............... i T t
lxxi The most significant 8-bits of the DACO Data Word is in DAC0H[7:0], while the Least
significant 4-bits are in DAOQLf7:41.
J___1111______ 1 i i lsb
Fig 3.5 DAC [high and low byte) 12 bits selection Control Register

In some instances, input data should be shifted prior to a DACO write operation to

properly justify data within the DAC input registers. This action would typically

require one or more load and shift operations, adding software overhead and slowing

DAC throughput. To.alleviate this problem, the data-formatting feature provides a

means for the user to program the orientation of the DACO data word within data

registers DACOH and DACOL. The three DACODF bits (DAC0CN.[2:0]) allow the

user to specify one of five data word orientations as shown in the DACOCN register

definition. DAC1 is functionally and electrical specifications are same as DACO.

3.3.6 Port Input/Output

The C8051F020/1/2/3 are fully integrated mixed-signal System on Chip MCUs with

64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3), organized as

8-bit Ports. The lower ports: PO, PI, P2, and P3, are both bit- and byte-addressable

through their corresponding Port Data registers. The upper ports: P4, P5, P6, andP7

are byte-addressable. All Port pins are 5 V-tolerant, and all support configurable

Open-Drain or Push-Pull output modes and weak pull-ups.

3.3.7 Serial communication

Serial data transmission has become so important to the overall computing strategy of

industrial and commercial applications. This standard was enhanced in the early

1960’s with the establishment of an electrical/mechanical specification for serial data

transmission that was assigned that number RS 232 by the electronics industry

association. Physically the data is a series of voltage levels that re sampled, in the

center of the bit period, at a frequency that is determined by the serial data mode and

the program that controls that mode. The serial port present on the microcontroller

chip is used for development/testing/debugging (monitor) of the application software

[33]. —__ ___________

9 • I ^ \JF »•*»>'

UARTO is an enhanced serial port with frame error detection and address recognition

hardware. UARTO may operate in full-duplex asynchronous or half duplex

synchronous modes, and multiprocessor communication is fully supported. Received

data is buffered in a holding register, allowing UARTO to start reception of a second

incoming data byte before software has finished reading the previous data byte.

UARTO is accessed via its associated SFRs, Serial control (SCONO) and Serial Data

Buffer (SBUFO).

UART-1 (RS-232 Communication! Specification

S.No Serial controller register 1,8 bit UART, enable RX


1 Timer Mode (TMOD) Timerl ,mode 2, 8-bit Auto reload

2 Baudrate 11,5000

3 System clock external 22 MHz

4 Power control register(PCON) Serial mode (Normal)

The single SBUFO location provides accesses to both transmit and receive registers.

UARTO may be operated in polled or interrupt mode. UARTO has a two Transmit

interrupt flag, TIO (SCONO. 1) set when transmission of a data byte is complete, and a

receive interrupt flag, RIO(SCONO.O)s Et when reception of a data byte is completed.

UARTO interrupt flags are not cleared by hardware when the CPU vectors to the

interrupt service routine, they must be cleared manually by software.


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