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* PG Scholar, Department of Electrical Engineering, Politecnico di milano, Milan, Italy.
** Research Scholar, Department of Electrical Engineering, Vignan's Foundation for Science, Technology & Research, Andhra Pradesh, India.
*** Department of Electrical Engineering, Vignan's Lara Institute of Technology & Science, Guntur, Andhra Pradesh, India.

Date Received: 23/05/2018 Date Revised: 13/08/2018 Date Accepted: 28/08/2018

In this paper, a new power factor correction circuit known as bridgeless Single Ended Primary Inductor Converter (SEPIC)
is designed for universal input voltage applications. Now-a-days, entire electrical grid is connected with non-linear
loads, so there is a need to improve power factor implied on the grid as well as power quality. The main drawbacks of the
conventional SEPIC PFC is lower efficiency due to the conduction losses of the diodes. To improve efficiency of the
system, a modified bridgeless SEPIC converter is proposed in this paper. The proposed modified PFC converter offers
higher operating efficiency with high gain. The high gain is obtained by multiplier circuits. The main advantages of the
proposed system are that diode bridge circuits is completely eliminated for conventional circuits and also the control
circuit is very simple. The proposed converter is analysed in terms of THD and also gain of the converter is analysed with
respect to the different duty cycle varying from 10% to 90%. The proposed converter is analysed with mathematical
expressions. The results of the modified PFC have been verified using MATLAB Simulink.
Keywords: Bridgeless SEPIC Converter, High Gain, Multiplier Cell, Non-linear Loads, PFC.

INTRODUCTION The DC electrical power efficiency increases from one

The SEPIC (Single Ended Primary Inductor Converter) is a voltage level to another. DC-DC converter can be viewed
DC-DC converter and it is used to convert DC voltage as the DC transformer that delivers a DC voltage or current
either less than or greater than the input voltage (Verma at a different levels than the input source. DC-DC
& Kumar, 2016). This type of converter is mainly preferred converter is non-linear in nature due to which, it is a
i n c h a r g e r s, S M P S, e l e c t r o n i c b a l l a s t, a n d challenge for control and power electronics engineers to
telecommunication applications (Ganesh et al., 2017). control the DC-DC converter voltage levels (Liu et al.,
The output voltage of SEPIC converter is varied by the duty 2009). The different types of DC-DC converters are
cycle of the switch. The MOSFET is preferred for low power available among these converters, a SEPIC is selected for
applications and IGBT is used for switch power power factor correction purpose (Mahdavi &
applications. In an electrical power system, unlike AC, DC Farzanehfard 2014). The basic SEPIC converter is formed
cannot simply be stepped up or down using a from boost converter. By adding another capacitor and
transformer. Here an electronic device like DC-DC inductor in a boost converter design, it will formed as a
converter is used to change input voltage either greater SEPIC PFC converter. At low and high power applications,
than or less than the input voltage. DC-DC Boost converter SEPIC converter is prefered because it has a high voltage
has been used to boost up input voltage. The boosted rating compared with the Boost converter (Kumar,
output voltage greater than 5-6 times of the input voltage 2016).The power devices MOSFET and IGBT may be used
are possible (Mahdavi & Farzanehfard, 2011). for design of SEPIC converter. MOSFETs are most suitable
for low power and high frequency applications, whereas

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medium and high power applications like IGBT is a highly converter has been tested through MATLAB Simulink. The
suitable device (Ismail, 2009). The SEPIC converter is performance of the system is analysed in terms of THD
mainly used for Buck-Boost operations, but SEPIC is usually and voltage gain.
prefered compared to a buck-boost. Here only the 1. Conventional SEPIC Converter Topology
capacitor and inductor causes a high amount of ripples
Mostly in power electronics, boost/buck–boost converter
and harmonics of input current. The major issue with the
topologies are used for power factor correction at their
buck-boost converter is that it inverts the output voltage.
front end due to its High Power Factor (HPF) capability (Ki et
This problem is eliminated in CUK converter, but it creates
al., 2006). However, a conventional SEPIC PFC converter
an ample amount of electrical stress in components
has lower efficiency due to significant conduction losses
(Jasmine & Raj, 2014). This can result in device failure or
in the diode bridge. During each switching cycle interval,
overheating. SEPIC will solve the above problems without
the current flows through three power semiconductor
any harm to components and also a cheap solution to
devices (Cho et al., 1998). The forward voltage-drop
problems with less electrical stress and overheating. The
across the bridge diodes degrades the converter
output of the SEPIC is controlled by duty cycle of the
efficiency, especially at low-line input voltage.
control switch. Input side AC-DC conversion done by one
In conventional SEPIC, the output ground is always
bridge rectifier is called a conventional SEPIC PFC
connected to an AC source through full bridge, due to
converter (Onal & Sozer, 2016).
this, the common mode rejection noise is low.
Active PFC can be implemented by controlling the
2. Bridgeless Modified Sepic Converter Topology
conduction time of the converter switches to force the AC
The conventional SEPIC converter is shown in Figure 1. A
current to flow the waveform of applied voltage (García,
systematic review of the bridgeless SEPIC PFC
et al., 2003). Active PFC have mostly two techniques. In
implementation that have received the most attention
two stage scheme, AC-DC converter and DC-DC
has been presented.
converter are cascaded to provide electrical isolation
and good voltage regulation. A non-isolated PFC AC-DC Power electronic engineers have concentrated on many
converter is used to create intermediate DC bus in the two possible ways to minimize power losses in DC-DC
stage scheme (Kishore & Tripathi, 2017). This DC bus converters. Many power and semi-conductor devices
voltage contains full of second harmonic ripples. The and manufacturing industries have started looking into
merit of this scheme is that two stages can be controlled bridgeless circuit topologies in order to reduce the
separately so this makes both the converters optimized. conduction loss by decreasing the use of a number of
But it has so many drawbacks, such as lower efficiency semi-conductor components in the line path. The
due to twice conversion process, complex in control bridgeless SEPIC converter has significantly larger
circuits, the high cost, and low reliability. Considering common-mode noise compared with the conventional
these drawbacks, one stage scheme comes into action. SEPIC converter. In conventional SEPIC, the output ground
One stage scheme combines PFC circuit and power is always connected to an AC source through full bridge.
conversion circuit and due to its simplified structure, it I L1 I C1 ID

works with more efficiency. However, it has a very slow L

C1 D
dynamic response. D1 D3

I Co Ra
In this paper, performance, and comparison between VS
Co Load
IL 2
conventional and bridgeless SEPIC converter are mainly
focussed. In bridgeless converter, common mode D2 D4

rejection noise is high with pulsated high frequency

voltage. The results of the proposed modified SEPIC Figure 1. Conventional SEPIC Converter

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In bridge rectifier, D3 and D4 acts as slow diodes, which minimize input ripple current, as well as the EMI noise level
are used to make a connection with the output ground is also minimized (Mahdavi & Farzanehfard, 2011; Onal &
(Bachok et al., 2015). Sozer, 2016).
In bridgeless SEPIC, the output ground is directly 3. Design and Analysis
connected to AC source only. During operation in the The high gain bridgeless SEPIC converter has two
negative half line cycle, the output ground is pulsated with symmetrical configurations, such as positive half line
High Frequency (HF) related to the AC source. This high configuration and negative half line configuration. The
frequency pulsating voltage source charges and switching time (Ts) is switching period of the converter, the
discharges the equivalent parasitic capacitance inductors L1, L2, and L0 are operating in a discontinuous
between output ground and AC line ground, resulting in conduction mode. During the positive half line mode, the
significantly increased common-mode noise (Ikeda et Ts period is divided into three operating stages. Here the
al., 2016). switches Q1 and Q2 have same control signal, which has a
2.1 Principle of Operation simple control strategy (García et al., 2003).
Figure 2 shows the modified bridgeless SEPIC PFC Stage-1: In this mode, with the positive half line control
converter with voltage Multiplier cell. The multiplier cell is signal, switch Q1 is ON and both diodes D1 and D0 are
formed with D1, D2, and C3 elements and due to bridgeless reverse biased. During this stage, the three inductors L1, L2,
topology, conduction losses will be reduced. Dp and Dn and L0 currents are increased linearly with proportional to
are always connected across AC terminals and called as the input voltage.
slow diodes, which are used to stabilize the output to
ground voltages and reduce common mode
Electromagnetic Interferences (EMI). The modified SEPIC
Stage-2: In this mode, the switch Q1 is turned OFF and both
converter configuration will operate in two modes that
diodes D1 and D0 conducted are forward biased. The
divides the half line cycle. The circuit has two non-floating
three inductors will discharge their current through
switches such as Q1 and Q2; the switch Q1 is ON or OFF
capacitor C1 and voltage VC1 is obtained. When the
during the positive half line cycle of input voltage and
inductor current comes to zero, the diodes are reversed
Switch Q2 is ON or OFF during the negative half line cycle
biased (Ki et al., 2006; Bachok et al., 2015).
of input voltage. When Q1 is ON the current flows back to
the source through Dp and when Q2 is ON, the current flows
back to source through Dn. The inductors L1, L2, and L0 are (2)
magnetically coupled into a single magnetic core to Stage-3: Diodes D1 and D0 are reverse biased and switch
D0 Q1 remains turned OFF. Diode Dp provides a path for IL0 and
the three inductors current is at constant.
C1 C2 The design of the bridgeless SEPIC converter circuit will be
analyzed with the component and the calculated values
L1 iL1 D1 are taken for simulation.
C0 VO RL 3.1 Voltage Transformation Ratio (M)
L2 iL2
The average diode current over half one line cycle is
Q1 Q2
Dp Dn C3
where TL is the time period of line voltage.
Figure 2. Modified Bridgeless SEPIC Converter

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ID0 is the average output diode current.

3.2 Input Current and Effective Input Resistance (12)
The output current over switching cycle is represented by, 3.5 Output Capacitor Design
To minimize the output voltage ripple, the output
(4) capacitor value must be high and along with the output
voltage ripple, frequency is twice the input line frequency.
Output voltage ripple is equal to 2% of output voltage.
where (5)


From Figure 3, it is observed that a modified SEPIC
Let us take a lossless converter with power balance
converter operates at high voltage gain compared to
conventional SEPIC converter. The voltage gain of the
converter against duty cycle is shown in Figure 3.
Substitute equations (4) and (5) in (8).
4. MATLAB/Simulation Results
A PFC-Bridgeless SEPIC converter with Multiplier Cell for
universal input voltage applications have been simulated
From equation (9), the Harmonic Distortion in current using MATLAB siumlink. The results of the proposed SEPIC
waveform is explained based on the value of M. converter with multiplier cell are presented in this section.
If M has high value, the line current, which is less distorted is The simulation results of the conventional and modified
almost sinusoidal. On the other hand, if the M value is low, system were presented and also the duty cycle against
it shows high distortion in current with an increased gain is presented. The power rating of the system is 200 W
harmonic content (Kishore & Tripathi, 2017). with input voltage of 120 V. the switching frequency is 50
3.3 Inductor Design KHz. The parameters used for simulation is presented in

Based on inductor ripple, the inductor values are shown Table 1.

below. 4.1 Conventional SEPIC Converter

The MATLAB simulink model of the conventional SEPIC

(10) converter is shown in Figure 4. The simulation results of the

The maximum Inductor current ripple is found on peak

input current ∆ iL1-max = 10% of iac peak
Substitute calculated L1, L2 and L0
3.4 Intermediate Capacitor Design
The C1 and C2 are very important in converter design.
Those are used for energy transfer; their values are highly
influenced on the quality of input current. The C1 and C2
values depends on Line, resonant, and switching
frequencies (Cho et al.,1998).
(11) Figure 3. Converter Voltage Gain - a Function of the Duty Cycle

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Parameters Value current and it is shown in Figure 4.

Input voltage 120 V 4.2 Bridgeless SEPIC converter with Multiplier Cell
Inductors L1, L2 and L0 2.2, 2.2 mH and 180 uH
Capacitors C1=C2=C3 1.2 uF
Figure 7 shows simulink model of a bridgeless SEPIC
Switching frequency 50 Khz converter. Figure 8 shows input current and input voltage.
Power 200 W Initially, the input current having ripples is appeared due to
Table 1. Simulation Parameters pulsated high frequency components presented in the
Figures 9 and 10 show the simulation results of SEPIC
converter Inductor currents and capacitor voltages. The

Figure 4. Simulink Design for the Conventional SEPIC Converter

conventional SEPIC converter, such as input, inductor,

and switching currents are shown in Figure 5. The input
and output voltage of the conventional SEPIC converter is
shown in Figure 6. The charging and discharging of
Figure 7. Simulink of a Modified Bridgeless SEPIC Converter
inductor currents and the output of converter shows
ripples and also the ripples are presented in the input

Figure 8. Input current and voltage of the converter

Figure 5. Conventional SEPIC Converter Input,
Inductor and Switch Current

Figure 6. Input Voltage and Output Voltage Figure 9. Inductor Currents of the Converter

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Figure 10. Capacitor Voltages of Converter

charging and discharging of inductor currents and

capacitor voltages show converter operation and ripples
in input current.
Figure 11 shows the SEPIC converter output voltage with Figure 12. Simulated and Experimental Harmonic Spectrum
for Input Line Current of the Conventional Full Bridge
magnitude 415 V and output current with 15 A Magnitude. Converter at an Input Voltage
This voltage is mainly used in high input AC voltage
applications. It has less ripples in output compared to
conventional circuit. Common mode rejection noise is
also minimized.
Figures 12 and 13 show the THD analysis of the
conventional SEPIC and modified SEPIC converter.
The THD of the proposed system is 10.91%, whereas THD of
the conventional system is 49.95%. From the figures, it is
clearly observed that the proposed system offers less THD
compared to conventional one.
The gain comparison of conventional and modified
system is given in Table 2. From the table, it is observed
that the modified SEPIC converter offers high gain
compared to the conventional converter.
Conclusion Figure 13. Simulated and Experimental Harmonic
Spectrum for Input Line Current of the Converter
In this paper, a systematic review of bridgeless power at an Input Voltage of 120 Vrms
factor correction SEPIC converter is presented.
Duty Cycle (%) Gain for Conventional Gain for Modified
SEPIC Converter SEPIC Converter
10 0.17 1.06
20 0.35 1.47
30 0.53 1.76
40 0.66 1.77
50 0.79 1.77
60 1.49 1.77
70 1.63 1.77
80 1.63 1.73
90 1.63 1.77

Table 2. Gain Comparison with Conventional

Figure 11. Output Voltage and Current of Bridgeless SEPIC Converter and Modified SEPIC Converter

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Ganesh Yamavarapu is currently pursuing his Masters in the Department of Electrical Engineering at Politecnico di milano, Milan,
Italy. He received his B.Tech, in Electrical and Electronics Engineering from Jawaharlal Nehru Technological University, Kakinada,
Andhra Pradesh, India and M.Tech. in Power Electronics and Drives from Vignan Foundation for Science, Technology and
Research University, Guntur, Andhra Pradesh, India. His current research interests, include Smart Electric Grids, Electricity Market,
Electrical Switching Devices, Power Electronics, DC-DC Converter, Communication Systems in Electrical Grids, and Photovoltaic
Based System Design.

Dasari Manikanta Swamy is currently pursuing his Ph.D. in the Department of Electrical Engineering at Vignan Foundation for
Science, Technology and Research University, Guntur, Andhra Pradesh, India. He received his B.Tech, in Electrical and Electronics
Engineering from Vignan Foundation for Science, Technology and Research University, Guntur, Andhra Pradesh, India, in 2015,
and M.Tech. in Power Electronics and Drives from Vignan Foundation for Science, Technology and Research University, Guntur,
Andhra Pradesh, India. His current research interests include Power Electronics, DC-DC Converter, Multilevel Inverter, and
Photovoltaic Based System Design.

Dr. Venkatesan Mani is currently associated with the Department of Electrical Engineering at Vignan's Lara Institute of Technology
& Science, Guntur (Dt), India. He received his B.E., in Electronics and Communication Engineering from Anna University, Chennai,
Tamil Nadu, India, M.E. in Power Electronics and Drives from Government College of Technology, Coimbatore, Tamil Nadu, India,
and Ph.D. in Power Electronics from Anna University, Chennai, Tamil Nadu, India. His current research interests, include Power
Electronics, DC-DC Converter, Multilevel Inverter, PV Based System Design. He is life Associate member of the Institution of
Engineers (India).

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