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# Outline Introduction

##  Introduction  So far, we have treated transistors as ideal switches

 MOS Capacitor  An ON transistor passes a finite amount of current
 nMOS I-V Characteristics – Depends on terminal voltages
 pMOS I-V Characteristics – Derive current-voltage (I-V) relationships
 Gate and Diffusion Capacitance  Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 1 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 2

## MOS Capacitor Terminal Voltages

 Gate and body form MOS  Mode of operation depends on Vg, Vd, Vs Vg

capacitor – Vgs = Vg – Vs + +
V <0
polysilicon gate V gs V gd
 Operating modes g

+
silicon dioxide insulator
– Vgd = Vg – Vd - -
- p-type body
– Accumulation – Vds = Vd – Vs = Vgs - Vgd Vs
- +
Vd
Vds
– Depletion (a)  Source and drain are symmetric diffusion terminals
– Inversion – By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation

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nMOS Cutoff nMOS Linear
 No channel  Channel forms
 Ids ≈ 0  Current flows from d to s
V > Vt
– e- from s to d Vgd = Vgs
gs
+ g +
- -
Vgs = 0 Vgd
+ g +  Ids increases with Vds s d
Vds = 0
- - n+ n+
s d  Similar to linear resistor p-type body
n+ n+ b

## p-type body Vgs > Vt

Vgs > Vgd > Vt
b + g +
- - Ids
s d
n+ n+
0 < Vds < Vgs -Vt
p-type body
b

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 5 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 6

## nMOS Saturation I-V Characteristics

 Channel pinches off  In Linear region, Ids depends on
 Ids independent of Vds – How much charge is in the channel?
 We say current saturates – How fast is the charge moving?
 Similar to current source

Vgs > Vt
g V gd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 7 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 8

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Channel Charge Carrier velocity
 MOS structure looks like parallel plate capacitor  Charge is carried by e-
while operating in inversions  Electrons are propelled by the lateral electric field
– Gate – oxide – channel between source and drain
 Qchannel = CV – E = Vds/L
 C = Cg = eoxWL/tox = CoxWL Cox = eox / tox  Carrier velocity v proportional to lateral E-field
 V = Vgc – Vt = (Vgs – Vds/2) – Vt – v = mE m called mobility
gate  Time for carrier to cross channel:
Vg
+ +
polysilicon
gate source Vgs Cg Vgd drain – t=L/v
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, eox = 3.9) p-type body
p-type body

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 9 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 10

## nMOS Linear I-V nMOS Saturation I-V

 Now we know  If Vgd < Vt, channel pinches off near drain
– How much charge Qchannel is in the channel – When Vds > Vdsat = Vgs – Vt
– How much time t each carrier takes to cross  Now drain voltage no longer increases current
Qchannel V
I ds  I ds    Vgs  Vt  dsat Vdsat
t  2
W V
 Cox Vgs  Vt  ds Vds  2
L 2 
2
V gs  Vt 
V W
  Vgs  Vt  ds Vds  = Cox
 2 L

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nMOS I-V Summary Example
 Shockley 1st order transistor models  We will be using a 0.6 mm process for your project
– From AMI Semiconductor
– tox = 100 Å 2.5
 – m = 350 cm2/V*s
V =5 gs

 0 Vgs  Vt cutoff 2

 – Vt = 0.7 V 1.5 V =4

Ids (mA)
 V
gs

## I ds    Vgs  Vt  ds Vds Vds  Vdsat linear  Plot Ids vs. Vds 1

2
 
V =3
– Vgs = 0, 1, 2, 3, 4, 5 0.5
gs

V =2
  2 – Use W/L = 4/2 l gs

 2
Vgs  Vt  Vds  Vdsat saturation
V =1

14
0
0 1 2
gs

Vds
3 4 5
W  3.9  8.85  10 W  W 2
   Cox   350   8     120 μA/V
L  100  10  L  L

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## pMOS I-V Capacitance

 All dopings and voltages are inverted for pMOS  Any two conductors separated by an insulator have
– Source is the more positive terminal capacitance
 Mobility mp is determined by holes  Gate to channel capacitor is very important
– Typically 2-3x lower than that of electrons mn – Creates channel charge necessary for operation
– 120 cm2/V•s in AMI 0.6 mm process  Source and drain have capacitance to body
0

##  Thus pMOS must be wider to

Vgs = -1
Vgs = -2
– Across reverse-biased diodes
provide same current
-0.2
Vgs = -3 – Called diffusion capacitance because it is
associated with source/drain diffusion
Ids (mA)

## – In this class, assume -0.4

Vgs = -4

mn / mp = 2 -0.6

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 15 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 16

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Gate Capacitance Diffusion Capacitance
 Approximate channel as connected to source  Csb, Cdb
 Cgs = eoxWL/tox = CoxWL = CpermicronW  Undesirable, called parasitic capacitance
 Cpermicron is typically about 2 fF/mm  Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
polysilicon
gate
for contacted diff
W – ½ Cg for uncontacted
tox – Varies with process
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body

3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 17 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 18