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Memristor-based Nonvolatile Synchronous

Flip-Flop Circuits
Jian Zheng, Zhigang Zeng, and Yidong Zhu
School of Automation, Huazhong University of Science and Technology
Key Laboratory of Image Processing and Intelligent Control of Education Ministry of China
Wuhan, P. R. China, 430074
Emails: zhengjian0817@163.com; zgzeng@hust.edu.cn; zyd hust@163.com

Abstract—Flip-flops are basic units for all kinds of sequential 6

logic circuits and complex digital electronics systems, which can 4
6 6 4
be used to store binary data owing to their two stable logic
states 0 and 1. SR flip-flop and D flip-flop are widely employed &3 &3 &
in digital circuits as representative types of basic flip-flops. In 5 5 
4

this paper, logic circuits of nonvolatile synchronous SR flip-flop 4
5
and D flip-flop are proposed, which utilize nanoscale memristors
as the nonvolatile memory elements to store the information with D E

different conductance states. The resistive switching property 6 6

'
of memristors is well-suited for implementing trigger function 4
in flip-flop circuits. Compared with traditional flip-flop ones, ' ' 4
&3
the proposed memristor-based SR flip-flop and D flip-flop have
nonvolatile characteristic, which is suitable for occasions with &3 & 
4

unstable power supply. Meanwhile, the designed circuits provide 4

experimental references for the development of digital circuit 5 5
structures based on the feasibility of tight integration of mem-
ristors with CMOS circuitry.
Keywords—Memristor; SR Flip-flop; D Flip-flop; Nonvolatile
I. I NTRODUCTION
Memristor was theoretically postulated as the fourth fun-
damental electric element along with resistor, inductor and
capacitor by Leon Chua in 1971 [1]. It attracted many re-
searchers’ attention since the first practical memristor was
experimentally found in 2008 by the scientists of Hewlett-
Packard Laboratories (HP Labs) [2]. Benefit from the favorable
performance merits of memristor, such as nonvolatility, fast
switching speed, high-density, low energy dissipation, good-
scalability, etc [3]. Researchers have applied memristor to
memory [4], digital logic [5], [6], analog circuits [7], neu-
romorphic systems [8], [9] and so on [10].
Flip-flops are the basic units of sequential logic circuits
and complex digital electronics systems, which can be used
to store binary data since they have two stable logic states
of 0 and 1. The traditional flop-flip circuits are composed of
logic gates, and they can achieve some logic functions such as
resetting, setting, flipping and holding. Because of its unique
logic functions, the flip-flops can deal with the relationship
between input signals and clock frequency, so it is widely
used in the generation, transformation and storage of digital
signals. SR flip-flop and D flip-flop are typical representatives
of basic flip-flops that can act as the basis for other types
of flip-flop. A common form of synchronous SR flip-flop is
shown in Fig. 1(a). It includes a set terminal (S) and a reset
terminal (R), and the logic states of the outputs Q and Q̄ (Q̄
‹,(((
F G
Fig. 1. (a) A logic circuit of synchronous SR flip-flop. (b) The logic symbol
of SR flip-flop. (c) A logic circuit of synchronous D flip-flop. (d) The logic
symbol of D flip-flop.
is always the inverse of Q) can be controlled by the change
of states at S and R when the clock pulse (CP ) is high (at
logic 1). But when the CP input is low (at logic 0), the Q
and Q̄ are completely isolated from the inputs and retain any
previous logic state since the two former NAND gates are
disabled. A logic circuit of synchronous D flip-flop is shown
in Fig. 1(c) which is basically a high activated SR flip-flop
with an additional inverter to ensure that the S and R inputs
cannot both be high or low at the same time. As the CP is
low, the states of Q and Q̄ keep the same regardless of the
changes at D input. When the CP is high, then whichever
logic state is at D will appear at Q. The logic symbols of D
type and SR flip-flop are illustrated in Fig. 1(b) and Fig. 1(d),
respectively.
Nowadays, flip-flops have many different circuit designs
and are widely used in digital circuits, such as counters,
computers, responders, etc. However, under the existing tech-
nical conditions, the sequential circuits composed of flip-
flops work only in situations where the power supply is
stable. If we want to maintain the working status in case
of power failure, the external memory cells are needed to
store the states information. It not only makes the circuit
more complicated, but also increases the power consumption
and data processing time. With the emergence of memristor,

the nonvolatility renders it well-suited for signal storing in I 90 

flip-flops. Meanwhile, memristor is a kind of potential device

which combines information processing and storage in itself,
researchers found that the application of memristor in memory
N ȕ
circuits can improve the shortages of circuit complexity and
97
data loss when power off. The HP Labs designed a memristor- 90
 97
based nonvolatile flip-flop circuit by using a memristor to
N ȕ
save the state of the flip-flop when power is interrupted and
read the saved state from memristor when power is restored
[11]. Although this design requires additional control modules
and increases the complexity of the circuit, it provides a new
experimental reference and direction for the development of Fig. 2. The graph of the threshold function f (VM ).
digital circuits and flip-flops. Also, the new flip-flop circuit
structures which are constructed by using memristors can
greatly increase response speed and reduce power consumption ,
[12], [13]. Moreover, integrating memristors and CMOS in 521

circuits could save the significant physical integration area

52))
while increasing the device density since memristor has the 95(6(7
  9
advantages of nanoscale size and CMOS-compatibility. 96(7

II. P ROPOSED M EMRISTOR - BASED F LIP -F LOP C IRCUITS
Different from the conventional SR flip-flop and D flip-
flop circuits which consist of several logic gates, the pro-
posed nonvolatile synchronous SR flip-flop and D flip-flop,
discussed in this work, are based on the combination of CMOS
and threshold-type voltage-controlled bipolar memristors [14].
This section explains the topologies and operating principles
of the flip-flops.
A. Memristor Model
In this work, we use the threshold-type memristor of which
memristance can be changed abruptly when applied voltages
exceed thresholds, this device exhibits two distinctive resis-
tance states that one is high resistance state (HRS) ROFF and
the other is low resistance state (LRS) RON , which can be
used to store binary data. A model of a voltage-controlled
memristive system with voltage threshold is developed in
reference [14]. In this model, the memristance M (t) acts as
the internal state variable, the device state is defined by the
following formulas:
I = M (t)−1 · VM ,
dM (t)
= f (VM ) · W (M (t), VM ),
dt
where I is the current through the memristor and VM is the
voltage applied to the memristor, f (·) is a function for describ-
ing the device voltage threshold property, W (·) is a window
function that can limit the memristance to [RON , ROFF ]. The
threshold function f (·) and window function W (·) are defined
as
f (VM ) = β · (VM − 0.5[|VM + VT | − |VM − VT |]),
W (M (t), VM ) = θ(VM ) · θ(ROFF − M (t)) + θ(M (t) − RON ),
(4)
D E
Fig. 3. (a) The schematic of memristor. (b) The qualitative current-voltage
characteristic of the threshold-type switching memristor.
where β is a positive constant characterizing the rate of
memristance change when |VM | > VT , VT is the threshold
voltage of memristor, θ(·) is the step function.
The threshold function f (VM ) is a piecewise function
which is shown in Fig. 2. Only when the applied voltage is
larger than the positive threshold or smaller than the negative
threshold, the state of memristance will change, otherwise
the memristor state will hold the same. β can control the
rate of memristance change, the larger β meant the greater
influence on the memristance. If the applied voltage exceeds
the threshold value, the state of the memristor will switch
quickly between RON and ROFF when β is large enough.
The schematic of memristor is shown in Fig. 3(a), bottom
terminal is denoted by the black thick line. The memris-
(1) tance will decrease when the forward bias voltage is applied
across memristor, and it will increase when the memristor
is reversely-biased. In Fig. 3(b), we show the qualitative
(2)
current-voltage characteristic of the threshold-type switching
memristor. When the applied voltage is lager than the positive
threshold VSET , the memristance switches to RON . Then, when
the applied voltage is smaller than the negative threshold
VRESET , the memristance returns to ROFF . If the applied
voltage in between VRESET and VSET the memristance will
remain unchanged. Therefore, the two distinctive resistance
states of memristor can represent logic 0 and logic 1. The
(3) binary data can be written to the memristor through a writing
voltage, and the data stored in the memristor can also be read
by a small reading voltage, so that the states will not be lost
even if the power is off.

 9VV
6 &3
3
,QY
0 0
0(
,QY ,QY
9'' 0
4 memristance changes to ROFF (RON ) since negative (positive)
0
5/ 
4
,QY &3
5 When the S input goes to logic 0 and the R input goes to
Fig. 4. Proposed memristor-based nonvolatile synchronous SR flip-flop
circuit.
B. SR Flip-Flop Circuit Architecture and Operations
As shown in Fig. 4, we proposed a memristor-based non-
volatile synchronous SR flip-flop circuit. It consists of a
threshold-type memristor (ME) connected in series to a pull-
down resistor (RL ), two pairs of NMOS transistors (M 1,
M 2, M 3, M 4), a PMOS transistor (P 1) and four inverters
(Inv1, Inv2, Inv3, Inv4). The set voltage is applied to S
and reset voltage is applied to R. The CP controls the switch
states of M 3, M 4 and P 1 and different transistor states can
form different equivalent circuit structures to achieve different
trigger functions of SR flip-flop. Compared with traditional SR
flip-flop circuit, the new circuit structure is not only simpler,
but also has the nonvolatility.
When CP is at low level, then M 3 and M 4 turn off while
P 1 turns on. As a result, the input pathways of circuit are cut
off so that the initial applied voltages of S and R have no
effect on the state of output Q. The output VOUT of voltage
divider across ME and RL is defined by formulas as follows:
VOUT = [RL /(RL + RME )] · VSS , (5)
0 < VSS ≤ VSET , (6)
RON ≤ RME ≤ ROFF , (7)
RON  RL  ROFF , (8)
where RME represents the memristance of ME, VSS is an
external positive voltage which is smaller than the threshold
voltage VSET . Because the partial voltage on the memristor
is VME = [RME /(RL + RME )] · VSS , which is less than
VSET , so the state of ME is not changed and the logic
state of output Q is directly related to the memristance in
the previous CP . If the memristance in the previous CP is
ROFF , then VOUT = [RL /(RL + ROFF )] · VSS ≈ 0, the Q is
logic 0. If the memristance in the previous CP is RON , then
VOUT = [RL /(RL + RON )] · VSS ≈ VSS , the Q is logic 1.
When CP is at high level, then M 3 and M 4 turn on while
P 1 turns off. Since S and R both have two input states of
logic 0 and logic 1, so four cases need to be discussed. When
the S input goes to logic 0 and the R input goes to logic
0, M 1 and M 2 turn off, hence the state of ME will not be
affected by external voltages VSS and VDD . If the present state
Qn (Qn is the state of the flip-flop before the CP arrives) is

logic 0 (logic 1), because of the mutual influence between the
two inverters, the outputs of Inv1 and Inv2 are logic 1 (logic
0) and logic 0 (logic 1), respectively. So the next state Qn+1
(Qn+1 is the state of the flip-flop after the CP arrives) is logic
0 (logic 1), the same as the output of Inv2. Meanwhile, the
voltage applied to ME. When CP changes from logic 1 to
logic 0, the output state of Q still remains unchanged.
logic 1, M 1 turns off and M 2 turns on, the VDD is connected
to the output Q through Inv2, Inv3 and Inv4. Due to the
high level of VDD , regardless of the present state Qn is logic
0 or logic 1, the Qn+1 is always logic 0. Because the outputs
of Inv1 and Inv2 are logic 1 and logic 0, respectively, so
the memristance switchs to ROFF in the case of applying a
negative voltage, the output state of Q can still maintain logic
0 in CP=0. Similarly, when the S input goes to logic 1 and the
R input goes to logic 0, M 1 turns on and M 2 turns off, VDD
is directly connected to the output Q through Inv3 and Inv4,
therefore, the Qn+1 is set to logic 1. Because the outputs of
Inv1 and Inv2 are logic 0 and logic 1, so the memristance
changes to RON , the output state of Q can hold logic 1 in
CP=0. When the S input goes to logic 1 and the R input goes
to logic 1, both M 1 and M 2 turn on so that the outputs of
Inv1 and Inv2 cannot be determined, this makes the Qn+1
of flip-flop uncertain.
The truth table and state diagram of proposed SR flip-flop
are shown in Table I and Fig. 5. 0 and 1 represent states of
logic 0 and logic 1, × represents any logic state. In summary,
when CP = 0, the next state Qn+1 remains on hold. When
CP = 1, if S = R = 0, Qn+1 remains on hold, too. If R
= 1 and S = 0, Qn+1 is reset to logic 0. By contrast, if S
= 1 and R = 0, Qn+1 is set to logic 1. If R = 1 and S =
1, Qn+1 cannot be determined. The characteristic equation
and constraint condition of SR flip-flop are described by the
following expressions:
Qn+1 = S + RQn , (9)
SR = 0. (10)
C. D Flip-Flop Circuit Architecture and Operations
The proposed memristor-based D flip-flop circuit is illustrat-
ed in Fig. 6, which is very different from tranditional circuit ar-
TABLE I
T HE T RUTH TABLE OF SR F LIP -F LOP C IRCUIT
CP S R Qn Qn+1 Characteristic
0 × × × Qn Hold the state
0 0
0
1 1
Hold the state
0
1
0 0
Reset to logic 0
1 0
1
0 1
0
1 1
Set to logic 1
1
0 ×
1 State of uncertainty
1 ×
 6WDWHRIXQFHUWDLQW\ ' 

6 5  6 5 
'    ' 
6  6 î
5 î
  5 
' 
6 5  6 5 
Fig. 7. The state diagram of D flip-flop circuit (CP = 1).
6WDWHRIXQFHUWDLQW\

Fig. 5. The state diagram of SR flip-flop circuit (CP = 1).

&3 9VV

3
,QY
'
0 0
0(
,QY ,QY
4

5/ 
4

Fig. 8. The simulated transient waveforms of CP , VS , VR and VQ in the

Fig. 6. Proposed memristor-based nonvolatile synchronous D flip-flop circuit. proposed SR flip-flop circuit.

chitectures. The components of the circuit include a threshold-
type memristor (ME), a resistor (RL ), NMOS transistors (M 1,
M 2), a PMOS transistor (P 1) and inverters (Inv1, Inv2,
Inv3). Its operation principles and circuit structure are similar
to SR flip-flop presented in Section II-B. When the CP is at
logic 0, the M 1 and M 2 turn off while P 1 turns on, so changes
at the D input make no difference to the Q and Q̄. Similar to
the SR flip-flop, the Q will remain unchanged. When the CP
is at logic 1, then P 1 turns off while M 1 and M 2 turn on. If
the D input goes to logic 0 (logic 1), the Q is logic 0 (logic
1) since the output terminal of Q is connected to the input
terminal of D. Also, the input of Inv2 is logic 0 (logic 1)
and the output of Inv1 is logic 1 (logic 0), causing RME to
be switched to ROFF (RON ) that the Q sets to logic 0 (logic
1) when the CP changes from high to low.
The truth table and state diagram of proposed D flip-flop
are shown in Table II and Fig. 7. In summary, when CP = 0,
the Qn+1 remains on hold. When CP = 1, if D = 0, Qn+1 is
set to logic 0. Alternatively, if D = 1, Qn+1 is set to logic 1.
The characteristic equation of D flip-flop is:
Qn+1 = D.
TABLE II
T HE T RUTH TABLE OF D F LIP -F LOP C IRCUIT
CP D Qn Qn+1 Characteristic
0 × × Qn Hold the state
0 0
0
1 0
Set to logic 0
1
1
0 1
Set to logic 1
1 1
III. S IMULATION R ESULTS
As analyzed previously in Section II, the logical operations
of SR flip-flop and D flip-flop are clear. In this section, the
proposed circuits have been simulated in SPICE simulation
environment and the figures of the simulation results have been
plotted in MATLAB. The behaviors of the memristor device
[14] were described for RON = 1kΩ, ROFF = 100kΩ, VSET =
3.5V and VRESET = -3.5V.
The variables of the hybrid CMOS-memristor SR flip-flop
circuit used for simulations are as follows: RL = 10kΩ, VDD =
5V, VSS = 3V. Fig. 8 shows the simulated transient waveforms
of CP , VS , VR and VQ , where VS , VR represent the input
voltages of S and R while VQ is the output voltage of Q. As
expected, the Q changes to a new state only in the case of
CP = 1, when the VS and VR change states during the high
CP period, the results are in accordance with the contents of
Table I.
For the proposed D flip-flop circuit designed with the
parameters of RL = 10kΩ and VSS = 3V, Fig. 9 exhibits the
simulated transient waveforms of CP , VD and corresponding
output VQ , where VD is the input voltage of D. When CP =
(11) 0, the outputs Q and Q̄ remain the same as the initial states.
When CP = 1, the state of Q is determined by VD , that is to
say, if D = 0, then Q = 0 while Q = 1 in the case of D =
1. Thus, the simulation results and the theoretical analysis are
anastomose.
IV. C ONCLUSION
Memristor-based nonvolatile synchronous SR flip-flop and
D flip-flop circuits have been proposed in this work, where the
threshold-type memrsitor has two distinctive resistance states
to store the information of logic 0 or logic 1. We have analyzed



Fig. 9. The simulated transient waveforms of CP , VD and VQ in the proposed
D flip-flop circuit.
the circuit structures and operating principles of the flip-flops
in details. Through analysis and simulations, we can find that
the effectiveness of the proposed SR flip-flop and D flip-flop
are verified. Because memristor has the favorable performance
merits of nonvolatility, nano size and CMOS-compatibility,
the proposed circuits can not only realize the traditional flip-
flop functions with more simple circuit structures and smaller
physical integration areas, but also applicable to computing
systems powered by highly erratic intermittent power sources
since the memristor state could be saved in a signal cycle.
Meanwhile, the proposed circuits will provide experimental
references for the development of flip-flop circuits and new
digital circuit structures based on the feasibility of tight
integration of memristors with CMOS circuitry.
ACKNOWLEDGMENT
The work was supported by the Natural Science Foundation
of China under Grant 61673188, the National Key Research
and Development Program of China under Grant 2016YF-
B0800402, the Science and Technology Support Program of
Hubei Province under Grant 2015BHE013.

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