Design of comparator for slewing and linear response

Rishabh Prasad
18MECV16

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Contents
1 Objective 4

2 Theory 4
2.1 Two - Stage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Implementation 5
3.1 Process Parametres . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Steps to design two stage comparator for linear response . . . . . . . . . . . . . . . . 6
3.4 Circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Observations 9
4.1 Resultant waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Transistor operating regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Results 13

6 Conclusion 14

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List of Figures
1 Circuit symbol for a comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Ideal transfer curve for a comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Step to design comparator for linear response . . . . . . . . . . . . . . . . . . . . . . . 6
4 Steps to design comparator for slewing response . . . . . . . . . . . . . . . . . . . . . 6
5 Transistor level circuit schematic for comparator with W/L ratio for each MOSFET . 7
6 Layout for comparator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Circuit for DC operating point analysis at Vicm- . . . . . . . . . . . . . . . . . . . . . 8
8 Circuit for DC operating point analysis at Vicm+ . . . . . . . . . . . . . . . . . . . . 8
9 Circuit for DC analysis when common mode input voltage is swept from 0 V to Vdd . 9
10 Noise analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
11 ICMR analysis for comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Transient analysis for comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Transient analysis for comparator for propagation delay and slew rate calculation . . . 11
14 Offset voltage calculation for MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . 11
15 Transient analysis for comparator after RC extraction . . . . . . . . . . . . . . . . . . 12
16 ICMR analysis for comparator after RC extraction . . . . . . . . . . . . . . . . . . . . 12

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1 Objective
To design a comparator for linear response as well as slewing response by assuming suitable specifi-
cations on cadence virtuoso platform.

2 Theory
A comparator is defined as a circuit that has a binary output whose value depends on comparison
of two analog inputs. The ciruit symbol for comparator is shown in Figure 1 . The symbol for
comparator is similar to that of an operational amplifier as a comparator has the same characteristics
as that of a high gain amplifier. A positive voltage applied at vp will cause the comparator output to
go positive , whereas a positive voltage applied at vn will cause the comparator output to go negative.
The upper as well as lower voltage limits of the comparator output are defined as VOH and VOL
respectively.
As shown in Figure 2 the output of the comparator is high (VOH ) when the difference between
noninverting and inverting inputs is positive and low ( VOL ) when this is negative.

2.1 Two - Stage Comparator

A close examination of the requirements for a comparator reveal that it requires a differential input
and a sufficient gain to be able to reach desired resolution. Hence, two stage op-amp makes an
excellent implementation of a comparator. There are two approaches to the design of a comparator
depending whether it is slewing or not. If the comparator is not slewing then, then the pole locations
are very important. On the other hand if the comparator slews then the ability of comparator to
charge or discharge capacitor becomes more important.

Figure 1: Circuit symbol for a comparator.

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 Figure 2: Ideal transfer curve for a comparator.

3 Implementation
3.1 Process Parametres
3.2 Specifications
The comparator was developed for the following specifications using 180nm process parameters:-

VOH = 1.45 V , VOL = 0.13 V , VDD = 1.8 V , VSS = 0 V, CII = 5pF

Vin(min) = 1 mV , ICM R+ = 1.5 V , ICM R− = 0.8 V , tp = 1ns
While the value of Vbias = 0.5 V and Vbias2 = 1.6 V was chosen to get the required current from
MOSFET NM7 and NM8 working as current source in Figure 5

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3.3 Steps to design two stage comparator for linear response

Figure 3: Step to design comparator for linear response

Figure 4: Steps to design comparator for slewing response

3.4 Circuit schematic

The circuit schematc at various abstraction level such as layout level, transistor level and symbol
(symbol for comparator transistor level circuit) level were used. They are shown in Figure5, Figure6,
Figure7, Figure8 and Figure 9.

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 Figure 5: Transistor level circuit schematic for comparator with W/L ratio for each MOSFET

As shown in Figure5 the transistor level schematic is shown for each MOSFET with its W/L ratio.
This transistor level schematic is used to create the layout which is shown in Figure6.

Figure 6: Layout for comparator circuit

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 Figure 7: Circuit for DC operating point analysis at Vicm-

The circuit shown in Figure7 is used to obtain the transistor operating points when common mode
input ICM R− is applied to both the terminals of the comparator.

Figure 8: Circuit for DC operating point analysis at Vicm+

The circuit shown in Figure8 is used to obtain the transistor operating points when common mode
input ICM R+ is applied to both the terminals of the comparator.

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 Figure 9: Circuit for DC analysis when common mode input voltage is swept from 0 V to Vdd

The circuit shown in Figure 9 is used to sweep common mode input from 0V to Vdd and obtain
DC sweep analysis.

4 Observations
4.1 Resultant waveforms

Figure 10: Noise analysis

Figure10 shows resultant waveform for input reffered noise v/s frequency when noise analysis is
performed. It can be that noise at low frequency is higher. This can be attributed to the fact that
at lower frequency we have noise component due to flicker noise and white noise. While at higher
frequency the input reffered noise is due to white noise only.

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 Figure 11: ICMR analysis for comparator

Results obtained for DC sweep analysis when common mode input shown in Figure9 is swept from
0V to Vdd using the circuit shown in Figure9.

Figure 12: Transient analysis for comparator

Transient response results is shown in Figure12 when the vn terminal is kept at a constant potential
of 1V and a sinewave is applied to vp terminal. When voltage at vp exceeds that of vn then a positive
voltage of VOH is obtained at the output otherwise a voltage of VOL is obtained at the output.

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 Figure 13: Transient analysis for comparator for propagation delay and slew rate calculation

Figure 14: Offset voltage calculation for MOSFET

To obtain a voltage of the output voltage of VO =( ( VOH + VOL )/2) a constant DC voltage is
applied between the terminals. This voltage is called the offset voltage VOS . The value obtained is
given as VOS = 15 µV. and its value obtained here is

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 Figure 15: Transient analysis for comparator after RC extraction

Transient response results is shown in Figure15 when the vn terminal is kept at a constant potential
of 1V and a sinewave is applied to vp terminal. When voltage at vp exceeds that of vn then a positive
voltage of VOH is obtained at the output otherwise a voltage of VOL is obtained at the output. This
result is obtained for layout after RC extraction.

Figure 16: ICMR analysis for comparator after RC extraction

Results obtained for DC sweep analysis when common mode input shown in Figure16 is swept
from 0V to Vdd using the circuit shown in Figure9. Here, the circuit used inside the symbol is the
layout after RC extraction.

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4.2 Transistor operating regions
After completion of DC operating point analysis by using circuit as shown in Figure 7 at ICM R−
and the circuit as shown in Figure 8 at ICM R+ we get the transistor currents and operating regions
as shown in the following table. The name of transistor in second column in given as per schmatic
shown in Figure 5

Transistor operatin region and drain current at ICM R−

Transistor name Transistor name Transistor oper- Drain current
in schematic ating region
M1 NM0 2 4.759µA
M2 NM1 2 4.759µA
M3 PM0 2 4.759µA
M4 PM1 2 4.759µA
M5 NM1 2 10.0µA
M6 PM2 2 62.345µA
M7 NM6 2 62.3412µA
M8 NM5 2 10.0µA
Transistor operatin region and drain current at ICM R+
Transistor name Transistor name Transistor oper- Drain current
in schematic ating region
M1 NM0 2 5.04µA
M2 NM1 2 5.04µA
M3 PM0 2 5.04µA
M4 PM1 2 5.04µA
M5 NM1 2 10.0µA
M6 PM2 2 64.25µA
M7 NM6 2 64.25µA
M8 NM5 2 10.099µA

5 Results
Comparison of various comparator parametres obatined graphically with the theroritical values can
be seen below:-

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 Comparison of theoritical v/s practical values
Parametre name Theoritical value Practically ob-
tained values
Propagation delay ( tp ) 100ns 1ns
Slew Rate 11V/µs 15.21V/µs
VOH 1.45 V 1.75 V
VOL 0.13 V 0V
Offset Voltage VOS 0 0.15/µV
Gain ( Av (0)) 62.41 dB 64.86 dB

6 Conclusion
Hence, a comparator was designed by assuming suitable specifications on cadence virtuoso platform.
The comparator was analysed for DC analysis, transient analysis , AC analysis , noise analysis and
various resultant waveforms were obtained. Also various theroritical values assumed for specifiations
were compared with actual obtained result.

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