MOS Transistor Basics

and Theory

Lecture - 2
 Introduction
• MOSFET or Metal Oxide-Semiconductor
(MOS) are field effect devices that use the
electric field to create a conduction
channel.

• There are two kinds of MOSFET

transistors:
– N channel MOSFET Transistor or NMOS
– P channel MOSFET Transistor or PMOS
• An MOS transistor is termed a majority-
carrier device, in which the current in a
conducting channel between the source and
drain is modulated by a voltage applied to the
gate.

• In an n-type MOS transistor (i.e. nMOS), the

majority carriers are electrons.

• A positive voltage applied on the gate with

respect to the substrate enhances the number
of electrons in the channel (the region
immediately under the gate) and hence
increases the conductivity of the channel.
• For gate voltages less than a threshold
value denoted by Vt, the channel is cut-off,
thus causing a very low drain-to-source
current.

• The operation of a p-type transistor (i.e.

pMOS) is analogous to the nMOS
transistor with the exception that the
majority carriers are holes and the
voltages are negative with respect to the
substrate.
• The first parameter of interest that
characterizes the switching behavior of an
MOS device is the threshold volatge, Vt .

• This is defined as the voltage at which an

MOS device begins to conduct (“turn on”).

• Those devices that are normally cut-off (i.e.

non-conducting) with zero gate bias (gate
voltage-source voltage) are further classed as
enhancement mode devices, whereas those
devices that conduct with zero gate bias are
called depletion mode devices.
Figure 2: Conduction characteristics for enhancement and depletion
mode transistors (assuming fixed Vds)
• The n-channel transistors and p-channel
transistors are the duals of each other; that is, the
voltage polarities required for correct operation
are opposite.

• The threshold voltages for n-channel and p-

channel devices are denoted by Vtn, and Vtp
respectively.
• In CMOS technologies both n-channel and p-
channel transistors are fabricated on the same
chip.

• Furthermore, most CMOS integrated circuits, at

present, use transistors of the enhancement type.
 nMOS Enhancement Transistor
• The structure for an n-channel enhancement type
transistor shown in figure 2 consists of a
moderately doped p-type silicon substrate into
which two heavily doped n+ regions, the source
and drain are diffused

Figure 3: Physical Structure of nMOS Transistor

• Between these two regions there is a narrow
region of p-type substrate called the channel,
which is covered by a thin insulating layer of
silicon dioxide (SiO2) called gate oxide.

• Over this oxide layer is polycrystalline silicon

(polysilicon) electrode, referred to as the
gate.

• Polycrystalline silicon is silicon that us not

composed of a single crystal.

• Since the oxide layer is an insulator, the

current through the gate and channel is
essentially zero.
• Because of the inherent symmetry of the
structure, there is no physical distinction
between the drain and source regions.

• In operation, a positive voltage is applied

between the source and drain (Vds).

• With zero gate bias (Vgs = 0), no current

flows from source to drain because they
are effectively insulated from each other
by the two reverse biased p-n junctions.
• However, a voltage applied to the gate,
which is positive with respect to the source
and substrate, produces an electric field E
across the substrate, which attracts
electrons towards the gate and repels
holes.

• If the gate voltage is sufficiently large, the

region under the gate changes from p-type
to n-type (due to accumulation of attracted
electrons) and provides a conduction path
between the source and drain.
• Under such a condition, the surface of the
underlying p-type silicon is said to be
inverted. The term n-channel is applied to
the structure.

Figure : Creation of an inversion layer in an n transistor

• The difference between a p-n junction that exists
in a bipolar transistor or diode (or between the
source or drain and substrate) and the inversion
layer-substrate junction is that :
– In the p-n junction, the n-type conductivity is brought
about by a metallurgical process: that is, the electrons
are introduced into semiconductor by the
introduction of donor ions.

– In an inversion layer-substrate junction, the n-type

layer is induced by the electric field E applied to the
gate.

• Thus, this junction, instead of being a

metallurgical junction, is a field-induced
junction.
• Electrically, an MOS device therefore acts
as a voltage-controlled switch that
conducts initially when the gate-to-source
voltage, Vgs, is equal to the threshold
voltage Vt.

• When a voltage Vds is applied between

source and drain, with Vgs = Vt,
– The horizontal and vertical components of the
electrical field due to the source-drain voltage
and gate-to-substrate voltage interact, causing
conduction to occur along the channel.
• The horizontal component of the electric
field associated with the drain-to-source
voltage (i.e. Vds >0), is responsible for
sweeping the electrons from the channel
towards the drain.

• As the voltage from drain-to-source is

increased, the resistive drop along the
channel begins to change the shape of the
channel characteristic.
Figure: nMOS device behavior under the influence of different
terminal voltages
• At the source end of the channel, the full gate
voltage is effective in inverting the channel.

• However, at the drain end of the channel,

only the difference between the gate and the
drain voltage is effective.

• When the effective gate voltage (Vgs – Vt) is

greater than the drain voltage, the channel
becomes deeper as Vgs is increased.

• This is termed the “linear”, “resistive”, or

“unsaturated” region, where the channel
current Ids is a function of both gate and
drain voltages.
• If Vds > Vgs – Vt, then Vgd < Vt (Vgd is the gate-to-drain
voltage), and the channel becomes pinched-off --- the
channel no longer reaches the drain.

• However, in this case, conduction is brought about by a

drift mechanism of electrons under the influence of the
positive drain voltage.

• As the electrons leave the channel they are injected into

drain depletion region and are subsequently accelerated
towards drain.

• The voltage across the pinched-off channel tends to

remain fixed at (Vgs – Vt).

• This condition is the “Saturated” state in which the

channel current is controlled by the gate voltage and is
almost independent of drain voltage.
• For fixed drain-to-source voltage and fixed
gate voltage, the factors that influence the
level of drain current Ids flowing between
source and drain (for a given substrate
resistivity) are:
– The distance between source and drain
– The channel width
– The threshold voltage Vt
– The thickness of the gate-insulating oxide
layer
– The dielectric constant of the gate insulator
– The carrier (electron or hole) mobility μ
• The normal conduction characteristics of
an MOS transistor can be categorized as
follows:
– “Cut-off” region: where the current flow is
due to what is termed the source-drain
leakage current.
– “Linear” region: region of weak inversion
where the drain current increases linearly
with gate voltage.
– “Saturation” region: channel is strongly
inverted and drain current is independent of
the drain voltage.
 pMOS Transistor

Figure: Physical structure of pMOS Transistor

 Threshold Voltage
• For all practical purposes, we can identify
four physical components of the threshold
voltage:
– The work function difference between the gate
and the channel
– The gate voltage component to change the surface
potential
– The gate voltage component to offset the
depletion region charge
– And the voltage component to offset the fixed
charges in the gate oxide and the silicon-oxide
interface.
• The work function difference ΦGC between the
gate and the channel reflects the built-in
potential of the MOS system, which consists of
– the p-type substrate,
– the thin silicon dioxide layer
– and the gate electrode.
• Depending on the gate material, the work
function difference is
ΦGC = ΦF (substrate) – ΦM for metal gate
ΦGC = ΦF (substrate) – ΦF (gate) for polysilicon gate
• This first component of the threshold
voltage accounts for part of the voltage drop
across the MOS system that is built-in.

• Now, the externally applied gate voltage

must be changed to achieve surface
inversion, i.e. to change the surface
potential by - 2ΦF .
– This will be the second component of the
threshold voltage/
• Another component of the applied gate voltage
is necessary to offset the depletion region
charge, which is due to the fixed acceptor ions
located in the depletion region near the surface.
• We can calculate the depletion region charge
density at surface inversion (Φs = - ΦF )
QB 0   2q.N A . si .  2 F
• Note that if the substrate (body) is biased at a
different voltage level than the source, which is
at ground potential (reference), then the
depletion region charge density can be
expressed as a function of source-to-substrate
voltage VSB.
QB   2q.N A . si .  2 F  VSB
• The component that offsets the depletion region
charge is then equal to –QB/Cox, where Cox is the
gate oxide capacitance per unit area:
 ox
Cox 
tox
• Finally, we must consider the influence of a
nonideal physical phenomenon which we have
neglected till now.
• There always exists a fixed positive charge density
Qox at the interface between the gate oxide and
the silicon substrate, due to impurities and/or
lattice imperfections at the interface.
• The gate voltage component that is necessary to
offset this positive charge at the interface is –
Qox/Cox.
• For zero substrate bias, the threshold voltage
VT0 is expressed as follows:
QB 0 Qox
VT 0   GC  2 F  
Cox Cox

• For nonzero substrate bias, on the other

hand, the depletion charge density term must
be modified to reflect the influence of VSB
upon that charge, resulting in the following
generalized threshold voltage expression:
QB Qox
VT   GC  2 F  
Cox Cox
 • The generalized form of the threshold
voltage can also be written as
QB 0 Qox QB  QB 0 QB  QB 0
VT   GC  2 F     VT 0 
Cox Cox Cox Cox
2q.N A . Si
QB  QB 0
Cox

Cox
.   2 F  VSB  2 F 
• Thus, the most general expression of the
threshold voltage VT can be found as
follows:
VT  VT 0   .   2 F  V SB  2 F  (A)

2 q . N A . Si Where γ is the substrate-bias (or body-effect)

 
C ox Coefficient.
• The threshold voltage expression given in (A)
can be used both for n-channel and p-
channel MOS transistors.

• One must be careful, however, since some of

the terms and coefficients in this equations
have different polarities for the n-channel
(nMOS) case and for the p-channel (pMOS)
case.

• The reason for this polarity difference is that

the substrate semiconductor is p-type in an
n-channel MOSFET and n-type in a p-
channel MOSFET.
 – The substrate Fermi potential ΦF is negative in
nMOS, positive in pMOS.

– The depletion region charge densities QB0 and

QB are negative in nMOS, positive in pMOS.

– The substrate bias coefficient γ is positive in

nMOS, negative in pMOS.

– The substrate bias voltage VSB is positive in nMOS

, negative in pMOS.

• Typically, the threshold voltage of an

enhancement-type n-channel MOSFET is a
positive quantity, whereas the threshold
voltage of p-channel MOSFET is negative.