Roll No.

Total No. of Questions:097 U-u"* , a/Lk blttt{Q [Total No. of Pages: 02

Wa,ear\^
B.Tech. (Sdrn. - 3f'I)
COMPUTER ARCHITE CTURE,
SUB.IECT CODE : CS - 2O1.
Paper ID : [AO451-]
[Note : Please fill subject code and paper ID on OMR]

Time : 03 Hours Maximum Marks : 60

Instruction to Candidates:
1) Section- A is Compulsory.
2) Attempt any Four questionsfrom Section- B.
3) Attempt any TWo questionsfrom Section- C.
Section- A
81) (10x2=20)

a) Convertthe following logic function into minterm

ABC,DE, + AB, C,DE, + ABCDE, + AB,CD, E,

b) Define the terms real time computer & processcontrol computer.

c) Give the layeredview of a computersystem.

d) What is the role of Shift Registersin digital computers?

e) Performthe subtractionwith the following unsignedbinary numberby

taking the 2's complimentof the subtrahend
1 0 1 0 1 0-0 1 0 1 0 1 0 0

0 Explain the meaningof the memory - referenceinstructionSTA.

g) What is the differencebetweenmicro programand micro code?
h) What do you meanby softwareinterrupt?
i) How CacheMemory is useful in memory hierarchy?
j) What do you meanby Intemrpt - initiated I/O concept?
Section- B
x 5 = 20)
Q2). Explainin brief aboutMIMD machines

Q3) Give an overview of CISC Architecture.

J-410tsl2gl P.T.O.
Q4) AcomputeremploysRAM chipsof 256x 8 andROM chipsof 1024x 8. The
computersystemneeds2K bytesof RAM, 4K bytesof ROM,andfourinterface
units,eachwith fourregisters.A memory- mappedI/O configurationis used.
The two highest-orderbits of the addressbusareassigned
00 for RAM, 01
for ROM,and10for interfaceregisters.Givetheaddressrangein hexadecimal
for RAM, ROM, andinterface.

QS) A DMA controllertransfers16 - bit wordsto memoryusingcyclestealing.

Thewordsareassembled from a devicethattransmitscharacters
at a rateof
2400charactersper second.TheCPUis fetchingandexecutinginstructions
at anaverage persecond.
rateof 1 million instructions By how muchwill the
CPUbe sloweddownbecause of theDMA transfer?

of divisionfor signed-magnitude
Q6) Discussthe hardwareimplementation data.
Section- C
(2x10=20)

Q7) Explain in detail the main featuresof at leasttwo performanceevaluation

benchmarks.

Q8) (a) Explain why poor load balancingleadsto less-than-linearspeedup?

(b) A given processorhas32 registers,uses16-bitimmediates,and has I42
instructionsin its ISA. In a given program,207oof the instructionstake
one input register and have one output register,307ohave two input
registersand one output register,257ohave one output and one input
registerand take an immediateinput as well, and the remaining257o
have one immediateinput registerand one output register.For eachof
the four typesof instructions,how many bits arerequired?Assumethat
the ISA requiresthat all instructionsbe a multiple of 8 bits in length.

Qe) (a) How doespipelining improve performance?

(b) What is the result of the following operationswhen executedon a 8-bit
processorthat usesa 2's complementrepresentationfor negativeintegers?
LSH 14,3
ASH T7,,5
LSH-23,-2
ASH-23.-2

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