1. A central processing unit, 7. Microprocessor is the _____ c.

Secondary memory
fabricated on a single chip of of computer: d. All of these
semiconductor is called:

a. Hand 13. MOS stand for:

a. Microprocessor b. Heart
b. RAM c. Brain
c. ROM d. Leg a. Metal oxide semiconductor
d. None of these b. Memory oxide semiconductor
c. A and B
8. Microprocessor is fabricated d. None of these
2. Which is the architecture of on single chip using:
microprocessor:
14. Which system communicates
a. MOS with the outside word via the I/O
a. CISC b. ALU devices interfaced to it:
b. RISC c. CPU
c. All of these d. All of these
d. None of these a. Microprocessor
b. Microcomputer
9. Which is the components of c. Digital computer
3. CISC stands for: microprocessor: d. All of these
a. Complex Instruction System
Computer
b. Complex Instruction Set Car a. Register unit 15. A computer which has the
c. Complex Instruction Set b. Arithmetic and logical unit microprocessor as______ is called
Computer c. Timing and control unit as a microcomputer:
d. None of these d. All of these

a. CPU
4. RISC stands for: 10. Which is an integral part of any b. ALU
a. Reduced Instruction Set microcomputer system and its c. RU
Computer primary purpose is to hold program d. None of these
b. Reduced Intergraded Set and data:
Computer
c. Resource Instruction Set 16. The organization of I/O devices
Computer a. Memory unit create a difference between _____:
d. Resource Instruction System b. Register unit
Computer c. A and B
d. None of these a. Digital computer
b. Micro computer
5. Which is the components of c. A and B
computer: 11. How many group of memory d. None of these
unit:
a. System Bus
b. CPU 17. How many generation of
c. Memory Unit a. Four microprocessor:
d. All of these b. Three
c. Two
d. One a. Four
6. System Bus Contains: b. Five
c. Six
a. Address Bus 12. Which is the parts of memory d. Three
b. Data Bus unit:
c. Control Bus
d. All of these
a. Processor memory
b. Main memory
18. The___ was very successful in 24. The beginning of very
the calculator market at that time: efficient____ microprocessor in 30. Third generation
second generation: microprocessor is dominated
by____ microprocessor:
a. Motorola 6800 and 6809 a. 4-bit
b. Microprocessor 4004 b. 8-bit a. 8 bit
c. Intel 8085 c. 16-bit b. 4 bit
d. None of these d. 64-bit c. 16 bit
d. 64 bit

19. How are the successful 25. Which are some of popular
microprocessor: processor: 31. Intel used HMOS technology to
recreate_____:

a. 8004 a. Motorola 6800 and 6809

b. 5006 b. Intel 8085 a. 8084 A
c. 4004 c. Zilog Z80 b. 8086 A
d. All of these d. All the above c. 8085 A
d. 8088 A

20. How many microprocessor in 26. NMOS stands for:

the market during the same period: a. N-channel metal-oxide- 32. HMOS stands for:
semiconductor a. High performance metal oxide
b. P-channel metal-oxide- semiconductor
a. 6 semiconductor b. High processor metal oxide
b. 8 c. N-channel memory-oxide- semiconductor
c. 3 semiconductor c. Both A and b
d. 5 d. All the above d. None of these
27. _____ Was more common 33. What is the period of fourth
year: generation:
21. PMOS stands for:
a. P-channel metal-oxide-
semiconductor a. CRT a. 1979-1980
b. P-channel memory –oxide- b. TTL b. 1981-1995
semiconductor c. Both A and B c. 1995-2000
c. Both A and B d. None of these d. 1974-1980
d. None of these
22. Which provided the current:
28. Which technology speed faster 34. The fourth generation of
and higher density: microprocessor came really as a
a. Low-cost soon boon to the_____:
b. Slow-cost
c. Low-Output a. PMOS
d. All the above b. NMOS a. Computing environment
c. HMOS b. Processing environment
d. All the above c. Hot environment
23. Second Generation_____? d. All of these

29. What is the period of 3

a. 1974-1976 generation: 35. How many bit microprocessor
b. 1974-1978 in the era marked beginning of
c. 1974-1972 fourth generation:
d. None of these a. 1979-1981
b. 1979-1980
c. 1978-1979 a. 4 bit
d. 1978-1980 b. 8 bit
c. 16 bit
d. 32 bit
36. They were fabricated using a 42. How are the growth of SSI c. Intel
low power version of the HMOS technology in_____: d. Zilog
technology called____:

a. HSMOS a. 1956 on words 48. How can we make computers

b. HCMOS b. 1965 on words work faster?
c. HSSOM c. 1978 on words
d. None of these d. 1978 on words
a. The fetch-execute cycle and
pipelining
37. Motorola introduced _____ 43. The growth of medium scale b. The assembly
processor: integration in______: c. Both A and B
d. None of these

a. 2 bit-RISC a. Till 1971

b. 4 bit-RISC b. Till 1970 49. Who is the represents the
c. 8 bit-RISC c. Till 1972 fundamental process in the
d. 32 bit-RISC d. Till 1969 operation of the CPU:

38. Motorola introduced 32 bit 44. The growth of SSI up to____: a. The fetch-execute cycle and
RISC processor called______: pipelining
b. The assembly
a. 100 device on a chip c. Both A and B
a. MC 88100 b. 200 device on a chip
b. MC 81100 c. 300 device on a chip d. None of these
c. MC 80100 d. 400 device on a chip
d. MC 81000
50. Which process information at a
45. The growth of LSI technology much faster rate than it can
39. Period of fifth generation? on_____: retrieve it from memory:

a. 1974-1978 a. 1994-1995 a. ALU

b. 1979-1980 b. 1971-1977 b. Processor
c. 1981-1985 c. 1972-1978 c. Microprocessor
d. 1995-till date d. None of these d. CPU

40. The growth of vacuum tube 46. Which is most commonly 51. _____ memory system which is
technology has been listed as measured in terms of MIPS discussed later can improve
follow: previously million instruction per matters in this respect:
second:

a. 1946-1957 a. Data memory

b. 1958-1964 a. Microprocessor b. Cache memory
c. 1985-1999 b. Performance of a c. Memory
d. None of these microprocessor d. None of these
c. Assembly line
d. None of these
41. The growth of transistor 52. The fetch-execute cycle is to
technology in_____: use a system know as:
47. The range of this rating for
which microprocessor of_____:
a. 1946-1957 a. Assembly line
b. 1958-1964 b. Pipelining
c. 1985-1999 a. VLSI c. Cache
d. None of these b. Motorola d. None of these
53. The time taken for all stages of c. IMP-8 64. MOSFET stands for?
the assembly line to become active d. RPS-8 a. Metal-oxide-semiconductor
is called the: field effect transistor
b. Metal-oxide-semiconductor
59. How many bit MC6800 fan effort transistor
a. Flow through time microprocessor: c. Both A and B
b. Clock period d. None of these
c. Throughput 65. What is the main problem of
d. All of these a. 4-bit Intel 4004 microprocessor:
b. 8-bit
c. 16-bit
54. The clock period is denoted by: d. 32-bit a. Speed
b. Memory size
c. World width
a. Tp 60. Motorola has declined from d. All of these
b. T1+T2+T3-------+T n having nearly __________ share of
c. Pt the microprocessor market to much
d. None of these smaller share: 66. The evolution of the 4 bit
microprocessor ended when Intel
released in:
55. Ti is the time taken for the ith a. 30%
stage and there are n stages in the: b. 40%
c. 50% a. 4004
d. 60% b. 8008
a. Throughput c. 40964
b. Assembly line d. 4040
c. Both A and B 61. Which is the microprocessor
d. None of these launch by Fairchild company:
67. How many bit microprocessor
still survives in low-end application
56. Who is the determined by the a. F-6 such as microwave ovens and small
time taken by the stages the b. F-8 control system:
requires the most processing time: c. Both A and B
d. None of these
a. 4 bit
a. Clock period b. 16 bit
b. Flow through 62. How many stages has fetch c. 32 bit
c. Throughput execute cycle: d. 64 bit
d. None of these

a. 3 68. Calculator are based on______

57. The ____ of can assembly line b. 4 microprocessor:
to be I/t p: c. 5
d. 6
a. 4 bit
a. Clock period b. 16 bit
b. Pipelining 63. Which is the world’s first c. 32 bit
c. Throughput microprocessor? d. 64 bit
d. Flow through

a. Intel 4004
58. Which is the microprocessor b. Motorola 68020 69. BCD stands for:
launched by Motorola corporation c. Intel8008
introduced: d. None of these
a. Binary coded decimal
b. Based coded decimal
a. Mc6800 c. Both A and B
b. 8080 d. None of these
 75. Motorola has declined how
70. Intel 8008 microprocessor many % share of the
realizing in: microprocessor market to a much 81. How many speed of
smaller share: 8088,8085,8086 microprocessor:
a. 2.5 Million instruction per
a. 1971 second
b. 1973 a. 50% b. 1.5 Million instruction per
c. 1999 b. 55% second
d. 1988 c. 48% c. 3.5 Million instruction per
d. 51% second
d. 1.6 Million instruction per
71. Intel 8008 microprocessor’s second
upgraded version is: 76. Which year Intel corporation 82. Which year Intel family
introduced an updated version of ensured:
the 8080- the 8085:
a. 8080
b. 4004 a. 1965
c. Both A and B a. 1965 b. 1978
d. None of these b. 1976 c. 1981
c. 1977 d. 1999
d. 1985
72. Intel 8008 microprocessor was
introduced in: 83. Which corporation decided to
77. In 1977 which corporation use 8088 microprocessor in
introduced an updated version of personal computer:
a. 1971 the 8080- the 8085:
b. 1973
c. 1999 a. IBM
d. 1988 a. Motorola b. CRT
b. Intel c. PMN
c. Rockwell d. SPS
73. MC6800 microprocessor was d. National
introduced by:
84. Which processor provided 1
78. How many bit microprocessor MB memory:
a. Motorola corporation developed by Intel:
b. Fairchild
c. Both A and B a. 16-bit 8086 and 8088
d. None of these a. 4 bit b. 32-bit 8086 and 8088
b. 8 bit c. 64-bit 8086 and 8088
c. 32 bit d. 8-bit 8086 and 8088
74. Which Microprocessor d. 64 bit
producer continue successfully to
create newer and improved version 85. Who was introduce the 80286
of the microprocessor: 79. Which is the main feature of microprocessor updated on 8086,in
8085: 1983:

a. Intel a. Internal clock generator

b. Motorola b. Internal system controller a. Intel
c. Both A and B c. Higher clock frequency b. Motorola
d. None of these d. All of these c. Fairchild
d. None of these
80. Which is 16 Bit microprocessor:

a. 8088
b. 8086
c. 8085
d. All of these
86. Which is the microprocessor 92. VGA stands for:
launched by Intel:

a. Visual graph area 98. Pentium III processor is

a. Z-8 b. Visual graphics array released in the form of:
b. 8080 c. Visual graph accept a. Socket 370 Version
c. 8000 d. All of these b. Slot 1 Version in Plastic
d. None of these Cartridge
c. Both a and b
93. Pentium Pro Processor d. None of these
87. Which is the microprocessor contains: 99. What is the maximum clock
launched by national speed of P III processors
semiconductor:
a. L1 Cache
b. L2 Cache a. 1.0 GHz
a. IMP-4 c. Both L1 & L2 b. 1.1 GHz
b. IMP-8 d. None of these c. 1.2 GHz
c. IMP-6 d. 1.3 GHz
d. IMP-7
94. L1 cache memory is places at
______ 100. Power PC microprocessor
88. Which is the microprocessor architecture is developed by:
launched by Rockwell international:
a. On Processor
b. On Mother Board a. Apple
a. RPS-4 c. On Memory b. IBM
b. RPS-6 d. All of these c. Motorola
c. RPS-8 d. All of these
d. All of these
95. L2 cache memory is places at
______ 101. Which is not the main
89. Which is the microprocessor architectural feature of Power PC:
launched by Zilog: a. It is not based on RISC
a. On Processor b. Superscalar implementation
b. On Mother Board c. Both 32 & 64 Bit
a. Z-2 c. On Memory d. Paged Memory management
b. Z-4 d. All of these architecture
c. Z-6 102. Alpha AXP is developed
d. Z-8 by:
96. Pentium Pro can address _____
of memory:
90. CAD stands for: a. DEC
b. IBM
a. 4 GB c. Motorola
a. Computer aided drafting b. 128 GB d. Intel
b. Compare aided drafting c. 256 GB
c. Both A and B d. 512 GB
d. None of these 103. Which is not the main
feature of DEC Alpha:
97. Which is the professional or a. 64 Bit RISC processor
91. GUI stands for: Business version of Intel b. Designed to replace 32
Processors: VAX(CISC)
c. Seven stage split
a. Graphical user interface integer/floating point pipeline
b. Graph used Intel a. Pentium II d. Variable Instruction length
c. Graphical use inter b. Pentium Pro 104. Which is not the open-
d. None of these c. Pentium MMX source OS:
d. Pentium Xeon
a. Debian 110. CISC stands for:
b. BSD Unix a. Complex instruction set
c. Gentoo & Red Hat Linux computer
d. Windows b. Camper instruct set of
computer
c. Compared instruction set
105. ISA stands for: computer
d. None of these

a. Instruct set area 111. PC’s use____ based on

b. Instruction set architecture this architecture:
c. Both a and b
d. None of these
a. CPU
b. ALU
106. RISC stands for: c. MU
a. Reduced Instruction set d. None of these
computer
b. Reduced Instruct set compare
c. Reduced instruction stands
computer
d. All of these

107. DEC stands for:

a. Digital electronic computer

b. Digital electronic corporation

c. Digital equipment corporation
d. None of these

108. How many architectural

paradigms in microprocessor:

a. 2
b. 3
c. 4
d. 6

109. Which are the

architectural paradigms in
microprocessor:

a. RISC
b. CISC
c. PISC
d. A and B
1) Who is the brain of computer: b. operands a. general purpose
c. memory register
a. ALU d. None of these b. dedicated register
b. CPU c. A and B
c. MU 9) How many types of d. none of these
d. None of these classification of processor based on
register section: 16) How many parts of dedicated
2) Which technology using the register:
microprocessor is fabricated on a a. 1
single chip: b. 2 a. 2
c. 3 b. 4
a. POS d. 4 c. 5
b. MOS d. 6
c. ALU 10) In Microprocessor one of the
d. ABM operands holds a special register 17) Name of typical dedicated
called: register is:
3) MOS stands for:
a. Metal oxide a. Calculator a. PC
semiconductor b. Dedicated b. IR
b. Memory oxide c. Accumulator c. SP
semiconductor d. None of these d. All of these
c. Metal oxide select
d. None of these 11) Accumulator based 18) PC stands for:
4) In which form CPU provide microprocessor example are:
output: a. Program counter
a. Intel 8085 b. Points counter
a. Computer signals b. Motorola 6809 c. Paragraph counter
b. Digital signals c. A and B d. Paint counter
c. Metal signals d. None of these
d. None of these 19) IR stands for:
12) A set of register which contain
5) How many types of are: a. Intel register
microprocessor comprises: b. In counter register
a. data c. Index register
a. 3 b. memory addresses d. Instruction register
b. 6 c. result
c. 9 d. all of these 20) SP stands for:
d. 4
13) How many types are primarily a. Status pointer
6) Which is the microprocessor register: b. Stack pointer
comprises: c. a and b
a. 1 d. None of these
a. Register section b. 2
b. One or more ALU c. 3 21) The act of acquiring an
c. Control unit d. 4 instruction is referred as the____
d. All of these the instruction:
14) There are primarily two types
7) The register section is related of register: a. Fetching
to______ of the computer: b. Fetch cycle
a. general purpose c. Both a and b
a. Processing register d. None of these
b. ALU b. dedicated register
c. Main memory c. A and B 22) How many bit of instruction on
d. None of these d. none of these our simple computer consist of
one____:
8) What is the store by register: 15) Which register is a temporary
storage location: a. 2-bit
a. data b. 6-bit
c. 12-bit 40) Which is used to store critical
d. None of these 30) The carry is operand by: pieces of data during subroutines
a. C and interrupts:
23) How many parts of single 31) The sign is operand by:
address computer instruction : a. S a. Stack
32) The zero is operand by: b. Queue
a. 1 a. Z c. Accumulator
b. 2 33) The overflow is operand by: d. Data register
c. 3 a. O
d. 4 34) _____ is the condition: 41) The area of memory with
addresses near zero are called:
24) Single address computer a. CD
instruction has two parts: b. IR a. High memory
c. Both a and b b. Mid memory
a. The operation code d. None of these c. Memory
b. The operand d. Low memory
c. A and B 35) ____ causes the address of the
d. None of these next microprocessor to be obtained 42) The point where control
from the memory: returns after a subprogram is
25) LA stands for: completed is known as the :
a. CRJA a. Return address
a. Load accumulator b. ROM b. Main Address
b. Least accumulator c. MAP c. Program Address
c. Last accumulator d. HLT d. Current Address
d. None of these 43) The subprogram finish the
36) _________ Stores the return instruction recovers the
26) ED stands for: instruction currently being return address from the:
executed: a. Queue
a. Enable MRD b. Stack
b. Enable MDR a. Instruction register c. Program counter
c. Both a and b b. Current register d. Pointer
d. None of these c. Both a and b 44) The processor uses the stack to
d. None of these keep track of where the items are
27) LM stands for: stored on it this by using the:
37) In which register instruction is a. Stack pointer register
a. Least MAR decoded prepared and ultimately b. Queue pointer register
b. Load MAR executed: c. Both a & b
c. Least MRA d. None of these
d. Load MRA a. Instruction register 45) Which point to the ___ of the
b. Current register stack:
28) Causing a flag to became 0 is c. Both a and b a. TOP
called: d. None of these b. START
c. MID
a. Clearing a flag 38) The status register is also called d. None of these
b. Case a flag the____: 46) Stack words on:
c. Both a and b a. LILO
d. None of these a. Condition code register b. LIFO
b. Flag register c. FIFO
29) Which are the flags of status c. A and B d. None of these
register: d. None of these 47) Which is the basic stack
operation:
a. Over flow flag 39) BCD stands for: a. PUSH
b. Carry flag b. POP
c. Half carry flag a. Binary coded decimal c. BOTH A and B
d. Zero flag b. Binary coded decoded d. None of these
e. Interrupt flag c. Both a & b 48) SP stand for:
f. Negative flag d. none of these a. Stack pointer
g. All of these b. Stack pop
c. Stack push c. Medium significant c. Address bus
d. None of these digit d. None of these
49) How many bit stored by status d. low significant digit 67) Which bus transfer singles from
register: 58) _____ a subsystem that the CPU to external device and
a. 1 bit transfer data between computer others that carry singles from
b. 4 bit components inside a computer or external device to the CPU:
c. 6 bit between computer: a. Control bus
d. 8 bit a. Chip b. Data bus
50) Which is the important part of b. Register c. Address bus
a combinational logic block: c. Processor d. None of these
a. Index register d. Bus 68) Which is not the control bus
b. Barrel shifter 59) Which is called superhighway: signal:
c. Both a & b a. Processor a. READ
d. None of these b. Multiplexer b. WRITE
c. Backbone bus c. RESET
d. None of these d. None of these
51) The structure of the stack is 60) The external system bus 69) When memory read or I/O read
_______ type structure: architecture is created using from are active data is to the processor :
a. First in last out ______ architecture: a. Input
b. Last in last out a. Pascal b. Output
c. Both a & b b. Dennis Ritchie c. Processor
d. None of these c. Charles Babbage d. None of these
52) The data in the stack is called: d. Von Neumann 70) When memory write or I/O
a. Pushing data 61) The network of wires or read are active data is from the
b. Pushed electronic path ways on mother processor:
c. Pulling board back side: a. Input
d. None of these a. PCB b. Output
53) The CU is designed by using b. BUS c. Processor
which techniques: c. BOTH A and B d. None of these
a. HARDWIRED d. None of these 71) Using 12 binary digits how
CONTROLS 62) Which Bus connects CPU & many unique house addresses
b. MICROPROGRAMING level 2 cache: would be possible:
c. NANOPROGRAMING a. Rear side bus a. 28=256
d. ALL OF THESE b. Front side bus b. 212=4096
54) The 16 bit register is separated c. Memory side bus c. 216=65536
into groups of 4 bit where each d. None of these d. None of these
groups is called: 63) Which bus carry addresses: 72) PROM stands for:
a. BCD a. System bus a. Programmable read-
b. Nibble b. Address bus only memory
c. Half byte c. Control bus 73) EPROM stands for:
d. None of these d. Data bus a. Erasable Programmable
55) A nibble can be represented in 64) A 16 bit address bus can read-only memory
the from of: generate___ addresses: 74) Each memory location has:
a. Octal digit a. 32767 a. Address
b. Decimal b. 25652 b. Contents
c. Hexadecimal c. 65536 c. Both A and B
d. None of these d. none of these d. None of these
56) The left side of any binary 65) The processor 80386/80486 75) Which is the type of
number is called: and the Pentium processor uses microcomputer memory:
a. Least significant digit _____ bits address bus: a. Processor memory
b. Most significant digit a. 16 b. Primary memory
c. Medium significant b. 32 c. Secondary memory
digit c. 36 d. All of these
d. low significant digit d. 64 76) Secondary memory can
57) MSD stands for: 66) CPU can read & write data by store____:
a. Least significant digit using : a. Program store code
b. Most significant digit a. Control bus b. Compiler
b. Data bus c. Operating system
d. All of these 86) WE stands for: d. Virtual memory
77) Secondary memory is also a. Write enable 94) Which register is used to
called____: b. Wrote enable communicate with memory:
a. Auxiliary c. Write envy a. MAR
b. Backup store d. None of these b. MDR
c. Both A and B 87) When CS _____ the chip is not c. Both A and B
d. None of these selected at all hence D7 to D0 are d. None of these
78) Customized ROMS are called: driven to high impedance state: 95) SAM stands for:
a. Mask ROM a. High a. Simple architecture
b. Flash ROM b. Low machine
c. EPROM c. Medium b. Solved architecture
d. None of these d. Stand by machine
79) The ram which is created using 88) The capacity of this chip is 1KB c. Both a & b
bipolar transistors is called: they are organized in the form of d. None of these
a. Dynamic RAM 1024 words with 8 bit word The 96) MAR stands for:
b. Static RAM what is the site of address bus: a. Memory address
c. Permanent RAM a. 8 bit register
d. DDR RAM b. 10 bit b. Memory address
80) Which type of RAM needs c. 12 bit recode
regular referred: d. 16 bit c. Micro address register
a. Dynamic RAM 89) Which storage technique dose d. None of these
b. Static RAM not decoding circuit: 97) MDR stands for:
c. Permanent RAM a. Linear decoding a. Memory data register
d. SD RAM b. Fully decoding b. Memory data recode
81) Which RAM is created using c. Partially c. Micro data register
MOS transistors: d. None of these d. None of these
a. Dynamic RAM 90) In linear decoding address bus 98) VAM stands for:
b. Static RAM of 16-bit wide can connect only a. Valid memory address
c. Permanent RAM ____ of RAM. b. Virtual memory address
d. SD RAM a. 16 KB c. Variable memory
82) Which latch is mostly used b. 6KB address
creating memory register: c. 12KB d. None of these
a. SR-Latch d. 64KB 99) Which microprocessor to read
b. JK-Latch 91) Which statement is wrong an item from memory:
c. D-Latch according to linear decoding : a. VAM
d. T-Latch a. Address map is not b. SAM
83) Which statement is false about contiguous. c. MOC
WR signal: b. Confects occur if two of d. None of these
a. WR signal controls the the select lines become active at 100) Which bus plays a crucial
input buffer the same time role in I/O:
b. The bar over WR means c. If all unused address a. System bus
that this is an active low signal lines are not used as chip selectors b. Control bus
c. The bar over WR then these unused lines become c. Address bus
means that this is an active high don’t cares d. Both A and B
signal d. None of these 101) Which register is
d. If WR is 0 then the 92) The problem of bus confect connected to the memory by way
input data reaches the latch input and sparse address distribution are of the address bus:
84) Which technique is used for eliminated by the use of ______ a. MAR
main memory array design: address technique: b. MDR
a. Linear decoding a. Fully decoding c. SAM
b. Fully decoding b. Half decoding d. None of these
c. Both A and B c. Both a & b 102) How many bit of MAR
d. None of these d. None of these register:
85) CS stands for: 93) A microprocessor retries a. 8-bit
a. Cable select instructions from : b. 16-bit
b. Chip select a. Control memory c. 32-bit
c. Control select b. Cache memory d. 64-bit
d. Cable system c. Main memory 103) MOC stands for:
a. Memory operation b. Compared ray tube 120) standard I/O uses which
complex c. Command ray tube control pin on the micro processor:
b. Micro operation d. None of these a. IO/M
complex 112) The CPU sends out a ____ 121) A___ on this pin indicates
c. Memory operation signal to indicate that valid data is a memory operation:
complete available on the data bus: a. Low
d. None of these a. Read b. High
104) Which are the READ b. Write c. Medium
operation can in simple steps: c. Both A and B d. None of these
a. Address d. None of these 122) The external device is
b. Data 113) The ____ place the data connected to a pin called the
c. Control from a register onto the data bus: ______ pin on the processor chip.
d. All of these a. CPU a. Interrupt
105) The upper red arrow b. ALU b. Transfer
show that CPU sends out the c. Both A and B c. Both
control signals____ and _____ d. None of these d. None of these
indicate the data is read from the 114) The CPU removes the 123) The DMA controllers are
memory: ___ signal to complete the memory special hardware embedded into
a. Memory request write operation: the chip in modern integrate
b. Read a. Read processor that ____and_____ to
c. Both A and B b. Write the system;
d. None of these c. Both A and B a. Data transfer
106) The information is d. None of these b. arbitrate access
transferred from the_____ and 115) The value memvar must c. Both A and B
____ specified register: be transferred to the ___: d. None of these
a. MDR a. Computer 124) The CPU completes yields
b. CPU b. CPU control of the bus to the DMA
c. Both A and B c. Both A and B controller via:
d. None of these d. None of these a. DMA acknowledge
107) The information on the 116) The microcomputer signal
data bus is transferred to the system by using the ____device b. DMA integrated signal
______register: interface: c. DMA implicitly signal
a. MOC a. Input d. None of these
b. MDR b. Output 125) The mode of DMA are:
c. VAM c. Both A and B a. Single transfer
d. CPU d. None of these b. Block transfer
108) The lower red curvy 117) How bit microprocessor c. Burst –block transfer
arrow show that CPU places the inexpensive a separate interface is d. Repeated single
address extracted from the provided with I/O device: transfer
memory location on the_____: a. 2 bit e. Repeated–block
a. Address bus b. 4 bit transfer
b. System bus c. 8 bit f. Repeated Burst –block
c. Control bus d. 32 bit transfer
d. Data bus 118) How many ways of g. All of these
109) DMA stands for: transferring data between the
a. Direct memory access microprocessor and a physical I/O
b. Direct memory device:
allocation a. 2
c. Data memory access b. 3
d. Data memory allocation c. 4
110) DMA stands for: d. 5
a. Dynamic memory 119) The standard I/O is also
access called:
b. Data memory access a. Isolated I/O
c. Direct memory access b. Parallel I/O
d. Both B and C c. both a and b
111) CRT stands for: d. none of these
a. Cathode ray tube
1. BIU STAND FOR: b. Instruction purpose 16. Which has great important in
c. Instruction paints modular programming:
a. Bus interface unit d. None of these
b. Bess interface unit a. Stack segment
c. A and B 9. CS Stand for: b. Queue segment
d. None of these c. Array segment
a. Code segment d. All of these
2. EU STAND FOR: b. Coot segment
c. Cost segment 17. Which register containing the
a. Execution unit d. Counter segment 8086/8088 flag:
b. Execute unit
c. Exchange unit 10. DS Stand for: a. Status register
d. None of these b. Stack register
a. Data segment c. Flag register
3. The register can be divided b. Direct segment d. Stand register
are: c. Declare segment
d. Divide segment 18. Which flag are used to record
a. 3 specific characteristics of arithmetic
b. 4 11. Which are the segment: and logical instructions:
c. 5
d. 6 a. CS: Code segment a. The stack
b. DS: data segment b. The stand
4. Which are the part of c. SS: Stack segment c. The status
architecture of 8086: d. ES:extra segment d. The queue

a. The bus interface unit e. All of these 19. How many bits the instruction
b. The execution unit 12. The acculatator is 16 bit wide pointer is wide:
c. Both A and B and is called:
d. None of these a. 16 bit
a. AX b. 32 bit
5. Which are the four categories b. AH c. 64 bit
of registers: c. AL d. 128 bit
d. DL
a. General- purpose register 20. How many type of addressing
b. Pointer or index registers 13. The upper 8 bit are in memory:
c. Segment registers called______:
d. Other register a. Logical address
e. All of these a. BH b. Physical address
b. BL c. Both A and B
6. Eight of the register are c. AH d. None of these
known as: d. CH
21. The size of each segment in
a. General- purpose register 14. The lower 8 bit are 8086 is:
b. Pointer or index registers called_______:
c. Segment registers a. 64 kb
d. Other register a. AL b. 24 kb
b. CL c. 50 kb
7. The four index register can be c. BL d. 16kb
used for: d. DL
22. The physical address of
a. Arithmetic operation 15. IP stand for: memory is :
b. Multipulation operation
c. Subtraction operation a. Industry pointer a. 20 bit
d. All of these b. Instruction pointer b. 16 bit
c. Index pointer c. 32 bit
8. IP Stand for: d. None of these d. 64 bit

a. Instruction pointer
23. The _______ address of a b. Base pointer d. Application high
memory is a 20 bit address for the c. Bus pointer
8086 microprocessor: d. Byte pointer 39. AL stand for:

a. Physical 31. DI stand for: a. Accumulator low

b. Logical b. Address low
c. Both a. Destination index c. Appropriate low
d. None of these b. Defect index d. Application low
c. Definition index
24. To provide clarity in case of the d. Delete index 40. Which are the categorized of
status register_______ and flag:
__________ placeholders are 32. SI stand for:
displayed: a. Conditional flag
a. Stand index b. Control flag
a. Binary b. Source index c. Both a and b
b. Hexadecimal c. Segment index d. None of these
c. Both d. Simple index
d. None of these 41. Which are the general register:
33. DS stand for:
25. The pin configuration of 8086 is a. AX: Accumulator
available in the________: a. Default segment b. BX: Base
b. Defect segment c. CX: Count
a. 40 pin c. Delete segment d. DX: Data
b. 50 pin d. Definition segment e. All of these
c. 30 pin
d. 20 pin 34. ALE stand for: 42. ________ is the most
important segment and it contains
26. DIP stand for: a. Address latch enable the actual assembly language
b. Address light enable instruction to be executed by the
a. Deal inline package c. Address lower enable microprocessor:
b. Dual inline package d. Address last enable
c. Direct inline package a. Data segment
d. Digital inline package 35. AD stand for: b. Code segment
c. Stack segment
27. PA stand for: a. Address data d. Extra segment
b. Address delete
a. Project address c. Address date 43. The offset of a particular
b. Physical address d. Address deal segment varies from _________:
c. Pin address
d. Pointer address 36. NMI stand for: a. 000H to FFFH
b. 0000H to FFFFH
28. SBA stand for: a. Non mask able interrupt c. 00H to FFH
b. Non mistake interrupt d. 00000H to FFFFFH
a. Segment bus address c. Both
b. Segment bit address d. None of these 44. Which are the factor of cache
c. Segment base address memory:
d. Segment byte address 37. PC stand for:
a. Architecture of the
29. EA stand for: a. program counter microprocessor
b. project counter b. Properties of the programs
a. Effective address c. protect counter being executed
b. Electrical address d. planning counter c. Size organization of the cache
c. Effect address d. All of these
d. None of these 38. AH stand for:
45. ________ is usually the first
30. BP stand for: a. Accumulator high level of memory access by the
b. Address high microprocessor:
a. Bit pointer c. Appropriate high
a. Cache memory 59. LRB stand for:
b. Data memory 52. Direct mapping is a _________
c. Main memory to implement cache memory : a. Line read buffers
d. All of these b. Line ready buffers
a. Cheaper way c. Line root buffers
46. which is the small amount of b. Case way d. Line right buffers
high- speed memory used to work c. Cache way
directly with the microprocessor: d. None of these 60. EB stand for:

a. Cache 53. A fourth bit called the a. Effect buffers

b. Case _________: b. Effecting buffers
c. Cost c. Effection buffers
d. Coos a. Direct bit d. None of these
b. Cache bit
47. The cache usually gets its data c. Valid bit 61. EB stand for:
from the_________ whenever the d. All of these
instruction or data is required by a. Effect buffers
the CPU: 54. FIFO stand for: b. Effecting buffers
c. Effection buffers
a. Main memory a. First in first other d. Eviction buffers
b. Case memory b. First in first out
c. Cache memory c. First in first over 62. WB stand for:
d. All of these d. None of these
a. Write buffers
48. The amount of information 55. Microprocessor reference that b. Written buffers
which can be placed at one time in are available in the cache are c. Wrote buffers
the cache memory is called______: d. None of these
called_________:
a. Cache hits 63. WA stand for:
a. Circle size b. Cache line
b. Line size c. Cache memory a. Write allocate
c. Wide line size d. All of these b. Wrote allocate
d. None of these c. Way allocate
56. Microprocessor reference that d. Word allocate
49. How many type of cache are not available in the cache are
memory: called_________: 64. In case of direct- mapped cache
lower order line address bits are
a. 1 a. Cache hits used the access the ___________:
b. 2 b. Cache line
c. 3 c. Cache misses a. RAM
d. 4 d. Cache memory b. ROM
c. Directory
50. Which is the type of cache 57. __________ is the most d. HDD
memory: commonly used cache controller
with a number of processor sets: 65. The index high order bits in the
a. Fully associative cache address known as_________:
b. Direct-mapped cache a. L211 controller
c. Set-associative cache b. L210 controller a. tags
d. All of these c. L214 controller b. label
d. None of these c. point
51. Which memory is used to holds d. location
the address of the data stored in 58. LFB stand for:
the cache : e.
a. Line full buffers 66. The parity bits are used to
a. Associative memory b. Line fill buffers check that a__________:
b. Case memory c. Line fan buffers
c. Ordinary memory d. None of these a. Two bit error
d. None of these b. Single bit error
c. Multi bit error a. Reads* Read miss rate * Read
d. None of these miss penalty a. BIU
b. Write* (Write miss rate * b. PIU
67. Who works as cache on the Write miss penalty)+write buffer c. TIU
variable: stalls d. LIU
c. Memory access * Cache miss
a. Register rate * Cache miss penalty e.
b. Memory d. None of these 80. INTR: it implies the__________
c. Pointer 74. Which formula is used to signal:
d. Segment calculate the number of write stall
cycles: a. INTRRUPT REQUEST
68. Second level is a cache on the a. Reads* Read miss rate * Read b. INTRRUPT RIGHT
________: miss penalty c. INTRRUPT RONGH
b. Write* (Write miss rate * d. INTRRUPT RESET
a. Main memory Write miss penalty)+write buffer
b. RAM stalls
c. Both c. Memory access * Cache miss
d. None of these rate * Cache miss penalty
d. None of these
69. The memory system is said to 75. Which formula is used to
be effective if the access time of calculate the number of memory
the cache is close to the effective stall cycles:
access time of the_____: a. Reads* Read miss rate * Read
miss penalty
a. ROM b. Write* (Write miss rate *
b. RAM Write miss penalty)+write buffer
c. HDD stalls
d. Processor c. Memory access * Cache miss
rate * Cache miss penalty
70. Cache is usually d. None of these
the____________ of memory 76. Which causes the
access by the microprocessor: microprocessor to immediately
terminate its present activity:
a. First level
b. Second level a. RESET signal
c. Third level b. INTERUPT signal
d. Fourth level c. Both
d. None of these
71. The principal of working of the
cache memory largely depends on 77. Which are the cache controller
which locality: ports:

a. Spatial locality a. 64-bit AHB-Lite slave ports

b. Temporal locality b. 64-bit AHB-Lite master ports
c. Sequentially c. Both
d. All of these d. None of these

72. Who work as a cache for the 78. Cache can be controlled
page table: __________:

a. TLB a. 16KB-2MB
b. TLP b. 17 KB-2MB
c. LEB c. 18 KB-2MB
d. WAB d. 19 KB-2MB

73. Which formula is used to 79. Which is responsible for all the
calculate the number of read stall outside world communication by
cycles: the microprocessor:
1. EOC stands for: c. Request c.
a. End of d. Real Acknowledgment enable
conversion 10. ICW stands d. Acknowledgment
b. Emphasize of for: equivalent
conversion a. Interrupt 17. ADSTB stands
c. End of controller command words for:
d. None of these b. Interrupt command a. Access strobe
2. IRR stands for: write b. Access strobe
a. Interrupt request c. Initialization command c. Address store
register words d. Address strobe
b. Input request d. Initialization 18. MEMER and
register command write MEMW means:
c. Interrupt 11. OCW stands a. Memory read
resolver register for: b. Memory write
d. Input resolver a. Operational c. Both a and b
register command words d. None of these
3. ISR stands for: b. Operational 19. HRQ
a. Interrupt service conjunction words and HLDA means:
register c. Operational a. Hold request
b. Input service control words b. Hold acknowledgment
register d. Operational cost c. Both a and b
c. In-service words d. None of these
register 12. DMA stands 20. ADC stands for:
d. All of these for: a. Analogue to analogue
4. PR stands for: a. Direct memory converters
a. Priority register allocation b. Analogue to digital
b. Priority resolver b. Direct memory converters
c. Priority request access c. Digital to digital
d. None of these c. Direct memory converters
5. IMR stands for: application d. Digital to analogue
a. Input mask d. Direct memory converters
register acknowledgment 21. DAC stands for:
b. Input mask 13. HLD stands a. Analogue to analogue
resolver for: converters
c. Interrupt mask a. High b. Analogue to digital
resolver b. Hour converters
d. Interrupt mask c. Hold c. Digital to digital
register d. None of these converters
6. INT stands for: 14. HLDA stands d. Digital to analogue
a. Input for: converters
b. Interrupt a. High 22. Which is the
c. Both a and b acknowledgment commonly used programmable
d. None of these b. Hold interface and particular used to
7. INTA stands for: acknowledgment provide handshaking:
a. Interrupt c. High access a. 8251
acknowledge d. Hold access b. 8254
b. Interrupt access 15. HRQ stands c. 8259
c. Interrupt for: d. 8255
address a. Hold request 23. Which is a
d. None of these b. Hold read programmable communication
8. CS stands for: c. Hold register interface:
a. Command select d. Hold resolver a. 8255
b. Chip select 16. AEN stands b. 8254
c. Chip series for: c. 8251
d. Command series a. Address enable d. 8259
9. RD stands for: b. Address 24. Which
a. Read equivalent programmable timer is used to
b. Register generate timing signal :
a. 8255 b. Mode 1 a. Conversion over
b. 8254 c. Mode 2 b. Conversion delay
c. 8251 d. None of these c. Conversion signal
d. 8259 33. Which mode is d. None of these
25. Which is widely used for double handshake in 8255: 42. Arrange the
used in interrupt controller with a a. Mode 0 flowing step of the general
number of microprocessor: b. Mode 1 algorithm for ADC interfacing:
a. 8251 c. Mode 2
b. 8254 d. None of these i. Issuing start of conversion
c. 8255 34. Which mode is pulse to ADC.
d. 8259 used for simple input or output
26. Which are used without handshaking: ii. Marking the end of the
DMA controllers with 8085/8086 a. Mode 0 conversion processes by the.
microprocessor: b. Mode 1
a. 8237 c. Mode 2 iii. Read digital data output of
b. 8257 d. None of these the ADC as equivalent digital
c. Both a and b 35. Which are used output.
d. None of these for port B in 8255:
27. Which provide a a. PC0-PC2 iv. Ensuring the stability of
mechanism to establish a link b. PC3-PC7 analogue input applied to the ADC.
between the microprocessor and c. PC6-PC7 a. 2,1,3,4
i/o device: d. PC3-PC5 b. 4,1,2,3
a. Input interface 36. Which are used c. 1,2,3,4
b. Output interface for port A in 8255 mode 1: d. 4,3,2,1
c. Both a and b a. PC0-PC2 43. Which chip is
d. None of these b. PC3-PC7 used for analogue to digital
28. In which the c. PC6-PC7 converter:
processor uses a protection of the d. PC3-PC5 a. 0809
memory address to represent I/O 37. Which are used b. 0808
ports: for handshake lines for port A in c. Both a & b
a. Memory mapped I/O 8255 mode 2: d. None of these
b. I/O memory mapped a. PC0-PC2 44. Which multiplexer
c. Both a and b b. PC3-PC7 by ADC 0808/0809:
d. None of these c. PC6-PC7 a. 2:4
29. The standard I /O d. PC3-PC5 b. 3:8
is also called: 38. AL&99H which c. 4:16
a. I/O mapped I/O operation is performed here: d. None of these
b. Isolated I/O a. Input 45. Which chip is
c. Both a and b b. Output used for DAC:
d. None of these c. Both a & b a. AD7521
30. The processor of d. None of these b. AD7522
knowing the status of device and 39. 34H&AX which c. AD7523
transferring the data with matching operation is performed here: d. AD7524
speeds is called: a. Input 46. Which converters
a. Handshaking b. Output convert binary number into their
b. Peripheral c. Progress equivalent voltages:
c. Ports d. None of these a. Analogue to analogue
d. None of these 40. Which chip used b. Analogue to digital
31. Which is designed for AD&DA converters in 8086 c. Digital to digital
to automatically manage the processor: d. Digital to analogue
handshake operation: a. 8251 47. An external
a. 8251 b. 8255 feedback resistor acts to control
b. 8254 c. 8254 the:
c. 8255 d. 8259 a. Gain
d. 8259 41. The time taken by b. Gate
32. Which mode is the ADC from the active edge of c. Loss
used for single handshake in 8255: SOC pulse till the active edge of d. Profit
a. Mode 0 EOC signal is called:
48. Which used to 56. Which generate
generate accurate time delays and an interrupt to the microprocessor
can be used for other timing after a certain interval of time:
application such as a real time clock a. 8251
an event counter a digital one shot b. 8254
a square wave generator and a c. 8255
complex wave form generator: d. 8259
a. 8251 programmable
timer
b. 8255 programmable
timer
c. 8254 programmable
timer
d. 8259 programmable
timer
49. 8254
programmable timer counter has
two inputs signals:
a. CLK
b. Gate
c. Both a & b
d. None of these
50. 8254
programmable timer counter has:
a. 1output signal
b. 2output signal
c. 3output signal
d. 4output signal
51. 8254 can operate
how many operating modes:
a. 2
b. 4
c. 6
d. 8
52. 8254 gate of a
counter is to either:
a. Enable counting
b. Disable counting
c. Both
d. None of these
53. 8254 counters can
count in the:
a. Binary
b. Decimal
c. Hexadecimal
d. A&B
54. How many modes
in 8254:
a. 2
b. 4
c. 6
d. 8
55. Which is the state
of gate signal for normal contains:
a. Low
b. High
c. Undefined
d. None of these
1. A central processing 10. Which is an integral part
unit, fabricated on a single of any microcomputer
chip of semiconductor is 6. System Bus Contains: system and its primary
called: purpose is to hold program
and data:
a. Address Bus
a. Microprocessor b. Data Bus
b. RAM c. Control Bus a. Memory unit
c. ROM d. All of these b. Register unit
d. None of these c. A and B
d. None of these
7. Microprocessor is the
2. Which is the architecture _____ of computer:
of microprocessor: 11. How many group of
memory unit:
a. Hand
a. CISC b. Heart
b. RISC c. Brain a. Four
c. All of these d. Leg b. Three
d. None of these c. Two
d. One
8. Microprocessor is
3. CISC stands for: fabricated on single chip
a. Complex Instruction using: 12. Which is the parts of
System Computer memory unit:
b. Complex Instruction Set
Car a. MOS
c. Complex Instruction Set b. ALU a. Processor memory
Computer c. CPU b. Main memory
d. None of these d. All of these c. Secondary memory
4. RISC stands for: d. All of these
a. Reduced Instruction Set
Computer 9. Which is the
b. Reduced Intergraded Set components of 13. MOS stand for:
Computer microprocessor:
c. Resource Instruction Set
Computer a. Metal oxide
d. Resource Instruction a. Register unit semiconductor
System Computer b. Arithmetic and logical b. Memory oxide
5. Which is the unit semiconductor
components of computer: c. Timing and control unit c. A and B
d. All of these d. None of these

a. System Bus
b. CPU
c. Memory Unit
d. All of these
14. Which system
communicates with the
outside word via the I/O
devices interfaced to it:
a. Microprocessor
b. Microcomputer
c. Digital computer
d. All of these
15. A computer which has
the microprocessor as______
is called as a microcomputer:
a. CPU
b. ALU
c. RU
d. None of these
16. The organization of I/O
devices create a difference
between _____:
a. Digital computer
b. Micro computer
c. A and B
d. None of these
17. How many generation of
microprocessor:
a. Four
b. Five
c. Six
d. Three
18. The___ was very d. All the above
successful in the calculator
market at that time:
23. Second
Generation_____?
a. Motorola 6800 and 6809
b. Microprocessor 4004
c. Intel 8085 a. 1974-1976
d. None of these b. 1974-1978
c. 1974-1972
d. None of these
19. How are the successful
microprocessor:
24. The beginning of very
efficient____ microprocessor
a. 8004 in second generation:
b. 5006
c. 4004
d. All of these a. 4-bit
b. 8-bit
c. 16-bit
20. How many d. 64-bit
microprocessor in the
market during the same
period: 25. Which are some of
popular processor:
a. 6
b. 8 a. Motorola 6800 and 6809
c. 3 b. Intel 8085
d. 5 c. Zilog Z80
d. All the above
21. PMOS stands for:
a. P-channel metal-oxide- 26. NMOS stands for:
semiconductor
b. P-channel memory – a. N-channel metal-oxide-
oxide-semiconductor semiconductor
c. Both A and B b. P-channel metal-oxide-
d. None of these semiconductor
22. Which provided the c. N-channel memory-
current: oxide-semiconductor
d. All the above
a. Low-cost
b. Slow-cost
c. Low-Output
 31. Intel used HMOS c. 16 bit
27. _____ Was more technology to d. 32 bit
common year: recreate_____:

36. They were fabricated

a. CRT a. 8084 A using a low power version of
b. TTL b. 8086 A the HMOS technology
c. Both A and B c. 8085 A called____:
d. None of these d. 8088 A

a. HSMOS
28. Which technology speed 32. HMOS stands for: b. HCMOS
faster and higher density: a. High performance metal c. HSSOM
oxide semiconductor d. None of these
b. High processor metal
a. PMOS oxide semiconductor
b. NMOS c. Both A and b 37. Motorola introduced
c. HMOS d. None of these _____ processor:
d. All the above 33. What is the period of
fourth generation:
a. 2 bit-RISC
29. What is the period of 3 b. 4 bit-RISC
generation: a. 1979-1980 c. 8 bit-RISC
b. 1981-1995 d. 32 bit-RISC
c. 1995-2000
a. 1979-1981 d. 1974-1980
b. 1979-1980 38. Motorola introduced 32
c. 1978-1979 bit RISC processor
d. 1978-1980 34. The fourth generation of called______:
microprocessor came really
as a soon boon to the_____:
30. Third generation a. MC 88100
microprocessor is dominated b. MC 81100
by____ microprocessor: a. Computing environment c. MC 80100
b. Processing environment d. MC 81000
c. Hot environment
a. 8 bit d. All of these
b. 4 bit 39. Period of fifth
c. 16 bit generation?
d. 64 bit 35. How many bit
microprocessor in the era
marked beginning of fourth a. 1974-1978
generation: b. 1979-1980
c. 1981-1985
d. 1995-till date
a. 4 bit
b. 8 bit
40. The growth of vacuum
tube technology has been
listed as follow:
a. 1946-1957
b. 1958-1964
c. 1985-1999
d. None of these
41. The growth of transistor
technology in_____:
a. 1946-1957
b. 1958-1964
c. 1985-1999
d. None of these
42. How are the growth of
SSI technology in_____:
a. 1956 on words
b. 1965 on words
c. 1978 on words
d. 1978 on words
43. The growth of medium
scale integration in______:
a. Till 1971
b. Till 1970
c. Till 1972
d. Till 1969
44. The growth of SSI up
to____:
a. 100 device on a chip
b. 200 device on a chip
c. 300 device on a chip
d. 400 device on a chip
49. Who is the represents
the fundamental process in
45. The growth of LSI the operation of the CPU:
technology on_____:
a. The fetch-execute cycle
a. 1994-1995 and pipelining
b. 1971-1977 b. The assembly
c. 1972-1978 c. Both A and B
d. None of these
d. None of these
46. Which is most commonly
measured in terms of MIPS 50. Which process
previously million instruction information at a much faster
per second: rate than it can retrieve it
from memory:
a. Microprocessor
b. Performance of a a. ALU
microprocessor b. Processor
c. Assembly line c. Microprocessor
d. None of these d. CPU
47. The range of this rating 51. _____ memory system
for which microprocessor which is discussed later can
of_____: improve matters in this
respect:
a. VLSI
b. Motorola a. Data memory
c. Intel b. Cache memory
d. Zilog c. Memory
d. None of these
48. How can we make
computers work faster? 52. The fetch-execute cycle
is to use a system know as:
a. The fetch-execute cycle
and pipelining a. Assembly line
b. The assembly b. Pipelining
c. Both A and B c. Cache
d. None of these d. None of these
 57. The ____ of can 61. Which is the
assembly line to be I/t p: microprocessor launch by
53. The time taken for all Fairchild company:
stages of the assembly line to
become active is called the: a. Clock period
b. Pipelining a. F-6
c. Throughput b. F-8
a. Flow through time d. Flow through c. Both A and B
b. Clock period d. None of these
c. Throughput
d. All of these 58. Which is the
microprocessor launched by 62. How many stages has
Motorola corporation fetch execute cycle:
54. The clock period is introduced:
denoted by:
a. 3
a. Mc6800 b. 4
a. T p b. 8080 c. 5
b. T1+T2+T3-------+T n c. IMP-8 d. 6
c. Pt d. RPS-8
d. None of these
63. Which is the world’s first
59. How many bit MC6800 microprocessor?
55. Ti is the time taken for microprocessor:
the ith stage and there are n
stages in the: a. Intel 4004
a. 4-bit b. Motorola 68020
b. 8-bit c. Intel8008
a. Throughput c. 16-bit d. None of these
b. Assembly line d. 32-bit
c. Both A and B
d. None of these 64. MOSFET stands for?
60. Motorola has declined a. Metal-oxide-
from having nearly semiconductor field effect
56. Who is the determined __________ share of the transistor
by the time taken by the microprocessor market to b. Metal-oxide-
stages the requires the most much smaller share: semiconductor fan effort
processing time: transistor
c. Both A and B
a. 30% d. None of these
a. Clock period b. 40%
b. Flow through c. 50%
c. Throughput d. 60%
d. None of these
65. What is the main 69. BCD stands for: c. Both A and B
problem of Intel 4004 d. None of these
microprocessor:
a. Binary coded decimal
b. Based coded decimal 74. Which Microprocessor
a. Speed c. Both A and B producer continue
b. Memory size d. None of these successfully to create newer
c. World width and improved version of the
d. All of these microprocessor:
70. Intel 8008
microprocessor realizing in:
66. The evolution of the 4 bit a. Intel
microprocessor ended when b. Motorola
Intel released in: a. 1971 c. Both A and B
b. 1973 d. None of these
c. 1999
a. 4004 d. 1988
b. 8008 75. Motorola has declined
c. 40964 how many % share of the
d. 4040 71. Intel 8008 microprocessor market to a
microprocessor’s upgraded much smaller share:
version is:
67. How many bit
microprocessor still survives a. 50%
in low-end application such a. 8080 b. 55%
as microwave ovens and b. 4004 c. 48%
small control system: c. Both A and B d. 51%
d. None of these

a. 4 bit 76. Which year Intel

b. 16 bit 72. Intel 8008 corporation introduced an
c. 32 bit microprocessor was updated version of the 8080-
d. 64 bit introduced in: the 8085:

68. Calculator are based a. 1971 a. 1965

on______ microprocessor: b. 1973 b. 1976
c. 1999 c. 1977
d. 1988 d. 1985
a. 4 bit
b. 16 bit
c. 32 bit 73. MC6800 microprocessor
d. 64 bit was introduced by:

a. Motorola corporation
b. Fairchild
77. In 1977 which 81. How many speed of 85. Who was introduce the
corporation introduced an 8088,8085,8086 80286 microprocessor
updated version of the 8080- microprocessor: updated on 8086,in 1983:
the 8085: a. 2.5 Million instruction
per second
b. 1.5 Million instruction a. Intel
a. Motorola per second b. Motorola
b. Intel c. 3.5 Million instruction c. Fairchild
c. Rockwell per second d. None of these
d. National d. 1.6 Million instruction
per second
82. Which year Intel family 86. Which is the
78. How many bit ensured: microprocessor launched by
microprocessor developed Intel:
by Intel:
a. 1965
b. 1978 a. Z-8
a. 4 bit c. 1981 b. 8080
b. 8 bit d. 1999 c. 8000
c. 32 bit d. None of these
d. 64 bit
83. Which corporation
decided to use 8088 87. Which is the
79. Which is the main microprocessor in personal microprocessor launched by
feature of 8085: computer: national semiconductor:

a. Internal clock generator a. IBM a. IMP-4

b. Internal system b. CRT b. IMP-8
controller c. PMN c. IMP-6
c. Higher clock frequency d. SPS d. IMP-7
d. All of these

84. Which processor 88. Which is the

80. Which is 16 Bit provided 1 MB memory: microprocessor launched by
microprocessor: Rockwell international:

a. 16-bit 8086 and 8088

a. 8088 b. 32-bit 8086 and 8088 a. RPS-4
b. 8086 c. 64-bit 8086 and 8088 b. RPS-6
c. 8085 d. 8-bit 8086 and 8088 c. RPS-8
d. All of these d. All of these
89. Which is the b. Slot 1 Version in Plastic
microprocessor launched by Cartridge
Zilog: 94. L1 cache memory is c. Both a and b
places at ______ d. None of these
99. What is the maximum
a. Z-2 clock speed of P III
b. Z-4 a. On Processor processors
c. Z-6 b. On Mother Board
d. Z-8 c. On Memory
d. All of these a. 1.0 GHz
b. 1.1 GHz
90. CAD stands for: c. 1.2 GHz
95. L2 cache memory is d. 1.3 GHz
places at ______
a. Computer aided drafting
b. Compare aided drafting 100. Power PC
c. Both A and B a. On Processor microprocessor architecture
d. None of these b. On Mother Board is developed by:
c. On Memory
d. All of these
91. GUI stands for: a. Apple
b. IBM
96. Pentium Pro can address c. Motorola
a. Graphical user interface _____ of memory: d. All of these
b. Graph used Intel
c. Graphical use inter
d. None of these a. 4 GB 101. Which is not the
b. 128 GB main architectural feature of
c. 256 GB Power PC:
92. VGA stands for: d. 512 GB a. It is not based on RISC
b. Superscalar
implementation
a. Visual graph area 97. Which is the professional c. Both 32 & 64 Bit
b. Visual graphics array or Business version of Intel d. Paged
c. Visual graph accept Processors: Memory management
d. All of these architecture
102. Alpha AXP is
a. Pentium II developed by:
93. Pentium Pro Processor b. Pentium Pro
contains: c. Pentium MMX
d. Pentium Xeon a. DEC
b. IBM
a. L1 Cache c. Motorola
b. L2 Cache d. Intel
c. Both L1 & L2 98. Pentium III processor is
d. None of these released in the form of:
a. Socket 370 Version
103. Which is not the c. Digital equipment
main feature of DEC Alpha: corporation
a. 64 Bit RISC processor d. None of these
b. Designed to replace 32
VAX(CISC)
c. Seven stage split 108. How many
integer/floating point architectural paradigms in
pipeline microprocessor:
d. Variable Instruction
length
104. Which is not the a. 2
open-source OS: b. 3
c. 4
d. 6
a. Debian
b. BSD Unix
c. Gentoo & Red Hat Linux 109. Which are the
d. Windows architectural paradigms in
microprocessor:

105. ISA stands for:

a. RISC
b. CISC
a. Instruct set area c. PISC
b. Instruction set d. A and B
architecture
c. Both a and b
d. None of these
110. CISC stands for:
a. Complex instruction set
106. RISC stands for: computer
a. Reduced Instruction set b. Camper instruct set of
computer computer
b. Reduced Instruct set c. Compared instruction
compare set computer
c. Reduced instruction d. None of these
stands computer 111. PC’s use____ based
d. All of these on this architecture:
107. DEC stands for:

a. CPU
a. Digital electronic b. ALU
computer c. MU
d. None of these
b. Digital electronic
corporation
1) Who is the brain of
6) Which is the a. Calculator
computer:
microprocessor comprises: b. Dedicated
c. Accumulator
d. None of these
a. ALU
a. Register section
b. CPU
b. One or more ALU
c. MU
c. Control unit 11) Accumulator based
d. None of these d. All of these microprocessor example are:

2) Which technology using

7) The register section is a. Intel 8085
the microprocessor is
related to______ of the b. Motorola 6809
fabricated on a single chip:
computer: c. A and B
d. None of these
a. POS
a. Processing
b. MOS
b. ALU 12) A set of register which
c. ALU
c. Main memory contain are:
d. ABM
d. None of these

a. data
3) MOS stands for:
8) What is the store by b. memory addresses
a. Metal oxide register: c. result
semiconductor
d. all of these
b. Memory oxide
semiconductor
a. data
c. Metal oxide select
b. operands 13) How many types are
d. None of these
c. memory primarily register:
4) In which form CPU
d. None of these
provide output:
a. 1
9) How many types of b. 2
a. Computer signals
classification of processor c. 3
b. Digital signals
based on register section: d. 4
c. Metal signals
d. None of these
a. 1 14) There are primarily two
b. 2 types of register:
5) How many types of
c. 3
microprocessor comprises:
d. 4
a. general purpose
register
a. 3
10) In Microprocessor one of b. dedicated register
b. 6
the operands holds a special c. A and B
c. 9
register called: d. none of these
d. 4
15) Which register is a 24) Single address computer
temporary storage location: instruction has two parts:
20) SP stands for:

a. general purpose a. The operation code

register a. Status pointer b. The operand
b. dedicated register b. Stack pointer c. A and B
c. A and B c. a and b d. None of these
d. none of these d. None of these

25) LA stands for:

16) How many parts of 21) The act of acquiring an
dedicated register: instruction is referred as
the____ the instruction: a. Load accumulator
b. Least accumulator
a. 2 c. Last accumulator
b. 4 a. Fetching d. None of these
c. 5 b. Fetch cycle
d. 6 c. Both a and b
d. None of these 26) ED stands for:

17) Name of typical

dedicated register is: 22) How many bit of a. Enable MRD
instruction on our simple b. Enable MDR
computer consist of c. Both a and b
a. PC one____: d. None of these
b. IR
c. SP
d. All of these a. 2-bit 27) LM stands for:
b. 6-bit
c. 12-bit
18) PC stands for: d. None of these a. Least MAR
b. Load MAR
c. Least MRA
a. Program counter 23) How many parts of single d. Load MRA
b. Points counter address computer instruction
c. Paragraph counter :
d. Paint counter 28) Causing a flag to became
0 is called:
a. 1
19) IR stands for: b. 2
c. 3 a. Clearing a flag
d. 4 b. Case a flag
a. Intel register c. Both a and b
b. In counter register d. None of these
c. Index register
d. Instruction register
29) Which are the flags of 36) _________ Stores the 40) Which is used to store
status register: instruction currently being critical pieces of data during
executed: subroutines and interrupts:

a. Over flow flag

b. Carry flag a. Instruction register a. Stack
c. Half carry flag b. Current register b. Queue
d. Zero flag c. Both a and b c. Accumulator
e. Interrupt flag d. None of these d. Data register
f. Negative flag
g. All of these
37) In which register 41) The area of memory with
instruction is decoded addresses near zero are
30) The carry is operand by: prepared and ultimately called:
a. C executed:
31) The sign is operand by:
a. S a. High memory
32) The zero is operand by: a. Instruction register b. Mid memory
a. Z b. Current register c. Memory
33) The overflow is operand c. Both a and b d. Low memory
by: d. None of these
a. O
34) _____ is the condition: 42) The point where control
38) The status register is also returns after a subprogram is
called the____: completed is known as the :
a. CD a. Return address
b. IR b. Main Address
c. Both a and b a. Condition code c. Program Address
d. None of these register d. Current Address
b. Flag register 43) The subprogram finish
c. A and B the return instruction
35) ____ causes the address d. None of these recovers the return address
of the next microprocessor from the:
to be obtained from the a. Queue
memory: 39) BCD stands for: b. Stack
c. Program counter
d. Pointer
a. CRJA a. Binary coded 44) The processor uses the
b. ROM decimal stack to keep track of where
c. MAP b. Binary coded the items are stored on it
d. HLT decoded this by using the:
c. Both a & b a. Stack pointer
d. none of these register
b. Queue pointer
register
c. Both a & b
d. None of these
45) Which point to the ___ c. Pulling b. Register
of the stack: d. None of these c. Processor
a. TOP 53) The CU is designed by d. Bus
b. START using which techniques: 59) Which is called
c. MID a. HARDWIRED superhighway:
d. None of these CONTROLS a. Processor
46) Stack words on: b. MICROPROGRAMIN b. Multiplexer
a. LILO G c. Backbone bus
b. LIFO c. NANOPROGRAMIN d. None of these
c. FIFO G 60) The external system bus
d. None of these d. ALL OF THESE architecture is created using
47) Which is the basic stack 54) The 16 bit register is from ______ architecture:
operation: separated into groups of 4 a. Pascal
a. PUSH bit where each groups is b. Dennis Ritchie
b. POP called: c. Charles Babbage
c. BOTH A and B a. BCD d. Von Neumann
d. None of these b. Nibble 61) The network of wires or
48) SP stand for: c. Half byte electronic path ways on
a. Stack pointer d. None of these mother board back side:
b. Stack pop 55) A nibble can be a. PCB
c. Stack push represented in the from of: b. BUS
d. None of these a. Octal digit c. BOTH A and B
49) How many bit stored by b. Decimal d. None of these
status register: c. Hexadecimal 62) Which Bus connects CPU
a. 1 bit d. None of these & level 2 cache:
b. 4 bit 56) The left side of any a. Rear side bus
c. 6 bit binary number is called: b. Front side bus
d. 8 bit a. Least significant c. Memory side bus
50) Which is the important digit d. None of these
part of a combinational logic b. Most significant 63) Which bus carry
block: digit addresses:
a. Index register c. Medium significant a. System bus
b. Barrel shifter digit b. Address bus
c. Both a & b d. low significant digit c. Control bus
d. None of these 57) MSD stands for: d. Data bus
a. Least significant 64) A 16 bit address bus can
digit generate___ addresses:
51) The structure of the b. Most significant a. 32767
stack is _______ type digit b. 25652
structure: c. Medium significant c. 65536
a. First in last out digit d. none of these
b. Last in last out d. low significant digit
c. Both a & b 58) _____ a subsystem that
d. None of these transfer data between
52) The data in the stack is computer components inside
called: a computer or between
a. Pushing data computer:
b. Pushed a. Chip
65) The processor c. 216=65536 a. Dynamic RAM
80386/80486 and the d. None of these b. Static RAM
Pentium processor uses 72) PROM stands for: c. Permanent RAM
_____ bits address bus: a. Programmable d. SD RAM
a. 16 read-only memory 81) Which RAM is created
b. 32 73) EPROM stands for: using MOS transistors:
c. 36 a. Erasable a. Dynamic RAM
d. 64 Programmable read-only b. Static RAM
66) CPU can read & write memory c. Permanent RAM
data by using : 74) Each memory location d. SD RAM
a. Control bus has: 82) Which latch is mostly
b. Data bus a. Address used creating memory
c. Address bus b. Contents register:
d. None of these c. Both A and B a. SR-Latch
67) Which bus transfer d. None of these b. JK-Latch
singles from the CPU to 75) Which is the type of c. D-Latch
external device and others microcomputer memory: d. T-Latch
that carry singles from a. Processor memory 83) Which statement is false
external device to the CPU: b. Primary memory about WR signal:
a. Control bus c. Secondary memory a. WR signal controls
b. Data bus d. All of these the input buffer
c. Address bus 76) Secondary memory can b. The bar over WR
d. None of these store____: means that this is an active
68) Which is not the control a. Program store code low signal
bus signal: b. Compiler c. The bar over WR
a. READ c. Operating system means that this is an active
b. WRITE d. All of these high signal
c. RESET 77) Secondary memory is d. If WR is 0 then the
d. None of these also called____: input data reaches the latch
69) When memory read or a. Auxiliary input
I/O read are active data is to b. Backup store 84) Which technique is used
the processor : c. Both A and B for main memory array
a. Input d. None of these design:
b. Output 78) Customized ROMS are a. Linear decoding
c. Processor called: b. Fully decoding
d. None of these a. Mask ROM c. Both A and B
70) When memory write or b. Flash ROM d. None of these
I/O read are active data is c. EPROM 85) CS stands for:
from the processor: d. None of these a. Cable select
a. Input 79) The ram which is created b. Chip select
b. Output using bipolar transistors is c. Control select
c. Processor called: d. Cable system
d. None of these a. Dynamic RAM 86) WE stands for:
71) Using 12 binary digits b. Static RAM a. Write enable
how many unique house c. Permanent RAM b. Wrote enable
addresses would be possible: d. DDR RAM c. Write envy
a. 28=256 80) Which type of RAM d. None of these
b. 212=4096 needs regular referred:
87) When CS _____ the chip distribution are eliminated d. None of these
is not selected at all hence by the use of ______ address 99) Which microprocessor
D7 to D0 are driven to high technique: to read an item from
impedance state: a. Fully decoding memory:
a. High b. Half decoding a. VAM
b. Low c. Both a & b b. SAM
c. Medium d. None of these c. MOC
d. Stand by 93) A microprocessor retries d. None of these
88) The capacity of this chip instructions from : 100) Which bus plays a
is 1KB they are organized in a. Control memory crucial role in I/O:
the form of 1024 words with b. Cache memory a. System bus
8 bit word The what is the c. Main memory b. Control bus
site of address bus: d. Virtual memory c. Address bus
a. 8 bit 94) Which register is used to d. Both A and B
b. 10 bit communicate with memory: 101) Which register is
c. 12 bit a. MAR connected to the memory by
d. 16 bit b. MDR way of the address bus:
89) Which storage technique c. Both A and B a. MAR
dose not decoding circuit: d. None of these b. MDR
a. Linear decoding 95) SAM stands for: c. SAM
b. Fully decoding a. Simple architecture d. None of these
c. Partially machine 102) How many bit of
d. None of these b. Solved architecture MAR register:
90) In linear decoding machine a. 8-bit
address bus of 16-bit wide c. Both a & b b. 16-bit
can connect only ____ of d. None of these c. 32-bit
RAM. 96) MAR stands for: d. 64-bit
a. 16 KB a. Memory address 103) MOC stands for:
b. 6KB register a. Memory operation
c. 12KB b. Memory address complex
d. 64KB recode b. Micro operation
91) Which statement is c. Micro address complex
wrong according to linear register c. Memory operation
decoding : d. None of these complete
a. Address map is not 97) MDR stands for: d. None of these
contiguous. a. Memory data 104) Which are the READ
b. Confects occur if register operation can in simple
two of the select lines b. Memory data steps:
become active at the same recode a. Address
time c. Micro data register b. Data
c. If all unused d. None of these c. Control
address lines are not used as 98) VAM stands for: d. All of these
chip selectors then these a. Valid memory 105) The upper red arrow
unused lines become don’t address show that CPU sends out the
cares b. Virtual memory control signals____ and
d. None of these address _____ indicate the data is
92) The problem of bus c. Variable memory read from the memory:
confect and sparse address address a. Memory request
b. Read 112) The CPU sends out a the microprocessor and a
c. Both A and B ____ signal to indicate that physical I/O device:
d. None of these valid data is available on the a. 2
106) The information is data bus: b. 3
transferred from the_____ a. Read c. 4
and ____ specified register: b. Write d. 5
a. MDR c. Both A and B 119) The standard I/O is
b. CPU d. None of these also called:
c. Both A and B 113) The ____ place the a. Isolated I/O
d. None of these data from a register onto the b. Parallel I/O
107) The information on data bus: c. both a and b
the data bus is transferred to a. CPU d. none of these
the ______register: b. ALU 120) standard I/O uses
a. MOC c. Both A and B which control pin on the
b. MDR d. None of these micro processor:
c. VAM 114) The CPU removes a. IO/M
d. CPU the ___ signal to 121) A___ on this pin
108) The lower red curvy complete the memory write indicates a memory
arrow show that CPU places operation: operation:
the address extracted from a. Read a. Low
the memory location on b. Write b. High
the_____: c. Both A and B c. Medium
a. Address bus d. None of these d. None of these
b. System bus 115) The value memvar 122) The external device
c. Control bus must be transferred to the is connected to a pin called
d. Data bus ___: the ______ pin on the
109) DMA stands for: a. Computer processor chip.
a. Direct memory b. CPU a. Interrupt
access c. Both A and B b. Transfer
b. Direct memory d. None of these c. Both
allocation 116) The microcomputer d. None of these
c. Data memory system by using the 123) The DMA controllers
access ____device interface: are special hardware
d. Data memory a. Input embedded into the chip in
allocation b. Output modern integrate processor
110) DMA stands for: c. Both A and B that ____and_____ to the
a. Dynamic memory d. None of these system;
access 117) How bit a. Data transfer
b. Data memory microprocessor inexpensive b. arbitrate access
access a separate interface is c. Both A and B
c. Direct memory provided with I/O device: d. None of these
access a. 2 bit
d. Both B and C b. 4 bit
111) CRT stands for: c. 8 bit
a. Cathode ray tube d. 32 bit
b. Compared ray tube 118) How many ways of
c. Command ray tube transferring data between
d. None of these
124) The CPU completes
yields control of the bus to
the DMA controller via:
a. DMA acknowledge
signal
b. DMA integrated
signal
c. DMA implicitly
signal
d. None of these
125) The mode of DMA
are:
a. Single transfer
b. Block transfer
c. Burst –block
transfer
d. Repeated single
transfer
e. Repeated–block
transfer
f. Repeated Burst –
block transfer
g. All of these
1. BIU STAND FOR:
a. Bus interface unit
b. Bess interface unit
c. A and B
d. None of these
2. EU STAND FOR:
a. Execution unit
b. Execute unit
c. Exchange unit
d. None of these
3. The register can be
divided are:
a. 3
b. 4
c. 5
d. 6
4. Which are the part of
architecture of 8086:
a. The bus interface unit
b. The execution unit
c. Both A and B
d. None of these
5. Which are the four
categories of registers:
a. General- purpose
register
b. Pointer or index registers
c. Segment registers
d. Other register
e. All of these
6. Eight of the register are 11. Which are the segment:
known as:
a. CS: Code segment
a. General- purpose b. DS: data segment
register c. SS: Stack segment
b. Pointer or index registers d. ES:extra segment
c. Segment registers
d. Other register
e. All of these
12. The acculatator is 16 bit
7. The four index register wide and is called:
can be used for:
a. AX
a. Arithmetic operation b. AH
b. Multipulation operation c. AL
c. Subtraction operation d. DL
d. All of these
13. The upper 8 bit are
8. IP Stand for: called______:
a. Instruction pointer a. BH
b. Instruction purpose b. BL
c. Instruction paints c. AH
d. None of these d. CH
9. CS Stand for: 14. The lower 8 bit are
called_______:
a. Code segment
b. Coot segment a. AL
c. Cost segment b. CL
d. Counter segment c. BL
d. DL
10. DS Stand for:
a. Data segment
b. Direct segment
c. Declare segment
d. Divide segment
15. IP stand for: 19. How many bits the
instruction pointer is wide:
a. Industry pointer
b. Instruction pointer a. 16 bit
c. Index pointer b. 32 bit
d. None of these c. 64 bit
d. 128 bit
16. Which has great
important in modular 20. How many type of
programming: addressing in memory:
a. Stack segment a. Logical address
b. Queue segment b. Physical address
c. Array segment c. Both A and B
d. All of these d. None of these
17. Which register 21. The size of each segment
containing the 8086/8088 in 8086 is:
flag:
a. 64 kb
a. Status register b. 24 kb
b. Stack register c. 50 kb
c. Flag register d. 16kb
d. Stand register
22. The physical address of
18. Which flag are used to memory is :
record specific
characteristics of arithmetic
and logical instructions: a. 20 bit
b. 16 bit
c. 32 bit
a. The stack d. 64 bit
b. The stand
c. The status
d. The queue 23. The _______ address of a
memory is a 20 bit address
for the 8086 microprocessor:
a. Physical
b. Logical
c. Both
d. None of these
24. To provide clarity in case
of the status register_______
and __________
placeholders are displayed:
a. Binary
b. Hexadecimal
c. Both
d. None of these
25. The pin configuration of
8086 is available in
the________:
a. 40 pin
b. 50 pin
c. 30 pin
d. 20 pin
26. DIP stand for:
a. Deal inline package
b. Dual inline package
c. Direct inline package
d. Digital inline package
27. PA stand for:
a. Project address
b. Physical address
c. Pin address
d. Pointer address
28. SBA stand for: 33. DS stand for: 38. AH stand for:

a. Segment bus address a. Default segment a. Accumulator high

b. Segment bit address b. Defect segment b. Address high
c. Segment base address c. Delete segment c. Appropriate high
d. Segment byte address d. Definition segment d. Application high

29. EA stand for: 34. ALE stand for: 39. AL stand for:

a. Effective address a. Address latch enable a. Accumulator low

b. Electrical address b. Address light enable b. Address low
c. Effect address c. Address lower enable c. Appropriate low
d. None of these d. Address last enable d. Application low

30. BP stand for: 35. AD stand for: 40. Which are the
categorized of flag:

a. Bit pointer a. Address data

b. Base pointer b. Address delete a. Conditional flag
c. Bus pointer c. Address date b. Control flag
d. Byte pointer d. Address deal c. Both a and b
d. None of these

31. DI stand for: 36. NMI stand for:

41. Which are the general
register:
a. Destination index a. Non mask able interrupt
b. Defect index b. Non mistake interrupt
c. Definition index c. Both a. AX: Accumulator
d. Delete index d. None of these b. BX: Base
c. CX: Count
d. DX: Data
32. SI stand for: 37. PC stand for: e. All of these

a. Stand index a. program counter

b. Source index b. project counter
c. Segment index c. protect counter
d. Simple index d. planning counter
42. ________ is the most
important segment and it
contains the actual assembly 46. which is the small 50. Which is the type of
language instruction to be amount of high- speed cache memory:
executed by the memory used to work
microprocessor: directly with the
microprocessor: a. Fully associative cache
b. Direct-mapped cache
a. Data segment c. Set-associative cache
b. Code segment a. Cache d. All of these
c. Stack segment b. Case
d. Extra segment c. Cost
d. Coos 51. Which memory is used to
holds the address of the data
43. The offset of a particular stored in the cache :
segment varies from 47. The cache usually gets its
_________: data from the_________
whenever the instruction or a. Associative memory
data is required by the CPU: b. Case memory
a. 000H to FFFH c. Ordinary memory
b. 0000H to FFFFH d. None of these
c. 00H to FFH a. Main memory
d. 00000H to FFFFFH b. Case memory
c. Cache memory 52. Direct mapping is a
d. All of these _________ to implement
44. Which are the factor of cache memory :
cache memory:
48. The amount of
information which can be a. Cheaper way
a. Architecture of the placed at one time in the b. Case way
microprocessor cache memory is c. Cache way
b. Properties of the called_________: d. None of these
programs being executed
c. Size organization of the
cache a. Circle size 53. A fourth bit called the
d. All of these b. Line size _________:
c. Wide line size
d. None of these
45. ________ is usually the a. Direct bit
first level of memory access 49. How many type of cache b. Cache bit
by the microprocessor: memory: c. Valid bit
d. All of these

a. Cache memory a. 1
b. Data memory b. 2
c. Main memory c. 3
d. All of these d. 4
54. FIFO stand for:
a. First in first other
b. First in first out
c. First in first over
d. None of these
55. Microprocessor
reference that are available
in the cache are
called______:
a. Cache hits
b. Cache line
c. Cache memory
d. All of these
56. Microprocessor
reference that are not
available in the cache are
called_________:
a. Cache hits
b. Cache line
c. Cache misses
d. Cache memory
57. __________ is the most
commonly used cache
controller with a number of
processor sets:
a. L211 controller
b. L210 controller
c. L214 controller
d. None of these
58. LFB stand for: 63. WA stand for:
a. Line full buffers a. Write allocate
b. Line fill buffers b. Wrote allocate
c. Line fan buffers c. Way allocate
d. None of these d. Word allocate
59. LRB stand for: 64. In case of direct- mapped
cache lower order line
address bits are used the
a. Line read buffers access the ___________:
b. Line ready buffers
c. Line root buffers
d. Line right buffers a. RAM
b. ROM
c. Directory
60. EB stand for: d. HDD
a. Effect buffers 65. The index high order bits
b. Effecting buffers in the address known
c. Effection buffers as_________:
d. None of these
a. tags
61. EB stand for: b. label
c. point
d. location
a. Effect buffers
b. Effecting buffers
c. Effection buffers e.
d. Eviction buffers 66. The parity bits are used
to check that a__________:
62. WB stand for:
a. Two bit error
b. Single bit error
a. Write buffers c. Multi bit error
b. Written buffers d. None of these
c. Wrote buffers
d. None of these
67. Who works as cache on 71. The principal of working
the variable: of the cache memory largely
depends on which locality:
a. Register
b. Memory a. Spatial locality
c. Pointer b. Temporal locality
d. Segment c. Sequentially
d. All of these
68. Second level is a cache
on the ________: 72. Who work as a cache for
the page table:
a. Main memory
b. RAM a. TLB
c. Both b. TLP
d. None of these c. LEB
d. WAB
69. The memory system is
said to be effective if the 73. Which formula is used to
access time of the cache is calculate the number of read
close to the effective access stall cycles:
time of the_____: a. Reads* Read miss rate *
Read miss penalty
b. Write* (Write miss rate
a. ROM * Write miss penalty)+write
b. RAM buffer stalls
c. HDD c. Memory access * Cache
d. Processor miss rate * Cache miss
penalty
d. None of these
70. Cache is usually 74. Which formula is used to
the____________ of calculate the number of
memory access by the write stall cycles:
microprocessor: a. Reads* Read miss rate *
Read miss penalty
b. Write* (Write miss rate
a. First level * Write miss penalty)+write
b. Second level buffer stalls
c. Third level c. Memory access * Cache
d. Fourth level miss rate * Cache miss
penalty
d. None of these
75. Which formula is used to
calculate the number of
memory stall cycles:
a. Reads* Read miss rate *
Read miss penalty
b. Write* (Write miss rate
* Write miss penalty)+write
buffer stalls
c. Memory access * Cache
miss rate * Cache miss
penalty
d. None of these
76. Which causes the
microprocessor to
immediately terminate its
present activity:
a. RESET signal
b. INTERUPT signal
c. Both
d. None of these
77. Which are the cache
controller ports:
a. 64-bit AHB-Lite slave
ports
b. 64-bit AHB-Lite master
ports
c. Both
d. None of these
78. Cache can be controlled
__________:
a. 16KB-2MB
b. 17 KB-2MB
c. 18 KB-2MB
d. 19 KB-2MB
79. Which is responsible for
all the outside world
communication by the
microprocessor:
a. BIU
b. PIU
c. TIU
d. LIU

e.
80. INTR: it implies
the__________ signal:

a. INTRRUPT REQUEST
b. INTRRUPT RIGHT
c. INTRRUPT RONGH
d. INTRRUPT RESET
 a. Interrupt d. Direct memory
1. EOC stands for: acknowledge acknowledgment
a. End of b. Interrupt 13. HLD stands
conversion access for:
b. Emphasize of c. Interrupt a. High
conversion address b. Hour
c. End of d. None of these c. Hold
controller 8. CS stands for: d. None of these
d. None of these a. Command 14. HLDA stands
2. IRR stands for: select for:
a. Interrupt b. Chip select a. High
request register c. Chip series acknowledgment
b. Input request d. Command b. Hold
register series acknowledgment
c. Interrupt 9. RD stands for: c. High access
resolver register a. Read d. Hold access
d. Input resolver b. Register 15. HRQ stands
register c. Request for:
3. ISR stands for: d. Real a. Hold request
a. Interrupt 10. ICW stands b. Hold read
service register for: c. Hold register
b. Input service a. Interrupt d. Hold resolver
register command words 16. AEN stands
c. In-service b. Interrupt command for:
register write a. Address enable
d. All of these c. Initialization b. Address
4. PR stands for: command words equivalent
a. Priority register d. Initialization c. Acknowledgme
b. Priority command write nt enable
resolver 11. OCW stands d. Acknowledgme
c. Priority request for: nt equivalent
d. None of these a. Operational 17. ADSTB stands
5. IMR stands for: command words for:
a. Input mask b. Operational a. Access strobe
register conjunction words b. Access strobe
b. Input mask c. Operational c. Address store
resolver control words d. Address
c. Interrupt mask d. Operational strobe
resolver cost words 18. MEMER and
d. Interrupt mask 12. DMA stands MEMW means:
register for: a. Memory read
6. INT stands for: a. Direct memory b. Memory write
a. Input allocation c. Both a and b
b. Interrupt b. Direct memory d. None of these
c. Both a and b access 19. HRQ and
d. None of these c. Direct memory HLDA means:
7. INTA stands application a. Hold request
for:
b. Hold with a number of 31. Which is
acknowledgment microprocessor: designed to automatically
c. Both a and b a. 8251 manage the handshake
d. None of these b. 8254 operation:
20. ADC stands for: c. 8255 a. 8251
a. Analogue to d. 8259 b. 8254
analogue converters 26. Which are used c. 8255
b. Analogue to digital DMA controllers with d. 8259
converters 8085/8086 microprocessor: 32. Which mode is
c. Digital to digital a. 8237 used for single handshake in
converters b. 8257 8255:
d. Digital to analogue c. Both a and b a. Mode 0
converters d. None of these b. Mode 1
21. DAC stands for: 27. Which provide c. Mode 2
a. Analogue to a mechanism to establish a d. None of these
analogue converters link between the 33. Which mode is
b. Analogue to digital microprocessor and i/o used for double handshake
converters device: in 8255:
c. Digital to digital a. Input interface a. Mode 0
converters b. Output interface b. Mode 1
d. Digital to analogue c. Both a and b c. Mode 2
converters d. None of these d. None of these
22. Which is the 28. In which the 34. Which mode is
commonly used processor uses a protection used for simple input or
programmable interface and of the memory address to output without handshaking:
particular used to provide represent I/O ports: a. Mode 0
handshaking: a. Memory mapped b. Mode 1
a. 8251 I/O c. Mode 2
b. 8254 b. I/O memory d. None of these
c. 8259 mapped 35. Which are used
d. 8255 c. Both a and b for port B in 8255:
23. Which is a d. None of these a. PC0-PC2
programmable 29. The standard I b. PC3-PC7
communication interface: /O is also called: c. PC6-PC7
a. 8255 a. I/O mapped I/O d. PC3-PC5
b. 8254 b. Isolated I/O 36. Which are used
c. 8251 c. Both a and b for port A in 8255 mode 1:
d. 8259 d. None of these a. PC0-PC2
24. Which 30. The processor b. PC3-PC7
programmable timer is used of knowing the status of c. PC6-PC7
to generate timing signal : device and transferring the d. PC3-PC5
a. 8255 data with matching speeds is 37. Which are used
b. 8254 called: for handshake lines for port
c. 8251 a. Handshaking A in 8255 mode 2:
d. 8259 b. Peripheral a. PC0-PC2
25. Which is widely c. Ports b. PC3-PC7
used in interrupt controller d. None of these c. PC6-PC7
d. PC3-PC5
38. AL&99H which c. 1,2,3,4 48. Which used to
operation is performed here: d. 4,3,2,1 generate accurate time
a. Input 43. Which chip is delays and can be used for
b. Output used for analogue to digital other timing application such
c. Both a & b converter: as a real time clock an event
d. None of these a. 0809 counter a digital one shot a
39. 34H&AX which b. 0808 square wave generator and a
operation is performed here: c. Both a & b complex wave form
a. Input d. None of these generator:
b. Output 44. Which a. 8251
c. Progress multiplexer by ADC programmable timer
d. None of these 0808/0809: b. 8255 programmable
40. Which chip a. 2:4 timer
used for AD&DA converters b. 3:8 c. 8254
in 8086 processor: c. 4:16 programmable timer
a. 8251 d. None of these d. 8259 programmable
b. 8255 45. Which chip is timer
c. 8254 used for DAC: 49. 8254
d. 8259 a. AD7521 programmable timer counter
41. The time taken b. AD7522 has two inputs signals:
by the ADC from the active c. AD7523 a. CLK
edge of SOC pulse till the d. AD7524 b. Gate
active edge of EOC signal is 46. Which c. Both a & b
called: converters convert binary d. None of these
a. Conversion over number into their equivalent 50. 8254
b. Conversion delay voltages: programmable timer counter
c. Conversion signal a. Analogue to has:
d. None of these analogue a. 1output signal
42. Arrange the b. Analogue to digital b. 2output signal
flowing step of the general c. Digital to digital c. 3output signal
algorithm for ADC d. Digital to analogue d. 4output signal
interfacing: 47. An external 51. 8254 can
i. feedback resistor acts to operate how many operating
Issuing start of conversion control the: modes:
pulse to ADC. a. Gain a. 2
ii. b. Gate b. 4
Marking the end of the c. Loss c. 6
conversion processes by the. d. Profit d. 8
iii. 52. 8254 gate of a
Read digital data output of counter is to either:
the ADC as equivalent digital a. Enable counting
output. b. Disable counting
iv. c. Both
Ensuring the stability of d. None of these
analogue input applied to 53. 8254 counters
the ADC. can count in the:
a. 2,1,3,4 a. Binary
b. 4,1,2,3 b. Decimal
c. Hexadecimal
d. A&B
54. How many
modes in 8254:
a. 2
b. 4
c. 6
d. 8
55. Which is the
state of gate signal for
normal contains:
a. Low
b. High
c. Undefined
d. None of these
56. Which
generate an interrupt to the
microprocessor after a
certain interval of time:
a. 8251
b. 8254
c. 8255
d. 8259