Gray to Binary Conversion design in

Xilinx

Submitted by:
PUNEET AGARWAL (13000117076)

Submitted for the partial fulfillment for the course

Techno India,
EM 4/1, SaltLake, Sector V, Kolkata – 700 091

Techno Main Salt Lake

EM-4/1, Sector-V, Salt Lake
Kolkata- 700091

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DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

 ACKNOWLEDGEMENT

We would like to express our sincere gratitude to Prof. Nairanjana Chowdhury, faculty for the course on
Computer Architecture (CS403), of the department of Computer Science and Engineering, whose role was
invaluable for this mini project. We are extremely thankful for the keen interest she took in advising us, for the
books and reference materials provided and for the moral support extended to us.

Place: Techno Main, Salt Lake

Date:

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Table of Contents
 Introduction……………………………………..1
 Problem Definition……………………………...2
a) Design Utilities
b) Technical Details
 Implementation………………………………3-4
a) Source code for schematic and test bench….5
b) Schematic Diagram………………………….5
 Test Results…………………………………….6
 Conclusion……………………………………..7
 References……………………………………...8
Introduction
The reflected binary code (RBC), also known just as reflected binary (RB) or Gray code after
Frank Gray, is an ordering of the binary numeral system such that two successive values differ in
only one bit (binary digit). The reflected binary code was originally designed to prevent spurious
output from electromechanical switches. Today, Gray codes are widely used to facilitate error
correction in digital communications such as digital terrestrial television and some cable TV
systems.
Problem Definition
Gray to binary code converter in Xilinx ISE

Design
3.1. Technical Environment –
1. We have used Xilinx ISE on Ubuntu 18.04 in order to do this project.
2. Test bench Viewing tool used is iSim
3.2. Detailed Design –
 The code converts a 4 bit binary to gray code.
 Xor Gates are used
Implementation
Schematic:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity gray2bin is
port( G : in std_logic_vector(3 downto 0); --gray code input
bin : out std_logic_vector(3 downto 0) --binary output
);
end gray2bin;

architecture gate_level of gray2bin is

begin

--xor gates.
bin(3) <= G(3);
bin(2) <= G(3) xor G(2);
bin(1) <= G(3) xor G(2) xor G(1);
bin(0) <= G(3) xor G(2) xor G(1) xor G(0);

end;

TestBench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity gray2bin is
port( G : in std_logic_vector(3 downto 0); --gray code input
bin : out std_logic_vector(3 downto 0) --binary output
);
end gray2bin;

architecture gate_level of gray2bin is

begin

--xor gates.
bin(3) <= G(3);
bin(2) <= G(3) xor G(2);
bin(1) <= G(3) xor G(2) xor G(1);
bin(0) <= G(3) xor G(2) xor G(1) xor G(0);

end;

Single Testbench for both the designs:

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is

-- component declaration for the unit under test's (uut)

component bin2gray is
port( bin : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0)
);
end component;

component gray2bin is
port( g : in std_logic_vector(3 downto 0);
bin : out std_logic_vector(3 downto 0)
);
end component;

signal bin,g,bin_out : std_logic_vector(3 downto 0) := (others => '0');

begin
-- instantiate the unit under test's (uut)
uut1: bin2gray port map (
bin => bin,
g => g
);

uut2: gray2bin port map (

g => g,
bin => bin_out
);

-- stimulus process
stim_proc: process
begin
bin <= "0000"; wait for 10 ns;
bin <= "0001"; wait for 10 ns;
bin <= "0010"; wait for 10 ns;
bin <= "0011"; wait for 10 ns;
bin <= "0100"; wait for 10 ns;
bin <= "0101"; wait for 10 ns;
bin <= "0110"; wait for 10 ns;
bin <= "0111"; wait for 10 ns;
bin <= "1000"; wait for 10 ns;
bin <= "1001"; wait for 10 ns;
bin <= "1010"; wait for 10 ns;
bin <= "1011"; wait for 10 ns;
bin <= "1100"; wait for 10 ns;
bin <= "1101"; wait for 10 ns;
bin <= "1110"; wait for 10 ns;
bin <= "1111"; wait for 10 ns;
wait;
end process;
end;

Test Results:
Conclusion
The problem with natural binary codes is that physical switches are not ideal: it is very unlikely
that physical switches will change states exactly in synchrony. In the transition between the two
states shown above, all three switches change state. In the brief period while all are changing, the
switches will read some spurious position. Even without keybounce, the transition might look
like 011 — 001 — 101 — 100. When the switches appear to be in position 001, the observer
cannot tell if that is the "real" position 001, or a transitional state between two other positions. If
the output feeds into a sequential system, possibly via combinational logic, then the sequential
system may store a false value.
The test results for all the cases are successful and we may conclude that the design works.
References
 https://en.wikipedia.org/
 http://verilogcodes.blogspot.com