PROJECT REPORT PHASE 1

DESIGN OF MEMORIES USING ADIABATIC LOGIC

GROUP NUMBER: 22

BRUNDA V (1PE15EC039)
JIGYASA N. (1PE15EC060)
MAHESHWARI

PAVITRA M (1PE15EC097)
NIKHIL H V (1PE15EC418)
VISVESVARAYA TECHNOLOGICAL UNIVERSITY
Belgavi-590014

Project Report
On
“DESIGN OF MEMORIES USING ADIABATIC LOGIC”
Submitted in partial fulfillment of the requirements for the VII Semester

Bachelor of Engineering
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

For the Academic year

2018-2019
BY
Brunda V 1PE15EC039
Jigyasa N. Maheshwari 1PE15EC060
Pavitra M 1PE15EC097
Nikhil H V 1PE15EC418

UNDER THE GUIDANCE OF

MR. VINAY REDDY N
ASSISTANT PROFESSOR
Department of ECE, PESIT, BSC.

Department of Electronics and Communication Engineering

PESIT, Bangalore South Campus
HOSUR ROAD BANGALORE- 560100
 PESIT, Bangalore South Campus
HOSUR ROAD
BANGALORE-560100

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

This is to certify that the project entitled

“DESIGN OF MEMORIES USING ADIABATIC LOGIC” is a bonafide work carried out
by Brunda V, Jigyasa N. Maheshwari, Pavitra M, Nikhil H V bearing USN 1PE15EC039,
1PE15EC060, 1PE15EC097, 1PE15EC418 in partial fulfillment for the award of Degree of
Bachelors (Bachelors of Engineering) in Electronics and communication Engineering of
Visvesvaraya Technological University, Belgavi during the year 2018-2019.

Signatures:

Project Guide Head of the Dept Principal

Mr. Vinay Reddy N Dr. Subhash Kulkarni Dr J Surya Prasad

Assistant Professor, ECE HOD, ECE Principal
PESIT, BSC PESIT, BSC PESIT, BSC

Examiners:
1.
2.
 ACKNOWLEDGEMENTS

The success of any venture depends substantially on the encouragement and the directions of
many others. We take this opportunity to express our gratitude to the people who have been
influential in the successful completion of this project.

We would like to express deepest appreciation towards Dr. J Surya Prasad, Principal,
PESIT-BSC for providing us with excellent facilities.

We would like to thank our Head of Department, ECE, Dr. Subhash Kulkarni for all the help
and kindness.

We would also like to show our greatest appreciation to Mr. Vinay Reddy N for his expert
guidance and continuous encouragement throughout to see that this project rights its target
since its commencement to its completion.

Finally, we like to thank Mrs. B Hema and Dr. Shashidhar Tantry, Project Coordinators and
the entire faculty whose invaluable guidance supported us in completing this project.

To all of you, we extend our deep appreciation.

Brunda V (1PE15EC039)
Jigyasa N. Maheshwari (1PE15EC060)
Pavitra M (1PE15EC097)
Nikhil H V (1PE15EC418)
 ABSTRACT

Today in all high-performance and computational systems, energy efficiency has become a
major concern in design. Excessive power dissipation requires expensive machines like heat
sinks, heat pipes, fans etc. Battery life is becoming a product differentiator in many portable
devices.

Several effective power management design techniques have been developed over the past
few years, including lowering the supply voltage. As process scaling continues below 90nm,
however, it becomes more difficult to scale the supply voltage for several reasons. As a
result, there is a demand on novel circuits whose power saving mechanism is not heavily
dependent supply voltage scaling.

Adiabatic logic is a new approach to the VLSI circuit design to achieve low power. Adiabatic
logic circuits are low power circuits. They restrict the current to flow across the device with
low voltage drop. The success of adiabatic logic depends on efficient implementation of
memories as well as any random logic.
CONTENTS

1 Introduction
1.1 Adiabatic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Comparison between various adiabatic logic families . . . . . . . . . . 1

2 Literature survey
2.1 comparison between various adiabatic logic families . . . . . . . . . . . . 3

3 memories
3.1 memory cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Types of memory
3.2.1 volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.2 non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 SRAM
4.1 6T SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Adiabatic SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 CAM
5.1 Overview of CAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Types of architecture of CAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 Power consumption in CMOS and Adiabatic circuits

6.1 Static CMOS circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2 conventional charging and discharging . . . . . . . . . . . . . . . . . . . . . . 12
6.3 Adiabatic charging and discharging . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4 Adiabatic logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5 Stepwise charging circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Sense amplifier
7.1 overview of sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2 Differential voltage mode sense amplifier . . . . . . . . . . . . . . . . . . . . . 18
7.2.1 Working . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

8 Software requirement specifications

8.1 Cadence Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9 Project planning 21
10 Simulation results
10.1 Conventional AND/NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.2 Adiabatic AND/NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.3 Conventional SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.4 Adiabatic SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.5 Sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.6 conventional SRAM with sense amplifier . . . . . . . . . . . . . . . . . . . 27
10.7 Adiabatic SRAM with sense amplifier . . . . . . . . . . . . . . . . . . . . . . .28
10.8 Power analysis results . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . 29

11 Conclusion and future scope

11.1 conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.2 Future scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

12 References 31
1
1
1
1
 CHAPTER 1

INTRODUCTION

1.1 ADIABATIC LOGIC

Adiabatic logic is used to describe logic families that could theoretically operate
without losses. Adiabatic logic is a new approach to the VLSI circuit design to achieve low
power.

The dynamic energy dissipation in a circuit is due to charging and discharging for its
node capacitance. The charging and discharging paths are different, causing energy to be
dissipated in the form of heat. An adiabatic switching technique reduces the dynamic energy
dissipation by recycling the charge stored in the node capacitance in circuits. This recycling
is achieved by using an AC power source instead of the traditional DC power source. The
energy dissipation is reduced by maintaining a very low potential difference across the two
terminals of turn-on MOS transistors.

1.2 ADIABATIC LOGIC FAMILIES

Adiabatic logic circuits classified into two types:

(a) Quasi/ Partial Adiabatic Logic Circuits
(b) Full Adiabatic Logic Circuits

(a) Quasi/Partial Adiabatic Logic Circuits

Quasi-adiabatic circuits have simple architecture and power clock system. The adiabatic
loss occurs when current flows through non-ideal switch, which is proportional to the
frequency of the power-clock.
Popular Partially Adiabatic families include the following:
i. Efficient Charge Recovery Logic (ECRL).
ii. 2N-2N2P Adiabatic Logic.
iii. Positive Feedback Adiabatic Logic (PFAL).
iv. NMOS Energy Recovery Logic (NERL).

1
 v. Clocked Adiabatic Logic (CAL).
vi. True Single-Phase Adiabatic Logic (TSEL).
vii. Source-coupled Adiabatic Logic (SCAL).

(b) Full Adiabatic Logic Circuits:

Full-adiabatic circuits have no non-adiabatic loss, but they are much more complex than
quasi-adiabatic circuits. All the charge on the load capacitance is recovered by the power
supply. Fully adiabatic circuits face a lot of problems with respect to the operating speed
and the inputs power clock synchronization.

Some Fully adiabatic logic families include:

i. Pass Transistor Adiabatic Logic (PAL).
ii. Split- Rail Charge Recovery Logic (SCRL).

2
 Chapter 2 : Literature Survey
Comparison between Various Adiabatic logics
Name Application Advantage Disadvantage
(Operating
Frequency )

 Ultra Low Power  Increased  Coupling

ECRL benefits of Effects
(10KHz) scaling
 Lowest Energy
Consumption
 4 bit Shifter  Dual rail  High
PFAL circuit with production
(>10KHz) Partial Energy cost
 Poor
production
planning
 Applications that don't  Area overhead  Coupling
require high and energy Effects
NERL performance but low consumption is
energy consumption smaller
TSEL  4 bit NAND Decoder  Low energy  Power
(10MHz- Dissipation supplied is by
200MHz) Energy Gate- single
Recovery phase
Logic sinusoidal
power- clock
SCAL  Time Varying Power  Broad range of  Coupling
(50 to 500 MHz) sources Frequency Effects
Operation.
 Increased
Energy
Efficiency
PAL  Computer  Two phase  High supply
(10MHz) Applications power clock voltage and
for its lower speed
operation. of operation.
SCRL  Carry Look Ahead  Clocks needed  Coupling
(2.4 GHz) Adders to sustain a effects
reversible. Can't be
directly
interfaced
Dual  Memories  Suitable for  Increased
Transmission driving large area
Gate capacitance
(25 – 200 MHz)

3
 CHAPTER 3
Memories

3.1 Memory Cell

The memory cell is the fundamental building block of computer memory. The memory cell is
an electronic circuit that stores one bit of binary information and it must be set to store a logic
1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained /
stored until it is changed by the set/reset process. The value in the memory cell can be
accessed by reading it.
A memory chip can be thought of as a matrix of locations that are each able to store one
binary bit – either a 1 or a 0. Each location that is able to store a bit is known as a cell. To
simplify the design and to save space, the memory matrix usually has a set width of bits that
is usually one or more bytes long. This group has one complete unit of information and is
known as the memories word length. The entire word of memory is stored at a specific
location known as its address, and all actions performed on the memory such as reading and
writing values will be done to the entire word at a specific address at the same time. The size
of a memory describes how many different locations are available to store bits of
information.

3.2 Types of Memories

Memories are classified as volatile and Non-volatile memories.
3.2.1 Volatile memories
Volatile memory, is computer memory that requires power to maintain the stored
information; it retains its contents while powered on but when the power is
interrupted, the stored data is quickly lost.
Major types are:
a) DRAM (Dynamic random-access memory): which uses memory cells consisting of
one capacitor and one transistor to store each bit. This is the cheapest and highest in
density, so it is used for the main memory in computers. However the electric charge
that stores the data in the memory cells slowly leaks out, so the memory cells must
be periodically refreshed (rewritten) which requires additional circuitry. The refresh
process is handled internally by the computer and is transparent to its user.
b) SRAM (Static random-access memory): which relies on several transistors forming
a digital flip-flop to store each bit. This is less dense and more expensive per bit than

4
 DRAM, but faster and does not require memory refresh. It is used for smaller cache
memories in computers.
c) Content-addressable memory: This is a specialized type in which, instead of
accessing data using an address, a data word is applied and the memory returns the
location if the word is stored in the memory. It is mostly incorporated in other chips
such as microprocessors where it is used for cache memory.

3.2.2 Non volatile memories

Non-volatile memory preserves the data stored in it during periods when the power to the chip is
turned off. Therefore, it is used for the memory in portable devices, which don't have disks, and
for removable memory cards among other uses. Major types are:
a) ROM (Read-only memory): This is designed to hold permanent data, and in normal operation
is only read from, not written to. Although many types can be written to, the writing process is
slow and usually all the data in the chip must be rewritten at once. It is usually used to
store system software which must be immediately accessible to the computer, such as
the BIOS program which starts the computer, and the software (microcode) for portable
devices and embedded computers such as microcontrollers.

b) NVRAM (Flash memory): In this type the writing process is intermediate in speed between
EEPROMS and RAM memory; it can be written to, but not fast enough to serve as main
memory. It is often used as a semiconductor version of a hard disk, to store files. It is used in
portable devices such as PDAs, USB flash drives, and removable memory cards used
in digital cameras and cellphones.

5
 CHAPTER 4
SRAM

4.1 6T SRAM

Figure 1 : 6T SRAM

The most commonly used SRAM cell is the full CMOS 6-transistor memory cell. The SRAM
cell consists of two inverters and two access MOSFETs which are connected to a pair of bit
lines. The gates of two access MOSFETs are also connected to a word line (WL). To form a
cross coupled inverter, the output of one inverter is connected to the input of the other and its
output is connected to the input of the previous inverter.
The access transistors enable access to the cell during read and write operations.

OPERATION OF SRAM

Read operation: In SRAM, for any operation to be performed, the word line should be high.
To perform read operation, initially memory should have some value. Let Q = 1 and ~Q = 0.
Raise the word line to high, to perform the read operation, these bit lines are initially pre-
charged to Vdd. As Q and BL are high, there will be no discharge in the circuit. But there will
be potential difference between ~Q and ~BL and this leads to discharge and current flows.

6
Write operation: If the memory bits consist of Q=0 and ~Q=1.
Initially word line is high and hence write operation can be performed. In write operation BL
and ~BL are input lines. As there is control on the input bit lines, initially making ~BL as low
would create the potential difference between the ~Q and ~BL.
If BL is made high the output Q obtained is high. Hence write operation is accomplished
successfully into the memory.

4.2 Adiabatic SRAM

Figure 2: Adiabatic SRAM and the clock’s used

7
The implemented Adiabatic SRAM cell has two access transistors and the latch similar to the
conventional 6T SRAM cell.
The latch part has been implemented using the SCRL technique. MP1 and MN1 forms the
conventional NOT gate MP2 and MN2 forms the NOT gate.
T1 and T2 are the transmission gates.

Clock 1 and Clock 3 has half rail swing that is either from Vdd/2 to 0 or from Vdd/2 to Vdd.
Clock2 and Clock4 swings from 0 to Vdd or from Vdd to 0. Let us assume that all the internal
nodes are at Vdd/2.

Consider the clock diagram as shown above for the implemented SRAM cell.
Let us assume that the initial value stored in the SRAM cell is ‘0’.
Now WL = 1, and the logic 1 will be written through the bit-line.

At t1, the potential of node D slowly increased from 0 to Vdd which makes the transistor
MN1 to be in ON state. The node n1 will be at Vdd/2. The transistor MN1 is turned ON
without any non-adiabatic loss since there is no potential difference between source and drain
of MN1.
The node n1 will be Vdd/2. ~D slowly decreases from Vdd to 0. The node n2 is maintained at
Vdd/2.

At t2, D is at Vdd and clock1 is slowly increasing from Vdd/2 to Vdd. Since the transistor MN1
is in ON state, the node n1 will follows the ~clock1.

At t3, Clock2 slowly increases from 0 to Vdd by making the transmission gate T1 be ON and
connecting the nodes n1 and ~D. Now the transistor MP2 will be switched ON adiabatically
and the node n2 will follow the Clock3.
Clock3 slowly increases from Vdd/2 to Vdd.

At t4, Clock4 rises from 0 to Vdd there by turning ON transmission gates and
connecting node n2 and D.

At t5, Clock2 is switched off adiabatically since the potentials of node n2 and ~D are same.

8
At t6, Clock1 is reduced slowly from Vdd to Vdd/2 which makes node n1 to rise from 0 to
Vdd/2.

At t7, the transmission gate T2 is switched OFF adiabatically by reducing the Clock4 from
Vdd to zero.

At t8, Clock3 is reduced from Vdd to Vdd/2 there by making nodes n2 to be Vdd/2. The values
of D and ~D stored in the cell will be used for the next stage of the cycle.

9
 CHAPTER 5
CAM(Content-Addressable Memory)

5.1 Overview of CAM

CMOS devices have been scaled down in order to achieve higher speed. Leakage current
reduction is the major concern in CMOS technology. Power consumption and the speed are
the major factors of concern for designing a chip along with the leakage power. The
consumption of power and speed of SRAMs are some important issues among a number of
factors that provides a solution with multiple designs that minimize the consumption of
power. The main CAM-design challenge is to reduce power consumption associated with the
large amount of parallel active circuitry, without sacrificing speed or memory density. At the
circuit level, the low power match line sensing techniques and search line driving approaches
are major concerns.

5.2 Types of architectures of CAM Cells

NAND CAM: The CAM cell consists of the memory cell of either 6T SRAM or the single bit
line SRAM. The comparison circuit used is the 3 transistor circuit to compare the data stored
in the memory and the search data. It consumes least power but is slow.

NOR CAM: The CAM cell consists of the memory cell of either 6T SRAM or the single bit
line SRAM. The comparison circuit used is the 4 transistor circuit to compare the data stored
in the memory and the search data. It is fast but consumes more power.

10
 CHAPTER 6
Power consumption in CMOS and Adiabatic circuits

6.1 STATIC CMOS CIRCUITS

Figure 3: Basic structure of CMOS circuits

Power dissipation in conventional CMOS circuits primarily occurs during device switching.
As shown in Fig. 4, both PMOS and NMOS transistors can be modeled by including an ideal
switch in series with a resistor in order to represent the effective channel resistance of the
switch and the interconnect resistance.
The pull-up and pull-down networks are connected to the node capacitance C L, which is also
referred to as the load capacitance.
When the logic level in the system is “1” there is a sudden flow of current through R.Q. =
CLVdd is the charge supplied by the positive power supply rail for charging C L to Vdd. Hence,
the energy drawn from the power supply is Q .Vdd = CLVdd2. If it is assumed that the
energy drawn from the power supply is equal to that supplied to CL, the energy stored in CL
becomes one-half the supplied energy, i.e.
Estored = 0.5 CLVdd2
The remaining energy is dissipated in R. The same amount of energy is dissipated during
discharging in the NMOS pull-down network when the logic level in the system is “0.”
Therefore, the total amount of energy dissipated as heat during charging and discharging is

11
Etotal = Echarge+ Edischarge
= 0.5 CLVdd2+ 0.5 CLVdd2
= CLVdd2

Figure 4: Equivalent representation of CMOS circuits

From the above equation, it is apparent that the energy consumption in a conventional CMOS
circuit can be reduced by reducing Vdd. By decreasing the switching activity in the circuit, the
power consumption (P = dE/dt) can also be proportionally suppressed.

6.2 CONVENTIONAL CHARGING AND DISCHARGING

Figure 5: Conventional charging and discharging curve

12
 Consider the capacitor C. This capacitor has to be charged. The simplest circuit by
which it can be done is through a power supply Vdd, a switch and a resistor as shown in figure
3. As switch closes at t = 0, as the initial charge on the capacitor is zero, the complete Vdd
drops across resistor R. The capacitor starts to charge slowly when t >0 and the voltage
across R starts reducing.
Hence the current that was maximum initially i.e I=Vdd/R starts to reduce as shown in the
figure 3. This current will keep on decreasing with time and asymptotically it will approach
zero and the corresponding equation of current is
Vdd −t
I= exp (RC)
R

On applying KVL,
Vdd = IR + Q/C
Where,
Q = C . Vc
−t
VC = Vdd (1- exp (RC))

Vc is the voltage across the capacitor C.

6.3 ADIABATIC CHARGING AND DISCHARGING

Figure 6: General structure of adiabatic circuits

Consider the circuit as shown in figure 4.A time varying current I(t) is applied across
RC circuit through a switch. Hence the voltage across C is also time-dependent given by the
equation (assuming Vc=0 at t=0)
1
Vc = 𝑐 . 𝐼(𝑡). 𝑡

Hence the average current from 0 to t is:

𝑉𝑐(𝑡)
I(t) = 𝐶. 𝑡

13
The energy dissipation in R from 0 to t=T is given by:
𝑅𝐶
Ediss = RT∫0 I2 dt = RI2(T)T = . 𝐶 Vc2(T)
𝑇

The following observations can be done from the energy dissipation equation:
 For T>RC, the dissipated energy is smaller than the conventional case.
 The dissipation can be made arbitrarily small by further extending the charging time
T.
 The dissipated energy is proportional to R. A smaller R results in a lower dissipation
unlike conventional case.

6.4 ADIABATIC LOGIC GATES

Adiabatic logic gates are realized by replacing each of the PMOS and NMOS devices in the
pull-up and pull-down networks with transmission gates. An extended pull-up network is
used to drive the true output and an extended pull-down network is used to drive the
complimentary output. Both the networks in the transformed circuit are used to charge and
discharge the load capacitance. The DC voltage supply Vdd is replaced by a pulsed power
supply with varying voltage to allow the adiabatic operation. .

Figure 7: General structure of CMOS and Adiabatic logic gates

14
Adiabatic NAND/AND gate

Figure 8: Adiabatic AND/NAND gate

Working
AND gate: The output f goes high only when both x and y are high. The path from Va to f
closes and f follows Va.
NAND gate: The output f goes high even if one of the inputs x or y go high and hence the
path from Va to ~f closes and ~f follows Va.

6.5 Stepwise charging circuits

Figure 9(a) Figure 9(b)

Case (1): In figure(a) when a capacitor is charged to Vdd through a resistor R the Energy
dissipated is 0.5 CLVdd2

15
Case (2): In figure b, the capacitor is charged initially to Vdd/2 by closing the switch S1 .The
energy dissipated is

1 1
Ediss=2.CL.(Vdd/2)2=8.CL.Vdd2

and later the switch S1 is opened and S2 is closed to charge the capacitor from Vdd/2 to Vdd.
The energy dissipated is

1 1
Ediss = .CL.(Vdd/2)2 = .CL.Vdd2
2 8

Hence the total energy dissipated is

1 1 1
Ediss = 8.CL.Vdd2 + 8.CL.Vdd2 = 4.CL.Vdd2

Figure 10: Circuit of charge using N steps

When N steps are taken to charge the capacitor C

Estepwise = N.Estep = N.(CL.Vdd2)/2N2
1
Estepwise = 2𝑁.CL.Vdd2

16
 CHAPTER 7
Sense Amplifier

7.1 Overview of sense amplifiers

A sense amplifier is part of the read circuitry in semiconductor memory chip that is used
when data is read from the memory; its role is to sense the low power signals from
a bitline that represents a data bit (1 or 0) stored in a memory cell, and amplify the small
voltage swing to recognizable logic levels so the data can be interpreted properly by logic
outside the memory.

Figure 11: Basic structure of Sense Amplifier

The sense amplifiers are classified as follows:
Circuit Types Operation Mode
Differential Voltage mode
Non-Differential Current mode

1) Voltage Mode sense amplifier

Differential sense amplifiers, also known as voltage mode sense amplifiers, are
connected directly to the bitlines. At the beginning of a read cycle, the bitlines are pre-
charged. As one bitline begins to discharge, the difference between the bitline voltages
determines the output logic value that is seen at the output. The performance of voltage mode
sense amplifiers depends on the bitline capacitances.

17
 2) Current Mode sense amplifier

Non-differential amplifiers are also known as current mode sense amplifiers. Current
mode sense amplifiers may also be used independently .The amplifier inputs are connected to
the bitlines, and after precharge, the discharging bitline causes a decrease in current flow
which is used to determine the output voltage level.

7.2 Differential Voltage Mode Sense Amplifier

Figure 12: Differential voltage sense amplifier

The differential sense amplifier is a dynamic voltage mode amplifier. The amplifier is
composed of a differential pair (Transistors N1 and N2) with an active current mirror load
(P1 and P2) and a biasing current source (N3). The bitlines are connected to the gates of the
differential pair transistors and the output is taken from the same side as BL.

18
 7.2.1 Working

A read cycle begins when the signal SE is brought high. This causes a constant
biasing current, ISS, to flow through the biasing current source (N3). If both input voltages
are exactly equal, this will cause a current equal to ISS/2 to flow through both halves of the
amplifier. To ensure that the current is divided equally, the PMOS devices P1 and P2 must be
sized identically. The NMOS devices N1 and N2 must also be sized identically.
When the amplifier is first enabled, the input voltages are approximately equal
because the bitlines are pre-charged. After the SRAM cells are enabled, one bitline will begin
to discharge. As the bitline discharges, the voltage supplied to the gate of the transistor on
that side of the amplifier will decrease, causing the drain current to decrease as the transistor
begins to turn off. Because the current source is supplying a total current to the amplifier
equal to ISS, the decrease in drain current on one side will cause the current in the opposite
side of the amplifier to increase. As the transistor continues to turn off, the output voltage will
rise to equal the supply voltage, VDD. A relatively small difference between the bitlines will
produce a large difference in output voltages

19
 CHAPTER 8
Software requirements specification

8.1 Cadence tool

Cadence software is used for the design projects in the graduate level courses Wireless IC
Design. It supports analog and digital designs at the device, cell, and block levels.
Standard device models are used in conjunction with Spectre and SpectreRF simulation in
Cadence to design circuits for Ultra Wide-Band applications.

Baseband and time domain simulations of analog-front end and back-end circuits are
performed.

The tool used is gpdk 180nm which is implemented in Cadence Virtuoso.

20
 Chapter 9 Project Planning
Aug Sep Oct Nov Dec Jan Feb Mar April
Sl.No Task (2018) (2018) (2018) (2018) (2018) (2019) (2019) (2019) (2019)
1 Literature Survey
Testing Adiabatic
2 circuits
Study of SRAM
and CAM Memory
3 cells
Simulation of
conventional and
4 Adiabatic SRAM
Study of Sense
amplifiers and
Simulation of
Differential
Voltage sense
5 amplifier
Optimization of
6 Adiabatic SRAM
Simulation of
Adiabatic
NAND/NOR CAM
7 Memory cell
Simulation of
Conventional
NAND/NOR CAM
8 Memory cell
Comparison of
Conventional and
9 adiabatic results
Documentation of
10 the project

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 CHAPTER 10
SIMULATION RESULTS
Using Cadence Virtuoso 180nm

10.1 Conventional AND/NAND Gate

Conventional AND/NAND Gate Transient Analysis

22
 10.2 Adiabatic AND/NAND gate

Adiabatic And/Nand Gate Transient Analysis

23
 10.3 Conventional SRAM

Transient Response for Conventional SRAM

24
 10.4 Adiabatic SRAM

Clock’s Used for Adiabatic SRAM

25
Transient Response for Adiabatic SRAM

10.5 Sense Amplifier

26
10.6 Conventional SRAM with Sense Amplifier

27
10.7 Adiabatic SRAM with sense amplifier

28
 10.8 Power analysis results

1) AND/NAND gate
Power dissipated

Conventional 28.6uW

Adiabatic 574.3nW

Efficiency 97.99%

2)SRAM memory cell

Power dissipated

Conventional 290.7uW

Adiabatic 171.4uW

Efficiency 41.03%

3)SRAM with Sense Amplifier

Power dissipated

Conventional 3.628mW

Adiabatic 247.3uW

Efficiency 93.18%

29
 Chapter 11
Conclusion and future scope

11.1 Conclusion
As the density and operating speed of CMOS chips increase, power dissipation has become a
critical concern in the design of VLSI circuits, especially in mobile and portable ASIC
systems.

In this work, we have reported the use of Adiabatic logic for low power VLSI circuit design.
Various families of the adiabatic logic are studied, their advantages , disadvantages and the
potential areas of application are discussed. The mathematical proof explaining the power
consumed in conventional CMOS circuits and adiabatic circuits is given. It is seen that
theoretically, adiabatic circuits should minimize total energy dissipation to realize power-
efficient design.

The adiabatic SRAM is constructed and its working is verified using Cadence Virtuoso Tool.
A conventional 6T SRAM is also constructed for the comparison of power results with the
adiabatic SRAM.

Power results of various circuits on comparison showed that power dissipated in adiabatic
circuits is the least.

11.2 Future scope

The adiabatic SRAM can be further optimized to give better output voltage levels. The static
noise margin (SNM) analysis of the same would give the best (W/L) ratio of the MOSFET’s
that should be used so that the designed SRAM is immune to noise. A CAM memory array
can be constructed with the storage element implemented using Adiabatic logic to obtain a
power efficient design.

30
 Chapter 12:References
1. “Charge-Recovery Computing on Silicon”, Suhwan Kim, Member, IEEE, Conrad H.
Ziesler, Member, IEEE, and Marios C. Papaefthymiou, Senior Member, IEEE,IEEE
TRANSACTIONS ON COMPUTERS, VOL. 54, NO. 6, JUNE 2005

2. “An Energy-Efficient Power-Gating Adiabatic Circuits Using Transmission Gate

Switches “ DongZhou, JianpingHu*, HuiyingDong ,1-4244-1132-7/07/$25.00 © 2007
IEEE

3. “A Novel Low Power 16X16 Content Addressable Memory using PAL “,G.Josemin
Bala,J.Raja Paul Perinbam , Proceedings of the 18th International Conference on
VLSI Design held jointly with 4th International Conference on Embedded Systems
Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE

4. Low Power VLSI Circuits by Professor Ajit Pal, IIT Khargpur,

https://youtu.be/8gYlVsz2JWk.

5. “A Novel Adiabatic SRAM Cell Implementation using Split Level Charge Recovery
Logic” S Dinesh Kumar M.Des Scholar, Dept. of EDM, IIITD&M Kancheepuram.

6. “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and

Survey” Kostas Pagiamtzis, Student Member, IEEE, and Ali Sheikholeslami, Senior
Member, IEEE, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 3,
MARCH 2006

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