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SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

Universidad
Mayor de San
Andrés D-6 Grupo

Facultad de Grupo
Ingeniería
Ingeniería
Electrónica
Sistemas
PRE- Digitales I INFORME

2
ETN-601

Tema:
Introducción a los circuitos digitales
Estudiante:
Tinco Pari Abraham

Fecha de Entrega:
18/04/2019

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

A) METODO MAPAS DE KARNAUGH:


i)
QUARTUS II:
--METODO MAPAS DE KARNAUGH
--INCISO a)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D: IN STD_LOGIC;
F1: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
F1<=(A AND(NOT B)AND D)OR((NOT A)AND C AND(NOT D))OR(A AND B AND(NOT C)AND D)OR((NOT
A)AND(NOT B)AND C AND(NOT D))OR((NOT A)AND B AND C AND D);
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
F1 : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal F1 : std_logic;
BEGIN

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

uut: ABRAHAM_TP PORT MAP (


A => A,
B => B,
C => C,
D => D,
F1 => F1
);
stim_proc: process
begin
WAIT FOR 200 NS; A <= NOT A; end process;
stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B; end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C; end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D; end process;
END;

PROTEUS:
A B C D
12

13

10
2

U11:A U10:D U10:C U10:B


7400 7400 7400 7400
3

11

U8:B
3
4 6
5

7410

U8:C
9
10 8
11 F1
1 U12:A
7410 2
6
U9:A 4
1 5
2 12 74LS22
13

7410

U9:C
9
10 8
11

7410

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

ii)
QUARTUS II:
--METODO MAPAS DE KARNAUGH
--INCISO b)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D: IN STD_LOGIC;
F2: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
SIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
SEL<=A&B&C&D;
WITH SEL SELECT
F2<= '1' WHEN "0000",'1' WHEN "0001",'1' WHEN "0011",'1' WHEN "0101",
'1' WHEN "0110",'1' WHEN "1000",'1' WHEN "1001",'1' WHEN "1100",
'1' WHEN "1101",'1' WHEN "1111",'0' WHEN OTHERS;
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
F2 : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

signal C : std_logic := '0';


signal D : std_logic := '0';
--Outputs
signal F2 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A,
B => B,
C => C,
D => D,
F2 => F2
);
stim_proc: process
begin
WAIT FOR 200 NS; A <= NOT A;end process;
stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D;end process;
END;

PROTEUS:

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

A1 B1 C1 D1

12

13

10
9

1
U14:D U14:C U14:B U14:A
7400 7400 7400 7400

11

3
U9:B
3
4 6
5

7410

U13:A
1
2 12
13 1 U16
2 F2
7410 3
4
U13:B 8
3 5
4 6 6
5 11
12
7410 74LS30

9 U12:B
10
8
12
13
74LS22

9 U15:B
10
8
12
13
74LS22

iii)
QUARTUS II:
--METODO MAPAS DE KARNAUGH
--INCISO c)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D,E: IN STD_LOGIC;
F3: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
SIGNAL SEL: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
SEL<=A&B&C&D&E;
WITH SEL SELECT
F3<='1' WHEN "00001",'1' WHEN "00010",'1' WHEN "00100",'1' WHEN "00111",
'1' WHEN "01000",'1' WHEN "01011",'1' WHEN "01100",'1' WHEN "01110",
'1' WHEN "01111",'1' WHEN "11011",'1' WHEN "11110",'1' WHEN "11111",
'0' WHEN OTHERS;
END GRUPO_D_6;

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
E: IN std_logic;
F3 : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
signal E : std_logic := '0';
--Outputs
signal F3 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A,
B => B,
C => C,
D => D,
E => E,
F3 => F3
);
stim_proc: process
begin
WAIT FOR 200 NS; A <= NOT A;end process;
stim_proc1: process
begin

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

WAIT FOR 100 NS; B <= NOT B; end process;


stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C; end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D; end process;
stim_proc4: process
begin
WAIT FOR 12.5 NS; E<= NOT E; end process;
END;

PROTEUS:

A2 B2 C2 D2 E2
12

13

10
2

U19:A U18:D U18:C U18:B U18:A


7400 7400 7400 7400 7400
3

11

U13:C
9
10 8
11

7410

1 U15:A U17:C U19:B


2 9 4
6 10 8 6
4 11 5
5
74LS22 7410 7400

1 U24:A
2
6
4
5
74LS22

1 U20:A
2
6
4
5
7420

9 U20:B U23:A U19:C U23:C


10 1 10 9 F3
8 2 12 8 10 8
12 13 9 11
13
7420 7410 7400 7410

1 U21
2
3
4
8
5
6
11
12
74LS30
1 U22
2
3
4
8
5
6
11
12
74LS30

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

B) OREX/NOREX:
QUARTUS II:
i)
--METODO OREX/NOREX:
--INCISO a)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D: IN STD_LOGIC;
X: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
SIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
SEL<=A&B&C&D;
WITH SEL SELECT
X<= '1' WHEN "0010",'1' WHEN "0100",'1' WHEN "0101",'1' WHEN "0110",
'1' WHEN "1000",'1' WHEN "1100",'1' WHEN "1101",'1' WHEN "1111",
'0' WHEN OTHERS;
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

D : IN std_logic;
X : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal X : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A,
B => B,
C => C,
D => D,
X => X);
stim_proc: process
begin
WAIT FOR 200 NS; A <= NOT A;end process;
stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D;end process;
END;

PROTEUS:

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

A B C D

13
1

5
U10:A U10:C U10:D
74LS04 74LS04 74LS04

12
U11:A
1
3
2
U12:A
74LS86 1
2 12
13 U15:A
1
74LS11 3
U13:A 2
1
U11:B 3 74LS32
4 2
6 X
5 74LS08
U11:C U15:C
74LS86 9 9
8 8
10 10

74LS86 74LS32
U12:B
3 U15:B
4 6 4
U11:D 5 6
12 5
11 74LS11
13 74LS32
U13:B
74LS86 4
6
5
U14:A
1 74LS08
3
2

74LS266

ii)
QUARTUS II:
--METODO OREX/NOREX:
--INCISO b)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D: IN STD_LOGIC;
Y: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
SIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
SEL<=A&B&C&D;
WITH SEL SELECT
Y<= '1' WHEN "0011",'1' WHEN "0101",'1' WHEN "0110",'1' WHEN "1001",
'1' WHEN "1010",'1' WHEN "1100",'0' WHEN OTHERS;
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal Y : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A,
B => B,
C => C,
D => D,
Y => Y);
stim_proc: process
begin
WAIT FOR 200 NS; A <= NOT A;end process;
stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D;end process;
END;

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

PROTEUS: A2 B2 C2 D2

U16:A
1
3
2
U13:C
74LS86 9
8
U16:B 10
4
6 74LS08 Y
5
U15:D
74LS86 12
11
U16:C 13
9
8 74LS32
10 U13:D
12
74LS86 11
U16:D 13
12
11 74LS08
13

74LS86

C) QUINE McCLUSKEY:
QUARTUS II:
--METODO QUINE McCLUSKEY:
--INCISO b)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D,E:IN STD_LOGIC;
F1,F2,F3: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
F1<=((NOT A)AND(NOT C)AND(NOT D))OR(B AND(NOT C)AND(NOT D))OR((NOT A)AND C AND
D)OR((NOT B)AND C AND D);
F2<=((NOT A)AND B AND C AND D AND E)OR((NOT A)AND(NOT B)AND(NOT C)AND(NOT D))
OR((NOT A)AND(NOT B)AND(NOT C)AND(NOT E))OR((NOT B)AND(NOT C)AND(NOT
D)AND(NOT E))
OR(A AND(NOT B)AND D AND E);
F3<=(A AND B AND C AND D)OR((NOT A)AND B AND(NOT D))OR((NOT A)AND(NOT C))OR((NOT
B)AND(NOT C));

END GRUPO_D_6;

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic; B : IN std_logic; C : IN std_logic; D : IN std_logic; E : IN std_logic;
F1 : OUT std_logic; F2 : OUT std_logic; F3 : OUT std_logic);
END COMPONENT;
--Inputs
signal A : std_logic := '0'; signal B : std_logic := '0'; signal C : std_logic := '0';
signal D : std_logic := '0'; signal E : std_logic := '0';
--Outputs
signal F1 : std_logic; signal F2 : std_logic; signal F3 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A, B => B, C => C, D => D, E => E,
F1 =>F1, F2 =>F2, F3 =>F3);
stim_proc: process
begin
WAIT FOR 200 NS; A <= NOT A;end process;
stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D;end process;
stim_proc4: process
begin
WAIT FOR 12.5 NS; E <= NOT E;end process;
END;
PROTEUS:

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

A3 B3 C3 D3 E3

11
3

3
U10:B U10:E U10:F U18:A U18:B
74LS04 74LS04 74LS04 74LS04 74LS04
U12:C
4

10

4
9
10 8
11 U19:A
1
74LS11 3
2
U17:A
1 74LS32
2 12 U19:C
13 9 F1.(PFC)
8
74LS11 10

U17:B 74LS32
3
4 6
5 U19:B
4
74LS11 6
U17:C 5
9
10 8 74LS32
11

74LS11 U23:A
1
3
2
1 U20:A U19:D
2 74LS08 12
6 11
4 13
5
74LS21 74LS32
9 U20:B
10
8
12
13 U24:C
74LS21 9 F2.(PFC)
1 U21:A 8
2 10
6
4 U24:A 74LS32
5 1
74LS21 3
9 U21:B 2 U24:B
10 4
8 74LS32 6
12 5
13
74LS21 74LS32
1 U22:A
2
6
4
5
74LS21

9 U22:B
10
8
12 U24:D
13 12
74LS21 11
13
U25:A
1 74LS32
2 12 U26:B
13 4 F3.(PFC)
6
74LS11 5
U23:B
4 74LS32
6
5 U26:A
1
74LS08 3
U23:C 2
9
8 74LS32
10

74LS08

D) VARIABLES BIFORME:
i)

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

QUARTUS II:
--METODO VARIABLES BIFORME:
--INCISO a)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D,E:IN STD_LOGIC;
F1: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
F1<=((NOT A)AND(NOT B)AND C AND D AND E)OR(A AND B AND C AND(NOT D)AND
E)OR((NOT B)AND C AND(NOT D)AND(NOT E))OR((NOT A)AND(NOT C)AND(NOT D)AND
E)OR(A AND(NOT C)AND(NOT D)AND(NOT E))OR((NOT B)AND(NOT D)AND(NOT E))OR
(A AND B AND C AND E)OR((NOT A)AND(NOT B)AND(NOT C)AND(NOT D));
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic;B : IN std_logic;C : IN std_logic; D : IN std_logic;E : IN std_logic;
F1 : OUT std_logic);
END COMPONENT;
--Inputs
signal A : std_logic := '0'; signal B : std_logic := '0'; signal C : std_logic := '0';
signal D : std_logic := '0';signal E : std_logic := '0';
--Outputs
signal F1 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A,B => B,C => C,D => D,E => E,F1 =>F1);
stim_proc: process
begin

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

WAIT FOR 200 NS; A <= NOT A;end process;


stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D;end process;
stim_proc4: process
begin
WAIT FOR 12.5 NS; E <= NOT E;end process;
END;

PROTEUS:
A3 B3 C3 D3 E3
11
3

U17:B U10:B U10:E U10:F U17:A


74LS04 74LS04 74LS04 74LS04 74LS04
U19:A
4

10

1
3
1 U18:A 2
2 U23:A
6 74LS08 1
4 3
5 2
74LS21 U19:B
4 74LS32
6
9 U18:B 5
10
8 74LS08 U24:B
12 4
13 6
74LS21 5

1 U20:A 74LS32
2
6
4
5 U23:B
74LS21 4
6 F
9 U20:B 5
10
8 74LS32 U24:C
12 9
13 8
74LS21 10

1 U21:A 74LS32
2
6
4
5 U23:C
74LS21 9
U12:C 8
9 10
10 8
11 74LS32 U24:A
1
74LS11 3
9 U21:B 2
10
8 74LS32
12 U23:D
13 12
74LS21 11
1 U22:A 13
2
6 74LS32
4
5
74LS21

ii)
QUARTUS II:
--METODO VARIABLES BIFORME:

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

--INCISO b)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(V,W,X,Y,Z:IN STD_LOGIC;
F2: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
F2<=(V AND(NOT W)AND X AND(NOT Y)AND Z)OR(V AND(NOT X)AND Y AND Z)OR((NOT
W)AND Y AND(NOT Z))
OR((NOT V)AND W AND(NOT X)AND Y);
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
V : IN std_logic; W : IN std_logic; X: IN std_logic;Y : IN std_logic; Z : IN std_logic;
F2 : OUT std_logic);
END COMPONENT;
--Inputs
signal V : std_logic := '0';
signal W : std_logic := '0';
signal X : std_logic := '0';
signal Y : std_logic := '0';
signal Z : std_logic := '0';
--Outputs
signal F2 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
V => V,W => W,X => X,Y => Y,Z => Z, F2 =>F2);
stim_proc: process
begin
WAIT FOR 200 NS; V<= NOT V;end process;

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

stim_proc1: process
begin
WAIT FOR 100 NS; W <= NOT W;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; X <= NOT X;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; Y <= NOT Y;end process;
stim_proc4: process
begin
WAIT FOR 12.5 NS; Z <= NOT Z;end process;
END;

PROTEUS:
V W X Y Z
13

11
1

U25:A U17:C U17:D U17:E U17:F


74LS04 74LS04 74LS04 74LS04 74LS04
U26:A
2

12

10

1
3
9 U22:B 2 U29:A
10 1 F2..
8 74LS08 3
12 2
13 U29:B
74LS21 74LS32 4
1 U27:A 6
2 5
6 U24:D
4 12 74LS32
5 11
74LS21 13

U28:A 74LS32
1
2 12
13

74LS11
9 U27:B
10
8
12
13
74LS21

E) APLICACION DE MAPAS DE KARNAUGH:


SOLO PARA LA PFC
QUARTUS II:
--APLICACION DE MAPAS DE KARNAUGH:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D:IN STD_LOGIC;
L1,L2: OUT STD_LOGIC);

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
L1<=(A XOR C)OR((NOT A)AND(B XOR D))OR(A AND B)OR(C AND D);
L2<=(C XOR D)XOR(A XOR B);
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic; B : IN std_logic; C: IN std_logic;D :IN std_logic;
L1: OUT std_logic;L2 : OUT std_logic);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal L1 : std_logic;
signal L2 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A,B=> B,C => C,D => D,L1 =>L1,L2 =>L2);
stim_proc: process
begin
WAIT FOR 200 NS; A<= NOT A;end process;
stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
stim_proc3: process
begin

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

WAIT FOR 25 NS; D <= NOT D;end process;


END;

PROTEUS:
A4 B4 C4 D4
5

U18:C
74LS04
U27:A
6

1
3
2 U26:D
12
74LS86 11
U23:D 13
12
11 74LS32 L1
U27:B 13 U29:A
4 1
6 74LS08 3
5 2

74LS86 74LS32
L2

U28:A
1
3 L3
2 U26:C
9
74LS08 8
10
U28:B
4 74LS32
6
5

74LS08

U27:C
9
8
10 U30:A
1
74LS86 3
U27:D 2
12
11 74LS86
13

74LS86

F) APLICACION OREX/NOREX:
QUARTUS II:
--APLICACION OREX/NOREX:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C,D:IN STD_LOGIC;
F2,F3,F5,F6,F7,F8: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
F2<=((A AND(NOT B))AND((C XOR D)OR(C XNOR D)))OR((A AND(NOT C))AND(B XOR D));
F3<=((((NOT A) AND B))AND((C XOR D)OR(C XNOR D)))OR(((NOT A) AND C)AND(B XOR D));
F5<=(A XOR B)AND((C AND D)OR(B AND(NOT D)));

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

F6<=(((NOT C) AND D)AND(A XOR B))OR((A AND(NOT B))AND(A XOR B))OR(NOT(A OR(NOT
B)OR C OR D));
F7<=((A XOR B)AND(B XOR C))OR(NOT((NOT A)OR B OR C OR D))OR(NOT(A OR(NOT
B)OR(NOT C)OR(NOT D)));
F8<=(A XOR B)OR((A XOR C)AND(B XOR D));
END GRUPO_D_6;
EL CODIGO ES EXESO_3

NOT: F1=0,F3=F4

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic; B : IN std_logic; C: IN std_logic;D :IN std_logic;
F2: OUT std_logic;F3 : OUT std_logic;F5 : OUT std_logic; F6 : OUT std_logic ;
F7 : OUT std_logic;F8 : OUT std_logic);
END COMPONENT;
--Inputs
signal A : std_logic := '0'; signal B : std_logic := '0'; signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal F2 : std_logic; signal F3 : std_logic; signal F5 : std_logic; signal F6: std_logic;
signal F7 : std_logic;
signal F8 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A => A,B=> B,C => C,D => D,F2 =>F2,F3 =>F3,F5 =>F5,F6 =>F6,F7 =>F7,F8 =>F8);
stim_proc: process

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

begin
WAIT FOR 200 NS; A<= NOT A;end process;
stim_proc1: process
begin
WAIT FOR 100 NS; B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; D <= NOT D;end process;
END;

PROTEUS:

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

C5NOT

D5NOT
A5NOT

11B5NOT
A5 B5 C5 D5

C5

D5
A5

B5
13

1
U18:D U18:E U18:F U31:A
74LS04 74LS04 74LS04 U36:A
74LS04
A5 1
12

10

2
3
2
U25:B
A5NOT U35:B 3
4 6
74LS86U30:B 4 5
B5
4 6 F-2
U36:B 65 74LS11 U29:C
B5NOT
5 U29:B 9
4 4 8
C5
74LS86 6 74LS08 6 10
C5NOT 5 U14:B 5 U39:B F-7
5 74LS32
4
4 74LS32
D5 74LS86 6
6
5
D5NOT
74LS266 U25:C
1 U37:A 9
10 8
74LS32
2 11
3 U30:C 5
12 9 U39:A
74LS11
8
13 10
1
74S260 3 U33:A
74LS86 2 1
4 U37:B 2 12
13
8 U14:C 74LS32
9 8 6 74LS11 F-3=F-4
10 10 U29:D U34:A
11 9 12 1
11 3
74S260
74LS266 13 2
U30:D
U36:C
12 74LS32 74LS32
11
9
13
8
10 74LS86 U33:B
3 U39:C F-8
4 6
74LS86 9
5
8
U36:D
U32:A 74LS11 10
12 1

2
3
11 U35:C 74LS32
13 9
U32:B
74LS86 8
4
74LS86 10
U40:A
5
6
U35:A
F-5

1 74LS08 1
74LS86 3 3
2 2
U28:C
9 74LS08
74LS86 8 U34:B
10 4
6
U28:D
74LS08 5
12
11 74LS32
13

74LS08
U38:A
1
2 12
13
U32:C U34:C
9 74LS11 9 F6
8 8
10 10 U34:D
12
74LS86 U33:C 74LS32 11
9 13
10 8
11 74LS32
U32:D
12 74LS11
11
13

74LS86

4 U8:B
8
9 6
10
11
74S260

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

G) APLICACIÓN QUINE McCLUSKEY:


QUARTUS II:
--APLICACION OREX/NOREX:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(E1,E2,E3,E4:IN STD_LOGIC;
S0,S1,S2: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
S0<=((NOT E1)AND(NOT E3))OR((NOT E1)AND E2);
S1<=((NOT E1)AND(NOT E4))OR((NOT E1)AND E3)OR((NOT E1)AND E2);
S2<=((NOT E2)AND(NOT E3)AND(NOT E4))OR(E1 AND(NOT E2))OR(E1 AND(NOT E3))OR(E1
AND(NOT E4));
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
E1 : IN std_logic; E2 : IN std_logic; E3: IN std_logic;E4 :IN std_logic;
S0: OUT std_logic;S1 : OUT std_logic;S2 : OUT std_logic);
END COMPONENT;
--Inputs
signal E1 : std_logic := '0';signal E2 : std_logic := '0';signal E3 : std_logic := '0';
signal E4 : std_logic := '0';
--Outputs
signal S0 : std_logic;
signal S1 : std_logic;signal S2 : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
E1=> E1,E2=> E2,E3 => E3,E4 => E4,S0 =>S0,S1 =>S1,S2 =>S2);

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

stim_proc: process
begin
WAIT FOR 200 NS; E1<= NOT E1;end process;
stim_proc1: process
begin
WAIT FOR 100 NS; E2 <= NOT E2;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; E3 <= NOT E3;end process;
stim_proc3: process
begin
WAIT FOR 25 NS; E4 <= NOT E4;end process;
END;

PROTEUS:
E1 E2 E3 E4
11
3

U10:B U10:E U10:F U18:A


74LS04 74LS04 74LS04 74LS04
4

10

U17:A
1
3
2 U19:A
1 S0
74LS08 3
2
U17:B
4 74LS32
6
5

74LS08

U17:C
9
8
10 U19:B
4
74LS08 6
U17:D 5
12 U19:C
11 74LS32 9 S1
13 8
10
74LS08
U20:A 74LS32
1
3
2

74LS08

U12:C
9
10 8
11 U19:D
12
74LS11 11
U20:B 13
4
6 74LS32
5 U21:B
4 S2
74LS08 6
U20:C 5
9
8 74LS32
10 U21:A
1
74LS08 3
2
U20:D
12 74LS32
11
13

74LS08

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

H) APLICACION VARIABLES BIFORME:


QUARTUS II:
--APLICACION VARIABLES BIFORME:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(S1,S2,S3:IN STD_LOGIC;
X,Y,Z: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
X<=(S1 AND(NOT S2))AND(NOT S3);
Y<=(S2 AND S3) OR(NOT S3);
Z<=S2 AND S3;
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
S1 : IN std_logic; S2 : IN std_logic; S3: IN std_logic;
X: OUT std_logic;Y : OUT std_logic;Z : OUT std_logic);
END COMPONENT;
--Inputs
signal S1 : std_logic := '0'; signal S2 : std_logic := '0'; signal S3 : std_logic := '0';
--Outputs
signal X : std_logic;signal Y : std_logic;signal Z : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
S1=> S1,S2=> S2,S3 => S3,X => X,Y =>Y,Z =>Z);
stim_proc: process
begin
WAIT FOR 200 NS; S1<= NOT S1;end process;
stim_proc1: process

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

begin
WAIT FOR 100 NS; S2 <= NOT S2;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; S3 <= NOT S3;end process;
END;

PROTEUS:
S1. S2. S3.
13

11
3

U18:B U18:D U18:E


74LS04 74LS04 74LS04
4

12

10

U22:A
1 X.
2 12
13

74LS11
U21:C
9 Y.
8
U23:A 10
1
3 74LS32
2

74LS08

U23:B
4 Z.
6
5

74LS08

I) APORTE DE ALUMNO:
APLICACIÓN MAPAS DE KARNAUGH
QUARTUS II:
--APORTE DE ALUMNO:
--APLICACION DEAGRAMAS DE KARNAUGH:
LIBRARY IEEE;

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ABRAHAM_TP IS
PORT(A,B,C:IN STD_LOGIC;
R: OUT STD_LOGIC);
END ABRAHAM_TP;
ARCHITECTURE GRUPO_D_6 OF ABRAHAM_TP IS
BEGIN
R<=((NOT A)AND(NOT B)AND C)OR((NOT A)AND B AND C)OR(A AND(NOT B)AND(NOT C))OR(A
AND(NOT B)AND C);
END GRUPO_D_6;

XILINX-(VHDL TEST BENCH)


ENTITY ATP IS
END ATP;
ARCHITECTURE behavior OF ATP IS
COMPONENT ABRAHAM_TP
PORT(
A : IN std_logic; B : IN std_logic; C: IN std_logic;
R: OUT std_logic);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
--Outputs
signal R : std_logic;
BEGIN
uut: ABRAHAM_TP PORT MAP (
A=> A,B=> B,C => C,R => R);
stim_proc: process
begin
WAIT FOR 200 NS; A<= NOT A;end process;
stim_proc1: process
begin
WAIT FOR 100 NS;B <= NOT B;end process;
stim_proc2: process
begin
WAIT FOR 50 NS; C <= NOT C;end process;
END;

TINCO PARI ABRAHAM ETN-601


SIMPLIFICACION DE FUNCIONES LOGICAS LABORATORIO #1

PROTEUS:

A.- 9 B.- C.-

1
U18:F U24:A
74LS04 74LS04
8

U23:C
9 R
8
10 U21:D
12
74LS08 11
U25:A 13
1
3 74LS32
2

74LS08

TINCO PARI ABRAHAM ETN-601