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  • Assignment 10

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    archana pandey
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    This document contains a summary of Gadiparthi Pavanisri's career objective, skills, projects, training, and education. Pavanisri is looking for a position in RTL design and verification where she can utilize her skills in Verilog, SystemVerilog, UVM methodology, and tools like Xilinx ISE and Aldec Riviera. Her projects include designing and verifying a 1x3 router and developing a UVM-based verification environment for an SPI master core. She has a B.Tech in electronics from Chalapathi Institute of Engineering and Technology and professional training in VLSI design and verification from Maven Silicon.

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    This document contains a summary of Gadiparthi Pavanisri's career objective, skills, projects, training, and education. Pavanisri is looking for a position in RTL design and verification where she can utilize her skills in Verilog, SystemVerilog, UVM methodology, and tools like Xilinx ISE and Aldec Riviera. Her projects include designing and verifying a 1x3 router and developing a UVM-based verification environment for an SPI master core. She has a B.Tech in electronics from Chalapathi Institute of Engineering and Technology and professional training in VLSI design and verification from Maven Silicon.

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    172 Ansichten2 Seiten

    Assignment 10

    Hochgeladen von

    archana pandey
    This document contains a summary of Gadiparthi Pavanisri's career objective, skills, projects, training, and education. Pavanisri is looking for a position in RTL design and verification where she can utilize her skills in Verilog, SystemVerilog, UVM methodology, and tools like Xilinx ISE and Aldec Riviera. Her projects include designing and verifying a 1x3 router and developing a UVM-based verification environment for an SPI master core. She has a B.Tech in electronics from Chalapathi Institute of Engineering and Technology and professional training in VLSI design and verification from Maven Silicon.

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    GADIPARTHI PAVANISRI

    EMAIL: GADIPARTHIPAVANISRI@GMAIL.COM PH: 8790443611.

    CAREER OBJECTIVE:
    Looking for the position of an innovative and competitive work environment in RTL
    Design and Verification, where I can utilize my skills in contributing to development of the organization
    and explore myself.

    TOOLS AND LANGUAGE KNOWLEDGE:


    ➢ HDL: Verilog.

    ➢ HVL: SystemVerilog.

    ➢ Verification methodology: UVM .

    ➢ Tools known: Xilinx-ISE 14.4, Aldec Riviera-Pro 2015.06, Questa Sim 10.0b.

    PROJECTS DETAILS:
    ➢ Router 1x3 Design and Verification

    HDL : Verilog
    HVL : System Verilog
    TB Methodology : UVM
    EDA Tools : Questasim and Rivera Pro
    Description : The router accepts data packets on a single 8-bit port and routes.

    Responsibilities :
    ➢ Architected the design.
    ➢ Implemented RTL using Verilog HDL.
    ➢ Architected the class based verification environment using system Verilog
    ➢ Verified the RTL model using SystemVerilog.
    ➢ Generated functional and code coverage for the RTL verification sign-off
    ➢ Synthesized the design.

    ➢ SPI Master Core –Verification


    HVL : System Verilog
    TB Methodology : UVM
    EDA Tools : Questasim and Rivera Pro
    Description : The Serial Peripheral Interface bus (SPI) is a synchronous
    serial communication interface specification used for short distance
    communication, primarily in embedded systems.SPI devices communicate in full
    duplex mode using a master-slave architecture with a single master.

    Responsibilities :
    ➢ Architected the class based verification environment in UVM
    ➢ Configuring the registers in the driver module
    ➢ Full duplex synchronous serial data transfer
    ➢ Fully static synchronous design with one clock domain
    ➢ Fully synthesizable
    ➢ B.Tech Projects:
    ➢“ Student Automation Using Rfid”
    Tools Used: Arduino RS232

    Description:

    The main objective of this project is to record the attendance of students using RFID tags.
    student is provided with his/her authorized tag to swipe over the reader to record their attendance.

    PROFESSIONAL TRAINING:
    Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon
    Softech Pvt Ltd. Bangalore (June 2017 – present).

    Apprentice Training Certificate: certificate from Existence Labs Limited; It is an export


    oriented company into the manufacturing of temperature sensing devices.

    ACADEMIC CHRONICLE:

    YEAR OF PERCENTAGE
    COURSE INSTITUTE BOARD/INSTITUTE
    PASSING %
    Chalapathi institute
    B.Tech Of engineering and ANU 2017 74.5
    Technology
    Sri Chaitanya
    PUC State Board Of Inter 2013 82.4
    Jr College
    Sun Shine High
    SSC State Board Of A.P 2011 79.9
    School

    Personal Profile:

    FATHER NAME : G.SrinivasaRao

    DATE OF BIRTH : 07-06-1995

    MARITAL STATUS : Single.

    LANGUAGES KNOWN : Telugu, English, and Hindi.

    PERMENENT ADDRESS : H.no: 2-147 Lingumguntla, Pedakurapadu (mandal),


    Guntur (dist), pin no.522402.Andhra Pradesh.

    Declaration: I firmly declare that the above details provided by me are true to the best of
    my knowledge and belief.
    Place: Bangalore
    Date:

    (G.Pavanisri)

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