Mrinmay Dutta

duttmrinmay@gmail.com
https://www.linkedin.com/in/mrinmaydutta

Objective
Obtain a technical leadership position in an organization that will utilize my 10 years of experience in VLSI domain with
proficiency in team building, mentoring, strategic thinking, problem solving, computer architecture, micro-architecture, logic
design, circuit/physical design, high speed design convergence, power optimization for mutual growth and success.

Experience
RTL TEAM LEAD INTEL CORPORATION [ 2016 + ]
Leading a Front End team of 10 members, responsible for delivering complete RTL design and validation of Execution cluster
of world most complicated IP ‘Intel Big Core IP’ over multiple project including big architectural changes and/or technology
node changes. Member of Intel strategic group ‘Machine Learning Center of Excellence (MLCoE)’ and driving multiple Machine
Learning features across geographical location of Intel Corporation.
Responsibilities
 Responsible for delivering entire Front End (RTL  Present ‘bill of cost’, ROI, execution planning, risk and
design and validation) solution in Execution cluster mitigation plan of each feature to project manager and get
throughout production cycle of Intel Microprocessor. approval.
 Motivate and inspire team with mission and vision of  Work with team to break feature implementation into
the organization. Encourage innovation, risk-taking, smaller task, and understand dependency at each stage.
constant improvement and arrange/deliver necessary Task planning and tracking using HSD-ES.
training to improve technical expertise of the team.  Resource allocation, stakeholder management and resolve
 Collaborate with Arch team on Path Finding (PF) and dependency/conflict to enable team to delivery on time.
High-level Architectural Specification (HAS)  Weekly sync meeting with team members and other
development. stakeholders and roll up progress, new issues, Bug trend,
 Features assignment, Tech Readiness (TR) work group coverage, Test Pass Rate. Discuss top-down direction, new
formation, planning and tracking to meet PF timeline. methodology/MoW and evaluate implication.
 Perform Micro-Architecture Specification (MAS) and  Perform code reviews of complex and risky features. Drive
validation Plan review. Features implementation and Cluster Bug Board and ECO Control Board.
integration staging planning.  Work with Intel strategical group to bring innovation on next
generation technology.
Achievement
 Excel in Quality: Team able to deliver very high quality of RTL code and pre-silicon validation. No Post Silicon bug found
in my cluster over the projects led by me.
 Outperform in Schedule: Team pull-in due date for most of the deliverables over last year.
 Award: Received “Intel India Divisional Award from Intel India GM” for excellent contribution in Machine Learning.

SR. RTL DESIGN ENGINEER INTEL CORPORATION [ 2014 - 2016 ]

RTL owner of complex functional unit of Big Core, FPU (Floating Point Unit) and mentor SIMD (Single Instruction Multiple
Data) and Crypto unit RTL designer. Worked on floating point adder, multiplier, FMA and various complex arithmetic block.
Responsibilities
 Responsible for delivering all features in FPU and  Drive TR work group, roll up various cost, effort and risk of
mentor RTL designer of SIMD and Crypto. the feature. Work with feature validator on validation plan
 Understand feature specification from HAS, design development.
microarchitecture, develop MAS, block and data flow  RTL Coding, Lint clean up, test bench creation and pre-
diagram, Visio. integration validation. Driving feature Integration.
Achievement
 Received “Organization Award from Intel IP Group VP and GM” for pull-in of a complex and intrusive feature, to an
earlier project.
 Received “Organization Award from Intel Core IP GM” for coming up with solutions on the toughest timing problem of
the big Core.
RTL DESIGN ENGINEER INTEL CORPORATION [ 2012 – 2014 ]
RTL designer of SIMD execution unit. Work with Sr. RTL designer to deliver various feature in SIMD. Worked various topology
of logarithmic adder, shifter, booth encoding of higher radix multiplier and horizontal task like DFx.
Responsibilities
 Build depth in architecture and microarchitecture of  Worked with Physical Designer (PD) to estimate area cost,
Intel Big Core, understand x86 Instruction Set timing complexity, power cost. Partial coding of proposed
Architecture, SIMD unit position in full core and it feature to gain more confidence during TR.
major functionality, adjacent unit and interface.  Feature Implementation: RTL Coding, Lint clean up, bucket
 Understand HAS of given feature, design debug and bug fix, worked PD on static timing closer by logic
microarchitecture, develop MAS, data flow diagram, optimization and retiming of sequential, develop and
Visio. Analysis feature complexity, effort and risk. implement power feature.
Achievement
 Received “Departmental Award”, in recognition of the design and implementation SIMD universal shifter which can
handle variable shift count.
 Received “Team Player of the year” award.

CUSTOM CIRCUIT DESIGNER INTEL CORPORATION [ 2010 - 2011 ]

Circuit designer of structural data path block. Worked on ALU, shifter and floating point adder.
Responsibilities
 Responsible for digital circuit design, schematic  Expert user of FEV tool and adder topology. Helped other
implementation, Formal Equivalence Validation (FEV), circuit designer in SCH2RTL FEV clean up, timing converge
floor planning, priority routing, timing and power related to adder and complex feature implementation which
convergence, quality tool report analysis and clean up need to use intermediate node of adder.
Achievement
 Received “Departmental Award”, in recognition of the development and deployment of the PV & Congestion Aware
Group Routing for Structural Data Path Design.

PROJECT ASSOCIATE CAD LAB, INDIAN INSTITUTE OF SCIENCE [ 2008 – 2009 ]

Design of a fully pipeline microarchitecture of Interpolation block of H.264 video decoder. Complete system design, which
contain filters, buffer and control unit. Buffer create interface and start processing data once buffer is full. Implement it in
“Reconfigurable Hardware”.
Highlights
 Micro-architecture and logic design, RTL coding, test  System validation by compared the outputs with output of
bench creation in ModelSim and waveform checking. JM software.
 FSM design, implantation and validation using  Clock gating for power, iteration of HW optimization and
waveform. compare result.

Education
M. TECH Electronics Design and Technology [2007 – 2009]
Department of Electronic Systems Engineering INDIAN INSTITUTE OF SCIENCE, BANGALORE
GPA: 6.4/8
B. E. Electronics and Telecommunication Engineering [ 2003 – 2007 ]
Department of Electronics and Telecomm INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY, SHIBPUR
Aggregate: 83.4%

Publication
 Construction and Maintenance of Energy Aware Virtual Backbone Tree in WSN, 13th National Conf. on Communication,
pp 58-62, 2007
 Timing Aware Routing for Structured Data Path (SDP) Designs in DTTC 2012, Intel Internal conference
 File US patent on Deep Learning/Machine Learning (2018 March) – Intel approved, external approval in progress.