2009 2nd International Workshop on Electron Devices and Semiconductor Technology
Characterization of Interface and Oxide Traps in Ge pMOSFETs based
on DCIV Technique
Debabrata Maji1, F. Crupi2, P. Magnone2, G. Giusi2, C. Pace2, E. Simoen3, and V. Ramgopal Rao1
1
Dept. of Electrical Engineering, Indian Institute of Technology, Bombay 400076, India
2
DEIS, University of Calabria, Via P. Bucci 41C, I-87036 Arcavacata di Rende (CS), Italy
3
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, e-mail: dmaji14@gmail.com
Abstract — The interface trap density of fresh TiN/TaN gated
HfO2/SiO2/Si/epi-Ge pMOSFETs is measured using the DCIV
technique. Its temperature dependence is also discussed here. We
observe a polarity dependent DCIV peak shift. The bias
temperature stress induced interface trapped charge and oxide
trapped charge shifts are also systematically investigated in this
work.
Index Terms — Ge pMOSFET, interface trap, oxide trap, DCIV.
I. INTRODUCTION
The huge demand to maintain increased transistor density as
well as increased saturation current to decrease the switching
delay [1] warrants the investigation of alternative channel
materials. It has been experimentally validated that
germanium offers high hole mobility at higher inversion
charge density and, hence, improves the MOSFETs
performance [2]-[3]. Recently, Nicolas et al. presented high
performance sub-micrometer Ge pMOSFETs with Si
monolayers passivated SiO2/HfO2 gate dielectric [3]. However,
the high density of pre-existing traps in high-k could lead to a
reliability issue. We have recently demonstrated that the high-
k gate dielectric is poor when deposited on Ge compared to Si
[4]. Moreover, Martens et al. showed the interface trap
13 -2
density is of the order of 1-2x10 cm and resides near the
valence band edge [5]-[6]. We also demonstrated that the hot
carrier induced damage is a matter of concern due to the low
band gap of Ge [7]. Based on all this information, in this
work, we look at the post stress interface and oxide charges
build up in Ge pMOSFETs. For this purpose the DCIV
technique [8] is applied to measure independently the interface
and oxide trap charge shifts.
II. DEVICES AND MEASUREMENT
Devices were fabricated using 200 mm Ge-on-Si wafers. A
relaxed ~1.6 - 2 µm Ge layer was deposited epitaxially on top
of the Si substrate. First, an n-well was formed with a P
13 -2
implants of 1 x 10 cm dose at 570 keV followed by 2.5 x
12 -2
10 cm at 180 keV. The threshold voltage adjust implant was
12 -2
4 x 10 cm at 90 keV with P. The Ge surface was passivated
with 6 MLs of epi Si grown at 500 °C using SiH4 as a
precursor, followed immediately by oxidation in slightly
978-1-4244-3832-7/09/$25.00 ©2009 IEEE
ozonated water to get approximately 0.5 nm SiO2. Immediately
after, 4 nm HfO2 was deposited by atomic layer deposition
(ALD). The gate metal consisted of TiN/TaN. A P dose of 4 x
13
10 at 60 keV was used for halo to control the short channel
performance. A detailed process flow can be found elsewhere
[3]-[5]. The device characterizations were done using a
Keithley 4200 semiconductor characterization system. In Fig.
1, a schematic diagram of the Ge-on-Si pMOSFET along with
the DCIV measurement setup [9] used in this work is shown.
The DCIV technique described in [8] is used here with source
well and drain well as emitter junctions and the n-well as base
contact. This is called top emitter DCIV configuration (TE-
DCIV). Here, the base current (IB) is measured by sweeping
the gate voltage (VG) from inversion to accumulation by
applying small forward bias (Ve) to the emitter junction. All
the measurements were done on 10 µm x 1 µm MOSFETs at
room temperature (RT) unless stated otherwise.
VG
Ve
HfO2
TiN
SiO2 A
TaN
Si
p+ p+ n+
n-well 1.6 − 2μm
Ge
Si
Fig. 1. Cross section of a Ge pMOSFET showing the bias
configuration for TE-DCIV measurement.
III. RESULTS AND DISCUSSION
Figure 2 shows the normalized TE-DCIV and DE-DCIV
(here only drain acts as emitter) curves for fresh TiN/TaN
gated HfO2/SiO2/Si/epi-Ge pMOSFETs. Here, Δ IB (= IB -
IBbaseline) is normalized by Δ IBpeak. TE-DCIV shows a better
behaved bell shaped curve with narrow line width compared
IEEE Catalog Number: CFP0926C
ISBN: 978-1-4244-3832-7
Library of Congress: 2009900354
with the DE-DCIV mode. For this reason we will use the TE- recombination origin. In Fig. 4, Si reference data from [10]
DCIV configuration throughout our next discussion. The has also been included for comparison. An interesting
Δ IBpeak value is approximately related to the interface trap observation is found in Fig. 4 which is the relation between
density (Nit) by the equation [9]: the activation energy and band gap (EG). For Ge pMOSFETs,
we found the activation energy depends on EG/2 whereas for
Si in ref [10] it depends on EG.
qN it WLn i σv th ⎡ ⎛ qV e ⎞ ⎤
ΔI Bpeak = ⎢exp⎜⎜ ⎟⎟ − 1⎥ (1)
2 ⎣ ⎝ nkT ⎠ ⎦ Now, from Fig. 1, by using the value of n, and taking
-17 -2
equal to 5 x 10 cm [5] we found Nit approximately equal to
13 -2
6.9 x 10 cm for our Ge pMOSFETs. Martens et al. reported
where q is the electronic charge, W and L are the width and 13 -2
the value of Nit equal to 1- 2 x 10 cm for similar Ge devices
length of the transistor, ni is the intrinsic carrier concentration,
vth is the thermal velocity, and σ is the capture cross-section. -5
10 Ve = 0.1V
n is a parameter around 1.8-2 introduced by Zhu et al. [9]. Ge pMOSFET
The distinct peak in Fig. 2 indicates that our fresh Ge 10/1 Ve = 0.15V

(A)
pMOSFET has a high density of interface traps (Nit). Now, to Ve = 0.2V
calculate the Nit we determine the parameter n by studying the Ve = 0.25V

2.5
-6

ΔIBpeak/(T/298)
temperature dependence of Δ IBpeak in the next section. 10

1.0 Ge pMOSFET -7
10/1
10
0.8 TE-DCIV
DE-DCIV 2.8 3.0 3.2 3.4
ΔIB/Peak

-1
0.6 1000/T (K )

0.4 Fig. 3. Temperature dependence of TE-DCIV peak for different Ve

values. Δ IBpeak of Ge pMOSFETs strongly depend on T in the
0.2 measured temperature range.

0.0 EA α (EG - qVe)

0.0 0.1 0.2 0.3 0.4 0.5 0.6
VG (V) 0.4 Si pMOSFET ref. [10]
ΔIBpeak
Fig. 2. Typical DCIV curve of a Ge pMOSFET with emitter
EA (eV)

forward bias Ve@ 0.2 V. TE-DCIV shows well behaved narrow width
DCIV characteristic. 0.2
Assuming the relations mentioned below [10]:
EA α (EG/2 - qVe)

⎡ ⎛ − E A ⎞⎤ Ge pMOSFET
ΔI Bpeak ∝ T 2.5 ⎢exp⎜⎜ ⎟⎟⎥ (2) 0.0
ΔIBpeak
⎣ ⎝ kT ⎠⎦
0.0 0.1 0.2 0.3 0.4 0.5
⎡ ⎛ qV ⎞⎤ Ve (V)
and ΔI Bpeak ∝ ⎢exp⎜⎜ e ⎟⎟⎥ (3)
⎣ ⎝ nkT ⎠⎦
Fig. 4. Activation energy is plotted against emitter forward bias
voltage. Activation energy depends on half of the band gap value for
we have plotted the Δ IBpeak/T vs. 1/T for different Ve ranging
2.5
the Ge pMOSFET.
from 0.1 V to 0.25 V in Fig. 3. The slope gives the activation using full conductance measurements [6], and 6 x 10 cm
12 -2

energy (EA). From Fig. 3 one can see that the Δ IBpeak of Ge
pMOSFETs strongly depends on the temperature in the range
298 K to 343 K. Finally, using equation (2) and (3) we have
plotted the activation energy (EA) with respect to Ve in Fig. 4.
By linear fitting the data in Fig. 4 we obtain the value of n
approximately equal to 2, indicating a pure surface
using the charge pumping (CP) technique at 80 K [5]. The
factor of 3.5 differences in Nit between TE-DCIV and full
conductance measurements, and one order differences from
CP is justified because of the differences in the measurement
techniques.

2
 On the other hand, the shift in oxide trap charge ( Δ Not) due On the other hand, for a positive stress electron trapping
to the application of stress is given by [9]: dominates, as the DCIV peak shifts to the positive VG
direction. We also observed de-trapping of both electrons and
C ox ΔVGpeak holes during our experiments which may occur from shallow
ΔN ot = (4) trap levels.
q
where Cox is oxide capacitance per unit area, q is electron It is already known that the threshold voltage instability is
charge, and Δ VGpeak DCIV peak voltage shift. strongly process dependent. To know the Nit and Not build up
with positive and negative gate stresses in the Ge pMOSFETs,
In Fig. 5, Δ IB vs. VG is plotted with Ve = 0.2 V for different
we have calculated independently Δ Nit and Δ Not, applying
stress cycles at a stress voltage -2.25 V and 2 V. One can see
equations (1) and (4) and plotted the results as a function of
that along with the DE-DCIV peak increments (due to the
stress time in Fig. 6. Fig. 6 shows the interface trap generation
increase of the interface trap density) there is a consistent
for both positive and negative stress biases. Our analysis
Δ VGpeak shift due to Not build up. It is clear from Fig. 5a, that
shows the initial Nit shift due to accumulation stress bias is
negative gate voltage stress in Ge pMOSFETs gives rise to
high and then it gradually slows down. This may be due to a
hole trapping as the DCIV peak shifts in the negative VG
de-trapping effect. It is also observed that Not increases
direction.
continuously when stress time increases during the negative
-7 voltage stress. However, Not saturation is possibly due to de-
6 x 10
Ge pMOSFET 10000 s
trapping when the stress voltage is positive.
10/1 a 14
VGstress = -2.25 V 10 Ge pMOSFET TE-DCIV@ RT a

Δ N i t & Δ N o t (c m - 2 )
4 TE-DCIV 10/1 Ve@ 0.2 V
Δ I B (A )

V @0.2 V 100s
e VGstress = -2.25V Not
10 s

2 1s 13
10
0s

0 Nit
-0.2 0 0.2 0.4 0.6
VG (V) 12
10 0 1 2 3 4
10 10 10 10 10
-7 Stress time (s)
6 x 10 1000 s
Ge pMOSFET 100 s 14
10/1 10 s 10
VGstress = 2 V Ge pMOSFET TE-DCIV@ RT b
4
Δ N i t & Δ N o t (c m - 2 )

1s
Δ I B (A )

10/1 Ve@ 0.2 V

DE-DCIV 0s VGstress = 2 V
Ve@ 0.2 V Nit
2 b 13
10

0 Not
0.1 0.2 0.3 0.4 0.5 0.6
VG (V) 12
10 0 1 2 3 4
10 10 10 10 10
Fig. 5. Δ IB - VG plot of Ge pMOSFETs using TE-DCIV technique.
a) Shows DCIV peak shift to the left direction when the applied
Stress time (s)
stress bias is negative. This indicates hole trapping in the oxide. b) Fig. 6. Time evolution of Nit and Not of Ge pMOSFETs measured
Shows DCIV peak shift to the right direction which implies electron from TE-DCIV peak current at emitter forward bias 0.2 V. a) For
trapping in the gate oxide. negative stress bias at -2.25 V. b) For positive stress bias at 2 V.

3
 The degradation behavior of Ge pMOSFETs due to bias is also observed using DCIV. Our measurement suggests
Negative Bias Temperature stress is also studied using the TE- that the degradation of interface traps measured by DCIV is
DCIV technique and shown in Fig. 7. Here, the time evolution well correlated with standard on the fly IDlin degradation.
of Nit using TE-DCIV and the degradation of IDlin is compared
for two stress biases (-2.3 V and -2.5 V) at a temperature 85
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