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3, JUNE 2003

Total-Dose Radiation Hardness Assurance

D. M. Fleetwood, Fellow, IEEE, and H. A. Eisen, Senior Member, IEEE

Abstract—Total-dose radiation hardness assurance is reviewed laboratory in exactly the radiation environment that the part is
for MOS and bipolar devices and integrated circuits (ICs), with an required to withstand. So, correlation between laboratory to use
emphasis on issues addressed by recent revisions to military and environments is required. Standard radiation tests must be ca-
commercial standard test methods. Hardness assurance typically
depends upon sample tests of a subgroup of devices or circuits to pable of being performed with commonly available equipment,
determine whether the full group meets its performance and func- often by personnel who are not expert in the field. All these and
tionality requirements to a desired confidence level. The dose rates other issues provide significant challenges to the economical as-
of many standard test methods match neither the very high dose sessment and assurance of the total-dose radiation hardness of
rates of some military environments nor the very low dose rates MOS and bipolar microelectronics.
of most space environments. So, one must ensure that hardness as-
surance test plans address device response in the radiation environ- Many reviews have been written on topics related to radiation
ment of interest. An increasing emphasis has been placed over the hardness assurance in military and space radiation environments
last few decades on standardized test procedures to qualify devices [2]–[10]; here, we will focus on issues that have driven the de-
for use in the natural space radiation environment. Challenging is- velopment and revision of standard test methods over the last
sues for defining test methods for space environments are MOS 20–25 years. In particular, we briefly review early test methods
transistor threshold-voltage rebound and enhanced low-dose-rate
sensitivity for linear bipolar devices and ICs. Effects of preirradi- that focus on using Co-60 irradiation at a modest dose rate to
ation elevated temperature stress on MOS radiation response are provide a reasonable surrogate for some tactical military envi-
also a significant concern. Trends are identified for future radia- ronments [2], [3]. We show how these tests can be extended to
tion hardness tests on advanced microelectronics technologies. cover the natural space environment for MOS devices and dis-
Index Terms—Bipolar radiation effects, hardness assurance, cuss the special challenge of testing linear bipolar devices for
MOS radiation effects, test methods. use in space. We also illustrate how scaling trends in micro-
electronics technologies have changed the way hardness assur-
I. INTRODUCTION ance is performed and how these trends will continue to affect
hardness assurance in the future. A conclusion that seems in-

T HE FUNDAMENTAL challenge of any hardness assur-

ance program is to assure in a cost-effective and timely
fashion that devices and integrated circuits (ICs) will perform
escapable is that there will be increasingly more emphasis on
modeling and simulation and less emphasis on testing programs.
Finally, an Appendix is provided that lists radiation hardness as-
as intended in systems and environments of interest. Because surance test methods.
total-dose irradiation is usually considered a destructive test, in
the sense that the tested device is no longer suitable for system II. HISTORICAL TRENDS
use, nearly all hardness assurance testing depends on sample
testing of a group of devices or circuits. From this population, Over the last 25 years, microelectronics technologies have
one must be able to infer with suitable confidence the radia- changed dramatically. MOS gate lengths have dropped from
tion response of the untested portion of the sample that will be greater than 10 to less than 0.1 m, and gate dielectric layers
used in a particular system. This requires that the sample popu- have shrunk from 70 to less than 2 nm in leading edge com-
lation be relatively homogeneous. Nominally identical devices mercial technologies. During this same time period, defense and
or ICs can show quite different radiation responses. So, there is space system microelectronics needs also have become more
a special problem for many commercial technologies for which diverse. For example, the natural space environment has be-
packaging lots that are grouped by date code do not necessarily come more of a concern to the radiation effects community, as
all come from the same “diffusion” lot, or for processes with opposed to the military systems that were the primary drivers
significant hardness variability. Moreover, total dose radiation during the Cold War era [2]–[12].
environments range in dose rate from above 10 rad(SiO )/s As ICs have become more complex and difficult to test
for certain military environments to less than 10 rad(SiO )/s in statistically significant numbers [13]–[15], the principles
for natural space environments [1]. MOS and bipolar radiation that underlie hardness assurance test methods have evolved in
response often depend strongly on dose rate, energy, and bias response. Originally, test standards were developed to apply
during irradiation, and one rarely is able to test a device in the to relatively inexpensive devices, available in relatively large
numbers, with a single predominant failure mode. Examples
of common failure modes that test methods were designed
Manuscript received January 13, 2003. This work was supported in part by
the Defense Threat Reduction Agency. to detect are gate or field oxide threshold-voltage shifts in
D. M. Fleetwood is with Vanderbilt University, Nashville, TN 37235 USA MOS devices and ICs, and gain degradation in linear bipolar
(e-mail: transistors. These methods often are not as easy to apply to
H. A. Eisen is with ITT AE&S, Bethesda, MD 20814 USA (e-mail: har- complex, expensive integrated circuits that are available only
Digital Object Identifier 10.1109/TNS.2003.813130 in limited numbers, and/or devices that exhibit multiple failure
0018-9499/03$17.00 © 2003 IEEE

modes. So, the standards community has had to adapt its test process [25], [26]. No high-temperature processing was allowed
methods accordingly. after the deposition of the Al-gate, owing to the relatively low
A notable shift in hardness assurance philosophy is the change melting point of Al. For these devices, the circuit failure mech-
fromanexclusive“qualifiedpartslist(QPL)”approach[2],[10]to anisms, and the transistor threshold-voltage ( ) shifts that
allowing (when possible) a “qualified manufacturers list (QML)” cause them, are still quite similar to those for modern Si-gate
approach[10],[16],[17].Theformerfocusesonrigorousandwell- CMOS [27], [28]:
definedteststhataremostlystatisticalindesign.Thelatterisamore • Failure to switch
holistic approach that credits manufacturers who “design in” ra- Positive or negative MOS
diation hardness in a verified and controlled fashion and recog- Negative MOS
nizestherelativedifficulty of“testingin”performance,reliability, • Excessive leakage
and/or radiation hardness that was not first designed and deliber- Negative MOS
ately built into a device or IC. • Speed reduction
The QML approach to hardness assurance presumes the Positive MOS or negative MOS
variables that affect the radiation response of a particular process • Loss of noise immunity
are under statistical process control [16], [17]. Hence, one may Positive or negative MOS
not employ QML methods to attempt to evaluate the suitability of Negative MOS .
devices and ICs for use in a particular system if the required degree To understand why these effects occur, one must recognize
of process and technology control is not present. So, one may not that oxide-trap charge is almost universally found to be net pos-
apply a QML approach to hardness assurance for commercial itive in MOS gate oxides [29], which leads to negative threshold
industrial grade parts that may exhibit a degree of fortuitous voltage shifts in both MOS and MOS transistors during ra-
radiation tolerance; one must use QPL test methods instead [10], diation exposure. Interface trap charge is predominantly nega-
[17], [19]. This is an example of how the variability in radiation tive for MOS transistors, leading to positive threshold voltage
response that is often observed in industrial-grade technologies shifts during radiation exposure, and positive for MOS transis-
that have not been purposefully radiation hardened can lead to tors, leading to negative threshold voltage shifts [30]. The time
hardness assurance and testing issues that are challenging to ad- dependence of the buildup and/or annealing of oxide- and in-
dress in a cost-effective fashion [16]–[22]. However, sometimes terface-trap charge differ greatly, which complicates the design
the savings in part costs and/or the increase in (at least initial) of total dose MOS hardness assurance tests [1], [31]. However,
system functionality can justify the extra expense in testing for early Al-gate devices, with relatively thick oxides, it was
and/or extra risk to a system [20]–[22]. In this regard, we should often the case that the total-dose response was dominated by
point out that a good hardness assurance plan is no substitute for the effects of net positive oxide-trap charge, causing the MOS
considering radiation hardness assurance issues early in system transistor threshold voltage to go into depletion mode at about
design. The best hardness assurance methodology in the world the point of circuit failure [24]–[26]. Device-to-device leakage
cannot salvage a device that is fundamentally unsuited for the use due to parasitic oxides was often controlled by the use of highly
environment. Early and ongoing communication between design doped “guard bands,” especially in radiation hardened technolo-
and test engineers is necessary to develop a practical, economical, gies [27], [28].
and effective hardness assurance test plan. In [24], Gregory compares two process lots, one with a rela-
tively hardened process and another with a less radiation-hard-
III. SINGLE-PARAMETER HARDNESS ASSURANCE TESTS ened process, as illustrated in Fig. 1. The histograms reflect the
unhardened process, and the approximately Gaussian distribu-
Before the mid-1970s, most of the radiation hardness assur- tion shows the greatly improved hardened process. The smaller
ance literature was focused on testing bipolar devices in neutron shifts and the significant reduction in variability for the harder
environments [7]–[9], [23]. With the emergence of CMOS tech- process both make hardness assurance testing much easier for
nology, test methods were initially designed to screen primarily the harder process than the softer process [16], [18]–[22]. If
for the effects of negative MOS gate or parasitic field-oxide tran- one takes as a definition of failure in Fig. 1 the criterion that
sistor threshold-voltage shifts due to the buildup of trapped posi- the MOS shifts less than 1 V, Fig. 2 shows a survival
tive charge in those regions. This testing is analogous in form to confidence for the radiation-hardened parts in this example of
neutron tests intended to assess bipolar transistor gain degrada- 90% for a starting threshold voltage of 1.4 V. A confidence of
tion [23], in the sense that each is a test in which one compares 99.9% is achieved with a starting threshold voltage of 1.9 V
the degradation of a single parameter against an allowable range [24]. Of course, increasing the starting MOS threshold voltage
of responses. This congruence in testing methodology allowed for reduces the speed and initial noise margin of a CMOS IC, so
many similarities in early statistics-based methods used for neu- this leads to tradeoffs between one’s desires to maximize cir-
tron and total-dose hardness assurance. cuit performance and radiation hardness. The dose rate of the
As an illustration of single point hardness assurance testing tests performed in Figs. 1 and 2 is not given in [24]; however,
methods, Gregory provides an early review of the failure mech- typically, Co-60 irradiation1 is done at 50–300 rad(SiO )/s
anisms in Al-gate MOS technologies [24], which is instructive
1In this document, we typically discuss dose rates in rad(SiO )/s, which is
to consider briefly. Unlike the oxides of modern Si-gate de-
the most relevant parameter for MOS and bipolar technologies. Older sources
vices, which are self-aligned and grown early in a processing se- tend to use the more traditional rad(Si)/s. These are interchangeable for gamma
quence, Al-gate oxides were grown toward the end of the device 
irradiation, but differ by a factor of 1.8 for 10-keV X-ray irradiation [58].

do most hardness assurance methods based on isochronal

annealing techniques. An example of a nondestructive hardness
assurance technique is the correlation of preirradiation
noise to postirradiation oxide-trap charge [43]–[45]. Examples
of isochronal and/or isothermal annealing techniques are
provided in [46]–[51]. All these and other related techniques
require characterization testing to determine whether they are
valid for a particular process and cannot easily be applied
to devices having more than one predominant failure mode
[32], [51]–[53]. Moreover, each demands a high level of
radiation-effects knowledge to implement successfully, which
makes the tests difficult to apply in a standard fashion. So, while
these are very useful vehicles for the study of fundamental
radiation effects, neither low-frequency noise nor isochronal
Fig. 1. Flatband voltage shifts for n-substrate capacitors processed in annealing-based hardness assurance tests have found wide-

unhardened (histograms) or hardened ( Gaussian distribution) at Sandia spread use in the MOS device and IC hardness assurance
National Laboratories, using Al-gate CMOS processes. Devices were irradiated
with Co-60 gamma rays at 10 V to 1.0 Mrad(SiO ). The inset is a measure of communities.
the gaussianity of the distribution of threshold-voltage shifts for the hardened
process. (After [24], IEEE ©, used by permission.)
The Appendix provides a comprehensive list of hardness
assurance test documents under present use. This includes
U.S. military performance specifications, handbooks, and test
methods; Defense Threat Reduction Agency (DTRA) docu-
ments; American Society for Testing and Materials (ASTM)
guidelines and standards documents; as well as Electronics
Industry Alliance (EIA) and European Space Agency (ESA)
test methods and guides. These documents are the results of
the efforts of several committees from government, industry,
and user groups who are stakeholders in establishing and
maintaining radiation hardness assurance standards. Also
included in the Appendix are current points of contact to obtain
these documents. In the sections that follow, we discuss several
significant technical issues associated with total-dose hardness
Fig. 2. Normalized average nMOS transistor threshold voltage shift, as assurance standards.
a function of the required standard deviation for the hardened technology
process distribution in Fig. 1, to achieve various survival probabilities after
exposure to 1.0 Mrad(SiO ). The inset shows that a higher starting threshold V. WAFER-LEVEL HARDNESS ASSURANCE
voltage permits devices to survive larger threshold voltage shifts, and/or more
device-to-device variation, without failure at the specified limits in the study. There has been a lot of work in attempting to use sources that
(After [24], IEEE ©, used by permission.) are faster, more convenient, and/or more representative of some
system use environments than Co-60 irradiation sources. Prob-
[1], [31], [32]. The results of Figs. 1 and 2 likely are not easy ably the most attention has been paid to wafer-level irradiation
to extrapolate to radiation environments that are much higher or using a 10-keV X-ray source, which has been sold commercially
lower [1], [32]. by ARACOR [54]. Much work by a number of investigators was
Much work using single-point definitions of failure along the performed to correlate dose enhancement and electron-hole re-
lines of Fig. 1 has been performed, as described in many pub- combination rates in Co-60 and 10-keV X-ray environments in
lications [2], [4], [6], [10], [33]–[36]. There is a large body of the 1980s and early 1990s [55]–[68]. This culminated in ASTM
literature on the statistics of acceptance and failure. These sta- Guide F-1467 that captures well the similarities and differences
tistics are based on the confidence that one has that a particular between 10-keV and Co-60 radiation response [69].
result from a sample lot that is tested reflects the properties of The 10-keV X-ray testing has been used chiefly as a process
the group of interest [4], [6], [10], [23], [33]. To improve this monitor and/or test structure evaluation tool [16], [70], [71] and
confidence level, Namenson and co-workers include informa- is typically not designated for lot acceptance in a procurement
tion derived from parametric degradation during a step-stress document. This is because 10-keV X-ray irradiation typically is
test in a more comprehensive analysis [37]–[42] in addition to done at different dose rates than Co-60 irradiation and because
pass/fail statistics. the effects of electron-hole recombination and dose enhance-
Although it is not often stated, attempts to perform hardness ment are often difficult to account for without detailed, com-
assurance via nondestructive tests that correlate a preirradiation parative testing [55]–[69]. The 10-keV X-ray irradiation can
electrical measurement with postirradiation response typically play a critical role in an overall hardness assurance test plan but
also presume one has a single dominant failure mode, as typically must be correlated to Co-60 irradiation or a radiation

source more representative of the use environment [1], [69]. It is

also important to consider the effects of packaging and/or preir-
radiation elevated temperature stress on MOS or bipolar radia-
tion response, as we discuss below, since these effects can lead
to changes in radiation response from that of devices on a wafer
immediately after processing.


In the mid-1980s, the phenomenon of MOS transistor
rebound was discovered during low-dose-rate irradiations and
postirradiation anneals [72], [73]. Rebound refers to positive
MOS transistor threshold voltage shifts, which are caused
by excess interface-trap charge. Especially in older genera-
tions of CMOS technologies, these shifts can sometimes be
large enough to cause IC failure [72], [73]. Because of the
Fig. 3. Threshold voltage shifts versus dose and dose rate for nMOS
differences in buildup and annealing rates of MOS oxide-trap transistors with 45 nm oxides irradiated with Cs-137 (0.1 rad(SiO )/s) or
charge (which causes negative threshold voltage shifts) and Co-60 (2–200 rad(SiO )/s) gamma rays at 10 V bias (after [31] and [78]).
interface-trap charge (which causes positive threshold voltage
shifts in MOS transistors [1], [30], [31], [72], [73]), a single for MOS ICs [72]. So, the standard range of dose rates used in
radiation test cannot predict the radiation response of MOS MIL-STD 883C, Test Method 1019.3 were inadequate to enable
devices and circuits over a wide range of environments. Hence, accurate prediction of the radiation response MOS devices with
tests that rely on radiation tests at a single dose rate with no significant interface-trap densities in space [31].
provision for making contact to real environments could lead MIL-STD 883D, Test Method 1019.4 addresses the above
to unsuitable parts being accepted for critical applications issues by including a “rebound test” to separately evaluate the
and good parts being rejected on the basis of tests that do not effects of interface traps on MOS device and IC performance
adequately reflect system needs. [1], [31], [52]. Based on early work by Schwank and co-workers
The first standard test method that included tests for both mil- [73], rebound testing uses Co-60 irradiation, followed by a
itary and space radiation environments was MIL-STD 883D, 100 C anneal, to provide an upper bound on the effects of
Test Method 1019.4 [31], [32], [52], [74]–[76]. Earlier versions interface traps on MOS response in a low-dose-rate radiation
of this standard had narrowed the range of allowed dose rates environment [31], [32], [52], [74]. The main test sequence for
from 2–2500 to 100–300 rad(SiO )/s in the desire to ensure MIL-STD 883D, Test Method 1019.4 is illustrated in Fig. 4.
greater uniformity of test results from manufacturer to manu- The basic idea is that the initial Co-60 irradiation provides a
facturer and system to system [77], [78]. However, it was recog- worst case measure of the effects of the net positive oxide-trap
nized that parts intended for use in space systems would be oper- charge on MOS response in space. Then, the subsequent
ated at dose rates more than four orders of magnitude lower than irradiation and elevated-temperature biased anneal provides a
those at which devices were tested. Because some device op- worst case measure of interface-trap effects on MOS response
erating parameters improve with time (e.g., leakage, caused by at low dose rates. For a part to be considered suitable for both
negative MOS transistor threshold voltage shifts) due to defect tactical military and space radiation environments, it must
annealing processes (reduction in net oxide-trap charge), this pass both tests in Fig. 4. In more recent versions of the test
prevented some useful devices from being accepted for space standard, the Co-60 irradiation in the first block of Fig. 4
application. Even more worrisome, interface traps tend to in- can be performed at a lower dose rate and/or followed by an
crease with increasing time, and their effects become more and optional room-temperature anneal, to gain some benefits of
more dominant as they continue to grow and oxide-trap charge room temperature annealing [12], [77], [79] for parts that will
is removed. This can lead to speed, timing, and noise margin only be used in low-dose-rate radiation environments. The
errors due to positive MOS transistor threshold voltage shifts range of alternative dose rates and the maximum time of any
[72]–[76]. room-temperature anneal is determined by the actual dose rate
The above issues are illustrated clearly in Fig. 3. Here, we of a particular system, as discussed in [74].
show MOS transistor threshold-voltage shifts at various dose MIL-STD 883, Test Method 1019 provides an effective con-
rates for a mid-1980s generation radiation-hardened technology servative test for MOS devices intended for use in space, as
built at Sandia National Laboratories [78]. At the higher rates, illustrated in Fig. 5 [80] for a late 1980s Sandia technology
typical of standard dose-rate ranges prescribed in MIL-STD that exhibited significant rebound effects for high total doses at
883C, Test Method 1019.3, the threshold voltage shifts are neg- low dose rates. In all cases shown here, the device degradation
ative, and devices tend to be limited by the buildup of net posi- is worse following room-temperature irradiation and 1-week,
tive oxide-trap charge. However, at the lowest dose rate in Fig. 3 100 C anneal than after low-dose-rate exposure [80], as re-
(which is still much higher than typical dose rates in space), cir- quired to provide a conservative estimate of MOS device re-
cuits are limited by the buildup of negative interface-trap charge. sponse in space [32]. That one may use a postirradiation anneal
This same trend is also observed clearly in circuit failure levels to put an upper bound on MOS low-dose-rate response is due in

Fig. 5. Read access time versus total dose for 16 k static random access
memories built in Sandia’s 2-m radiation-hardened process. Solid symbols
represent irradiation with Cs-137 gamma rays at 0.2 rad(SiO )/s; open circles
are device response after irradiation according to MIL-STD 883D, Test
Method, 1019.4 rebound test conditions specified in Fig. 4 (after [79].)

Fig. 4. Schematic diagram of main path for qualification of MOS devices and
ICs via MIL-STD 883D, Test Method, 1019.4. The three blocks that follow the
Fig. 6. Maximum positive nMOS transistor threshold voltage shift as a
first postirradiation electrical test comprise the “rebound test” in TM 1019 (after
[31], [52], and [76]).

function of dose and oxide thickness, assuming a charge yield of 80% and
an interface-trap generation efficiency of 20% per electron-hole pair that is
generated and escapes recombination (after [74]).
large part because “true” dose rate effects are typically not ob-
served in MOS devices under worst case operating conditions
ance tests [2], [4], [6], [10], [33]–[36]. So, device scaling has
made MOS hardness assurance testing easier to do for modern
While effective, the two-part irradiation and annealing test
devices in recent years. Older technologies with thicker gate ox-
sequence in MIL-STD 883, Test Method 1019 consumes time
ides still require the full testing sequence in Fig. 4. Of course,
and resources that may no longer be justified for many modern
if one does not know the oxide thickness of a particular device
technologies with ultrathin gate oxides. In very thin oxides, it is
or IC being tested, it is difficult to take advantages of simpli-
difficult for enough interface traps to build up to cause device
fications in testing sequence from which one could otherwise
failure [81], [82]. This trend is shown in Fig. 6, in which the
benefit, showing the necessity of understanding at least some
projected maximum MOS transistor threshold voltage rebound
basic processing details of devices intended for use in radiation
is calculated theoretically, assuming one interface trap is created
for every five electron-hole pairs created in the oxide [74].
Modern gate oxides can be more than ten times thinner than
the 20 nm oxide considered in Fig. 6. Thus, it is clear that, VII. BIPOLAR HARDNESS ASSURANCE FOR SPACE
except for very high total doses and/or exceedingly low noise For moderate and high-dose-rate radiation environments, one
margins, rebound will become less and less a problem for most can almost always use similar hardness assurance tests to eval-
modern MOS microelectronics technologies. Indeed, gate oxide uate the total-dose response of MOS and bipolar devices [32],
layers are now so thin in many cases that negative threshold [52], [86], [87]. However, this is not the case for low-dose-rate
voltage shifts are also less and less a problem [81]–[83]. So, environments. The ionizing radiation response of modern linear
the chief concern for modern MOS devices with gate insula- bipolar devices and ICs is mostly a function of oxide and inter-
tors thinner than 10 nm in space often is negative shifts face traps in the parasitic insulator that overlays the base-emitter
associated with parasitic field, edge, and/or buried insulators junction, as shown schematically for an npn transistor in Fig. 7
[28], [67], [84], [85]. These can be assessed easily using the [87], [88]. In 1991, Enlow and co-workers discovered a signifi-
first part of MIL-STD 883D, Test Method 1019.4 in Fig. 4 (not cant enhancement in gain degradation at low dose rates for linear
including the rebound test), in conjunction with the single-pa- bipolar devices that could not be bounded by testing using the
rameter statistical methods developed in early hardness assur- irradiation-and-anneal methodology of MIL-STD 883D, Test

Fig. 7. Cross section of an npn bipolar transistor, representative of devices

used in modern BiCMOS technologies (after [88]).

Method 1019.4 [89]. Follow-on studies have identified other

npn and pnp transistors that show similar, or even larger, exam-
ples of enhanced low-dose-rate sensitivity (ELDRS) [87]–[96]
Fig. 8. Relative damage enhancement, normalized to degradation at 50
and also have confirmed the presence of ELDRS effects at a rad(SiO )/s, for several linear bipolar microcircuits. (After [92], IEEE © 1994,
level similar to that expected from ground tests in space [95]. used by permission.)
Recent studies suggest that the differences between MOS and
bipolar responses occur because, in contrast to MOS devices test. This is based on the tendency, at least in most types of de-
that typically do not show “true” dose-rate effects, linear bipolar vices, for the radiation response to saturate in magnitude at a
devices frequently show effects at low dose rates that cannot be low enough dose rate (e.g., 10 mrad(SiO )/s), at least approxi-
simulated effectively with higher rate irradiation and postirradi- mately [118]–[120]. With suitable margin to account for the pos-
ation anneal [87], [89], [97]–[99]. This is likely due to signifi- sibility that device response at still lower rates in space may be
cant space charge effects that develop during high-dose-rate ir- worse yet, low-dose-rate irradiation is probably the best method
radiation of bipolar devices and ICs that fundamentally alter the of choice for linear bipolar radiation hardness assurance [119],
recombination, transport, and trapping of the charged species especially for fairly low-dose applications where testing can be
(holes, electrons, and protons) that lead to degraded bipolar radi- performed at a rate of 10 mrad(SiO )/s in reasonable amount
ation response [97]–[100]. In MOS devices, electric fields tend of time. Unfortunately, at a dose rate of 10 mrad(SiO )/s, one
to be large and monotonic in direction (vertical, from gate to can deliver only 864 rad(SiO ) to a device in a day. So under
substrate) for worst case operating conditions in a radiation en- these conditions 10 krad(SiO ) irradiation takes 11.5 days, and
vironment. For bipolar devices, the fields are small and non- 100 krad(SiO ) irradiation takes nearly four months to com-
monotonic in direction. So, one can easily achieve conditions plete. Moreover, in tests involving prolonged irradiation expo-
in bipolar devices for which the electric fields are totally dif- sures, there is also an increased risk that, if something goes
ferent for high- and low-dose-rate irradiations [97], [101]. The wrong logistically with a test (e.g., there is a power outage, a
resulting enhanced low-dose-rate sensitivity is much more dif- significant static glitch, etc.), this can have a major impact on
ficult to account for with standard test methods than is rebound system schedules. For a critical application where a device must
in MOS technologies [52], [87]. be assured of working for the life of the system, this level of time
The magnitude of the ELDRS problem in several representa- and expense may be warranted. However, there is a natural de-
tive devices can be seen in Fig. 8, for example. Here, it is shown sire to try to find a shorter more cost-effective testing approach.
that the response of some devices at low dose rates is more than One approach to try to accelerate hardness assurance testing
a factor of five times larger than the response of devices irra- for space applications that is effective for many (but not all)
diated at high dose rates. So, this is a very serious problem for linear bipolar devices and ICs is elevated-temperature irradia-
radiation hardness assurance for many low-dose-rate radiation tion [97], [106], [111], [118], [119]. Irradiating either an MOS
environments. or a bipolar device at a temperature that is significantly higher
Significant progress has been made in the understanding of than the maximum temperature at which a system is expected
ELDRS mechanisms [96]–[117] and the factors that influence to operate (for the majority of its life) can accelerate the an-
whether a particular device exhibits ELDRS or not. The influ- nealing of oxide-trap charge and the buildup of interface traps
ences of hydrogen [98]–[100] and/or mechanical stress due to [97], [106], [121], [122]. With MOS devices, elevated temper-
chip passivation layers [117] appear to be especially significant. ature annealing also accomplishes these goals successfully, but
Revised versions of military and commercial test methods are this is not typically the case for bipolar devices [89], [98], [104],
available (most notably, ASTM Guide F-1892 [118], [119], and [115], [119]. However, for many part types, degradation occurs
soon a revised version of MIL-STD 883, Test Method 1019) at a level during high-temperature irradiation that is comparable
to help users assess the suitability of bipolar devices for space to that during low-dose-rate irradiation at room temperature, es-
applications. At present, two primary strategies are available pecially if one uses appropriate safety factors in setting allowed
for hardness assurance testing of bipolar devices known or sus- parametric and functional failure levels during the high-temper-
pected of exhibiting ELDRS. The first is an actual low-dose-rate ature irradiations [106], [111], [118], [119], and/or performs the

Fig. 10. Input bias current as a function of preirradiation elevated temperature

Fig. 9. Excess base current, which is proportional to gain degradation, as a stress (PETS) time for LM111 devices irradiated to 100 krad(SiO ) at 0.1 or
function of irradiation temperature for 294 rad(SiO )/s irradiations of lateral 50 rad(SiO )/s with all pins grounded. One group of the devices irradiated at
pnp bipolar transistors, as compared to low dose rate response. (After [106].) 50 rad(SiO )/s also received an unbiased anneal at room temperature for a time
equal to that elapsed during the lower rate exposures (after [115]).

high-temperature irradiation at a dose rate of 1–10 rad(SiO )/s

[119], [123]. tion sources by up to ten times or more. However, it is presumed
A comparison between room-temperature and high tem- that there are knowledgeable engineers and scientists designing
perature irradiation is illustrated in Fig. 9 [106]. For these and helping to evaluate the tests, as the lack of validated test
devices, irradiation at 150 C at 300 rad(SiO )/s pro- standards otherwise would lead to a higher risk to these sys-
vides a fairly close approximation of device degradation at tems.
1 mrad(SiO )/s (the striped band at the top of the figure).
However, for other types of devices, such excellent agreement IX. PREIRRADIATION ELEVATED TEMPERATURE STRESS
between high-temperature irradiation and low-rate response is
not always observed [108], [119], and there is definite risk of Until fairly recently, there was at least the tacit assumption
interface-trap annealing above 100 C [31], [52]. The benefits that the total dose hardness of a MOS or bipolar device was
and risks of using high-temperature irradiation for linear fixed upon the last high-temperature (greater than 850 C)
bipolar hardness assurance have been discussed often in the step in device processing. However, recently there has been
literature [97], [106], [111], [118], [119], [123]–[126], and a a lot of evidence that, for many part types, total dose radi-
series of preliminary recommendations are included in ASTM ation response can change during postprocessing heating to
Guide F-1892 [118], [119]. At present, efforts to standardize temperatures of 100–400 C, and/or aging after device
on a dose-rate and temperature for high-temperature irradiation processing [115], [116], [128]–[134]. Of special concern for
of linear bipolar devices are focused on a temperature of hardness assurance test methods are accounting for the effects
100 C and a dose rate of 1–10 rad(SiO )/s [118], [119], of burn-in and packaging environments on radiation hardness
[125]. But, this guidance still should be regarded as somewhat [115], [117], [129]–[131], which can be quite significant.
preliminary, and the safest course in space system design is to For example, Shaneyfelt and co-workers have found a strong
try one’s best to avoid using linear bipolar devices that exhibit interdependence between ELDRS and preirradiation elevated
ELDRS whenever it is possible to do so and still meet system temperature stress (PETS) effects. This is illustrated in Fig. 10,
requirements [20], [21], [96], [127]. which shows a dramatic difference between the magnitudes
of ELDRS effects exhibited by bipolar devices, depending on
the type of PETS the device had received [115]. Significant
changes in radiation hardness with burn-in are also reported for
At present, military and commercial standards do not address some types of MOS devices and ICs as well, as illustrated in
the needs of some types of (primarily military) radiation envi- Fig. 11. PETS effects appear to be quite sensitive to hydrogen
ronments in which a significant amount of dose is delivered at and/or mechanical stress in the devices [115], [117], [128],
a rate much greater than 1 krad(SiO )/s. While there is some [134], each of which can be affected by the way a device is
guidance in the literature for how one might design a hardness packaged and/or burned-in before system use.
assurance test plan for these kinds of systems [1], [52], [80], it The sensitivity of microelectronic radiation response to post-
is usually expected that these systems will either perform tests processing temperature and stress is a significant challenge to
to simulate the actual radiation environment or use modeling hardness assurance. For example, a device might show accept-
and simulation to develop surrogate tests that are easier and less able radiation response at the wafer level when one performs
expensive to perform. The 10-keV X-ray testing can play a sig- 10-keV X-ray irradiation, but unacceptable response after the
nificant role in this regard [1], [52], [80] because the dose rate device is packaged, regardless of whether there are any other dif-
available is higher than that of typical laboratory Co-60 radia- ferences in radiation energy, dose rate, bias, etc. Changes in radi-

dimensions, the concept of total dose response may become

less useful. Instead, every radiation interaction may have to
be treated as a single event, as opposed to in a statistical,
cumulative fashion, as one typically does in total dose testing.
An example of this on a somewhat larger size scale is the
effects of “microdose” on highly scaled electronics, in which
a single cosmic ray can deposit enough local energy to cause
a hard error in a memory [137]. We expect similar and even
more challenging effects to be observed in nanotechnologies
and biologically inspired computing elements. These and other
emerging areas are expected to be quite challenging from the
standpoint of basic mechanisms and hardness assurance, and
the sensitivity of some kinds of extremely small devices may
limit their use in high radiation environments like space [138].

Fig. 11. Static power supply leakage for octal buffer/line drivers with or XI. CONCLUSION
without preirradiation burn in at 150 C for one week. Devices were irradiated
with Co-60 gamma rays at 90 rad(SiO )/s at 5.5 V (after [129]). Total-dose radiation hardness assurance for many tactical
military and low-dose-rate environments can be performed with
high confidence for MOS devices using existing standard test
ation response as a device ages in system use and/or storage is a methods, as long as devices are tested in the packages used in
closely related concern. Presently, MIL-STD 883, Test Method the system and have experienced an equivalent thermal history.
1019 and ASTM Guide F-1892 require the irradiation of devices For linear bipolar devices that exhibit ELDRS effects, there
in the packages in which they are to be fielded, after exposure can be significantly greater uncertainty in the ability of either
to the same thermal treatments they will receive in their use his- low-dose-rate testing or elevated-temperature irradiation to be
tory, unless the devices are demonstrated not to be sensitive to an adequate hardness assurance test method. In either case,
PETS effects [115], [131], [132]. But, this continues to be an hardness assurance testing is simplified if considered as early as
area of active study, both from mechanisms and hardness assur- possible in system design, as sometimes the success or failure
ance standpoints. of one’s hardness assurance test plan is determined almost
entirely by the selection of the part types to be evaluated. In the
X. FUTURE TRENDS IN HARDNESS ASSURANCE future, continued scaling down of device feature sizes and the
As technologies change, new effects like ELDRS and PETS introduction of new technologies into radiation environments
are almost certain to be found. A continuing trend is for de- will make radiation hardness assurance an ongoing challenge.
vices to have smaller feature sizes and to be more complex in There will be few short cuts to an understanding of basic device
design. This makes it virtually impossible to define a reasonable radiation response. This will increasingly include a heavier
set of test vectors and/or bias conditions that ensure approxi- reliance on modeling and simulation to understand how to
mately worst case response for the device or IC. Modeling and improve device response and/or design improved hardness
simulation are increasingly necessary to do analysis of circuit assurance tests. Validation and verification testing will always
response before and after irradiation to identify operating con- be required at one level or another to check for variations in
ditions under which a circuit may be expected to be most vul- device response as well as to continue to look for unexpected
nerable to radiation exposure [13]–[15], [28]. This clearly will failure mechanisms.
be an area of increasing study.
Most MOS radiation hardness assurance test techniques APPENDIX
are designed under the presumption that the gate dielectric is
The following are radiation hardness assurance test methods,
thermal SiO . It is already known that other dielectrics like
guidelines, and standards. Also included is present contact in-
Al O , Si N , and HfO and Hf silicates can have different
formation from which copies may be obtained. This list updates
radiation responses than thermal SiO [5], [135], [136]. So,
that provided in [2]; this list is updated at the Web site of the
assumptions made in relating irradiation and annealing to
Space Parts Working Group’s Hardness Assurance Committee:
low-dose-rate response for MOS devices, for example, likely
will have to be reevaluated when these kinds of insulating
layers become more common in microelectronics.
Farther into the future, there is presently a lot of speculation Military Performance Specifications
that non-Si based nanotechnologies and/or biologically inspired • 19 500, General Specification for Semiconductor Devices.
devices may replace or augment the capabilities of Si-based • 38 510, General Specification for Microcircuits.
electronics for some critical high-performance sensing and • 38 534, Performance Specification for Hybrid Microcir-
computing environments. Some of these technologies may cuits.
be very radiation tolerant; others may be extremely radiation • 38 535, General Specification for Integrated Circuits (Mi-
sensitive. One can make the case that, for small enough device crocircuits) Manufacturing.

Military Handbooks ASTM Standards

• 814, Ionizing Dose and Neutron Hardness Assurance
The following are test and measurement standards. They are
Guidelines for Microcircuits and Semiconductor Devices.
under the oversight of ASTM Subcommittee F1.11, Quality and
• 815, Dose Rate Hardness Assurance Guidelines.
Hardness Assurance; Chairman, Allan Johnston, 818-354-6425.
• 816, Guidelines for Developing Radiation Hardness As-
sured Device Specifications. • F448, Test Method for Measuring Steady-State Primary
• 817, System Development Radiation Hardness Assurance. Photocurrent.
• 339, Custom Large Scale Integrated Circuits, Develop- • F526, Test Method for Measuring Dose for Use in Linear
ment and Acquisition for Space Vehicles. Acceleration Pulsed Radiation Effects Tests.
• 1547, Electronic Parts, Materials, and Processes for Space • F528, Test Method of Measurement of Common-Emitter
and Launch Vehicles. D-C Current Gain of Junction Transistors.
• 1766, Nuclear Hardness and Survivability Program • F615, Practice for Determining Safe Current Pulse Oper-
Guidelines for ICBM Weapon Systems and Space Sys- ating Regions for Metallization on Semiconductor Com-
tems. ponents.
• F616, Test Method for Measuring MOSFET Drain
Military Test Methods Leakage Current.
• F617, Test Method for Measuring MOSFET Linear
In MIL-STD-750 (Test Methods for Semiconductor Devices)
Threshold Voltage.
• 1017, Neutron Irradiation Procedure. • F676, Test Method for Measuring Unsaturated TTL Sink
• 1019, Steady State Ionizing Radiation (Total Dose) Test Current.
Procedure. • F744, Test Method for Measuring Dose Rate Threshold
• 1032, Package Induced Soft Error Test Procedure (Due To for Upset of Digital Integrated Circuits.
Alpha Particles). • F769, Test Method for Measuring Transistor and Diode
• 1080, Single Event Burnout and Single Event Gate Rup- Leakage Currents.
ture. • F773, Practice for Measuring Dose Rate Response of
• 3478, Power MOSFET Electrical Dose Rate Test Method. Linear Integrated Circuit.
• 5001, Wafer Lot Acceptance Testing. • F980, Guide for the Measurement of Rapid Annealing of
In MIL-STD-883 (Test Methods and Procedures for Micro- Neutron-Induced Displacement Damage in Silicon Semi-
electronics) conductor Devices.
• 1017, Neutron Irradiation Procedure. • F996, Test Method for Separating an Ionizing Radiation-
• 1019, Steady State Ionizing Radiation (Total Dose) Test Induced MOSFET Threshold Voltage Shift into Compo-
Procedure. nents Due to Oxide Trapped Holes and Interface States
• 1020, Dose Rate Induced Latchup Test Procedure. Using the Subthreshold Current-Voltage Characteristics.
• 1021, Dose Rate Upset Testing of Digital Microcircuits. • F1190, Practice for the Neutron Irradiation of Unbiased
• 1023, Dose Rate Response of Linear Microcircuits. Electronic Components.
• 5004, Screening Procedures. • F1192, Guide for the Measurement of Single Event Phe-
• 5005, Qualification and Quality Conformance Procedures. nomena (SEP) Induced by Heavy Ion Irradiation of Semi-
• 5010, Test Procedures for Complex Monolithic Microcir- conductor Devices.
cuits. • F1262, Guide for Transient Radiation Upset Threshold
Military standards, specifications, and handbooks can be Testing of Digital Integrated Circuits.
viewed and ordered from the Web site of the DoD Docu- • F1263, Test Method for Analysis of Overtest Data in Ra-
ment Automation and Production Services (DAPS), Bldg. diation Testing of Electronic Parts.
4/D (DPM-DODSSP), 700 Robbins Ave., Philadelphia, PA • F1467, Guide for Use of an X-Ray Tester ( 10 keV Pho-
19111-5094 USA. Their URL is tons) in Ionizing Radiation Effects Testing of Semicon-
For assistance, one can phone 215-697-2179 or Fax—1462. ductor Devices and Microcircuits.
Most can also be viewed and downloaded at DSCC’s web site, • F1892, Guide for Ionizing Radiation (Total Dose) Effects Testing of Semiconductor Devices.
• F1893, Guide for the Measurement of Ionizing Dose-Rate
DTRA Documents Burnout of Semiconductor Devices.

• DNA-H-93-52, Program Management Handbook on Nu- The following are radiation dosimetry standards. They are
clear Survivability. under the oversight of ASTM Subcommittee E10.07; Chairman,
• DNA-H-95-61, Transient Radiation Effects on Electronics Dave Vehar, 505-845-3414.
(TREE) Handbook. • E265, Test Method for Measuring Reaction Rates and
• DNA-H-93-140, Military Handbook for Hardness Assur- Fast-Neutron Fluences by Radioactivation of Sulfur-32.
ance, Maintenance and Surveillance (HAMS). • E496, Test Method for Measuring Neutron Fluence Rate
DTRA documents can be obtained from the Defense Tech- and Average Energy from 3H(d,n)4He Neutron Genera-
nical Information Center (DTIC), phone 800-225-3842. tors by Radioactivation Techniques.

• E665, Practice for Determining Absorbed Dose Versus • EIA/JEP-133, Guideline for the Production and Acquisi-
Depth in Materials Exposed to the X-Ray Output of Flash tion of Radiation-Hardness Assured Multichip Modules
X-Ray Machines. and Hybrid Microcircuits.
• E666, Practice for Calculating Absorbed Dose from • EIA/TIA-455-64 (FOTP-64), Procedure for Measuring
Gamma or X Radiation. Radiation-Induced Attenuation in Optical Fibers and
• E668, Practice for Application of Thermoluminescence Cables.
Dosimetry Systems for Determining Absorbed Dose in Some EIA/JEDEC standards can be obtained from Global
Radiation-Hardness Testing of Electronics. Engineering Documents, 15 Inverness Way East, Engle-
• E720, Guide for Selection of a Set of Neutron-Activation wood CO 80112-5704. Phone 800-854-7179. Otherwise see
Foils for Determining Neutron Spectra Used in Radiation- or
Hardness Testing of Electronics.
• E721, Method for Determining Neutron Energy Spectra ESA Test Methods and Guides
with Neutron-Activation Foils for Radiation Hardness
Testing of Electronics. • ESA/SCC Basic Specification no. 22900, Total Dose
• E722, Practice for Characterizing Neutron Energy Fluence Steady-State Irradiation Test Method.
Spectra in Terms of an Equivalent Monoenergetic Neutron • ESA/SCC Basic Specification no. 25100, Single Event Ef-
Fluence for Radiation-Hardness Testing of Electronics. fects Test Method and Guidelines.
• E1026, Methods for Using the Fricke Dosimeter to Mea- • ESA PSS-01-609, The Radiation Design Handbook.
sure Absorbed Dose in Water. ESA documents can be obtained from ESA/SCC Secretariat
• E1249, Practice for Minimizing Dosimetry Errors in Ra- (TOS-QCS), ESTEC P.O. Box 299, 2200 AG Noordwijk, The
diation Hardness Testing of Silicon Electronic Devices Netherlands.
Using Co-60 Sources.
• E1250, Test Method for Application of Ionization Cham- ACKNOWLEDGMENT
bers to Assess the Low Energy Gamma Component of
Cobalt-60 Irradiators Used in Radiation-Hardness Testing The authors would like to thank L. Cohn of the Defense
of Silicon Electronic Devices. Threat Reduction Agency for sustained support of hardness
• E1854, Practice for Assuring Test Consistency in Neutron- assurance activities, as well as their professional colleagues
Induced Displacement Damage of Electronic Parts. and the many members of the DoD, ASTM, EIA, and ESA
• E1855, Method for Use of 2N2222 Silicon Bipolar Tran- committees who have devoted their time and efforts in support
sistors as Neutron Spectrum Sensors and Displacement of defining hardness assurance standards.
Damage Monitors.
• E1894, Guide for Selecting Dosimetry Systems for Appli- REFERENCES
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