Problem 1.

Give the timing diagram for the one OR gate, one AND gate circuit described by :
V=W+X; Z = YV. Assume that both gates have a propagation delay of 5ns, and W is '1'
only from times 10ns to 20 ns and from 30 to 40 ns; X is '1' only from 5ns to 15ns and
30ns to 40ns; and Y is '1' from 10ns to 35ns.

Solution:
Problem 2.
Give the timing diagram for the one AND gate and one INVERTER "feedback" circuit
described by Z = XY; Y=Z' . Assume that the inverter gate has 5ns propagation delay and
the AND gate has propagation delay of 10ns. Assume X is initially '0', Y is initially '1' ,
and X then goes to '1' for 80ns and then returns to '0'.

Solution:
The following figure shows the circuit and its waveforms.
Problem 3.
Design a counter, which counts in the following manner 0000, 1000, 1100, 1010, 1110,
0001, 1001, 1101, 1011, 1111, 0000, etc...
(a) Using clocked T flip flops and AND and OR gates. (b) using clocked D flip flops and
NOR gates. (c) using SR flip flops and AND and OR gates. (d) using clocked JK flip
flops and NAND gates.
Solution:
3a.
Present State Next State T Flip Flops
Qa Qb Qc Qd Qa Qb Qc Qd Ta Tb Tc Td

0 0 0 0 1 0 0 0 1 0 0 0
1 0 0 0 1 1 0 0 0 1 0 0
1 1 0 0 1 0 1 0 0 1 1 0
1 0 1 0 1 1 1 0 0 1 0 0
1 1 1 0 0 0 0 1 1 1 1 1
0 0 0 1 1 0 0 1 1 0 0 0
1 0 0 1 1 1 0 1 0 1 0 0
1 1 0 1 1 0 1 1 0 1 1 0
1 0 1 1 1 1 1 1 0 1 0 0
1 1 1 1 0 0 0 0 1 1 1 1

Ta Tb
abcd oo o1 11 10 abcd oo o1 11 10
oo 1 1 X X oo 0 0 X X
o1 X X X X o1 X X X X
11 0 0 1 1 11 1 1 1 1
10 0 0 0 0 10 1 1 1 1
Ta = A’+ BC Tb = A

Tc Td
abcd oo o1 11 10 abcd oo o1 11 10
oo 0 0 X X oo 0 0 X X
o1 X X X X o1 X X X X
11 1 1 1 1 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0
Tb = B Td = BC
3b.Should take 0’s from kmaps then convert to NOR-NOR
implementation -
Present State Next State D Flip Flops
Qa Qb Qc Qd Qa Qb Qc Qd Da Db Dc Dd

0 0 0 0 1 0 0 0 1 0 0 0
1 0 0 0 1 1 0 0 1 1 0 0
1 1 0 0 1 0 1 0 1 0 1 0
1 0 1 0 1 1 1 0 1 1 1 0
1 1 1 0 0 0 0 1 0 0 0 1
0 0 0 1 1 0 0 1 1 0 0 1
1 0 0 1 1 1 0 1 1 1 0 1
1 1 0 1 1 0 1 1 1 0 1 1
1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 0 0 0 0 0

Da Db
abcd oo o1 11 10 abcd oo o1 11 10
oo 1 1 X X oo 0 0 X X
o1 X X X X o1 X X X X
11 1 1 0 0 11 0 0 0 0
10 1 1 1 1 10 1 1 1 1
Da = Db = AB’
= C’ + B’ = ( ( C’+B’ )’)’ = ((AB’)’)’ = (A’+B)’
= ( (C’ + B’)’ + (C’ + B’)’ )’

Dc Dd
abcd oo o1 11 10 abcd oo o1 11 10
Oo 0 0 X X oo 0 1 X X
o1 X X X X o1 X X X X
11 1 1 0 0 11 0 1 0 1
10 0 0 1 1 10 0 1 1 0
Dc = Dd =
= ((B+C)’ + (B’+C’)’)’ = ((B+D)’ + (C+D)’ + (C’+B’+ D’)’ )’
3c.
Present State Next State S-R Flip Flops
Qa Qb Qc Qd Qa Qb Qc Qd Sa Ra Sb Rb Sc Rc Sd Rd

0 0 0 0 1 0 0 0 1 0 0 X 0 X 0 X
1 0 0 0 1 1 0 0 X 0 1 0 0 X 0 X
1 1 0 0 1 0 1 0 X 0 0 1 1 0 0 X
1 0 1 0 1 1 1 0 X 0 1 0 X 0 0 X
1 1 1 0 0 0 0 1 0 1 0 1 0 1 1 0
0 0 0 1 1 0 0 1 1 0 0 X 0 X X 0
1 0 0 1 1 1 0 1 X 0 1 0 0 X X 0
1 1 0 1 1 0 1 1 X 0 0 1 1 0 X 0
1 0 1 1 1 1 1 1 X 0 1 0 X 0 X 0
1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1

Sa Ra
abcd oo o1 11 10 abcd oo o1 11 10
oo 1 1 X X oo 0 0 X X
o1 X X X X o1 X X X X
11 X X 0 0 11 0 0 1 1
10 X X X X 10 0 0 0 0
Sa = A’ Ra = BC

Sb Rb
abcd oo o1 11 10 abcd oo o1 11 10
oo 0 0 X X oo X X X X
o1 X X X X o1 X X X X
11 0 0 0 0 11 1 1 1 1
10 1 1 1 1 10 0 0 0 0
Sb = AB’ Rb = B

Sc Rc
abcd oo o1 11 10 abcd oo o1 11 10
oo 0 0 X X oo X X X X
o1 X X X X o1 X X X X
11 1 1 0 0 11 0 0 1 1
10 0 0 X X 10 X X 0 0
Sc = BC’ Rc = BC
Sd Rd
abcd oo o1 11 10 abcd oo o1 11 10
oo 0 X X X oo X 0 X X
o1 X X X X o1 X X X X
11 0 X 0 1 11 X 0 1 0
10 0 X X 0 10 X 0 0 X
Sd = BCD’ Rd = BCD

3d.
Present State Next State J-K Flip Flops
Qa Qb Qc Qd Qa Qb Qc Qd Ja Ka Jb Kb Jc Kc Jd Kd

0 0 0 0 1 0 0 0 1 X 0 X 0 X 0 X
1 0 0 0 1 1 0 0 X 0 1 X 0 X 0 X
1 1 0 0 1 0 1 0 X 0 X 1 1 X 0 X
1 0 1 0 1 1 1 0 X 0 1 X X 0 0 X
1 1 1 0 0 0 0 1 X 1 X 1 X 1 1 X
0 0 0 1 1 0 0 1 1 X 0 X 0 X X 0
1 0 0 1 1 1 0 1 X 0 1 X 0 X X 0
1 1 0 1 1 0 1 1 X 0 X 1 1 X X 0
1 0 1 1 1 1 1 1 X 0 1 X X 0 X 0
1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1

Ja = 1

Ka
abcd oo o1 11 10
oo X X X X
o1 X X X X
11 0 0 1 1
10 0 0 0 0
Ka = BC = (( BC)’ )’ = ( (BC)’ (BC)’ )’
Kb = 1

Jb
abcd oo o1 11 10
oo 0 0 X X
o1 X X X X
11 X X X X
10 1 1 1 1
Jb = A

Jc Kc
abcd oo o1 11 10 abcd oo o1 11 10
oo 0 0 X X oo X X X X
o1 X X X X o1 X X X X
11 1 1 X X 11 X X 1 1
10 0 0 X X 10 X X 0 0
Jc = B Kc = B

Jd Kd
abcd oo o1 11 10 abcd oo o1 11 10
oo 0 X X X oo X 0 X X
o1 X X X X o1 X X X X
11 0 X X 1 11 X 0 1 X
10 0 X X 0 10 X 0 0 X
Jd = BC = ( ( BC)’ (BC)’)’ Kd = BC = ( ( BC)’ (BC)’)’
Problem 4.
Design a network which adds 5 to the contents of a 4bit register after a single input pulse
(C) is applied to the network. Use JK flip flops and assume the number in the 4-bit
register, N is 0000 <= N <= 1001.

Solution:
The following table shows the present states and next states of the register. The J/K
inputs of each flip flop are also shown in this table. The numbers under each J/K input is
obtained by comparing each column in the “Next State” by each column in the “Present
State”. Note that in a J-K flip flop the current state is kept if J/K=0/0, the current state is
inverted if J/K=1/1, the next state is “1” if J/K=1/0 and the next state is “0” if J/K=0/1.

Present State Next State

ABCD ABCD Ja Ka Jb Kb Jc Kc Jd Kd
0 0 0 0 0 1 0 1 0 X 1 X 0 X 1 X
0 0 0 1 0 1 1 0 0 X 1 X 1 X X 1
0 0 1 0 0 1 1 1 0 X 1 X X 0 1 X
0 0 1 1 1 0 0 0 1 X 0 X X 1 X 1
0 1 0 0 1 0 0 1 1 X X 1 0 X 1 X
0 1 0 1 1 0 1 0 1 X X 1 1 X X 1
0 1 1 0 1 0 1 1 1 X X 1 X 0 1 X
0 1 1 1 1 1 0 0 1 X X 0 X 1 X 1
1 0 0 0 1 1 0 1 X 0 1 X 0 X 1 X
1 0 0 1 1 1 1 0 X 0 1 X 1 X X 1

Now we should use the numbers under each J and K to find the relevant function for that
specific input. Using Kmap for J a for example we have:

Which results in: J a = B+CD.

Apparently, K a =0 and J d =K d =1.
Using Kmap for the rest of the inputs we get:

J b =K b =C’+d’.
J c =K c =D.