TN 423: VLSI CIRCUITS

Lecture 6

ASSEMBLY AND PACKAGING

TECHNIQUES
Ngeze, LV VLSI Circuits 1
 Outline
1. Introduction
2. Wafer Assembly Techniques
3. Packaging of VLSI
4. Package Design Considerations (Parameters)
5. Package Types

Ngeze, LV VLSI Circuits 2

 Introduction
Ω Packaging of VLSI ranges from preassembly
wafer preparation to fabrication technologies for
the packages
Ω It affects the cost, performance and reliability of
the packaged die
Ω Packaging techniques have to be upgraded
accordingly because of the increase in chip
complexity and chip size
Ω Number of I/O terminals required for logic and
microprocessor devices has continued to
increase in proportion to the number of gates on
the chip Ngeze, LV VLSI Circuits 3
 Introduction
Rent’s Rule
Ω In the 1960s, E. F. Rent, an IBM employee,
found a remarkable trend between the number
of I/O pins (terminals, T) at the boundaries of IC
designs and the number of internal components
(g), such as logic gates or standard cells.
Ω Rent’s rule states that the following relationship
exists between several chip parameters.

T = AKP

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 Introduction
 T is the number of I/O terminals,
 A the average number of terminals for one block and
 K the number of blocks within the chip,
 p the Rent’s exponent (p < 1.0, generally 0.5 < p < 0.8)

Ω Rent's rule has been widely used to

 estimate the number of interconnects.
 estimate power dissipation in interconnects.

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 Introduction
Questions:
1. The average number of connections for one
block is 72 pins. The chip has six block. Find the
number of external connections if p=0.6

2. A 360 legged chip has K blocks with 10

terminals each. If p = 0.7, find the K.

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 Introduction
Ω The decrease in feature size results in chips
with higher I/O count and more interconnections
to the silicon
Ω The chip is to be made as small as possible and
placed into high density packages requiring
smaller lead spacing
Ω The package design is also required to provide
 good heat dissipation
 Good electrical performance and
 high reliability

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 Wafer Assembly Techniques
Ω The assembly sequence for plastic and ceramic
packages include:
1. Wafer preparations
 Wafer backgrinding, wafer slicing, and wafer
handling are of utmost importance
 Thicker wafers place more demand on the
separation process and on VLSI package design
and assembly process
 Diamond wheel dicing method is used nowdays to
have better quality cuts that allowthe narrowing of
streets and improved capability for cutting through
dissimilar materials
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 Wafer Assembly Techniques
2. Die interconnection
 The back of the die is mechanically attached to an
appropriate mount medium
 Bond pads on the circuit side of the die are
electrically connected to the package
3. Die bonding
 Requires thermal and stress management for large
dies
 Eutectic die bonding
 Epoxy die bonding

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 Wafer Assembly Techniques
4. Wire bonding
 This step follows after die bonding
 Gold wire is ball-wedge bonded
 Symmetrical geometry of the capillary tip is used

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 Packaging of VLSI
What is Packaging of VLSI?
Ω It is the science and the art of establishing
interconnections and a suitable operating environment
for predominantly electrical circuits.

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 Packaging of VLSI
Need for Packaging?
ΩIt supplies the chips with wires to
1. distribute signals and power,
2. remove the heat generated by the circuits, and
3. provide them with physical support and
environmental protection.
ΩIt plays an important role in determining the
performance, cost, and reliability of the system.

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Electronic Packaging Requirements
Ω Speed
 Large bandwidth
 Short inter-chip propagation delay
Ω Size
 Compact size
Ω Thermal & Mechanical Properties
 High heat removal rate
 A good match between the thermal coefficients of the dice and
the chip carrier
Ω Test & Reliability
 Easy to test
 Easy to modify
 Highly reliable
 Low cost Ngeze, LV VLSI Circuits 13
Electronic Packaging Requirements
Ω Pin Count
 Large I/O count per chip
 Large I/O between the first and second level
package
Ω Noise
 Low noise coupling among wires
 Good-quality transmission line
 Good power distribution

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 Packaging Hierarchy
Ω The semiconductor chip is encapsulated into a
package, which constitutes the first level of
packaging.
Ω A printed circuit board is usually employed
because the total circuit and bit count required
might exceed that available on a single first-
level package.
Ω Further, there may be components that cannot
be readily integrated on first-level package,
such as capacitors, high power resistors,
inductors, etc
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 Packaging Hierarchy
Ω Several levels of packaging will be present.
Ω They are often referred to as a packaging
hierarchy.
Ω The number of levels within a hierarchy may
vary, depending on the degree of integration
and the totality of packaging needs

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 Packaging Hierarchy
Ω Package Hierarchy

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 Package Design Considerations
(Parameters)
Number of Terminals
Ω The total number of terminals at packaging
interfaces is a major cost factor.
Ω Signal interconnections and terminals constitute
the majority of conducting elements.
Ω Other conductors supply power and provide
ground or other reference voltages.

Ngeze, LV VLSI Circuits 18

 Package Design Considerations
(Parameters)
Electrical Design Considerations
Ω Electrical performance at the IC package level is of
great importance for microwave designs
Ω As a signal propagates through the package, it is
degraded due to reflections and line resistance.
Ω Control of the resistance and the inductance associated
with the power and ground distribution paths to combat
ground bounce and the simultaneous switching noise is
needed

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 Package Design Considerations
(Parameters)
Thermal Design Considerations
Ω Needed to keep the operating junction
temperature of a silicon chip low
Ω The package should provide a good medium for
heat transfer from junction to the ambient/heat
sink.
Ω The junction temperature should be kept below
150°C to ensure proper electrical performance
and to contain the propensity to fail

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 Package Design Considerations
(Parameters)
Reliability
Ω The package should have good
thermomechanical performance for better
reliability.
Testability
Ω Several tests are employed to assess the
reliability of the packages

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 IC Packages
Ω An IC package falls into two basic categories.
1. Single-layer technology
 the package is constructed around the IC chip on a
lead frame.
 the IC chip is first mechanically bonded to a lead
frame,
 It is then electrically interconnected with fine wires
from the chip bond pads to the corresponding lead-
frame fingers.
 The final package is then constructed around the
lead-frame subassembly

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 IC Packages
2. Multi-layer technology
 The IC chip is assembled into a prefabricated
package

Ω Two single-layer technologies are used in the

industry:
1. molded plastic and
2. glass-sealed pressed ceramic.

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 IC Packages
Plastic Packaging
Ω Plastic is a generic term for a host of man-made organic
polymers.
Ω Polymer materials are relatively porous structures,
which may allow absorption or transport of water
molecules and ions
Ceramic Packaging
Ω Pressed ceramic technology packages are used mainly
for economically encapsulating ICs and semiconductor
devices
Ω Silicon carbide (SiC), aluminum nitride, beryllia (BeO),
and alumina (Al2O3) are some of the ceramics used in
electronic packaging
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 Package Types
Ω IC packages have been developed over time to
meet the requirements of high speed and
density.
Ω These are classified as follows:

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 Package Types
1. Through Hole Packages
Ω Through-the-board hole mounting technology uses
precision holes drilled through the board and plated
with copper.
Ω This copper plating forms the connections between
separate layers.
Ω These layers consist of thin copper sheets stacked
together and insulated by epoxy fiberglass.
Ω There are no dedicated via structures to make
connections between wiring levels; through holes
serve that purpose.

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 Package Types
Ω Different types of through hole packages can be
further classified as:
(a) Dual-in-Line Packages (DIPs)
(b) Quad Flat Packages (QFPs)
(c) Pin Grid Arrays (PGA)

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 Package Types
(a) Dual-in-Line Packages (DIPs)
Ω A dual-in-line package is a rectangular package
with two rows of pins in its two sides.
Ω DIPs are the workhorse of the high-volume and
general-purpose logic products.

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 Package Types
(b) Quad Flat Packages (QFPs)
Ω DIP package has become up to 50 times larger than the
bare die size itself, thus defeating the objective of
shrinking the size of the integrated circuits.
Ω It provides pins all around.
Ω In QFPs, pins are provided on all four sides.
Ω Thin QFPs are developed to reduce the weight of the
package.

Ngeze, LV VLSI Circuits 29

 Package Types
(c) Pin Grid Arrays (PGA)
Ω A pin grid array has leads on its entire bottom surface
rather than only at its periphery.
Ω It offers a much larger pin count.
Ω It has cavity-up and cavity-down versions.
Ω High pin count and larger power dissipation capability of
PGAs make them attractive for different types of
packaging.

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 Package Types
2. Surface-Mounted Packages
ΩSurface mounting solves many of the shortcomings of
through-the-board mounting.
ΩA chip carrier is soldered to the pads on the surface of a
board without requiring any through holes.
ΩThe smaller component sizes, lack of through holes, and
the possibility of mounting chips on both sides of the PC
board improve the board density.
ΩTypes of surface-mount packages are available
a) Small-Outline Packages (SOPs)
b) Plastic-leaded Chip Carriers (PLCCs)
c) Leadless Ceramic Chip Carriers (LCCCs)

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 Package Types
(a) Small-Outline Packages (SOPs)
Ω The small-outline package has gull-wing shaped leads.
Ω It requires less pin spacing than through hole mounted
DIPs and PGAs.
Ω SOP packages usually have small lead counts and are
used for discrete, analog, and SSI/MSI logic parts.

Ngeze, LV VLSI Circuits 32

 Package Types
(b) Plastic-leaded Chip Carriers (PLCCs)
Ω PLCCs such as gull-wing and J-leaded chip carriers,
offer higher pin counts than SOP.
Ω J-leaded chip carriers pack denser and are more
suitable for automation than gull-wing leaded carriers
because their leads do not extend beyond the package.

Ngeze, LV VLSI Circuits 33

 Package Types
(c) Leadless Ceramic Chip Carriers (LCCCs)
Ω LCCCs take advantage of multilayer ceramic technology.
Ω The conductors are left exposed around the package
periphery to provide contacts for surface mounting.
Ω The ceramic substrate also has a high thermal
conductivity.

Ngeze, LV VLSI Circuits 34

 Package Types
3. Flip-Chip Packages
Ω The length of the electrical connections between the
chip and the substrate can be minimized by placing
solder bumps on the dice, flipping the chips over,
aligning them with the contacts pads on the substrate,
and reflowing the solder balls in a furnace to establish
the bonding between the chips and the package.
Ω This method provides electrical connections with minute
parasitic inductance and capacitance.
Ω Contact pads are distributed over the entire chip
surface.

Ngeze, LV VLSI Circuits 35

 Package Types
Ω This flipping
 saves silicon area,
 increases the maximum I/O and power/ground
terminals available with a given die size, and
 provides more efficiently routed signal and
power/ground interconnections on the chips.

Ngeze, LV VLSI Circuits 36

 Package Types
4. Chip Size Packages (CSPs)
ΩTo combine the advantages of both packaged
chip and bare chip in one solution, a variety of
CSPs have been developed.
ΩCSPs can be divided into two categories: the
fan-in type and the fan-out type.
1. Fan-in type CSPs are suitable for memory
applications that have relatively low pin counts.
2. The fan-out CSPs are used mainly for logic
applications: because of the die size to pin count
ratio, the solder bumps cannot be designed within
the chip area.
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 Package Types
Ω CSP Package

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 Package Types
5. Multi-Chip Modules (MCMs)
Ω Several chips are supported on a single
package.
Ω Most multi-chip packages are made of ceramic.
Ω By eliminating one level of packaging, the
inductance and capacitance of the electrical
connections among the dice are reduced.
Ω Usually, the dice are mounted on a multilayer
ceramic substrate via solder bumps, and the
ceramic substrate offers a dense
interconnection network
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Package Types

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