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Design and analysis of 3 stage ring oscillator based on MOS capacitance for
wireless applications

Conference Paper · February 2017

DOI: 10.1109/ECACE.2017.7912998

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 International Conference on Electrical, Computer and Communication Engineering (ECCE), February 16-18, 2017, Cox’s Bazar, Bangladesh

Design and Analysis of 3 Stage Ring Oscillator Based

on MOS Capacitance for Wireless Applications
Rafiul Islam, Ahmad Nafis Khan Suprotik, S. M. Zia Uddin & Md. Tawfiq Amin
Department of Electrical, Electronic and Communication Engineering
Military Institute of Science and Technology
Dhaka, Bangladesh
rafiul.islam.mist@gmail.com, nafisk15@gmail.com, smziaomi@gmail.com & tawfiqamin@gmail.com

Abstract— This paper comprises the study and performance
analysis of switched capacitor ring voltage controlled oscillator
(VCO) which uses the method of controlling capacitance to
regulate oscillation frequency. In this paper, three stage ring
oscillator is designed based on added MOS capacitor in the
output of each delay cell. 90 nm CMOS process technology has
been used in simulation with the supply voltage of 1.8V whereas
the variation of control voltage differs from 0V to 0.6V. A linear
tuning characteristic has been achieved ranging from 4.52 GHz
to 6.02 GHz in pursuit of wireless applications, specifically for
IEEE 802.11a standard. The circuit shows very stable output
waveform in different parameters with very low power
consumption of 0.295 mW. The figure of merit (FoM) is -155.5
dBc/Hz and the phase noise is very reasonable considering the
higher oscillation frequency of the circuit.
Keywords— Voltage-Controlled Oscillator (VCO), Ring VCO,
MOS Capacitance, Oscillation Frequency.
I. INTRODUCTION
The technological benediction carries out its rapid
processing by numerous wireless communication systems.
Wireless transmission is based on the high frequency signals
like radio frequency (RF) or microwave frequency whose
range is extended towards to GHz range and it has various
applicable areas like all types of radar, LANs etc. Achieving
the stability of wide range frequency with satisfactory energy
consumption is the main concern in most recent research
works [1].
In this sense at modern wireless communication field,
CMOS based voltage controlled Oscillator(VCO) is the most
captious and crucial element that can render performance in
such devices like PLL, ADC, RCC etc. [2], [3]. VCO is
offering the linear relationship between the variable control
voltage and tuning oscillation frequency which is the main
requirement of most applications [4].
Conventionally, Ring-VCO and LC-VCO are two most
used kinds in most of the Transceiver modules [5]. Both
VCOs have distinguished and comparable characteristic
parameters in chip design process. But if we bound to give
our concern on attaining higher frequency with suitable phase
noise, lower power dissipation and small chip area, ring VCO
has likely more efficiency than the LC-VCO especially in
nanometer based CMOS chip designing process [1], [4].
Besides Ring VCO occupies smaller chip area than LC-
VCO, the tuning frequency range is more than 50% in ring
VCO whereas LC-VCO has around 10% to 20% [5]. In case
of ring oscillator, the mainstream structure consists of number
of stages specifies the multiphase output in wide range
operating frequency. The oscillation frequency is determined
by the summation of individual delays and literally the
minimum stage-to-stage spacing in the conventional ring
oscillator must not be less than two inverter delay [6].
In this paper we describe the performance analysis of linear
3 stage switched capacitor ring oscillator in case of oscillation
frequency, phase noise with minimum power supply. The
whole paper has four sections which is organized in following
manner: Section II provides with the basic knowledge of
conventional ring VCO. In section III we describe the
architecture of mentioned ring VCO and the necessary
analysis of its characteristic operation in three subsections.
Section IV demonstrates the simulation result in various
manners with related explanation and the conclusion is
offered at section V.
II. CONVENTIONAL RING OSCILLATOR
Conventional ring oscillator is mainly the chain of odd
number of inverters in which output is connected to input as
feedback as shown in fig. 1. This oscillator creates phase shift
of 2ʌ and gain in each stage so that the Barkhausen criteria is

Fig. 1 Conventional Ring Oscillator

978-1-5090-5627-9/17/$31.00 ©2017 IEEE

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satisfied. The phase shift is ʌ/N in each stage, where N is the
number of stages [7]. The remaining phase shift is rendered
by dc inversion. This type of VCO can generate oscillation
frequency but no tuning range which is not expected as wide
tuning range is needed in modern digital communication
system. Therefore, this ring VCO is more sensitive to noise
(phase noise, supple sensitivity and common-mode-rejection)
than other kinds.
The oscillation frequency of ring VCO can be determined
by estimating the delay time ߬ of each inverter stage. If N
number of inverter stages are considered, then the oscillator
will take 2N߬ time to complete the total cycle [7]. So, the
oscillation frequency can be written as:
ଵ
݂௢௦௖ ൌ (1)
ଶேఛ
III. SWITCHED CAPACITOR RING OSCILLATOR
A. Circuit Description
The switched capacitor ring VCO is shown in fig. 2. The
modified VCO circuit presented here is a chain structure of
3 stage Ring VCO. As we know from the basic equation of
conventional ring VCO referred in equation (1), the less
number of stages can increase the oscillation frequency with
suitable power consumption [8]. Here every stage consists
of basic CMOS inverter whereas M1-M3 and M4-M6
denotes the MOS transistors having the W/L ratio of 1.15
and 2.17 respectively. The transconductance (Gm) of
PMOS and NOMS transistors of each inverter stage is kept
in almost similar margin. Three extra NMOS tubes are
added as driving transistors which are connected to the
output node at every stage. The input voltage of these
transistors remarked by M7-M9 is same and is set by
variable voltage ‘Vcon’
Fig. 2 Switched capacitor ring oscillator
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B. Controlling Capacitance
The linearity of VCO and the determination of operating
frequency range is ordained by the change of gate capacitance
with respect to the variable biasing voltage [9]. For agreeable
explanation regarding this phenomenon, we considered the C-
V characteristics which has been in fig. 3. In accumulation
region the capacitance is constant. When the Vcon is high
more specifically Ͳ ൏ …‘ ൏ ܸ௧௛ the depletion region occurs
and the value of the gate capacitance decreases as the width
(W) of the region grows correspondently until the inversion is
attained. The total capacitances can be derived in following
equations:
‫ܥ‬ௌ ൌ ߝ௢௫ ‫ܣ‬Ȁܺ௢௫ (2)
‫ܥ‬ௌ ൌ ߝௌ௜ ‫ܣ‬Ȁܹ (3)
ଶఌೄ೔ ‫׎‬ೞ
‫ݓ‬ൌට (4)
௤ேೌ
‫ܵܥכ ݔ݋ܥ‬
‫ܥ‬௅ Ԣ ൌ (5)
‫ ݔ݋ܥ‬൅‫ܵܥ‬
Whereas CS is defined as Semiconductor Capacitance.
This results in smaller delay according to the equation (5)
which leads to increase of the oscillation frequency linearly
with the variable control voltage until it reaches to the
threshold voltage (Vth). If …‘ ൐ ܸ௧௛ the operating mode
converts to the inversion region where the linear
characteristics of VCO will be disrupted [7].
B. Delay Estimation
An extra NMOS is added at the output terminal of each
Fig. 3 C-V characteristics of MOS transistor
inverter stage as shown in fig. 2. This NMOS is implemented
as MOS capacitor in the circuit. As the MOS transistors at
each stage are assumed as switches, it can be replaced by a
resistance (1/Gm) which can be shown by the fig. 4. If CL'
equates the capacitance of added NMOS and CL is the node IV. SIMULATION RESULTS
parasitic capacitance, then the total output node capacitance of
the oscillator at each stage will be (CL||୐ᇱ ). So, the delay per The 3 stage ring VCO is designed in 90 nm CMOS process
stage can be approximated as and all the simulations have been completed Cadence 6.1
environment. The delay cell for the 3 stage ring VCO is the
conventional CMOS inverter where PMOS and NMOS
ሺ஼ಽ ା஼ಽᇲ ሻ switching transistors are in series. To generate the same
߬ൌ (6) transconductance, the size of the switching transistors is
ீ௠
carefully selected.
Fig. 6 shows the transient analysis of the design at the center
frequency. The control voltage used for this simulation is
0.3V and the oscillation frequency is 5 GHz. The output
voltage swing is almost constant (1.55 V) for different control

Fig. 4 Ring VCO as Variable Capacitor

Delay approximation is illustrated at fig. 5. The oscillation

frequency in terms of variable capacitor is

ଵ ீ௠
݂௢௦௖ ൌ ൌ (7)
ଶேఛ ଶேሺ஼ಽ ା஼ಽᇲ ሻ

As frequency of the oscillation depends on mainly three

parameters: parasitic capacitance (CL), transconductance (Gm)
and variable capacitor (CL'). Since, tranconductance and
parasitic capacitance are device parameter and constant, the
frequency of the ring oscillator depends on regulating the
variable capacitance.
Fig. 6 Transient Analysis

voltages with the supply of 1.8V.

Fig. 7 shows the simulation of tuning characteristics of the
circuit where control voltage is denoted by Vcon. The circuit

Fig. 5 Delay estimation Fig. 7 Frequency Variation for Vcon

725
has kept linearity between control voltage and frequency of
oscillation. Output frequency increases as the Vcon is
increased. The frequency range from 4.52GHz to 6.02GHz
can be achieved by regulating the control voltage from 0 V to
0.6 V.
Table 1 summarizes the simulated performances for the
designed switched capacitor based ring VCO and compares
with other ring voltage controlled oscillator. The power
consumption of the circuit is extremely low (0.295 mW)
which is comparatively better than others. But according to
Leeson’s equation the phase noise is lower than others as we
know phase noise changes inversely with the power
consumption. A parameter called figure of merit (FoM) is
introduced to compare with others entirely [2].

௣௢௪௘௥ವ಴ ఠ
‫ ܯܱܨ‬ൌ ‫ܮ‬ሺο߱ሻ ൅ ͳͲ ‫ ‰‘Ž כ‬ቀ ቁ െ ʹͲ ‫‰‘Ž כ‬ሺ బ ሻ (8)
ଵ௠ௐ οఠ

Here, ߱଴ refers to the oscillation frequency and ‫ܮ‬ሺο߱ሻ

designates the phase noise at ο߱ offset frequency. We know
that in case of FoM the increase is a factor of 20% per
channel length decrease of 15 nm. Here, in our work FOM is
-155.5 dBc/Hz which is greater than 2.74% - 4.29% than
other two references [2] and [10] that indicates the decrease
of per channel length up to 2.06 - 3.21 nm.

V. CONCLUSIONS
The main focus of our paper has been pointed out in the
analysis of the performance of ring VCO by designing a
convenient structure based on MOS transistor capacitance for
Fig. 8 Phase Noise both schematic and simulations. The evaluations are based on
the several parameters like power, phase noise and operating
frequency range. The obtained results are analyzed and used to
Fig. 8 represents the phase noise of the design for different compare with two other relevant references having nearly
control voltage. The phase noise for frequency 5 GHz is - similar design structure. The comparison shows the better
76.27 dBc/Hz at 1 MHz offset and -99.83 dBc/Hz at 10 MHz efficiency of applied circuit in every qualitative criterion. The
offset. paper might be practicable in future study of ring VCO design
for further consistent improvement especially in the field of
Table 1 Comparison of Performance for Different wireless communication system like unlicensed national
Parameter information infrastructure (U-NII) bands which operate in the
5 – 6 GHz frequency range.
3 stage
Performance 3 stage 3 stage 4 stage
[This
parameters [2] [9] [10]
Work]
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