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PLACEMENT IN
PHYSICAL
DESIGN
(ASHISH KUMAR SINGH,PRIYANKA BRAHMA,SWEETY KUMARI)
M.TECH –VLSI
NIT SILCHAR,ASSAM
2
AGENDA
WHAT IS PLACEMENT AND ITS TYPES
BACK END PROCESS
PLACEMENT PROBLEM FORMULATION
ALGORITHMS
SIMULATED BASED PLACEMENT
PARTITIONING BASED PLACEMENT
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2. FLOORPLANNING
GOAL: CALCULATE THE SIZE OF BLOCKS AND ASSIGN THEM
LOCATIONS.
OBJECTIVE: KEEP HIGHLY CONNECTED BLOCKS
PHYSICALLY CLOSE TO EACH OTHER.
3. Placement 13
Goal: assign the interconnect areas and the locations
of all the logic cells within the flexible block
Objective: minimise the ASIC area and the
interconnects
4. Global routing
Goal: determine the location of all the interconnects
Objective: minimise the total interconnect area.
5. Detailed routing
Goal: completely route all the interconnects on the
chip
Objective: minimise the total interconnect length
used
14
OUTPUT:
The cells are placed to produce a routable chip that meets timing
PLACEMENT ALGORITHMS
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•TOTAL AREA
A TOP-DOWN METHOD:
MIN-CUT PARTITIONING AND PLACEMENT (BISECT THE CIRCUIT
RECURSIVELY)
MIN-CUT PLACEMENT METHOD:
1. CUT PLACEMENT AREA INTO TWO PIECES
2. SWAP LOGIC CELLS TO MINIMIZE CUT COST
3.REPEAT PROCESS FROM STEP 1, CUTTING SMALLER
PIECES UNTIL ALL LOGIC CELLS ARE PLACED
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26
A bottom-up method: cluster growth (select
cells with strongest connections one by one)
SIMULATED ANNEALING PLACEMENT 27
CLASSIFICATION OF ALGORITHM
Annealing in metals
Heat the solid state metal to a high temperature
Cool it down very slowly according to a specific
schedule.
If the heating temperature is sufficiently high to
ensure random state and the cooling process is
slow enough to ensure thermal equilibrium, then
the atoms will place themselves in a pattern that
corresponds to the global energy minimum of a
perfect crystal.
Simulated Annealing and 31
VLSI Placement:
Arrangement of atoms = a new configuration of cells (
a new solution)
Total configurations = Total solution set
Perturbation = small random movement of cells to get
new configuration (possible solution).
Energy = Cost function
Temperature = control parameter
Cooling schedule = starting temperature and a rule
how to decrease the temperate or how to cool
Steps- 32
Step 1: Initialize – Start with a random initial placement.
Initialize a very high “temperature”.
Algorithm SA_Placement
begin
T = initial_temperature;
P = initial_placement;
while ( T > final_temperature) do
while (no_of_trials_at_each_temp not yet completed) do
new_P = PERTURB (P);
ΔC = COST (new_P) – COST (P);
if (ΔC < 0) then
P = new_P;
else if (random(0,1) > exp(-ΔC/T)) then
P = new_P;
T = SCHEDULE (T); /** Decrease temperature **/
end
Parameters 34
INIT-TEMP = 4000000 C;
INIT-PLACEMENT = Random;
PERTURB(place)
1. Displacement of a block to a new
position.
2. Interchange blocks.
3. Orientation change for a block.
SCHEDULE.
Timber Wolf 35
One of the most successful placement algorithms.
Developed by Sechen and Sangiovanni-Vincentelli.
Parameters used:
– Initial_temperature = 4,000,000 C
– Final_temperature = 0.1 C
– SCHEDULE(T) = α(T) x T
• α(T) specifies the cooling rate which depends on the
current temperature.
• α(T) is 0.8 when the cooling process just starts.
• α(T) is 0.95 in the medium range of temperature.
• α(T) is 0.8 again when temperature is low.
36
Simulated Evolution / Genetic
Algorithm
The algorithm starts with an initial set of placement
configurations.
Called the population.
The process is iterative, where each iteration is called a
generation.
The individuals of a population are evaluated to measure
their goodness.
To move from one generation to the next, three genetic
operators are used:
Crossover
Mutation
Selection
Breuer’s Algorithm
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2. Quadrature Placement
3. Bisection Placement
Algorithm Cluster_Growth
begin
B = set of blocks to be placed;
Select a seed block S from B;
Place S in the layout;
B = B – S;
while (B ≠ φ) do
begin
Select a block X from B;
Place X in the layout;
B = B – X;
end;
end
Performance Driven 44
Placement
The delay at chip level plays an important role in
determining the performance of the chip.
- Depends on interconnecting wires.
As the blocks in a circuit becomes smaller and
smaller:
-The size of the chip decreases.
-Interconnection delay becomes a major issue in
highperformance circuits.
Placement algorithms for high-performance chips:
-Allow routing of nets within timing constraints.
45
Cont-