Microprocessor Systems and

Interfacing
EEE 342
Microprocessor 8088

◼ Outline
❑ Memory Interfacing with 8086

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 ◼ CLO/PLO Mapping
◼ CLO 2
❑ To integrate the memory, timer, I/O and PPI
with microprocessor using address decoding
techniques. (PLO3-C5)
◼ PLO 3
Design/Development of Solutions: An ability
to design solutions for complex engineering
problems and design systems, components or
processes that meet specified needs with
appropriate consideration for public health and
safety, cultural, societal, and environmental
considerations.

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Memory Interfacing

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 Memory organization
1M bytes memory using 2 512K byte chips

Odd boundary
Address requires
2 cycles

BHE – bank high enable

 Hardware organization
◼ In hardware, the 1M bytes memory is implemented
as two independent 512K-byte banks
◼ Low (even) bank, and the high (odd) bank
◼ Data from low bank use data bus 0-7
◼ Data from high bank use data bus 8-15
◼ Signal A0 enables the low bank
◼ Signal /BHE enables the high bank
◼ /BHE is active low
◼ How many address lines are required in order to
access 512K locations? (Ans. 19)
 Memory organization
Only A1 to A19 are used to drive the memory !!!

High bank Low bank

Memory Interfacing with 8086 CPU

◼ BHE (Byte High Enable or Bank High Enable)

◼ 𝐼𝑂/𝑀
◼ Odd and Even bytes
◼ Role of A0
◼ 16-bit data bus
◼ 20-bit address bus

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Memory Interfacing

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Memory Interfacing

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Separate Bank Selection (Example)

◼ Separate decoders are required for each bank

◼ Example describes 1MB SRAM interfacing
with 8086 CPU
◼ Memory map for total memory will be
00000H to FFFFFH

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12
Separate Write Strobe Approach

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Memory Interfacing

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