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A CMOS 79GHz PMCW Radar SoC

Jan Craninckx

PUBLIC
Abstract
▪ High-performance, small form factor millimeter-wave radar systems are
key enablers for the new smart society. Application for automotive
driver assistance and even autonomous cars is obvious, but also many
other systems like vital signs monitoring, gesture recognition, self-guided
drones, etc are envisioned.
▪ The research presented in this talk investigates the use of nanoscale
CMOS technology for 79GHz radar systems, which will be a key
enabler to open up this market for cost-effective high-volume
production, and allows integration of large digital processing in the same
System-on-Chip. A new concept of phase-modulated radar detection is
also introduced that blends perfectly with the integration capabilities of
CMOS.
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Why mmWave radars?
mmWave Sensors are Extremely Robust
noise &
vibration

fog
snow & rain smoke

dust

lighting dirt

4
heat
mmWave Sensors are Fully Sealed and Invisibly Mounted

discreet monitoring

perfect aesthetics

privacy
5
fixed
Radar
evolution
mobile

yesterday
automotive today

79 GHz radar SoC module


tomorrow

140 GHz antenna-on-chip systems?


6
Radar resolution (smaller is better)
Range
(improves with wider bandwidth)
Speed
(improves with
higher carrier) “voxel”

Angle
(improves with larger antenna)

24 GHz 77 GHz 79 GHz 140 GHz

7
10+ radars per car
▪ High-resolution, 360 degree radar coverage
Medium Range Radar
(MRR) up to 80m

Long Range Radar


Short Range Radar (LRR) up to 250m
(SRR) up to 30m
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79 GHz PMCW Radar System
New Paradigm: mmWave CMOS Radar-on-Chip

high resolution – low power – low cost – small size

leveraging standard foundry technology

10
Waveform Possibilities
Fast chirp
TX PA
VCO/PLL

FMCW Range-
Doppler
Fast-time Slow-time map
HPF LPF ADC
FFT FFT
RX LNA In-phase
(spillover
mixer (RMAX limit) Range Doppler
cancellation, processing processing
RMIN limit)

Bi-phase
mod Binary sequence
TX PA

PMCW LO Range-
Doppler
Correlator Slow-time map
LPF ADC
I,Q bank FFT
RX LNA Quadrature
mixer Range Doppler
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processing processing
High Level Comparison: PMCW vs FMCW
PMCW FMCW
Ambiguity function, sidelobes +
Sensitivity to phase noise, flicker noise +
ADC resolution +
ADC speed / IF bandwidth +++
PSD +
Sensitivity to interference +/-
TX orthogonality for MIMO +
Communications capability ++
Industrial acceptance +++
easier market entry / limited IP and patents ++

12
PMCW Radar Operating Principle

2 Gbps
Tchip TX
Distance D
m Tchip 79 GHz LO

RX Target

0 ∫
0 ∫
0 ∫
0 ∫ Target at
G*m ∫ D = (4 * Tchip * C) / 2
0 ∫ C = speed of light in air
0 ∫ G = Path Loss

m Correlations (multiplication and integration)


13
... and TX-to-RX Spillover

2 Gbps
Tchip TX
m Tchip 79 GHz LO
TX-to-RX
spillover
RX Target

Spillover produces a large


S*m ∫ response for 0 delay
0 ∫
0 ∫
0 ∫ Target at
G*m ∫ D = (4 * Tchip * C) / 2
0 ∫ C = speed of light in air
0 ∫ G = Path Loss

m Correlations (multiplication and integration)


14
PMCW Radar System
Radar IC
2R
Range Bins T
c

Correlations with delayed


Time / Doppler version of the PN sequence 
Determine the delay T  the
position R

Accumulations
 improve SNR
FFTs
 determine the frequency
shift of every range bin  the
speed of the object found on
that range bin (Doppler)
Also improves SNR

15
System design, Implementation and Verification

System
design

Validation & IC
demonstration design

Module
& antennas

16
System design
Matlab chain

17
PMCW Radar-on-Chip: SISO Block Diagram
antennas
RF TC  Range resolution
LC  Ambiguous range
M  Ambiguous speed
N  Speed resolution

PRN code
High-speed digital front-end Reconfigurable digital baseband

ADCs
S

Lc parallel paths Lc parallel Lc parallel Lc parallel


CFAR
detection
-
Integrate Lc Accumulate
ADC N-point DFT DoA
pulses M pulses
estimation
-
PRN code Tracking

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antennas
analog front-end
MIMO Block Diagram
PRN code
...

PRN code
High-speed digital front-end Reconfigurable digital baseband
ADCs
S

Lc parallel paths Lc parallel Lc parallel Lc parallel Lc parallel

Integrate Lc Accumulate
ADC N-point DFT
pulses M pulses

PRN code
Peak
...

Nrx*Ntx virtual extraction

...
Lc parallel paths Lc parallel MIMO antennas
MIMO -
Beam-
array DoA
forming
synthesis estimation
Integrate Lc Accumulate -
ADC Lc parallel
pulses M pulses Tracking

PRN code
N-point DFT

19
IC – Module - Platform
IC module platform

integrated circuit carrier containing antennas carrier containing module, components


containing the core and mounted ICs, and connectors, complemented with
functionality similar form factor to product computation component (PC, FPGA or
similar) for demonstration
20
SOC Implementation
PHADAR 2x2 SoC

TRX_CLKO

TRX_SYNC
NOC_CLK
NOC_RST

VDD18dig
TRX1_DO

TRX2_DO

TRX4_DO

TRX3_DO

VSS18dig
NOC_CE
TRX_DA
NOC_DI
NoC MS

▪ Integrated mmWave PLL, TRX, ADCs, digital front end


NOC_DO /
NOC_TE PLL_LOCK /
PLL_Fdiv
DIG DIG

NoC SL
VSSRX1dig VSSRX2dig

NoC SL
VDDRX1dig TX
TX TX
TX VDDRX2dig

PLL 2 TX VDDTX1

TX1P
VDDTX2

TX2P

TX1M ADC ADC TX2M

VSSTX1 PLL VSSTX2


RF

NoC SL
NoC SL
VDDRX1 VDDRX2
Δ RX RX RX RX
MIMO PRF=1/(Tc*Lc) VSSRX1 VSSRX2
VGA ADC Prog.
PN-LEAK ∫ Fc=1/Tc=2Gbps
CANC Buffer VDDPLL VDDLO
1 00 1 111

PRN Code VSSPLL VSSLO


Prog. NoC SL
Delay-Line

2 RX
2 GHz CK

VDDBB18
VSSBB18

RX2IP

RX2IM
PLL_Fref
VDDBB18

VSSBB18
RX1QP

RX1QM

RX2QP
RX2QM
RX1IM

RX1IP
PA
ILO Int-N ILO
LNA IQ MX Modulator
(x5) PLL (x5)
LO-PLL PA

2 GHz CK
Prog.
PRN Code
Delay-Line
1 00 1 111
MIMO Prog.
PN-LEAK ∫ VGA ADC
Fc=1/Tc=2Gbps
Buffer
CANC PRF=1/(Tc*Lc)

Δ

2 I/Q 2 Digital Correlator/Accumulator


ADC 22
LO Architecture: 5x ILO
▪ A 5th Subharmonic, Inverter-Based Injection Locked Oscillator
▪ Avoid frequency distribution at 79GHz across the IC
▪ Frequency multiplication
▪ Harmonic based multipliers
▪ Wide functional range, but less damping at ω0/N
▪ Injection locked oscillators
▪ Oscillator must be locked
▪ 3X or 5X?
▪ 3X locks easier, but PLL @26.333 GHz
▪ 5X is only 15.8GHz PLL and frequency distribution
▪ Needs lots of 5th order distortion generation
▪ Inverters!

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Inverter Based ILO for 79GHz
VDD
VDD
A=450mV

Tuned amplifier
iout∙e jΘ
A@ω0 iout∙ejΘ
A@ω0 @5ω0 A/3@3ω0 @5ω0
M1 A/5@5ω0 M1
ω0=15.8GHz * 2π
Vb .. Vb
..
Classical approach Inv based approach

Input iout(mA) Θ(°)


• A>1V for iout=0.82mA, ω0 0.31 148.6
while VDD in 28nm is 0.9V ω0,3ω0 0.58 148.7

• Also reliability is worse ω0,3ω0,5ω0 0.82 143.8


Up to 15ω0 0.91 145.1
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Implementation
▪ Inverter chain ▪ Oscillator core

20K Qvar=8.5~20
Qind=15

2 2 3 3 VCO+ VCO-

[3:0]
VDC VDC2 VDC
12um 16um
Lmos=35nm
Vinj+ Vinj-
M1 M2
9um 13.5um
M1:M2=5:1

▪ WP/WN ratio is adjusted to have ▪ VDC2 used to enhance self


50-50 duty cycle. resonance
Slice 25
Measurements 10GHz Locking Tange
-1

8GHz Free-running Tuning Range -2

84

Input Power (dBm)


-3
Oscillation Frequency (GHz)

82 -4

80 79 ± 2GHz Locked Phase Noise-5


-60
-6
SMR40@15.8GHz
78 VDC2=0.55 V
ILO@79GHz
-70 VDC2=0 V
-7
70 72 74 76 78 80 82 84
76 -80 Frequency (GHz)
Phase Noise (dBc/Hz)

-90
74
0 5 10 -100 15
Varactor bits
-110 14dB±1dB

-120

-130

-140 4 6 8
10 10 10
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Offset Frequency (Hz)
PLL and LO Distribution
Tx_ILO Tx_ILO TX
Cartesian combiner
In-Phase
ILOs

Combiner Combiner
I+ I- Q+ Q-
PPF for
Ibias,I Ibias,Q quadrature
phase shifters
2-stage PPF

15.8 GHz distribution


Subsamplig
15.8GHz VCO Poly-phase
PLL
SS- filters
Gm
PD generate
25MHz quadrature
PFD/C LP
P F

RX
Div/N
(79)
Div/8 QILOs
CP-PLL To Dig/ADC VCO @
Rx_QILO Integer-N PLL 27
15.8 GHz Rx_QILO
Antenna Path Details
Analog BB and
ADCs
TX-to-RX Spillover
Transmitter side-lobe
cancellation Digital Core
suppression

RX Front-End Transmitter
Sub-harmonic Injection Locked Oscillators
multiply the PLL frequency by 5
28
TX architecture
CMOS IL-VCO Modulator CMOS28
15.8GHz

BUF (x5)
PA

Harmonic Rejection &


BPSK frequency side-lobes
Pulse shaping
at least -17dBc needed!

PRN Code Fc=1/Tc=2Gbps • No LO quadrature


1 00 1 11 1
PRF=1/(Tc*Lc) • Transmits @ Psat
• Low side-lobes

29
79GHz Phase-Modulator
Linear BB Linear LO
X X
Non-linear LO Non-linear BB
1 0 0 1 0 1 .. Lc 79GHz
LO

PRN Code
generator PRN Code
generator
79GHz
79GHz
LO
LO 1 0 0 1 0 1 .. Lc
PRN Code 77 79 81 GHz
generator

1 0 0 1 0 1 .. Lc
77 79 81 GHz
• Lower 79GHz swing
• More power efficient
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TX Sidelobe Reduction by Harmonic Rejection

1
79GHz
LO Σ
1

Tc=1/Fc

1 0 0 1 0 1 .. Lc
Delay
Tc/3 Δ
77 79 81 GHz
PRN Code
generator Most effective side-lobe
rejection @ lowest cost

31
79GHz Modulator and PA: Schematic Detail
HR3 0
MMX
Mixer 3-stage PA
Gain MPA
180 Tuner Balun
LOp VSMX CnPA
VGPA
VDD 240 VDD
LOm CnPA
BBin Prog. 60 VDD MPA
Delay-Line
Prog. Buffer

BBin

60°
180°
240°
32
Receiver Implementation
Output To IO
I and Q
Buffer Pads
VDD
Gilbert cell Mixer
mixer
ADC
2dB Gain VGA
Buffer

LO- LO+ LO- 7bits


ADCs

VGA stage
k ≈ 3 → 10.5 dB
VDD
VDD in 7 steps
VDD VB ADC driver
2-stage LNA ≈-2dB gain
18dB Gain VBIAS RL
k Vout Vin
VDD
Vin Vout
RS
VBIAS
k
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Vin
RX Spillover Cancellation
BB
BB Weighted copy of BB injected at the
VDD mixer outputs to cancel the spillover

Mix
OUT Mixer BB BB BB BB
C
R
WM
WP
LO- LO+ LO-
R C2 C2
BB
C

Correlation
VDD (multiplication with the TX sequence and integration)
LNA OUT

In steady state the mixer output is uncorrelated with the TX BB sequence:


the spillover is cancelled!
Digital Core Block Diagram
▪ Digital core generates the sequence and performs correlation and
accumulation of the ADC samples
Correlator (Lc) Accumulator (M)

18 29 Out
D<6:0> 7 Data Out
interface
(from ADC) 1+1
CK CK/4

CK/<prog>

I and Q
1
To TX m’[k] CK gen Clock Out
TRX Sync
Data Available
CK (1.975 GHz)

35
Other antenna path
IC Realization
▪ 28nm CMOS
▪ Die size 3 x 2.63mm
▪ Supply 0.9V/1.8V
▪ Flip chip assembly

36
IC Floorplan
▪ 28nm CMOS
▪ Die size 3 x 2.63mm DIG. DIG.
CORE CORE
▪ Supply 0.9V/1.8V TX TX

▪ Flip chip assembly SH - ILOs


LO
Distr. SH - ILOs

ADC ADC
RX BB PLL RX BB

RX FE RX FE

37
IC Photograph
▪ 28nm CMOS
▪ Die size 3 x 2.63mm
▪ Supply 0.9V/1.8V
▪ Flip chip assembly

38
PLL Measurements
▪ 25 MHz reference
▪ 16GHz VCO
▪ VCO only Phase Noise
-116 dBc/Hz @ 10 MHz
▪ 2GHz VCO tuning range
corresponding to 78 to
88 GHz at TX output
▪ 79GHz ILO
▪ -107dBc/Hz @ 10 MHz

CP-PLL = Charge Pump PLL SS-PLL = Sub-Sampling PLL


Measured at 79 GHz with R&S FS-Z90 and FSU and Agilent E5052 Signal Analyzer
39
Transmitter Measurements
RBW 3 MHz Marker 1 [T1 ]
VBW 10 MHz -48.05 dBm
Ref -17 dBm EXTM IX E SWT 60 ms 79.839743590 GHz

▪ Pout > 10dBm


-20

1 AP
-30
4 GHz BW
VIEW

▪ 4 GHz BW
-40
2 AP
1
CLRWR

-50

-60

EXT
-70
3DB
BPSK
-80

-90
SideLobe Supp
-100

-110

Center 80 GHz 1 GHz/ Span 10 GHz

Measured with SAGE E band WR12 horn antenna, R&S FS-Z90 and FSU
Date: 15.DEC.2015 15:19:49

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Receiver Measurements

▪ NF < 12dB @ 1 GHz


▪ Including module input
transition

▪ More than 30dB gain


control in VGA
▪ BW > 1 GHz

Measured with NOISE COM 5112 and R&S FSU on a dedicated module with GSG pads instead of antennas
Base Band Analog output before the ADC measured

41
Indoor Antenna Module and Evaluation Board
2 dies on the
back of the
module

Antennas on the
front

Panasonic MegTron6® 42
PMCW Demonstrator
Matlab
framework
for data analysis
Radar module (2 chips):
• 4 TX antennas in azimuth
• 4 RX antennas in elevation
• MIMO configuration results in 2x2 and 4x4 array
• Targets can be localized in both azimuth and elevation

FPGA/ARM core platform for data capture and analysis


43
Radar Measurements
3 targets in an anechoic
RCS = 20dBs environment at different
distance, azimuth and
elevation

RCS = 15dBsm

RCS = 10dBsm

Radar board with antenna facing the


targets

Lc = 511 (m-Seq), M = 232


44
Range & Speed Measurements

45
MIMO 4x4 Measurements

Angle of Arrival:

46
Conclusions
▪ CMOS Radar SoCs area key building block for next-generation (self-
driving) cars
▪ And smart homes, buildings, things, etc.
▪ PMCW radar system is a feasible alternative for current FMCW
architectures
▪ Major advantage for large-scale radar imagers
▪ IMEC PMCW radar SoCs prototypes show functionality
▪ And are used by partner companies in various application experiments
▪ The future is still to come; we haven’t seen the last innovation in radars
yet ☺

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