03Ch08 Diffpair PartA PDF

1
Chapter 8
Differential
and
Multistage
Amplifiers
ECE 3120 Microelectronics II Dr. Suketu Naik

2
Operational Amplifier Circuit Components
1. Ch 7: Current Mirrors and Biasing

2. Ch 9: Frequency Response
3. Ch 8: Active-Loaded Differential Pair
4. Ch 10: Feedback
5. Ch 11: Output Stages

3
Active-Loaded Differential Pair
Two Stage
Op Amp
(MOSFET)

4
Learning Objectives
1) MOS and the bipolar differential amplifiers: how

they reject common-mode noise or interference and
amplify differential signals
2) The analysis and design of MOS and BJT differential

amplifiers: utilizing passive resistive loads, current-
source loads, and cascodes
3) The structure, analysis, and design of amplifiers

composed of two or more stages in cascade

5
Why Differential?
0) What is a differential signal?
1) Differential circuits are less sensitive to noise and
interference
2) Differential configuration enables biasing the amplifier and
coupling of amplifier stages without bypass and coupling
capacitors
3) Useful in IC design because of good matching between the
transistors

6
MOS Differential Pair

8.1. The MOS Differential Pair 7
Differential Pair
 Two matched transistors
(Q1 and Q2) joined and
biased by a constant current
source I
 FETs should not enter

triode region

8
Input Common Mode Range

9
8.1.1. Operation with a Common-Mode Input Voltage
 Suppose that two gate
terminals are joined
together and connected to
a common-mode voltage
(VCM)
 vG1 = vG2 = VCM
 Q1 and Q2 are matched
 Current I will divide

equally between the two
transistors.
 ID1 = ID2 = I/2,
 VS = VCM – VGS; where
VGS is the gate-to-
source voltage.

10
8.1.1. Operation with a Common-Mode Input Voltage
 Equations (8.2) through (8.8)
describe this circuit (channel- (8.2) I  1 kn W VGS  Vt 2
length modulation is neglected) 2 2 L
 Note the range (max and min) (8.3) VOV  VGS  Vt
of input common-mode voltage I 1 W 2
(VCM): beyond this range the (8.4)  kn VOV
2 2 L
diff pair leaves saturation
I W
(8.5) VOV 
kn L
I
(8.6) vD1  vD2  VDD  RD
2
I
(8.7) max VCM   Vt  VDD  RD
2
(8.8) min VCM   VSS  VCS  Vt  VOV
11
8.1.2. Operation with a Differential Input Voltage
 vid is applied to Q1 and Q2
is grounded:
 vid = vGS1 – vGS2 > 0
 iD1 > iD2
 The opposite applies if Q1

is grounded
 The differential pair

responds to a difference-
mode or differential
input signals.
 The diff pair provides

corresponding
differential output signal
between the two drains

12
Differential Input Voltage

13
8.1.2. Operation with a Differential Input Voltage
 Two input terminals
connected to a differntial
1 W 
(8.9) I   kn   vGS 1  Vt 
2
signal vid
2 L 
 Bias current I of a perfectly
symmetrical differential pair (8.9) vGS 1  Vt  2I / kn W / L 
divides equally (8.9) vGS 1  Vt  2VOV
 To steer the current (8.10) max  vid   VGS 1  v S
completely to one side of the
pair, a difference input voltage (8.10) max  vid   2VOV
vid of at least √2VOV is needed.

14
Large Signal Operation

15
8.1.3 Large-Signal Operation
 Objective: derive
expressions for drain
current iD1 and iD2 in
terms of differential
signal vid = vG1 – vG2
 Assumptions:
 Perfectly matched
transistors
 Channel-length
modulation is
neglected
 Load independence
is present
 Saturation region
16
1 W
(8.11) iD1  kn  vGS 1  Vt 

2
 Step #1: Expression drain 2 L

currents for Q1 and Q2. 1 W
(8.12) iD 2  kn  vGS 2  Vt 

2
 Step #2: Take the square roots 2 L

of both sides of both (8.11) 
and (8.12)
1 W
 Step #3: Subtract (8.14) from (8.13) iD1  kn  vGS 1  Vt 
2 L
(8.15) and perform appropriate
1 W
substitution. (8.14) iD2  kn  vGS 2  Vt 
 Step #4: Note the constant- 2 L
current bias constraint. 
(8.15) vGS 1  vGS 2  vG 1  vG 2  vid

17
 Step #5: Simplify
(8.15). (8.17) iD1  iD 2  I
 Step #6: Incorporate 
the constant-current 1 W 2
bias. (8.17) 2 iD1 iD 2  I  kn vid
2 L
 Step #7: Solve (8.16) 
and (8.17) for the two 2
unknowns – iD1 and iD2. I  I   vid   vid /2 
(8.23) iD1      1   
2  VOV  2   VOV 
2
I  I   vid   vid /2 
(8.24) iD2     1   
2  VOV   2 V
 OV 

18
 Transfer characteristics of (8.23) small-signal approximation
and (8.24) are nonlinear. I  I  vid

(8.25) iD1    
 Linear amplification is desirable 2  OV  2
V
and vid will be as small as possible. I  I  vid
(8.26) iD2    
 For a given value of VOV, the only 2  OV  2
V
option is to keep vid/2 much  I  vid
(8.27) id   
smaller than VOV.  VOV  2

19
Figure 8.7: The linear range of operation of the MOS differential pair can be extended
by operating the transistor at a higher value of VOV .
 VOV increases (smaller W/L): Gain will decrease, Linearity will increase
 VOV decreases (larger W/L): Gain will increase, Linearity will decrease
 Can increase the bias current to increase gm and gain

20
Small-signal Operation

21
8.2 Small-Signal Operation of the MOS Differential Pair
Virtual ground at the source

VCM = bias voltage at the gate
- Elimintates need for large vid = differential small signal
bypass capacitor

22
8.2.1 Differential Gain
1
(8.28) vG1  VCM  vid
2
 For MOS pair, each device 1
(8.29) vG 2  VCM  vid
operates with drain current 2
I/2 and corresponding 
overdrive voltage (VOV). 2ID 2(I /2) I
(8.30) gm   
 gm = I/VOV VOV VOV VOV

 ro = |VA|/(I/2).
vid
(8.31) vo1  gm RD
2
v
(8.32) vo2  gm id RD
2

vod
(8.35) Ad   gm RD
vid
23
8.2.1 Differential Gain
 vi1 = VCM + vid/2 and vi2 =
VCM – vid/2 causes a virtual
signal ground to appear on
the common-source
(common-emitter)
connection
 Current in Q1 increases by
gmvid/2 and the current in
Q2 decreases by gmvid/2
 Voltage amplitudes of
gm(RD||ro)vid/2 develop at the
two drains

24
8.2.2. The Differential Half-Circuit
 Figure 8.9 (right): The

equivalent differential half-
circuit of the differential
amplifier of Figure 8.8
 Here Q1 is biased at I/2 and

is operating at VOV
 This circuit may be used to

determine the differential
voltage gain of the
differential amplifier Ad =
vod/vid.
25
8.2.3 The Differential Amplifier with Current-Source Loads
 To obtain higher gain, the passive resistances (RD) can be
replaced with current sources.
 Ad = gm1(ro1||ro3)
Figure 8.11: (a) Differential amplifier

with current-source loads formed by
Q3 and Q4. (b) Differential half-circuit
of the amplifier in (a).
26
8.2.4 Cascode Differential Amplifier
 Gain can be
increased via
cascode
configuration –
discussed in Section
7.3
 Ad = gm1(Ron||Rop)
 Ron = (gm3ro3)ro1
 Rop = (gm5ro5)ro7
Figure 8.12: (a) Cascode differential

amplifier; and (b) its differential half
circuit.
27
Common Mode Rejection Ratio (CMRR)

8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR) 28
a) vin = VCM (DC common-mode signal) + vicm (common-mode noise

or interference)
b) current source with fininte output resistance RSS

c) T model without ro
d) common-mode half circuit

i
(8.41) vicm   2iRSS
gm

vicm
 Equation (8.43) describes (8.42) i 
1/ gm  2RSS
effect of common-mode
signal (vicm) on vo1 and 
vo2. RD
(8.43) vo1  vo2   vicm
1/ gm  2RSS

vicm RD
(8.44) vo1  vo2  
2RSS

(8.45) vod  vo2  vo1  0
 When the output is taken single- RD

ended, magnitude of common- (8.46) v o1   vicm
2RSS
mode gain is defined in (8.46) and RD 's are
(8.47) mismatched
RD  RD
(8.47) vo2   vicm
 Taking the output differentially 2RSS
results in the perfectly matched
case, in zero A (infinite CMRR)                      
cm
RD
(8.48) vod  vo2  vo1 
vicm
 Mismatches between the drain 2RSS
resistances make Acm finite even 
when the output is taken
differentially. vod  RD  RD  RD 
(8.49) Acm     
vicm 2RSS  2RSS   RD 
 CMRR is the ratio of differential                      
gain over common-mode gain
Ad
(8.50) CMRR 
Acm
32
8.4.1 Input Offset Voltage
Device mismatches cause a finite dc voltage at the output
Apply a small voltage of opposite polarity to cancel the offset

33
BJT Differential Pair

34
8.3 The BJT Differential Pair
 Figure 8.15 shows the basic

BJT differential-pair
configuration
 It is similar to the MOSFET

circuit – composed of two
matched transistors biased
by a constant-current source
– and is modeled by similar
expressions.

35
8.3.1 Basic Operation
 Suppose that the two bases joined together and connected to a common-
mode voltage VCM
 Since Q1 and Q2 are matched, and assuming an ideal bias current I with
infinite output resistance, this current will flow equally through both
transistors.

36
Input Common Mode Range

37
8.3.2 Input Common-Mode Range
 The allowable range of VCM
is determined at the upper
end by Q1 and Q2 leaving
the active mode and
entering saturation.
 Equations (8.66) and (8.67)
define the minimum and
maximum common-mode
input voltages.
I
(8.66) max VCM   VC  0.4  VCC   RC  0.4
2

(8.67) min VCM   VEE  VCS  VBE

38
Large Signal Operation

39
8.3.3 Large Signal Operation
(1) Note that the linear
range of BJT diff pair
is smaller than the
MOS diff pair
(2) It can be used for

fast switching (ECL
logic) by current
steering: e.g. current
flows entirely in one
branch then switches
to the other branch;
requires only 4VT
(3) The difference

input signal, vid should
be less than VT/2 to
linear amplification

40
How to increase the linear range?
Figure 8.18 The transfer characteristics of the BJT differential pair (a) can be linearized (b)
(i.e., the linear range of operation can be extended) by including resistances in the emitters.

41
Small Signal Operation

42
8.3.4 Small Signal Operation
Bias voltage
(DC)
+ small
signal (ac)
IC I
gm   ......(8.80)
VT 2VT
I vid vid vid
ic   gm  ie   ....(8.83)
2VT 2 2 2re
43
8.3.4 Small Signal Operation: half-circuit
Virtual
Ground
Ad  gm ( RC || ro )......(8.95)

44
8.3.4 Small Signal Operation: single-ended input
(1) Emitter voltage is no longer at virtual
ground.
(2) Voltage at the emitters is appx.

Vid /2
Note that we can apply

signal in the MOS diff
pair in similar fashion
45
8.3.5 Common-mode gain and CMRR
RC  RC  RC 
Acm      ......(8.98), (8.99)
2 REE  re  2 REE  RC 
Ad  R 
CMRR   2 g m REE   C  ......(8.100)
Acm  RC 
CMRR is the ratio of differential gain over common-mode gain

46
8.4.2 Input Offset Voltage
Device mismatches cause a finite dc voltage at the output
VOS smaller than

MOS diff pair
Apply a small voltage of opposite polarity to cancel the offset

47
List of Problems
MOS Diff Pair
p8.2: input common mode range of PMOS differential amplifier
ex8.4 MOS diff pair: differential gain
ex8.7 (simulate and verify) MOS diff pair: CMRR
p8.15: design of MOS differential amplifier
BJT Diff Pair

p8.34: input common mode range of npn differential amplifier
ex8.13: BJT diff pair: differential gain, CMRR
p8.49 (simulate): design of BJT differential amplifier
p8.62 (simulation only): npn differential amplifier

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1

ECE 3120 Microelectronics II Dr. Suketu Naik

1. Ch 7: Current Mirrors and Biasing

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

1) MOS and the bipolar differential amplifiers: how

2) The analysis and design of MOS and BJT differential

3) The structure, analysis, and design of amplifiers

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

MOS Differential Pair

ECE 3120 Microelectronics II Dr. Suketu Naik

 FETs should not enter

ECE 3120 Microelectronics II Dr. Suketu Naik

Input Common Mode Range

ECE 3120 Microelectronics II Dr. Suketu Naik

 Q1 and Q2 are matched

 Current I will divide

ECE 3120 Microelectronics II Dr. Suketu Naik

 The opposite applies if Q1

 The differential pair

 The diff pair provides

ECE 3120 Microelectronics II Dr. Suketu Naik

Differential Input Voltage

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

Large Signal Operation

ECE 3120 Microelectronics II Dr. Suketu Naik

 Step #1: Expression drain 2 L

 Step #2: Take the square roots 2 L

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

and (8.24) are nonlinear. I  I  vid

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

Virtual ground at the source

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

 Figure 8.9 (right): The

 Here Q1 is biased at I/2 and

 This circuit may be used to

Figure 8.11: (a) Differential amplifier

Figure 8.12: (a) Cascode differential

Common Mode Rejection Ratio (CMRR)

ECE 3120 Microelectronics II Dr. Suketu Naik

a) vin = VCM (DC common-mode signal) + vicm (common-mode noise

b) current source with fininte output resistance RSS

d) common-mode half circuit

 When the output is taken single- RD

Apply a small voltage of opposite polarity to cancel the offset

BJT Differential Pair

ECE 3120 Microelectronics II Dr. Suketu Naik

 Figure 8.15 shows the basic

 It is similar to the MOSFET

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

Input Common Mode Range

ECE 3120 Microelectronics II Dr. Suketu Naik

ECE 3120 Microelectronics II Dr. Suketu Naik

Large Signal Operation

ECE 3120 Microelectronics II Dr. Suketu Naik

(2) It can be used for